Display substrate and its manufacturing method, display device

Abstract

A display substrate and its manufacturing method, a display device, the display substrate comprises a base, a driving circuit layer disposed on the base, a light emitting structure layer disposed on a side of the driving circuit layer away from the base, and a color film structure layer disposed on a side of the light emitting structure layer away from the base, the light emitting structure layer comprises a pixel defining layer and an organic light emitting layer, the pixel defining layer defines a plurality of sub-pixel regions and has a first opening at least partially exposing the driving circuit layer, the organic light emitting layer is located in the sub-pixel regions and overlaps with the first opening of the pixel defining layer, the color film structure layer comprises a color film and a black matrix, the black matrix has a second opening at least partially exposing the first opening, the color film is disposed in the second opening, the black matrix comprises a first sub-side edge, and the first sub-side edge has a fold structure.

Description

[Technical field]

[0001] This application claims priority to a Chinese patent application filed with the China Patent Office on July 7, 2021, bearing application number 202110764582.0 and entitled "Display substrate and its manufacturing method, and display device", the contents of which should be understood to be incorporated herein by reference.

[0002] FIELD OF THE DISCLOSURE The embodiments of the present disclosure relate to, but are not limited to, the display technology field, and in particular to a display substrate and a manufacturing method thereof, and a display device. [Background technology]

[0003] Organic Light Emitting Diodes (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of autonomous light emission, wide viewing angle, high contrast ratio, low power consumption, extremely fast response speed, lightweight, bendable, and low cost. With the continuous development of display technology, flexible displays, which use OLED or QLED as a light-emitting device and control signals through thin film transistors (TFT), have become the main products in the current display field. Summary of the Invention

[0004] The following is a summary of the subject matter described herein. This summary is not intended to limit the scope of protection of the claims.

[0005] In an embodiment of the present disclosure, a display substrate is provided, comprising: a base; a driving circuit layer disposed on the base; a light-emitting structure layer disposed on a side of the driving circuit layer away from the base; and a color film structure layer disposed on a side of the light-emitting structure layer away from the base. The light-emitting structure layer includes a pixel definition layer and an organic light-emitting layer, the pixel definition layer defines a plurality of sub-pixel regions and has a first opening at least partially exposing the driving circuit layer, the organic light-emitting layer is located in the sub-pixel regions and overlaps with the first opening of the pixel definition layer. The color film structure layer includes a color film and a black matrix, the black matrix has a second opening at least partially exposing the first opening, the color film is disposed in the second opening, the black matrix includes a first sub-side edge, and the first sub-side edge has a fold structure.

[0006] In an exemplary embodiment, the first sub-side edge has a plurality of fold angles, and the number of fold angles of the first sub-side edge increases in an area farther away from the center line of the sub-pixel area.

[0007] In an exemplary embodiment, the sub-pixel region includes a center line, a first reference line, a second reference line, a third reference line, and a fourth reference line, which are arranged in sequence along a first direction, and the fourth reference line overlaps with the farthest boundary of the first sub-side edge away from the center line. A distance between the first reference line and the center line of the sub-pixel region is k, a distance between the first reference line and the second reference line is n1, a distance between the second reference line and the third reference line is n2, and a distance between the third reference line and the fourth reference line is n3, where k+n1+n2+n3=L / 2, and L is a length of the sub-pixel region along the first direction. A number x of folding angles between the center line and the first reference line, a number y of folding angles between the first reference line and the second reference line, and a number z of folding angles between the second reference line and the third reference line of the first sub-side edge satisfy a condition of x≦y≦z.

[0008] In an exemplary embodiment, n1=n2=n3.

[0009] In an exemplary embodiment, the number x of fold angles between the center line and the first reference line of the first sub-side edge is x≧3, the number y of fold angles between the first reference line and the second reference line of the first sub-side edge is y≧3, and the number z of fold angles between the second reference line and the third reference line of the first sub-side edge is z≧3.

[0010] In an exemplary embodiment, at least two fold angles between the center line and the first reference line of the first sub-side edge are approximately equal, at least two fold angles between the first reference line and the second reference line of the first sub-side edge are approximately equal, and at least two fold angles between the second reference line and the third reference line of the first sub-side edge are approximately equal.

[0011] In an exemplary embodiment, the first sub-side edge has at least one first fold angle between the center line and the first reference line, the first sub-side edge has at least one second fold angle between the first reference line and the second reference line, and the first sub-side edge has at least one third fold angle between the second reference line and the third reference line, and the angles of the first fold angle, the second fold angle, and the third fold angle are approximately equal.

[0012] In an exemplary embodiment, the number x of fold angles between the center line and the first reference line of the first sub-side edge is x≧3, the number y of fold angles between the first reference line and the second reference line of the first sub-side edge is y≧4, and the number z of fold angles between the second reference line and the third reference line of the first sub-side edge is z≧5.

[0013] In an exemplary embodiment, the first sub-side includes at least three fold angles x1, x2, and x3 between the center line and the first reference line, where x2 and x3 are approximately equal, and x1+x2 is approximately equal to 360 degrees. The first sub-side includes at least four fold angles y1, y2, y3, and y4 between the first reference line and the second reference line, where y1 and y2 are approximately equal, and y3+y4 is approximately equal to 360 degrees. The first sub-side includes at least four fold angles z1, z2, z3, and z4 between the second reference line and the third reference line, where z1 and z2 are approximately equal, and z3+z4 is approximately equal to 360 degrees.

[0014] In an exemplary embodiment, the first sub-side edge has at least three substantially equal fold angles between the center line and the first reference line.

[0015] In an exemplary embodiment, the at least three fold angles between the center line of the first sub-side edge and the first reference line are equal to n times 45 degrees, where n=3 or 5.

[0016] In an exemplary embodiment, the first sub-side edge has a first width along a first direction, the driving circuit layer includes at least one first signal line, the first signal line having a second width along the first direction, an orthogonal projection of the first signal line at a base and an orthogonal projection of the first sub-side edge at a base have a first overlapping portion, and the first overlapping portion has a third width along the first direction.

[0017] In an exemplary embodiment, the orthogonal projection at a base of the first signal line, the orthogonal projection at a base of the first sub-side edge, and the orthogonal projection at a base of the color film have a first overlapping portion.

[0018] In an exemplary embodiment, the first signal line has a fold line structure, the black matrix has a plurality of sub-side edges, and the number of fold angles of the first signal line within any sub-pixel region is smaller than the number of fold angles of at least one sub-side edge of the black matrix and greater than the number of fold angles of at least one other sub-side edge of the black matrix.

[0019] In an exemplary embodiment, the first width is l1, the second width is l2, the subpixel region includes a centerline and a first reference line along a first direction, a distance between the first reference line and the centerline of the subpixel region is k, and a length of the subpixel region along the first direction is L, where 10*l1≦L≦10*l2, and 2*k <L≦3*kである。

[0020] In an exemplary embodiment, the first width is l1, the second width is l2, the third width is l3, the subpixel region includes a centerline and a first reference line along a first direction, a distance between the first reference line and the centerline of the subpixel region is k, and a length of the subpixel region along the first direction is L, where 6*l2 <L<7*l2であり、20*l3<L<35*l3であり、3.5*l3<l2≦4*l3である。

[0021] In an exemplary embodiment, an orthogonal projection of the color film at a base at least partially covers an orthogonal projection of the first opening of the pixel definition layer at a base, a maximum thickness of the color film is greater than a maximum thickness of the first sub-side in a third direction, and the color film at least partially covers the first sub-side, the third direction being a direction along the base substrate towards the color film structure layer.

[0022] In an exemplary embodiment, the black matrix has a second thickness l4 in a third direction, the second thickness being between 0.9 microns and 1.2 microns, and the third direction being along the base substrate toward the color film structure layer.

[0023] In an exemplary embodiment, the first sub-side edge includes a third sub-segment that is neither parallel nor perpendicular to the first and second directions, and the black matrix includes a plurality of the third sub-segments.

[0024] In an exemplary embodiment, the first sub-side edge includes four third sub-segments that are spaced apart from one another, and the four third sub-segments are spaced apart from one another.

[0025] In an exemplary embodiment, the first sub-side has a staircase structure.

[0026] In an exemplary embodiment, the black matrix further includes a second sub-side edge opposite to the first sub-side edge, and the second sub-side edge has a fold line structure, and the first sub-side edge and the second sub-side edge are arranged asymmetrically with respect to a center line of the sub-pixel area.

[0027] In an exemplary embodiment, the sub-pixel region includes, sequentially along a first direction, an eighth reference line, a seventh reference line, a sixth reference line, a fifth reference line, a center line, a first reference line, a second reference line, a third reference line, and a fourth reference line, the fourth reference line overlapping with the farthest boundary of the first sub-side edge away from the center line, and the eighth reference line overlapping with the farthest boundary of the second sub-side edge away from the center line. The distance between the first reference line and the center line of the sub-pixel region is k, the distance between the fifth reference line and the center line of the sub-pixel region is k, the distance between the first reference line and the second reference line is n1, the distance between the sixth reference line and the fifth reference line is n1, the distance between the second reference line and the third reference line is n2, the distance between the seventh reference line and the sixth reference line is n2, the distance between the third reference line and the fourth reference line is n3, and the distance between the eighth reference line and the seventh reference line is n3, where k+n1+n2+n3=L / 2, where L is the length along the first direction of the sub-pixel region. The number x of fold angles between the center line and the first reference line of the first sub-side edge, the number y of fold angles between the first reference line and the second reference line of the first sub-side edge, the number z of fold angles between the second reference line and the third reference line of the first sub-side edge, the number x' of fold angles between the center line and the fifth reference line of the second sub-side edge, the number y' of fold angles between the fifth reference line and the sixth reference line of the second sub-side edge, and the number z' of fold angles between the sixth reference line and the seventh reference line of the second sub-side edge satisfy the conditions: x=x', y≠y', z≠z'.

[0028] In an exemplary embodiment, the black matrix further includes a third sub-side and a fourth sub-side arranged opposite each other, the first sub-side, the third sub-side, the second sub-side and the fourth sub-side are connected end-to-end, and the third sub-side and the fourth sub-side have a strip-like shape or an approximately strip-like shape.

[0029] In an exemplary embodiment, the subpixel regions include a first subpixel region, a second subpixel region, and a third subpixel region, the first subpixel region includes a first light-emitting unit and a color film of a first color, the second subpixel region includes a second light-emitting unit and a color film of a second color, the third subpixel region includes a third light-emitting unit and a color film of a third color, and an orthogonal projection at the base of the color film of the first color covers an orthogonal projection at the base of the first light-emitting unit, an orthogonal projection at the base of the color film of the second color covers an orthogonal projection at the base of the second light-emitting unit, and an orthogonal projection at the base of the color film of the third color covers an orthogonal projection at the base of the third light-emitting unit.

[0030] In an exemplary embodiment, the second light-emitting unit includes two sub-light-emitting units that are installed separately, and the color film of the second color includes two sub-color films that are installed separately, such that an orthogonal projection at the base of one sub-color film covers an orthogonal projection at the base of one sub-light-emitting unit, and an orthogonal projection at the base of the other sub-color film covers an orthogonal projection at the base of the other sub-light-emitting unit.

[0031] In an exemplary embodiment, the display substrate further comprises an encapsulation layer positioned on a side of the color film structure layer away from the light emitting structure layer, such that an orthogonal projection at the base of the encapsulation layer covers an orthogonal projection at the base of the color film structure layer.

[0032] In an exemplary embodiment, the subpixel regions include a first subpixel region, a second subpixel region, a third subpixel region, and a fourth subpixel region, the first subpixel region includes a first light-emitting unit and a color film of a first color, the second subpixel region includes a second light-emitting unit and a color film of a second color, the third subpixel region includes a third light-emitting unit and a color film of a third color, and the fourth subpixel region includes a fourth light-emitting unit and a color film of a fourth color, wherein an orthogonal projection at the base of the color film of the first color covers an orthogonal projection at the base of the first light-emitting unit, an orthogonal projection at the base of the color film of the second color covers an orthogonal projection at the base of the second light-emitting unit, an orthogonal projection at the base of the color film of the third color covers an orthogonal projection at the base of the third light-emitting unit, and an orthogonal projection at the base of the color film of the fourth color covers an orthogonal projection at the base of the fourth light-emitting unit.

[0033] In an exemplary embodiment, the display substrate further comprises an encapsulation layer covering the color film structure layer, the encapsulation layer covering the color film of the first color, the color film of the second color, and the color film of the third color, and the color film of the fourth color is formed in the same layer and of the same material as at least a portion of the encapsulation layer.

[0034] In an exemplary embodiment, the first subpixel region is a red subpixel region, the second subpixel region is a green subpixel region, the third subpixel region is a blue subpixel region, and the fourth subpixel region is a white subpixel region.

[0035] In an exemplary embodiment, a first sub-side of the white sub-pixel region is connected to a first sub-side of the red sub-pixel region, and a shape of the first sub-side of the white sub-pixel region is different from a shape of the first sub-side of the red sub-pixel region.

[0036] In an exemplary embodiment, the black matrix further includes a second sub-side edge opposite to the first sub-side edge, the second sub-side edge of the green sub-pixel region and the second sub-side edge of the blue sub-pixel region are adjacent to each other, and a number of fold angles of the second sub-side edge of the green sub-pixel region is greater than a number of fold angles of the second sub-side edge of the blue sub-pixel region.

[0037] In an exemplary embodiment, the black matrix between two adjacent subpixel regions is conformal.

[0038] In an exemplary embodiment, the number of fold angles of the black matrix between the white subpixel region and the green subpixel region is greater than the number of fold angles of the black matrix between the red subpixel region and the blue subpixel region.

[0039] In an exemplary embodiment, the areas of the different color subpixel regions are different.

[0040] In an exemplary embodiment, the display substrate further comprises a blank structure, wherein an orthogonal projection at a base of the blank structure and an orthogonal projection at a base of the sub-pixel region do not overlap.

[0041] In an exemplary embodiment, the ratio of the area of ​​the blank structure to the area of ​​the sub-pixel region is greater than or equal to 45%.

[0042] In an exemplary embodiment, the ratio of the area of ​​the blank structures to the area of ​​the sub-pixel regions is equal to 46%.

[0043] In an exemplary embodiment, the blank structure has a fifth width along a first direction, the fifth width being equal to or approximately equal to a total length of all fold line structures on the first sub-side edge.

[0044] In an exemplary embodiment, the plurality of subpixel regions include a white subpixel region and a red subpixel region, the blank structure has a first sub-edge adjacent to a first sub-side of the white subpixel region and a first sub-side of the red subpixel region, and a shape of the first sub-edge and a shape of the first sub-side of the white subpixel region and a shape of the first sub-side of the red subpixel region are conformal.

[0045] In an exemplary embodiment, the drive circuitry layer further includes a repair structure, wherein an orthogonal projection of the repair structure at a base and an orthogonal projection of the blank structure at a base at least partially overlap.

[0046] In an exemplary embodiment, the plurality of subpixel regions includes a red subpixel region and a blue subpixel region, and the repair structures of the red subpixel region and the repair structures of the blue subpixel region are at least partially symmetrical and at least partially asymmetrical.

[0047] In an exemplary embodiment, the light-emitting structure further includes an anode, the first opening at least partially exposes the anode, and at least one sub-pixel region includes a plurality of individually disposed sub-anode blocks.

[0048] In an exemplary embodiment, the plurality of individually located sub-anode blocks includes two.

[0049] In an exemplary embodiment, the two sub-anode blocks have different configurations.

[0050] In an exemplary embodiment, the driving circuit layer includes anode holes, which are electrically connected to two sub-anode blocks respectively.

[0051] In an exemplary embodiment, the driving circuit layer further includes a repair structure, and the two sub-anode blocks are electrically connected to each other and to the repair structure.

[0052] An embodiment of the present disclosure further provides a display device, comprising a display substrate as above.

[0053] An embodiment of the present disclosure further provides a method for manufacturing a display substrate, the method comprising: forming a drive circuit layer on a base; forming a light-emitting structure layer on a side of the driving circuit layer away from a base, the light-emitting structure layer including a pixel definition layer and an organic light-emitting layer, the pixel definition layer defining a plurality of sub-pixel regions and having a first opening at least partially exposing the driving circuit layer, the organic light-emitting layer being located in the sub-pixel regions and overlapping the first opening of the pixel definition layer; forming a color film structure layer on a side of the light-emitting structure layer away from the base, the color film structure layer including a color film and a black matrix, the black matrix having a second opening at least partially exposing the first opening, the color film being disposed in the second opening, the black matrix including a first sub-side edge, and the first sub-side edge having a fold line structure.

[0054] Other aspects will be understood after reading and understanding the drawings and detailed description. [Brief description of the drawings]

[0055] The drawings are intended to provide an understanding of the technical solution of the present disclosure, to be a part of the specification, and to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solution of the present disclosure. [Figure 1] FIG. 1 is a structural schematic diagram of a display device according to an exemplary embodiment of the present disclosure. [Diagram 2] 2A to 2C are schematic diagrams of pixel arrays of four display substrates according to an exemplary embodiment of the present disclosure. [Diagram 3] 2A to 2C are schematic diagrams of pixel arrays of four display substrates according to an exemplary embodiment of the present disclosure. [Figure 4] 2A to 2C are schematic diagrams of pixel arrays of four display substrates according to an exemplary embodiment of the present disclosure. [Diagram 5] 2A to 2C are schematic diagrams of pixel arrays of four display substrates according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 2 is a structural schematic diagram of a sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 7] 7 is a schematic cross-sectional view of a region OO' in FIG. [Figure 8] FIG. 2 is a structural schematic diagram of a pixel driving circuit of a display substrate according to an exemplary embodiment of the present disclosure; [Figure 9] FIG. 2 is a structural schematic diagram of a first sub-side of a black matrix in a sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 10] FIG. 13 is a structural schematic diagram of a first sub-side of a black matrix in another sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 11] FIG. 13 is a schematic diagram of an overlapping structure between a first signal line and a first sub-side edge in a sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic cross-sectional view of the aa' region in FIG. [Figure 13] FIG. 2 is a structural schematic diagram of a first opening and a second opening in a sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 14] FIG. 2 is a structural schematic diagram of a color film in a sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 15] FIG. 13 is a structural schematic diagram of an overlap between a first signal line and a first sub-side edge in another sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 16] FIG. 13 is a structural schematic diagram of a first sub-side edge of another sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 17] FIG. 2 is a structural schematic diagram of a first sub-side and a second sub-side in a sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 18] FIG. 13 is a structural schematic diagram of a second sub-side in a sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 19] FIG. 2 is a structural schematic diagram of black matrices in adjacent pixels according to an exemplary embodiment of the present disclosure. [Figure 20] FIG. 13 is a structural schematic diagram of a black matrix in another adjacent pixel according to an exemplary embodiment of the present disclosure. [Figure 21] FIG. 2 is a structural schematic diagram of color films in different color sub-pixels according to an exemplary embodiment of the present disclosure. [Figure 22] FIG. 2 is a structural schematic diagram of encapsulation in different color sub-pixels according to an exemplary embodiment of the present disclosure. [Figure 23] FIG. 13 is a structural schematic diagram of a blank structure in a sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 24] FIG. 2 is a schematic diagram of a repair structure in a sub-pixel according to an exemplary embodiment of the present disclosure. [Diagram 25] FIG. 13 is a schematic diagram of a repair structure in another sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 26] FIG. 13 is a schematic diagram of a repair structure in a further sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 27] FIG. 2 is a structural schematic diagram of an anode in a sub-pixel according to an exemplary embodiment of the present disclosure. [Figure 28] 28 is a schematic cross-sectional view of a bb' region in FIG. 27. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] In order to clarify the objectives, technical solutions and advantages of the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the drawings. Note that the embodiments can be implemented in many different forms. As can be easily understood by those skilled in the art, the manner and content can be converted into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the description of the following embodiments. If there is no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other.

[0057] In the drawings, the size, thickness or area of ​​each component may be enlarged for clarity. Therefore, one embodiment of the present disclosure is not limited to the size, and the shape and size of each part in the drawings do not reflect actual proportions. In addition, the drawings are schematic illustrations of ideal examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0058] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and are not intended to be limiting in terms of quantity.

[0059] In this specification, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., but this is for the purpose of explaining and simplifying the specification, and is not intended to indicate or suggest that the described device or element has a specific orientation and must be constructed and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationship of the components is appropriately changed depending on the direction in which each component is described. Therefore, it is not limited to the terms described in the specification, and may be appropriately changed in some cases.

[0060] In this specification, unless otherwise specified and limited, the terms "attached", "coupled" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection. It may be a mechanical connection or an electrical connection. It may be a direct connection, an indirect connection via a linker, or an internal communication between two elements. Those skilled in the art can understand the specific meaning of the above technical terms in the present disclosure according to the specific situation.

[0061] In this specification, a transistor refers to an element including at least three terminals, a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to a region through which a current mainly flows.

[0062] In this specification, the first pole may be a drain electrode and the second pole may be a source electrode, or the first pole may be a source electrode and the second pole may be a drain electrode. The functions of "source electrode" and "drain electrode" may be interchanged, such as when using transistors with opposite polarity, or when the current direction during operation in the circuit is changed. Thus, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0063] In this specification, "electrical connection" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it is capable of transmitting and receiving electrical signals between the components being connected. Examples of the "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0064] In this specification, "parallel" refers to a state in which the angle between two straight lines is between -10° and 10°, including a state in which the angle is between -5° and 5°, and "perpendicular" refers to a state in which the angle between two straight lines is between 80° and 100°, including a state in which the angle is between 85° and 95°.

[0065] In this specification, two angles being approximately equal refers to the ratio of the two angles being in the range of 0.9 to 1.1, including the case where the ratio of the two angles is in the range of 0.95 to 1.05. Thus, the sum of the two angles being approximately equal to 360° may include the case where the sum of the two angles is in the range of 342° to 378°.

[0066] In this specification, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0067] In the present disclosure, the term "about" refers to a case where the boundary is not strictly defined, but a numerical value within the error range of the process and measurement is allowed. FIG. 1 is a structural schematic diagram of a display device according to an exemplary embodiment of the present disclosure. As shown in FIG. 1, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller provides gray values ​​and control signals conforming to the specifications of the data signal driver to the data signal driver, and provides clock signals, scan start signals, etc. conforming to the specifications of the scan signal driver to the scan signal driver. The data signal driver uses the gray values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver may sample gray values ​​using a clock signal, and apply data voltages corresponding to the gray values ​​to the data signal lines D1 to Dn in units of sub-pixel rows, where n is a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driver can sequentially provide scan signals having turn-on level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register and generate scan signals by sequentially transmitting the scan start signal provided in the form of a turn-on level pulse to the next level circuit under the control of the clock signal, where m is a natural number. The subpixel array can include a plurality of subpixels Pxij. Each subpixel Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, where i and j are natural numbers. The subpixel Pxij may refer to a subpixel whose transistor is connected to the ith scan signal line and connected to the jth data signal line.

[0068] 2-4 are schematic diagrams of the planar structure of three kinds of display substrates according to the embodiments of the present disclosure. As shown in FIG. 2-4, the display substrate may include a plurality of pixel units P arranged in the form of a matrix. At least one of the plurality of pixel units P includes a first light-emitting unit (sub-pixel) P1 emitting a first color light, a second light-emitting unit P2 emitting a second color light, and a third light-emitting unit P3 emitting a third color light. The first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the scanning signal lines, the data signal lines, and the emission signal lines. The pixel driving circuit is configured to receive the data voltage transmitted from the data signal lines under the control of the scanning signal lines and the emission signal lines, and output a corresponding current to the light-emitting device. The light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuits of the light-emitting units in which they are located. The light emitting device is configured to emit light of a corresponding brightness in response to a current output from the pixel driving circuit of the light emitting unit in which it resides.

[0069] In an exemplary embodiment, the first light-emitting unit may be a red (R) light-emitting unit, the second light-emitting unit may be a green (G) light-emitting unit, and the third light-emitting unit may be a blue (B) light-emitting unit, where the present disclosure is not limited thereto.

[0070] In an exemplary embodiment, as shown in FIG. 5, at least one of the pixel units P further includes a fourth light-emitting unit P4 that emits a fourth color light, and for example, the fourth light-emitting unit P4 may be a white (W) light-emitting unit, and the present disclosure is not limited thereto. The fourth light-emitting unit P4 may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the fourth light-emitting unit P4 is respectively connected to the scanning signal line, the data signal line and the light-emitting signal line. The pixel driving circuit is configured to receive the data voltage transmitted from the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in the fourth light-emitting unit P4 is connected to the pixel driving circuit in the fourth light-emitting unit P4. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output from the pixel driving circuit of the light-emitting unit in which it is located.

[0071] In an exemplary embodiment, the shape of the light-emitting units in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon. If the pixel unit includes three light-emitting units, the three light-emitting units may be arranged in a horizontal parallel, vertical parallel, or hexagonal manner. If the pixel unit includes four light-emitting units, the four light-emitting units may be arranged in a horizontal parallel, vertical parallel, or square manner. This disclosure is not limited thereto.

[0072] With the continuous development of display technology, OLED technology is increasingly applied to transparent display. Transparent display is an important personalized display field of display technology, which refers to image display in a transparent state. Viewers can not only see the image on the display device, but also see the image behind the display device. Virtual reality (abbreviated as VR), augmented reality (abbreviated as AR) and 3D display functions can be realized. Transparent display devices using AMOLED technology generally divide each pixel into a display area and a transparent area, and install pixel driving circuits and light emitting elements in the display area to realize image display, and allow light to pass through the transparent area.

[0073] Displays over 27 inches can be called large-screen displays. In large-screen transparent display products, when external light passes through the gap between two adjacent pixel rows, it will produce strong diffraction, interference, scattering, color dispersion and other effects, which will cause the degradation of the display effect of the large-screen transparent display panel.

[0074] An exemplary embodiment of the present disclosure provides a display substrate, which may include a base, a driving circuit layer disposed on the base, a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, and a color film structure layer disposed on a side of the light-emitting structure layer away from the base. The light-emitting structure layer includes a pixel definition layer and an organic light-emitting layer, the pixel definition layer defines a plurality of sub-pixel regions and has a first opening at least partially exposing the driving circuit layer, the organic light-emitting layer is located in the sub-pixel regions and overlaps with the first opening of the pixel definition layer. The color film structure layer includes a color film and a black matrix, the black matrix of at least one sub-pixel region has a second opening at least partially exposing the first opening, the color film is disposed in the second opening, the black matrix of at least one sub-pixel region has at least one side, and the at least one side has a fold structure.

[0075] In the display substrate according to the embodiment of the present disclosure, a color film and a black matrix are disposed on the color film structure layer, and the black matrix has a side with a folding line structure, thereby reducing the reflectance and improving the purity of the emitted light. The display substrate according to the embodiment of the present disclosure does not require the use of a polarizer, thereby reducing the cost of the display substrate, reducing the thickness of the display substrate, improving the bendability of the display substrate, reducing the grating effect (such as the diffraction effect, interference effect, scattering, color dispersion, etc.), and improving the display effect.

[0076] Fig. 6 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure, and Fig. 7 is a cross-sectional structural schematic diagram of the OO' region in Fig. 6, showing the structure of one sub-pixel. As shown in Fig. 6 and Fig. 7, an embodiment of the present disclosure provides a display substrate, which includes a base 101, a driving circuit layer 102 disposed on the base 101, a light emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the base 101, and a color film structure layer 104 disposed on the side of the light emitting structure layer 103 away from the base 101; The light emitting structure layer 103 includes a pixel definition layer 103b and an organic light emitting layer 103c, the pixel definition layer 103b defines a plurality of sub-pixel regions and has a first opening K1 at least partially exposing the driving circuit layer 102, the organic light emitting layer 103c is located in the sub-pixel region and overlaps with the first opening K1 of the pixel definition layer 103b, The color film structure layer 104 includes a color film 104b and a black matrix 104a, the black matrix 104a has a second opening K2 at least partially exposing the first opening K1, the color film 104b is disposed in the second opening K2, the black matrix 104a includes a first sub-side edge 1041, and the first sub-side edge 1041 has a fold line structure.

[0077] In an exemplary embodiment, the display substrate further comprises an encapsulation layer 105 disposed on the side of the color film structure layer 104 away from the light emitting structure layer 103. In some possible implementations, the display substrate may include other film layers, such as spacer columns, and the present disclosure is not limited thereto.

[0078] In an exemplary embodiment, the base may be a flexible base or a rigid base. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and a storage capacitor that constitute a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. FIG. 8 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 8, the pixel driving circuit has a 3T1C structure, which includes three transistors (a first transistor T1, a second transistor T2 and a third transistor T3), one storage capacitor C STand six signal lines (data signal line Dn, first scanning signal line Gn, second scanning signal line Sn, compensation line Se, first power supply line VDD and second power supply line VSS). In an exemplary embodiment, the first transistor T1 is a switch transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The gate electrode of the first transistor T1 is coupled to the first scanning signal line Gn, the first pole of the first transistor T1 is coupled to the data signal line Dn, and the second pole of the first transistor T1 is coupled to the gate electrode of the second transistor T2. The first transistor T1 is used to receive a data signal transmitted from the data signal line Dn under the control of the first scanning signal line Gn, and make the gate electrode of the second transistor T2 receive the data signal. The gate electrode of the second transistor T2 is coupled to the second pole of the first transistor T1, the first pole of the second transistor T2 is coupled to the first power supply line VDD, and the second pole of the second transistor T2 is coupled to the first pole of the OLED. The second transistor T2 is used to generate a corresponding current at the second pole under the control of the data signal received by its gate electrode. The gate electrode of the third transistor T3 is coupled to the second scanning signal line Sn, the first pole of the third transistor T3 is connected to the compensation line Se, and the second pole of the third transistor T3 is coupled to the second pole of the second transistor T2. The third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing, and compensate the threshold voltage Vth. The first pole of the OLED is coupled to the second pole of the second transistor T2, and the second pole of the OLED is coupled to the second power supply line VSS. The OLED is used to emit light of a corresponding brightness in response to the current at the second pole of the second transistor T2. The storage capacitor C ST The first pole of the storage capacitor C is coupled to the gate electrode of the second transistor T2. ST The second pole of the storage capacitor C is coupled to the second pole of the second transistor T2. ST is used to store the potential of the gate electrode of the second transistor T2.

[0079] In an exemplary embodiment, the signal of the first power line VDD is a high-level signal that is continuously provided, and the signal of the second power line VSS is a low-level signal that is continuously provided. The first transistor T1 to the third transistor T3 may be P-type transistors or N-type transistors. By adopting the same type of transistors in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the yield rate of the product can be improved. In some possible embodiments, the first transistor T1 to the third transistor T3 may include P-type transistors and N-type transistors. In an exemplary embodiment, the light emitting device may be an organic light emitting transistor (OLED), and includes a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) that are stacked.

[0080] In an exemplary embodiment, the light emitting structure layer 103 may include an anode 103a, a pixel definition layer 103b, an organic light emitting layer 103c, and a cathode 103d. The pixel definition layer 103b defines a plurality of sub-pixel regions and has a first opening K1 at least partially exposing the driving circuit layer 102. The anode 103a is connected to a drain electrode of a transistor in the driving circuit layer 102 through a via. The organic light emitting layer 103c is connected to the anode 103a, and the cathode 103d is connected to the organic light emitting layer 103c. The organic light emitting layer 103c emits light of a corresponding color by driving the anode 103a and the cathode 103d. The color film structure layer 104 may include a black matrix 104a and a color film 104b. The black matrix 104a has a second opening K2 at least partially exposing the first opening K1, and the color film 104b is disposed in the second opening K2. The encapsulation layer 105 may include a first encapsulation layer and a second encapsulation layer that are stacked together, the first encapsulation layer may be made of an organic material, and the second encapsulation layer may be made of an inorganic material, which can prevent external water vapor from entering the light-emitting structure layer and the color film structure layer.

[0081] 9 is a structural schematic diagram of a first sub-side edge of a black matrix in one sub-pixel region according to an exemplary embodiment of the present disclosure. As shown in FIG. 6 and FIG. 9, in an exemplary embodiment, in one sub-pixel region, the black matrix includes a first sub-side edge 1041, the first sub-side edge 1041 has a certain width along a first direction, and the first sub-side edge 1041 has a fold line structure, and the fold line structure has a number of fold angles. The more the region is away from the center line A of the sub-pixel region, the more the number of fold angles.

[0082] In the display substrate according to the embodiment of the present disclosure, a fold line structure is provided on the first sub-side edge 1041 of the black matrix, and the number of fold angles increases in the region away from the center line A of the sub-pixel region, thereby further reducing the diffraction and interference effects of the display panel and improving the display effect.

[0083] As shown in FIG. 6, the sub-pixel region has sub-side I and sub-side III arranged along a first direction, and sub-side II and sub-side IV arranged along a second direction, and the sub-side I, sub-side II, sub-side III and sub-side IV are connected end-to-end. In the embodiment of the present disclosure, the sub-side is defined as the outer contour of the sub-pixel region (the outer contour is the boundary away from the center of the sub-pixel region). Exemplarily, if the outer contour of the black matrix is ​​the outermost contour of the sub-pixel region in a certain direction, the sub-side of the sub-pixel is the outer contour of the black matrix in the certain direction. On the other hand, if the outer contour of the pixel definition layer is the outermost contour of the sub-pixel region in a certain direction, the sub-side of the sub-pixel is the outer contour of the pixel definition layer in the certain direction.

[0084] In an exemplary embodiment, the sub-pixel region has a center line A, and the center line A can be defined as the center line of two oppositely disposed sub-sides. In an exemplary embodiment, when one or both of the two oppositely disposed sub-sides have a folding line, the center line of the two folding lines farthest apart among the two oppositely disposed sub-sides is selected as the center line of the sub-pixel region. For example, as shown in FIG. 6, the two oppositely disposed sub-sides may be sub-side I and sub-side III, or sub-side II and sub-side IV. The following describes the case where the two oppositely disposed sub-sides are sub-side II and sub-side IV.

[0085] In an exemplary embodiment, the length of the subpixel region along the first direction is L. As shown in FIG. 6, the length L of the subpixel region along the first direction may be defined as the farthest distance between two edges of the subpixel region that are arranged opposite to each other along the first direction, that is, the distance from the leftmost edge of the subpixel region to the rightmost edge of the subpixel region. A first reference line B may be arranged at a distance k from the center line A. The distance k between the center line A and the first reference line B is the length of the shortest line segment between the center line A and the first reference line B. In this embodiment, the center line A and the first reference line B are parallel, so the distance k between the center line A and the first reference line B is the length of the line segment perpendicular to the center line A and the first reference line B. The subpixel region may further include a second reference line C, a third reference line D, and a fourth reference line E. The sub-side IV has a sub-boundary m that is farthest from the center line A (if the sub-side IV is a straight line, the sub-boundary m is the sub-side IV). The fourth reference line E overlaps with the sub-boundary m. That is, the orthogonal projection of the fourth reference line E on the base substrate overlaps with the orthogonal projection of the sub-boundary m on the base substrate that is farthest from the center line in the sub-side where the subpixel 10 is located. The first reference line B and the second reference line C, the second reference line C and the third reference line D, and the third reference line D and the fourth reference line E have the same distance. As shown in FIG. 6 and FIG. 9, the distance between the first reference line B and the second reference line C is n1, the distance between the second reference line C and the third reference line D is n2, and the distance between the third reference line D and the fourth reference line E is n3. In an exemplary embodiment, n1=n2=n3, and k+n1+n2+n3=L / 2. In this embodiment, the center line A, the first reference line B, the second reference line C, the third reference line D and the fourth reference line E all extend along the second direction.

[0086] In an exemplary embodiment, in one sub-pixel region, the black matrix 104a has at least one first sub-side edge 1041, and the first sub-side edge 1041 has a constant width along a first direction. The first sub-side edge 1041 has a plurality of folding angles. The number of folding angles x between the center line A and the first reference line B, the number of folding angles y between the first reference line B and the second reference line C, and the number of folding angles z between the second reference line C and the third reference line D of the first sub-side edge 1041 satisfy a condition of x≦y≦z.

[0087] In this embodiment, the number of folding angles included in the first sub-side edge 1041 within a range where the perpendicular distance from the center line A is k or less (i.e., between the center line A and the first reference line B) is x. The folding angle described in the embodiment of the present disclosure refers to an angle that is less than 360° and not equal to 180° on the side toward the center line A. The number of folding angles included in the first sub-side edge 1041 within a range where the perpendicular distance from the center line is k to (k+(L / 2-k) / 3) (i.e., between the first reference line B and the second reference line C) is y. The number of folding angles included in the first sub-side edge 1041 within a range where the perpendicular distance from the center line is (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3) (i.e., between the second reference line C and the third reference line D) is z. x, y, and z satisfy the condition x≦y≦z.

[0088] In other exemplary embodiments, the fold angle is not equal to 90°, i.e., the fold angle is an angle toward the centerline A that is less than 360° and is not equal to 180° or 90°. In other exemplary embodiments, the fold angle is obtuse, ie, an angle toward centerline A that is less than 360° and greater than 90° and not equal to 180°.

[0089] In another exemplary embodiment, the number x of fold angles between the center line A and the first reference line B, the number y of fold angles between the first reference line B and the second reference line C, and the number z of fold angles between the second reference line C and the third reference line D of the first sub-side edge 1041 satisfy the conditions x≧3, y≧3, and z≧3.

[0090] In an exemplary embodiment, within a range where the vertical distance from the center line A is equal to or less than k, the first sub-side edge 1041 includes at least three fold angles, and at least two of the at least three fold angles are approximately equal; Within a range of a vertical distance from the center line A of k to (k+(L / 2-k) / 3), the first sub-side edge 1041 includes at least three folding angles, and at least two of the at least three folding angles are substantially equal; Within the range of the vertical distance from the center line A of (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3), the first sub-side edge 1041 includes at least three fold angles, and at least two of the at least three fold angles are approximately equal.

[0091] 10, within a range where the vertical distance from the center line A is k or less (i.e., between the center line A and the first reference line B), the first sub-side edge 1041 includes at least three folding angles x1, x2, and x3, and two of the folding angles are approximately equal, and for example, x2 and x3 are approximately equal. Within a range where the vertical distance from the center line A is k to (k+(L / 2-k) / 3) (i.e., between the first reference line B and the second reference line C), the first sub-side edge 1041 includes at least three folding angles y1, y2, and y3, and two of the folding angles are approximately equal, and for example, y2 and y3 are approximately equal. Within the range of vertical distance from center line A of (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3) (i.e., between second reference line C and third reference line D), first sub-side edge 1041 includes at least three fold angles z1, z2, and z3, two of which are approximately equal, for example, z1 and z4 are approximately equal.

[0092] In another exemplary embodiment, the first sub-side edge 1041 has at least one first fold angle within a range of perpendicular distance from the center line A that is equal to or less than k. The first sub-side edge 1041 has at least one second fold angle within a range of perpendicular distance from the center line A that is between k and (k+(L / 2-k) / 3). The first sub-side edge 1041 has at least one third fold angle within a range of perpendicular distance from the center line A that is between (k+(L / 2-k) / 3) and (k+2(L / 2-k) / 3). The angles of the first fold angle, the second fold angle, and the third fold angle are approximately equal.

[0093] 10, the first sub-side edge 1041 has a first folding angle x1=135° within a range where the vertical distance from the center line A is equal to or less than k. The first sub-side edge 1041 has a second folding angle y1=135° within a range where the vertical distance from the center line A is k to (k+(L / 2-k) / 3). The first sub-side edge 1041 has a third folding angle z1=135° within a range where the vertical distance from the center line A is (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3). According to the embodiment of the present disclosure, the angles of some folding angles in the black matrix are approximately equal, which further contributes to the realization of the process.

[0094] In another exemplary embodiment, the number x of fold angles between the center line A and the first reference line B, the number y of fold angles between the first reference line B and the second reference line C, and the number z of fold angles between the second reference line C and the third reference line D of the first sub-side edge 1041 satisfy the conditions x≧3, y≧4, and z≧5.

[0095] 10, the black matrix 104a has three folding angles x1, x2, and x3 within a range where the vertical distance from the center line A is equal to or less than k. The black matrix 104a has four folding angles y1, y2, y3, and y4 within a range where the vertical distance from the center line A is k to (k+(L / 2-k) / 3). The black matrix 104a has six folding angles z1, z2, z3, z4, z5, and z6 within a range where the vertical distance from the center line A is (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3). According to the embodiment of the present disclosure, the number of folding angles increases as the distance from the sub-pixel center line increases, and the grating effect (e.g., diffraction effect, interference effect, scattering, color dispersion, etc.) can be reduced.

[0096] In another exemplary embodiment, within a range where the vertical distance from the center line A is equal to or less than k (i.e., between the center line A and the first reference line B), the black matrix 104a includes at least three folding angles x1, x2, and x3, where x2 and x3 are approximately equal, and x1+x2 is approximately equal to 360°. Within a range where the vertical distance from the center line A is equal to or less than k (i.e., between the first reference line B and the second reference line C), the black matrix 104a includes at least four folding angles y1, y2, y3, and y4, where y1 and y2 are approximately equal, and y3+y4 is approximately equal to 360°. Within the range of vertical distance from center line A from (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3) (i.e., between the second reference line C and the third reference line D), black matrix 104a includes at least four fold angles z1, z2, z3, and z4, where z1 and z2 are approximately equal, and z3+z4 is approximately equal to 360°.

[0097] Illustratively, x1 is approximately equal to 135° and x2 is approximately equal to 225°. Illustratively, y1 is approximately equal to 135° and y3 is approximately equal to 225°.

[0098] In another exemplary embodiment, the black matrix 104a includes at least three fold angles x1, x2, and x3, where x1, x2, and x3 are approximately equal, within a range where the vertical distance from the center line A is equal to or less than k (i.e., between the center line A and the first reference line B). According to this embodiment, making the angles of some of the black matrix 104a approximately equal contributes to the realization of the process.

[0099] 10, within a range where the vertical distance from the center line A is equal to or less than k (i.e., between the center line A and the first reference line B), the black matrix 104a includes at least three folding angles, x1, x2, and x3, and the angles are equal to n times 45 degrees, where n=3 or 5. According to this embodiment, making some angles of the black matrix 104a an integer multiple of 45 degrees contributes to the realization of the process.

[0100] In an exemplary embodiment, FIG. 12 is a schematic cross-sectional view of the aa' region in FIG. 11. As shown in FIG. 11 and FIG. 12, the display substrate includes a base 101, a driving circuit layer 102 disposed on the base 101, a light-emitting structure layer 103 (including a pixel definition layer, an organic light-emitting layer, an anode, and a cathode, etc.) disposed on the driving circuit layer 102, and a color film structure layer 104 disposed on the light-emitting structure layer 103. The color film structure layer 104 includes a black matrix 104a, and the black matrix 104a includes at least one first sub-side edge 1041. The driving circuit layer 102 includes at least one first signal line 1021, and the first signal line 1021 has a second width l2 along a first direction, and the first sub-side edge 1041 has a first width l1 along the first direction. The orthogonal projection of the first signal line 1021 at its base and the orthogonal projection of the first sub-side edge 1041 at its base have a first overlapping portion, and the first overlapping portion has a third width l3 along the first direction.

[0101] The above width satisfies the following relationship: 10*l1≦L≦10*l2 2*k <L≦3*k

[0102] Illustratively, L=220 μm, l1=12-20 μm, k is equal to about 74 μm, l3 is equal to about 8 μm, and l2 is equal to about 32 μm.

[0103] In another exemplary embodiment, 6*l2 <L<7*l2である。

[0104] In another exemplary embodiment, 20*l3 <L<35*l3である。

[0105] In another exemplary embodiment, 3.5*l3 <l2≦4*l3である。

[0106] In an exemplary embodiment, the first signal line 1021 has a fold line structure, the black matrix has multiple sub-side edges, and the number of fold angles in any sub-pixel region of the first signal line is smaller than the number of fold angles in at least one sub-side edge of the black matrix and larger than the number of fold angles in at least one other sub-side edge of the black matrix.

[0107] As shown in Figures 6 and 11, the first signal line 1021 has a fold line structure, the black matrix has sub-side I, sub-side II, sub-side III and sub-side IV, and the number of fold angles in any sub-pixel region of the first signal line is smaller than the number of fold angles of at least one sub-side of the black matrix (e.g., sub-side II and sub-side IV) and greater than the number of fold angles of at least one other sub-side of the black matrix (e.g., sub-side I and sub-side III).

[0108] In an exemplary embodiment, as shown in FIG. 12, in the third direction (i.e., perpendicularly away from the base), the first sub-side 1041 has a first thickness l4 of 0.9 μm. <l4<1.2μmである。

[0109] In an exemplary embodiment, the color film structure layer 104 includes an annular black matrix 104a and a color film 104b located within an opening, i.e., the second opening, of the black matrix 104a, as shown in Fig. 13. The orthogonal projection at the base of the color film 104b at least partially covers the orthogonal projection at the base of the first opening K1 of the pixel defining layer 103b.

[0110] 13, in an exemplary embodiment, the sub-pixel region includes a pixel definition layer 103b and a color film structure layer 104 disposed on the pixel definition layer 103b. The color film structure layer 104 includes a black matrix 104a and a color film 104b disposed separately. The black matrix 104a includes at least one first sub-side 1041. In the third direction, the color film 104b has a maximum thickness greater than the maximum thickness of the first sub-side 1041 of the black matrix 104a, and the color film 104b at least partially covers the first sub-side 1041 of the black matrix.

[0111] In an exemplary embodiment, as shown in Fig. 13, the edge of the black matrix 104a close to the color film 104b has a staircase structure. Illustratively, the staircase structure is a one-step staircase structure, i.e., includes only one staircase surface. Since the edge of the black matrix 104a close to the color film 104b forms a staircase structure, the color film 104b can be in close contact with the edge of the black matrix 104a close to the color film 104b.

[0112] In an exemplary embodiment, as shown in FIG. 14, the color film 104b may have a first sub-portion 10421 and a second sub-portion 10422. The first sub-portion 10421 is connected to the first sub-side edge 1041 of the black matrix. The orthogonal projection at the base of the second sub-portion 10422 covers the orthogonal projection at the base of the first sub-portion 10421. In other words, the second sub-portion 10422 may have a protruding structure in a plane parallel to the base with respect to the first sub-portion 10421. In this embodiment, the orthogonal projection at the base of the second sub-portion 10422 covers the orthogonal projection at the base of the first sub-portion 10421, thereby improving the purity of the emitted light of the display substrate.

[0113] In an exemplary embodiment, as shown in FIG. 15, the first signal line 1021 also has a fold structure, and the fold structure has a fold angle. In any sub-pixel region, the number of fold angles of the first signal line 1021 is less than the number of fold angles of the first sub-side edge of the black matrix. Exemplarily, the number of fold angles of the first signal line 1021 is less than the number of fold angles of the first sub-side edge (or the second sub-side edge) of the black matrix and is greater than the number of fold angles of the third sub-side edge (or the fourth sub-side edge), which is conducive to process realization.

[0114] In an exemplary embodiment, the color film 104 b covers the fold structure of the first signal line 1021 .

[0115] In an exemplary embodiment, as shown in Fig. 15, the orthogonal projection at the base of the first signal line 1021 and the orthogonal projection at the base of the first sub-side edge 1041 of the black matrix 104a have a first overlapping portion 202, and the first overlapping portion 202 is covered by the color film 104b. The first signal line 1021 is made of metal and has high reflectivity, and has the first overlapping portion 202, and the width l3 of the first overlapping portion is small, so that the sub-color film can cover the first signal line 1021, as shown in Fig. 14, which contributes to reducing reflection and improving the purity of the emitted light.

[0116] In an exemplary embodiment, the first signal line 1021 has a fold line structure, the black matrix has multiple sub-sides (sub-side I, sub-side II, sub-side III and sub-side IV), and the number of fold angles in any sub-pixel region of the first signal line 1021 is smaller than the number of fold angles of at least one sub-side of the black matrix (e.g., sub-side II or sub-side IV) and larger than the number of fold angles of at least one other sub-side of the black matrix (e.g., sub-side I or sub-side III).

[0117] In an exemplary embodiment, as shown in Fig. 16, the first sub-side edge 1041 of the black matrix 104a has a plurality of third sub-segments, which are neither parallel nor perpendicular to the first direction and the second direction, and which are separately disposed and separated from each other by other sub-segments parallel to the first direction or parallel to the second direction.

[0118] 16, the first sub-side edge 1041 of the black matrix 104a has four third sub-segments 10411-10414. The four third sub-segments 10411-10414 are neither parallel nor perpendicular to the first direction and the second direction. The four third sub-segments 10411-10414 are disposed separately from each other, and the four third sub-segments 10411-10414 are separated by other sub-segments parallel to the second direction.

[0119] In an exemplary embodiment, as shown in Fig. 17, the black matrix 104a has a second sub-side 1042 disposed opposite the first sub-side 1041. As shown in Fig. 17, the sub-pixel 10' has another side, i.e., a second side II disposed opposite the fourth side IV, and the black matrix has the second sub-side 1042.

[0120] In FIG. 17, the first reference line B and the fifth reference line B' may be disposed at a distance k from the center line A. The sub-pixel region may further include the second reference line C, the third reference line D, the fourth reference line E, the sixth reference line C', the seventh reference line D', and the eighth reference line E'. The fifth reference line B', the sixth reference line C', the seventh reference line D', and the eighth reference line E' are symmetrical with respect to the center line A of the first reference line B, the second reference line C, the third reference line D, and the fourth reference line E, respectively. That is, the center line A and the fifth reference line B' have a distance of k in the same manner, and the distances of the fifth reference line B' to the sixth reference line C', the sixth reference line C' to the seventh reference line D', and the seventh reference line D' to the eighth reference line E' are also n. The second sub-side edge 1042 of the black matrix 104a also has a folding line structure, and the folding line structure has a folding angle.

[0121] In an exemplary embodiment, the number x' of fold angles between the center line A and the fifth reference line B', the number y' of fold angles between the fifth reference line B' and the sixth reference line C', and the number z' of fold angles between the sixth reference line C' and the seventh reference line D' satisfy the conditions x=x', y≠y', and z≠z'.

[0122] Since x is relatively small, x' is also relatively small, which means that the number of fold angles of the fold line structure close to the sub-pixel center line A is small. y ≠ y', z ≠ z' means that the first sub-side edge 1041 and the second sub-side edge 1042 are not symmetrically arranged, which can achieve a better display effect, that is, a less interference and diffraction structure can be achieved.

[0123] In an exemplary embodiment, within one subpixel region, the number x' of fold angles between the center line A and the fifth reference line B', the number y' of fold angles between the fifth reference line B' and the sixth reference line C', and the number z' of fold angles between the sixth reference line C' and the seventh reference line D' of the second sub-side edge 1042 satisfy the condition x'≦y'≦z'.

[0124] In an exemplary embodiment, the number of fold angles between the center line A and the fifth reference line B' of the second sub-side edge 1042 is two or more, the number of fold angles between the fifth reference line B' and the sixth reference line C' of the second sub-side edge 1042 is three or more, and the number of fold angles between the sixth reference line C' and the seventh reference line D' of the second sub-side edge 1042 is three or more.

[0125] 18, the number x' of the folding angles included in the second sub-side edge 1042 within a range where the vertical distance from the center line A is k or less (i.e., between the center line A and the fifth reference line B') is x'=2. The number y' of the folding angles included in the second sub-side edge 1042 within a range where the vertical distance from the center line A is k to (k+(L / 2-k) / 3) (i.e., between the fifth reference line B' and the sixth reference line C') is y'=3. The number z' of the folding angles included in the second sub-side edge 1042 within a range where the vertical distance from the center line A is (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3) (i.e., between the sixth reference line C' and the seventh reference line D') is z'=6.

[0126] In an exemplary embodiment, at least two fold angles between the center line A and the fifth reference line B' of the second sub-side edge 1042 are approximately equal, at least two fold angles between the fifth reference line B' and the sixth reference line C' of the second sub-side edge 1042 are approximately equal, and at least two fold angles between the sixth reference line C' and the seventh reference line D' of the second sub-side edge 1042 are approximately equal.

[0127] For example, the second sub-side edge 1042 has two folding angles x2' and x3' between the center line A and the fifth reference line B', where x2' and x3' are approximately equal. The second sub-side edge 1042 has three folding angles y1', y2', and y3' between the fifth reference line B' and the sixth reference line C', where y2' and y3' are approximately equal. The second sub-side edge 1042 has six folding angles z1', z2', z3', z4', z5', and z6' between the sixth reference line C' and the seventh reference line D', where z3' and z4' are approximately equal.

[0128] In the exemplary embodiment, the second sub-side edge 1042 has at least one fourth fold angle between the center line A and the fifth reference line B', the second sub-side edge 1042 has at least one fifth fold angle between the fifth reference line B' and the sixth reference line C', and the second sub-side edge 1042 has at least one sixth fold angle between the sixth reference line C' and the seventh reference line D', and the angles of the fourth fold angle, the fifth fold angle, and the sixth fold angle are approximately equal.

[0129] For example, the fold angle x2' between the center line A and the fifth reference line B', the fold angle y2' between the fifth reference line B' and the sixth reference line C', and the fold angle z3' between the sixth reference line C' and the seventh reference line D' of the second sub-side edge 1042 satisfy x2', y2', and z3' being approximately equal.

[0130] In an exemplary embodiment, as shown in Figure 19, the black matrix 104a includes a third sub-side and a fourth sub-side. The third sub-side connects the first sub-side and the second sub-side, and the fourth sub-side connects the first sub-side and the second sub-side. The first sub-side, the third sub-side, the fourth sub-side and the second sub-side are connected end-to-end to form a second opening.

[0131] In an exemplary embodiment, as shown in FIG. 19, the third sub-side is parallel to the first direction, and the fourth sub-side is parallel to the first direction.

[0132] In an exemplary embodiment, as shown in FIG. 19, one pixel unit on a display substrate may include a first sub-pixel 301, a second sub-pixel 302, and a third sub-pixel 303. The sides of the black matrices of any two adjacent sub-pixels are different, so that a better display effect can be achieved, that is, less interference and diffraction structure can be achieved. Exemplarily, the first sub-pixel 301, the second sub-pixel 302, and the third sub-pixel 303 may be a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, and the present disclosure is not limited thereto.

[0133] In another exemplary embodiment, as shown in Fig. 20, one pixel unit on the display substrate may include a first sub-pixel 301, a second sub-pixel 302, a third sub-pixel 303 and a fourth sub-pixel 304. In this case, the sub-sides of the black matrix in each sub-pixel may be different, thereby achieving a better display effect, that is, less interference and diffraction structure.

[0134] In an exemplary embodiment, the pixel arrangement may be such that two sub-pixels are arranged along a first direction and the other two sub-pixels are arranged along a second direction, as in the layout of Figure 20. Of course, the sub-pixels may be arranged according to other pixel structures.

[0135] Exemplarily, the first sub-pixel 301, the second sub-pixel 302, the third sub-pixel 303 and the fourth sub-pixel 304 may be a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel and a white (W) sub-pixel, and the present disclosure is not limited thereto.

[0136] In an exemplary embodiment, the number of fold angles of the first sub-side of the black matrix in the green (G) sub-pixel is less than the number of fold angles of the first sub-side of the black matrix in the blue (B) sub-pixel.

[0137] In an exemplary embodiment, the areas of the second openings of the black matrix of different sub-pixels may be different. The areas of the second openings of the black matrix of each sub-pixel may be set according to the demand for brightness. Exemplarily, the area of ​​the second openings of the green (G) sub-pixels is the smallest, and the area of ​​the second openings of the white (W) sub-pixels is the largest.

[0138] In an exemplary embodiment, when the subpixels include a red (R) subpixel, a green (G) subpixel, a blue (B) subpixel and a white (W) subpixel, the white (W) subpixel may be without a color film.

[0139] Exemplarily, as shown in FIG. 21, the green (G), red (R) and blue (B) sub-pixels all include a color film, and the white (W) sub-pixel may not have a color film.

[0140] In an exemplary embodiment, as shown in Fig. 22, the display substrate may further include an encapsulation layer 105 disposed on the side of the color film structure layer away from the light emitting structure layer 103. The encapsulation layer 105 may include a first encapsulation layer and a second encapsulation layer disposed in a stacked manner. The first encapsulation layer may adopt an organic material, and the second encapsulation layer may adopt an inorganic material, which can prevent external water vapor from entering the light emitting structure layer and the color film structure layer.

[0141] Since the white (W) sub-pixel does not need a color film, the first encapsulation layer can cover and fill the white (W) sub-pixel, that is, the filling structure and the first encapsulation layer in the white (W) sub-pixel are made of the same material and are an integrated structure.

[0142] In an exemplary embodiment, as shown in Figure 23, the display substrate may further include a blank structure 305. The orthogonal projection at the base of the blank structure 305 and the orthogonal projection at the base of the driving circuit do not overlap, which contributes to improving the transmittance.

[0143] In an exemplary embodiment, the area of ​​the display area occupied by the blank structures may be 45% or more. Illustratively, the area of ​​the display area occupied by the blank structures may be 46%.

[0144] In an exemplary embodiment, the blank structure has a width l5 in the first direction, where the width refers to the distance between two sides substantially parallel to the second direction, where the width l5 may be equal to or approximately equal to the total length of each folding line structure of the sub-side 1041 of the black matrix in the first direction, so that the blank structure 305 can be uniformly disposed on the display substrate to achieve a better display effect.

[0145] In an exemplary embodiment, the blank structure has a first sub-edge adjacent to the first sub-side of the white subpixel region and the first sub-side of the red subpixel region, and the shape of the first sub-edge and the shape of the first sub-side of the white subpixel region and the first sub-side of the red subpixel region are conformal. In the embodiments of the present disclosure, A and B are "conformal" means that the shapes of the adjacent edges of A and B are perfectly matched, or A and B share a side as an edge between A and B.

[0146] In an exemplary embodiment, the blank structure 305 is not necessarily rectangular, but may be an area between two sub-sides of the black matrix 104a along the first direction, that is, the side of the blank structure 305 also has a folding line structure and a folding angle, which can further eliminate the regular wiring, reduce the diffraction and interference effects, and improve the display effect.

[0147] In an exemplary embodiment, as shown in Fig. 24, the sub-pixel may include a first power line VDD, and the first power line VDD continues to provide a high potential voltage. Referring to Fig. 15, the first signal line 1021 may be the first power line VDD. In this embodiment, the color film between the black matrix completely covers the first power line VDD to reduce the reflectance and improve the purity of the emitted light.

[0148] In an exemplary embodiment, as shown in Fig. 24, the sub-pixel may include a second power line VSS, and the second power line VSS continues to provide a low potential voltage. Referring to Fig. 15, the first signal line 1021 may be the second power line VSS. In this embodiment, the color film between the black matrix completely covers the first power line VDD to reduce the reflectance and improve the purity of the emitted light.

[0149] In an exemplary embodiment, as shown in Figure 24, a sub-pixel may include a repair structure 401. The repair structure 401 may be electrically connected to multiple pixel electrodes.

[0150] In an exemplary embodiment, one repair structure 401 may be electrically connected to the first electrodes of two sub-pixels. Here, the light-emitting layer may be an electroluminescent layer including a first electrode and a second electrode. Illustratively, the first electrode is an anode, and the second electrode is a cathode. The anodes of adjacent sub-pixels may be separate block structures, and the cathodes of adjacent sub-pixels may be a whole surface structure.

[0151] In an exemplary embodiment, the plurality of subpixel regions includes a red subpixel region and a blue subpixel region, and the repair structures of the red subpixel region and the repair structures of the blue subpixel region are at least partially symmetrical and at least partially asymmetrical.

[0152] In an exemplary embodiment, the orthogonal projection at the base of the color film may cover the orthogonal projection at the base of the corresponding driving circuit layer, which can further reduce the reflection, increase the efficiency of the emitted light, and improve the display effect.

[0153] In an exemplary embodiment, the light-emitting structure further includes an anode, the first opening at least partially exposes the anode, and the at least one sub-pixel region includes a plurality of sub-anode blocks disposed separately.

[0154] In an exemplary embodiment, as shown in Figure 25, the anode of the display substrate includes at least two sub-anode blocks that are separately placed, i.e., the anode is a discrete structure, and the edge of at least one of the sub-anodes may include a fold structure, which can reduce the diffraction effect and improve the display effect.

[0155] In an exemplary embodiment, as shown in FIG. 25, taking any two adjacent sub-pixels 301 and 302 as an example, each sub-pixel may include at least two sub-anodes disposed separately. Exemplarily, the sub-pixel 301 includes a first sub-anode block 5011 and a second sub-anode block 5012 separated from each other, and the first sub-anode block 5011 and the second sub-anode block 5012 both have a folded structure to enhance the display effect. The sub-pixel 302 includes a third sub-anode block 5021 and a fourth sub-anode block 5022 separated from each other, and the third sub-anode block 5011 and the fourth sub-anode block 5012 both have a folded structure to enhance the display effect.

[0156] In an exemplary embodiment, the shapes of the sub-anode blocks are different. In this embodiment, the different shapes of the sub-anode blocks refer to the shapes of the orthogonal projections of the sub-anode blocks on the base being different, or the shapes of the orthogonal projections of the sub-anode blocks on the base being the same but the overlapping directions being different.

[0157] For example, as shown in FIG. 25, the shape of the orthogonal projection at the base of the first sub-anode block 5011 may be different from the shape of the orthogonal projection at the base of the second sub-anode block 5012.

[0158] In an exemplary embodiment, the shapes of the orthogonal projections at the bases of the sub-anode blocks in adjacent sub-pixels may be different. Illustratively, as shown in FIG. 25, the shapes of the orthogonal projections at the bases of multiple sub-anode blocks 5011, 5012, 5021, and 5022 are all different. The different shapes of the orthogonal projections in the embodiments of the present disclosure refer to the fact that the orthogonal projection at the base of one sub-anode block cannot overlap with the orthogonal projection at the base of another sub-anode block after translation.

[0159] In an exemplary embodiment, a plurality of sub-anode blocks in the same sub-pixel are respectively connected to a connecting structure. Exemplarily, as shown in FIG. 25, a first sub-anode block 5011 and a second sub-anode block 5012 are respectively electrically connected to a first connecting structure 601. A third sub-anode block 5021 and a fourth sub-anode block 5022 are respectively electrically connected to a second connecting structure 602.

[0160] 26, the first connection structure 601 may include a first connection electrode CE1 extending in the first direction from a first end of the first sub-anode block 5011, a second connection electrode CE2 extending in the first direction from a first end of the second sub-anode block 5012, a third connection electrode CE3 electrically connected to a driving transistor (which may be, for example, the second transistor T2 in FIG. 8) and extending in the first direction, and a fourth connection electrode CE4 having a first end contacting the first connection electrode CE1 and a second end contacting the second connection electrode CE2, and the fourth connection electrode CE4 and the third connection electrode CE3 are in contact between the first end and the second end. In this case, the fourth connection electrode CE4 is disposed in a layer different from at least one of the first connection electrodes CE1 to the third connection electrode CE3, and is in contact with the first connection electrode CE1 to the third connection electrode CE3.

[0161] The first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 are spaced apart from each other and arranged in parallel. The first connection electrode CE1 and the first sub-anode block 5011 may be integrally formed, and the second connection electrode CE2 and the second sub-anode block 5012 may be integrally formed. The third connection electrode CE3 is spaced apart from the first sub-anode block 5011 and the second sub-anode block 5012, and is arranged between the first sub-anode block 5011 and the second sub-anode block 5012.

[0162] The third connection electrode CE3 may be manufactured from the same material as that constituting at least one of the first sub-anode block 5011, the second sub-anode block 5012, the first connection electrode CE1, and the second connection electrode CE2. Alternatively, the third connection electrode CE3 may be disposed in the same layer as at least one of the first sub-anode block 5011, the second sub-anode block 5012, the first connection electrode CE1, and the second connection electrode CE2. The third connection electrode CE3 connected to the driving transistor may be electrically connected to the first connection electrode CE1 and the second connection electrode CE2, and may drive the first sub-light-emitting unit corresponding to the first sub-anode block 5011 and the second sub-light-emitting unit corresponding to the second sub-anode block 5012 by one driving transistor.

[0163] The connection electrode CE4 may be arranged along a second direction different from or perpendicular to the first direction in which the first connection electrode CE1 to the third connection electrode CE3 are arranged, and the connection electrode CE4 electrically connects the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 to each other. The fourth connection electrode CE4 is arranged in a layer different from at least one of the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3. The fourth connection electrode CE4 connects the first connection electrode CE1 and the third connection electrode CE3 by a bridge, or connects the second connection electrode CE2 and the third connection electrode CE3 by a bridge.

[0164] The fourth connection electrode CE4 may be disposed in the same layer as the active layer constituting the driving thin film transistor. The first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 contact the fourth connection electrode CE4 by passing through vias in an insulating layer disposed in the fourth connection electrode CE4. The fourth connection electrode CE4 may be manufactured from the same material as the material of the active layer constituting the driving thin film transistor.

[0165] Referring to Fig. 8, a driving transistor and at least two switch transistors may be required to drive a sub-pixel. The gate electrode of one switch transistor (first transistor T1 in Fig. 8) is connected to a first scan signal line Sn, thereby providing a signal of a data signal line Dn connected to the source electrode / drain electrode of the switch transistor to the gate electrode of a driving transistor (second transistor T2 in Fig. 8).

[0166] In response to a signal at the gate electrode, the driving transistor applies a voltage VDD of the source electrode / drain electrode connected to one side of the driving transistor to the first sub-anode block 5011 and the second sub-anode block 5012. In this case, the first connection structure 601 electrically connects between the source electrode / drain electrode at the other side of the driving transistor and the first sub-anode block 5011 and the second sub-anode block 5012, and the first connection structure 601 applies the voltage or current of the source electrode / drain electrode at the other side of the driving transistor to the first sub-anode block 5011 and the second sub-anode block 5012. Another switch transistor (the third transistor T3 in FIG. 8) is connected to the source electrode / drain electrode at the other side of the driving transistor, the gate electrode of the switch transistor is connected to the second scanning signal line Sn, and the reference voltage VRef is connected to the side of the source electrode / drain electrode of the switch transistor.

[0167] If a black spot or a bright spot appears in any of the subpixels of the display panel, a portion of the fourth connection electrode CE4 of the first connection structure 601 is cut by laser, so that the first sub-anode block 5011 or the second sub-anode block 5012 from one sub-pixel can be electrically connected to the driving transistor.

[0168] For example, the fourth connection electrode CE4 between the second connection electrode CE2 and the third connection electrode CE3 may be laser cut, so that the second sub-anode block 5012 connected to the second connection electrode CE2 is electrically disconnected from the driving transistor, and the second light-emitting unit corresponding to the second sub-anode block 5012 turns into a floating state. In this case, the first sub-anode block 5011 can be electrically connected to the driving transistor by the third connection electrode CE3, so that the first sub-anode block 5011 can be driven. The third connection electrode CE3 is electrically connected to the driving transistor by the first connection electrode CE1 and the fourth connection electrode CE4.

[0169] That is, even if a black spot or a bright spot appears in one sub-pixel, the fourth connection electrode CE4 can be laser cut to make one sub-light-emitting unit floating, so that the sub-pixel can be driven normally.

[0170] Although it has been shown that the target of laser cutting is the fourth connection electrode CE4 between the second connection electrode CE2 and the third connection electrode CE3, the target of laser cutting may also be the fourth connection electrode CE4 between the first connection electrode CE1 and the third connection electrode CE3.

[0171] If a black spot or a bright spot appears in the area of ​​the first sub-light-emitting unit corresponding to the first sub-anode block 5011, the fourth connection electrode CE4 between the first connection electrode CE1 and the third connection electrode CE3 may be laser-cut, so that the first sub-anode block 5011 connected to the first connection electrode CE1 is electrically disconnected from the driving transistor, and the first sub-light-emitting unit corresponding to the first sub-anode block 5011 turns into a floating state. In this case, the second sub-anode block 5012 can be electrically connected to the driving transistor by the third connection electrode CE3, so that the second sub-anode block 5012 can be driven. The third connection electrode CE3 is electrically connected to the driving transistor by the second connection electrode CE2 and the fourth connection electrode CE4.

[0172] Even if a black spot or a bright spot appears in one sub-pixel, the fourth connection electrode CE4 can be laser cut to drive the second sub-light-emitting unit, so that the sub-pixel can be driven normally.

[0173] If a black spot or a bright spot appears in one subpixel, the first connection electrode CE1 and the fourth connection electrode CE4 arranged in a layer different from the third connection electrode CE3 may be separated from each other between the first connection electrode CE1 and the third connection electrode CE3, and the second connection electrode CE2 and the fourth connection electrode CE4 arranged in a layer different from the third connection electrode CE3 may be separated from each other between the second connection electrode CE2 and the third connection electrode CE3.

[0174] If no dark or bright spot appears in one sub-pixel, the fourth connection electrode CE4 electrically connects the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 to each other, as described above.

[0175] In an exemplary embodiment, when a fault such as a disconnection occurs in a subpixel driving circuit corresponding to a subpixel, the repair structure and the connection structure can be electrically connected by ablation to electrically connect the subpixel and the adjacent subpixel driving circuit, thereby completing lighting. For example, when a fault such as a disconnection occurs in a subpixel driving circuit corresponding to a subpixel 301, the first repair structure 4011 and the first connection structure 601 can be electrically connected by ablation to electrically connect the subpixel 301 and the adjacent subpixel driving circuit, thereby completing lighting.

[0176] The manufacturing process of the display substrate will be described below by way of example. The "patterning process" described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal materials, inorganic materials, or transparent conductive materials, and organic material coating, mask exposure, and development for organic materials. The deposition may employ any one or more of sputtering, deposition coating, and chemical vapor deposition. The coating may employ any one or more of spray coating, spin coating, and inkjet printing. The etching may employ any one or more of dry etching and wet etching. This disclosure does not limit the same. A "thin film" refers to a layer of a thin film fabricated by deposition, coating, or other process on a base using a certain material. If the "thin film" does not require a patterning process in the entire manufacturing process, the "thin film" is also referred to as a "layer". If the "thin film" requires a patterning process in the entire manufacturing process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, "A and B are disposed in the same layer" refers to A and B being formed simultaneously by the same patterning process. The "thickness" of a film layer is the size of the film layer in a direction perpendicular to the display substrate. In an exemplary embodiment of the present disclosure, "the orthogonal projection of B is located within the range of the orthogonal projection of A" refers to the boundary of the orthogonal projection of B being within the range of the boundary of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlapping the boundary of the orthogonal projection of B.

[0177] In an exemplary embodiment, the manufacturing process of the display substrate may include the following operations.

[0178] (1) First, a driving circuit layer 102 pattern is manufactured on a base 101. The driving circuit layer 102 includes a plurality of gate lines and a plurality of data signal lines. The gate lines and the data signal lines cross each other to form a plurality of pixel units arranged in a matrix. Each pixel unit includes at least three sub-pixels, and each sub-pixel includes a thin film transistor (TFT). In this embodiment, one pixel unit includes three sub-pixels, which are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, respectively. Of course, the solution of this embodiment is also applicable to the case where one pixel unit includes four sub-pixels (a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W).

[0179] In an exemplary embodiment, the base 101 may be a flexible base or a rigid base. In an exemplary embodiment, the flexible base may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked. The materials of the first flexible material layer and the second flexible material layer may adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer adopt silicon nitride (SiNx) or silica (SiOx) etc. to improve the water-oxygen resistance ability of the base. The first inorganic material layer and the second inorganic material layer are also called barrier layers. The material of the semiconductor layer may adopt amorphous silicon (a-si). In an exemplary embodiment, taking a laminated structure as an example, its manufacturing process may include the following steps. First, a layer of polyimide is applied on a glass carrier plate, and then hardened and formed into a film to form a first flexible (PI1) layer. Then, one layer of a barrier thin film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer. Then, one layer of an amorphous silicon thin film is deposited on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer. Then, one layer of polyimide is further applied to the amorphous silicon layer, and after hardening and forming a film, a second flexible (PI2) layer is formed. Then, one layer of a barrier thin film is deposited on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer. This completes the manufacture of the base 101.

[0180] In an exemplary embodiment, the manufacturing process of the driving circuit layer 102 may include the following steps.

[0181] A first insulating thin film and an active layer thin film are sequentially deposited on the base 101, and the active layer thin film is patterned by a patterning process to form a first insulating layer covering the entire base 101 and an active layer pattern disposed on the first insulating layer, and the active layer pattern includes at least a first active layer.

[0182] Then, a second insulating thin film and a first metal thin film are sequentially deposited, and the first metal thin film is patterned by a patterning process to form a second insulating layer covering the active layer pattern, and a first gate metal layer pattern disposed on the second insulating layer, where the first gate metal layer pattern includes at least a first gate electrode, a first capacitor electrode, a plurality of gate lines and a plurality of gate leads.

[0183] Then, a third insulating thin film and a second metal thin film are sequentially deposited, and the second metal thin film is patterned by a patterning process to form a third insulating layer covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer, the second gate metal layer pattern including at least a second capacitor electrode and a second gate lead, and a position of the second capacitor electrode corresponds to a position of the first capacitor electrode.

[0184] Then, a fourth insulating thin film is deposited, and the fourth insulating thin film is patterned by a patterning process to form a fourth insulating layer pattern covering the second gate metal layer, a plurality of first vias are opened in the fourth insulating layer, the positions of the plurality of first vias respectively correspond to both ends of the first active layer, and the fourth insulating layer, the third insulating layer and the second insulating layer in the plurality of first vias are etched to respectively expose the surfaces of the first active layer.

[0185] Then, a third metal thin film is deposited, and the third metal thin film is patterned by a patterning process to form a source-drain metal layer pattern on the fourth insulating layer, the source-drain metal layer is formed in the display area, and includes at least a first source electrode, a first drain electrode, a low-voltage (VSS) line, a plurality of data signal lines and a plurality of data lead patterns, and the first source electrode and the first drain electrode are respectively connected to the first active layer through a first via. In an exemplary embodiment, according to actual needs, the source-drain metal layer may further include any one or more of a power supply line (VDD), a compensation line and an auxiliary cathode, and the source-drain metal layer is also referred to as a first source-drain metal layer (SD1).

[0186] Then, a fifth insulating thin film is deposited to form a fifth insulating layer pattern covering the source / drain metal layer.

[0187] A first planar thin film is applied to the base 101 on which the pattern is formed, forming a first planar (PLN) layer covering the entire base 101, and a second via is formed in the first planar layer by a patterning process, the second via is formed in the display area, and the first planar layer and the fifth insulating layer in the second via are etched to expose the surface of the first drain electrode of the first transistor 102a.

[0188] Up to now, the fabrication of the driving structure layer 102 pattern on the base 101 is completed. The first active layer, the first gate electrode, the first source electrode and the first drain electrode constitute a first transistor 102a, the first capacitor electrode and the second capacitor electrode constitute a first storage capacitor 102b, and the multiple gate leads and data leads constitute the driving leads of the array substrate gate driver (abbreviated as GOA). In an exemplary embodiment, the first transistor 102a may be a driving transistor in a pixel driving circuit, and the driving transistor may be a thin film transistor (abbreviated as TFT).

[0189] (2) Producing a light emitting structure layer 103 pattern on the patterned base 101. In an exemplary embodiment, the manufacturing process of the light emitting structure layer 103 may include the following steps.

[0190] A transparent conductive thin film is deposited on the base 101 on which the pattern is formed, and the transparent conductive thin film is patterned by a patterning process to form an anode 103a pattern. The anode 103a is formed in the display area and connected to the first drain electrode of the first transistor 102a through a second via.

[0191] A pixel defining thin film is applied to the base 101 on which the pattern is formed, and a pixel defining (PDL) layer 103b pattern is formed by a mask, exposure and development process, pixel openings are opened in the pixel defining layer 103b, and the pixel defining thin film in the pixel openings is developed to expose the surface of the anode 103a.

[0192] An organic material thin film is applied to the base on which the above pattern is formed, and a plurality of isolation column (PS) patterns are formed by a mask, exposure and development process.

[0193] On the base on which the above pattern is formed, an organic light emitting layer 103c and a cathode 103d are sequentially formed. The organic light emitting layer 103c may include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer and an electron injection layer, which are stacked, and is formed in the display area, and realizes the connection between the organic light emitting layer 103c and the anode 103a. The anode 103a is connected to the drain electrode of the first transistor 102a, thereby realizing the light emission control of the organic light emitting layer 103c. The cathode 103d is connected to the organic light emitting layer 103c.

[0194] (4) A second flat thin film is applied to the base 101 on which the above-mentioned pattern is formed, and a second flat layer pattern is formed on the light-emitting structure layer 103 by a mask, exposure and development process.

[0195] (5) Manufacturing a color film structure layer 104 pattern on the patterned base 101. In an exemplary embodiment, the manufacturing process of the color film structure layer 104 may include the following steps.

[0196] First, a polymer photoresist layer mixed with a black matrix material is coated on the second flat layer, and a pattern of the black matrix 104a is formed by exposure and development. Then, a polymer photoresist layer mixed with a red pigment is coated on the second flat layer, and a pattern of the red region is formed by exposure and development. Using the same method and steps, a pattern of the green region and a pattern of the blue region are formed in sequence, and finally, a color film pattern of the three primary colors of red, green, and blue arranged according to a certain rule is formed.

[0197] (4) As shown in Figures 27 and 28, an encapsulation layer 105 is formed on base 101 on which the pattern is formed. The encapsulation layer 105 is formed in the display area and adopts a laminated structure of organic material / inorganic material.

[0198] In an exemplary embodiment, when manufacturing a flexible display substrate, the manufacturing process of the display substrate may include processes such as peeling off a glass carrier plate, attaching a backing film, cutting, etc., and the present disclosure is not limited thereto.

[0199] As can be seen from the structure and manufacturing process of the display substrate according to the exemplary embodiment of the present disclosure, in the exemplary embodiment of the present disclosure, the black matrix has a folded line structure, thereby reducing the grating effect (e.g., diffraction effect, interference effect, scattering, color dispersion, etc.) and improving the display effect. The use of the black matrix and the color film reduces the reflectance and increases the purity of the emitted light. The elimination of the need for a polarizer reduces the cost, reduces the thickness of the display panel, and increases the bendability of the display panel. The manufacturing method of the display substrate according to the exemplary embodiment of the present disclosure has good process compatibility, is simple to realize the process, is easy to implement, has high production efficiency, low production cost, and high yield rate.

[0200] The structures and manufacturing processes according to the exemplary embodiments of the present disclosure are merely exemplary. In the exemplary embodiments, the corresponding structures can be changed or the patterning process can be increased or decreased according to actual needs. For example, the transistors in the driving circuit layer can be a top gate structure or a bottom gate structure, a single gate structure or a double gate structure. For example, the driving circuit layer and the light emitting structure layer can be provided with other film layer structures, electrode structures or lead structures. For example, the base can be a glass base, and the present disclosure is not specifically limited thereto.

[0201] The present disclosure further provides a method for manufacturing a display substrate. In an exemplary embodiment, the method includes: forming a drive circuit layer on a base; forming a light-emitting structure layer on a side of the driving circuit layer away from a base, the light-emitting structure layer including a pixel definition layer and an organic light-emitting layer, the pixel definition layer defining a plurality of sub-pixel regions and having a first opening at least partially exposing the driving circuit layer, the organic light-emitting layer being located in the sub-pixel regions and overlapping the first opening of the pixel definition layer; forming a color film structure layer on a side of the light-emitting structure layer away from the base, the color film structure layer including a color film and a black matrix, the black matrix having a second opening at least partially exposing the first opening, the color film being disposed in the second opening, the black matrix including a first sub-side edge, and the first sub-side edge having a fold line structure.

[0202] The following points need to be explained:

[0203] The drawings of the embodiments of the present disclosure relate only to the structures of the embodiments of the present disclosure, and other structures may refer to general designs.

[0204] Where there are no conflicts, the embodiments and features of the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0205] The above are the embodiments disclosed in the present disclosure, but the above contents are the embodiments used to facilitate understanding of the present disclosure, and are not intended to limit the present disclosure. Those skilled in the art can make any modifications and changes to the embodiments and details without departing from the spirit and scope disclosed in the present disclosure, but the scope of protection of the patent of the present disclosure is subject to the scope of the attached claims.

Claims

1. A display substrate, comprising a base, a driving circuit layer disposed on the base, a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, and a color filter structure layer disposed on a side of the light-emitting structure layer away from the base, wherein the light-emitting structure layer includes a pixel definition layer and an organic light-emitting layer, the pixel definition layer defines a plurality of sub-pixel regions and has a first opening that at least partially exposes the driving circuit layer, the organic light-emitting layer is located in the sub-pixel regions and overlaps with the first opening of the pixel definition layer, the color filter structure layer includes a color filter and a black matrix, the black matrix has a second opening that at least partially exposes the first opening, the color filter is disposed in the second opening, the black matrix includes a first sub-side, and the first sub-side has a folded line structure, the display substrate.

2. The display substrate according to claim 1, wherein the first sub-side has a plurality of folding angles, and the farther the region is from the center line of the sub-pixel region, the greater the number of folding angles of the first sub-side.

3. The sub-pixel region sequentially includes a center line, a first reference line, a second reference line, a third reference line, and a fourth reference line along a first direction, and the fourth reference line overlaps with the farthest boundary on a side of the first sub-side away from the center line, the distance between the first reference line and the center line of the sub-pixel region is k, the distance between the first reference line and the second reference line is n1, the distance between the second reference line and the third reference line is n2, the distance between the third reference line and the fourth reference line is n3, and k + n1 + n2 + n3 = L / 2, where L is the length of the sub-pixel region along the first direction, the number of folding angles x between the center line and the first reference line of the first sub-side, the number of folding angles y between the first reference line and the second reference line of the first sub-side, and the number of folding angles z between the second reference line and the third reference line of the first sub-side satisfy the condition of x ≤ y ≤ z, the display substrate according to claim 1.

4. The display substrate according to claim 3, wherein the number of folding angles x between the center line and the first reference line of the first sub-side is x ≥ 3, the number of folding angles y between the first reference line and the second reference line of the first sub-side is y ≥ 3, and the number of folding angles z between the second reference line and the third reference line of the first sub-side is z ≥ 3.

5. The first sub-side has a first width along a first direction, the driving circuit layer includes at least one first signal line, the first signal line has a second width along the first direction, a positive projection of the first signal line at a base and a positive projection of the first sub-side at a base have a first overlapping portion, and the first overlapping portion has a third width along the first direction. The display substrate according to claim 1.

6. The first width is l1, the second width is l2, the sub-pixel region includes a center line and a first reference line along the first direction, a distance between the first reference line and the center line of the sub-pixel region is k, a length of the sub-pixel region along the first direction is L, and in this case, 10 * l1 ≤ L ≤ 10 * l2 and 2 * k < L ≤ 3 * k. The display substrate according to claim 5.

7. The black matrix has a second thickness l4 in a third direction, the second thickness is 0.9 micron to 1.2 microns, and the third direction is a direction from the base substrate toward the color filter structure layer. The display substrate according to claim 1.

8. The first sub-side includes a third sub-line segment that is neither parallel nor perpendicular to the first direction and the second direction, and the black matrix includes a plurality of the third sub-line segments. The display substrate according to claim 1.

9. The black matrix further includes a second sub-side that is installed opposite to the first sub-side, and the second sub-side has a folded line structure, and the first sub-side and the second sub-side are installed asymmetrically with respect to the center line of the sub-pixel region. The display substrate according to claim 1.

10. The sub-pixel region includes a first sub-pixel region, a second sub-pixel region, a third sub-pixel region, and a fourth sub-pixel region. The first sub-pixel region includes a first light-emitting unit and a color filter of a first color. The second sub-pixel region includes a second light-emitting unit and a color filter of a second color. The third sub-pixel region includes a third light-emitting unit and a color filter of a third color. The fourth sub-pixel region includes a fourth light-emitting unit and a color filter of a fourth color. A front projection of the color filter of the first color on a base covers a front projection of the first light-emitting unit on the base. A front projection of the color filter of the second color on a base covers a front projection of the second light-emitting unit on the base. A front projection of the color filter of the third color on a base covers a front projection of the third light-emitting unit on the base. A front projection of the color filter of the fourth color on a base covers a front projection of the fourth light-emitting unit on the base. The display substrate according to claim 1.

11. The display substrate further includes a blank structure, and a front projection of the blank structure on a base does not overlap with a front projection of the sub-pixel region on the base. The display substrate according to claim 1.

12. A ratio of an area of the blank structure to an area of the sub-pixel region is 45% or more. The display substrate according to claim 11.

13. The plurality of sub-pixel regions include a white sub-pixel region and a red sub-pixel region. The blank structure has a first sub-edge adjacent to a first sub-side of the white sub-pixel region and a first sub-side of the red sub-pixel region. Shapes of the first sub-edge, the first sub-side of the white sub-pixel region, and the first sub-side of the red sub-pixel region are equiangular. The display substrate according to claim 11.

14. The light-emitting structure further includes an anode. The first opening at least partially exposes the anode. At least one sub-pixel region includes a plurality of sub-anode blocks installed individually. The display substrate according to claim 1.

15. A display device including the display substrate according to any one of claims 1 to 14.

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