Packages containing shielded block devices

Abstract

A package including a substrate, a first integrated device coupled to the substrate, a first block device coupled to the substrate, and a second encapsulation layer encapsulating the first integrated device and the first block device, the first block device including a first electrical component, a second electrical component, a first encapsulation layer at least partially encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of nonprovisional patent application Ser. No. 17 / 383,241, filed in the United States Patent Office on July 22, 2021, the entire contents of which are incorporated by reference herein for all applicable purposes as if fully set forth below.

[0002] Various features relate to a package having an integrated device. [Background technology]

[0003] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various electrical functions. Electromagnetic interference (EMI) can affect the overall performance of the components and the package. There is a continuing need to provide better performing packages and reduce the effects of EMI in and around the package. Summary of the Invention [Means for solving the problem]

[0004] Various features relate to a package having an integrated device.

[0005] One example provides a package including a substrate, a first integrated device coupled to the substrate, a first block device coupled to the substrate, and a second encapsulation layer at least partially encapsulating the first integrated device and the first block device, the first block device including a first electrical component, a second electrical component, the first encapsulation layer encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer.

[0006] Another example provides an apparatus including a substrate, a first integrated device coupled to the substrate, a first block device coupled to the substrate, and a second encapsulation means configured to at least partially encapsulate the first integrated device and the first block device, the first block device including a first electrical component, a second electrical component, the first encapsulation means configured to encapsulate the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation means.

[0007] Another example provides a method for making a package. The method includes providing a substrate. The method includes coupling a first integrated device to the substrate. The method includes coupling a first block device to the substrate. The first block device includes a first electrical component, a second electrical component, a first encapsulation layer encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer. The method includes forming a second encapsulation layer at least partially encapsulating the first integrated device and the first block device.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a cross-sectional profile view of a package including at least one block device having a shield. [Diagram 2] FIG. 2 is a cross-sectional plan view of a package including at least one block device having a shield. [Diagram 3] FIG. 13 is a cross-sectional profile of a block device having a shield. [Figure 4] FIG. 13 is another cross-sectional profile view of a block device having a shield. [Diagram 5]FIG. 13 is a bottom view of a block device with a shield. [Figure 6] FIG. 2 is a top view of a block device having a shield. [Figure 7] FIG. 1 is a cross-sectional profile of a block device having a shield and a block substrate. [Figure 8] FIG. 13 is another cross-sectional profile view of a block device having a shield and a block substrate. [Figure 9] FIG. 13 is a bottom view of a block device having a shield and a block substrate. [Figure 10] FIG. 2 is a top view of a block device having a shield and a block substrate. [Figure 11] FIG. 13 is a cross-sectional profile of a block device having a shield. [Figure 12] FIG. 13 is another cross-sectional profile view of a block device having a shield. [Figure 13] FIG. 13 is a bottom view of a block device with a shield. [Figure 14] FIG. 2 is a top view of a block device having a shield. [Figure 15A] 1A-1C illustrate an exemplary sequence for creating a package including at least one block device and a shield. [Figure 15B] 1A-1C illustrate an exemplary sequence for creating a package including at least one block device and a shield. [Figure 16] 1A-1C illustrate an exemplary sequence for creating a package including at least one block device and a shield. [Figure 17A] 1A-1C illustrate an exemplary sequence for fabricating a block device having a shield. [Figure 17B] 1A-1C illustrate an exemplary sequence for fabricating a block device having a shield. [Figure 18A] 1A-1C illustrate an exemplary sequence for fabricating a block device, a block substrate, and a shield. [Figure 18B] 1A-1C illustrate an exemplary sequence for fabricating a block device, a block substrate, and a shield. [Figure 18C] 1A-1C illustrate an exemplary sequence for fabricating a block device, a block substrate, and a shield. [Figure 19] 1 illustrates an example flow diagram of a method for making a block device having a shield. [Figure 20A] 1A-1C illustrate an exemplary sequence for preparing a substrate. [Figure 20B] 1A-1C illustrate an exemplary sequence for preparing a substrate. [Figure 21] 1 is an exemplary flow diagram of a method for fabricating a substrate. [Figure 22] 1A-1C illustrate various electronic devices that may integrate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are given to enable a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a package including a substrate, a first integrated device coupled to the substrate, a first block device coupled to the substrate, and a second encapsulation layer at least partially encapsulating the first integrated device and the first block device. The first block device includes a first electrical component (e.g., a first electrical device), a second electrical component (e.g., a second electrical device), a first encapsulation layer encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer, the first metal layer configured as a shield (e.g., an electromagnetic interference (EMI) shield) for the first block device. Examples of electrical components (e.g., electrical devices) include passive components (e.g., capacitors) and / or integrated devices (e.g., semiconductor dies). Using a block device with a shield helps provide shielding for the block device and / or other components (e.g., the first integrated device) in the package. For example, a shield for the first block device may be configured as a shield for the first integrated device to help prevent current passing through the first block device from interfering with current passing through the first integrated device of the package and / or to help prevent current passing through the first integrated device of the package from interfering with current passing through the first block device. In addition, the package configuration may also help reduce the size and / or footprint of the package while still providing improved package performance.

[0012] Exemplary Package with Block Device and Shield 1 shows a cross-sectional profile view of a package 100 including at least one block device with electromagnetic interference (EMI) shielding. Package 100 includes a substrate 102, an integrated device 104, a block device 105, a block device 107, an encapsulation layer 108, and a metal layer 109. Block device 105 and / or block device 107 may be examples of shielded block devices.

[0013] The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder resist layer 126. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). A plurality of solder interconnects 130 may be coupled to the substrate 102. For example, the plurality of solder interconnects 130 may be coupled to the plurality of interconnects 122.

[0014] The integrated device 104 is coupled to the first surface of the substrate 102 via a plurality of solder interconnects 140. The block device 105 may be a first block device. The block device 105 is coupled to the first surface of the substrate 102 via a plurality of solder interconnects 151 and / or a plurality of solder interconnects 153. The block device 105 is coupled to the plurality of interconnects 122 via a plurality of solder interconnects 151 and / or a plurality of solder interconnects 153. The block device 107 may be a second block device. The block device 107 is coupled to the first surface of the substrate 102 via a plurality of solder interconnects 178. The block device 107 is coupled to the plurality of interconnects 122 via a plurality of solder interconnects 178.

[0015] The encapsulation layer 108 may be a second encapsulation layer. The encapsulation layer 108 may be disposed on and / or around the integrated device 104, the block device 105, the block device 107, and / or the substrate 102. The encapsulation layer 108 may at least partially encapsulate the integrated device 104, the block device 105, and the block device 107. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be an encapsulation means (e.g., a second encapsulation means). The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0016] Metal layer 109 may be a second metal layer. Metal layer 109 is disposed and coupled to an outer surface of encapsulation layer 108. For example, metal layer 109 may be disposed on a top and / or side of the outer surface of encapsulation layer 108. Metal layer 109 may be disposed on a side of substrate 102. Metal layer 109 may include one or more metal layers. As described further below, metal layer 109 may be coupled to a metal layer of block device 105 and / or a metal layer of block device 107. Metal layer 109 may be configured to be coupled to a ground. Metal layer 109 may be configured as an EMI shield (e.g., a means for EMI shielding) for package 100. For example, metal layer 109 may be configured as a conformal shield for package 100. Metal layer 109 may help prevent signals outside package 100 from interfering with currents and / or signals traveling inside package 100.

[0017] Block device 105 includes at least two electrical components (e.g., at least two electrical devices). Block device 107 includes at least two electrical components (e.g., at least two electrical devices). Examples of electrical components (e.g., electrical devices) include passive components (e.g., capacitors) and / or integrated devices (e.g., semiconductor dies).

[0018] Block device 105 includes passive component 150 (e.g., a first capacitor), passive component 152 (e.g., a second capacitor), encapsulation layer 154, and metal layer 156. Passive component 150 may be an example of a first electrical component. Passive component 152 may be an example of a second electrical component. Encapsulation layer 154 may encapsulate passive component 150 and passive component 152. Encapsulation layer 154 may be a first encapsulation layer. Encapsulation layer 154 may include a mold, a resin, and / or an epoxy. Encapsulation layer 154 may be an encapsulation means (e.g., a first encapsulation means).

[0019] The metal layer 156 may be coupled to the encapsulation layer 154. The metal layer 156 may be coupled to a side of the block device 105. The metal layer 156 may be a first metal layer. The metal layer 156 may be configured to be coupled to ground. The metal layer 156 may be configured as an EMI shield (e.g., a means for EMI shielding) for the block device 105. The metal layer 156 may be configured as an EMI shield for the package 100. The metal layer 156 may provide shielding for the passive components 150 and / or the passive components 152. The metal layer 156 may also provide shielding for the integrated device 104 (and / or any other components within the package 100). For example, the metal layer 156 may help prevent currents traveling through the passive components 150 and / or the passive components 152 from interfering with currents and / or signals traveling through the integrated device 104, and vice versa. The metal layer 156 may be configured as a compartment shield for the package 100. Metal layer 156 may help prevent signals outside of package 100 from interfering with currents and / or signals traveling inside block device 105. Metal layer 156 may be coupled to metal layer 109.

[0020] The block device 107 includes a block substrate 175, a passive component 170 (e.g., a first capacitor), an integrated device 172, an encapsulation layer 174, and a metal layer 176. The passive component 170 may be an example of a first electrical component. The integrated device 172 (e.g., a semiconductor die) may be an example of a second electrical component. The encapsulation layer 174 may encapsulate the passive component 170 and the integrated device 172. The encapsulation layer 174 may be a third encapsulation layer. The encapsulation layer 174 may include a mold, a resin, and / or an epoxy. The encapsulation layer 174 may be an encapsulation means (e.g., a third encapsulation means). The encapsulation layer 174 may be disposed on the block substrate 175, the passive component 170, and the integrated device 172.

[0021] The block substrate 175 includes at least one dielectric layer 177 and a plurality of interconnects 179 (e.g., block substrate interconnects). Different implementations may use different materials for the at least one dielectric layer 177. For example, the at least one dielectric layer 177 may include glass, quartz, and / or prepreg. The passive components 170 are coupled to the block substrate 175 via a plurality of solder interconnects 171. The integrated devices 172 are coupled to the block substrate 175 via a plurality of solder interconnects 173. The block substrate 175 may be configured to at least partially provide an EMI shield. That is, some of the interconnects of the plurality of interconnects 179 may be configured as an EMI shield. Some of the interconnects of the plurality of interconnects 179 may be configured to be coupled to ground. Some of the interconnects of the plurality of interconnects 179 may be coupled to a metal layer 176. The block device 107 is coupled to the plurality of interconnects 122 of the substrate 102 via a plurality of solder interconnects 178. The plurality of solder interconnects 178 may be coupled to a plurality of interconnects 179 of the block substrate 175.

[0022] The metal layer 176 may be coupled to the encapsulation layer 174. The metal layer 176 may be coupled to a side of the block device 107. The metal layer 176 may be coupled to some of the interconnects 179 of the block substrate 175. The metal layer 176 may be a first metal layer. The metal layer 176 may be configured to be coupled to ground. The metal layer 176 may be configured as an EMI shield (e.g., a means for EMI shielding) for the block device 107. The metal layer 176 may be configured as an EMI shield for the package 100. The metal layer 176 may provide shielding for the passive components 170 and / or the integrated device 172. The metal layer 176 may also provide shielding for the integrated device 104 (and / or any other components in the package 100). For example, metal layer 176 may help prevent currents traveling through passive components 170 and / or integrated device 172 from interfering with currents and / or signals traveling through integrated device 104, and vice versa. Metal layer 176 may be configured as a compartment shield for package 100. Metal layer 176 may help prevent signals outside package 100 from interfering with currents and / or signals traveling inside block device 107. Metal layer 176 may be coupled to metal layer 109.

[0023] 2 shows a cross-sectional plan view of the package 100. As shown in FIG. 2, the package 100 includes an integrated device 104, a block device 105, a block device 107, a passive component 270, a passive component 272, an encapsulation layer 108, and a metal layer 109. The integrated device 104, the block device 105, the block device 107, the passive component 270, and the passive component 272 are coupled to a substrate 102 (not shown in FIG. 2). The encapsulation layer 108 at least partially encapsulates the integrated device 104, the block device 105, the block device 107, the passive component 270, and the passive component 272. The encapsulation layer 108 may be disposed over the substrate 102, the integrated device 104, the block device 105, the block device 107, the passive component 270, and / or the passive component 272.

[0024] Block device 105 includes passive components 150, 152, 250, 252, encapsulation layer 154, and metal layer 156. Encapsulation layer 154 encapsulates passive components 150, 152, 250, and 252.

[0025] The block device 107 includes passive components 170 , an integrated device 172 , an encapsulation layer 174 , and a metal layer 176 .

[0026] Metal layer 156 laterally surrounds encapsulation layer 154, passive components 150, passive components 152, passive components 250, and passive components 252. Metal layer 156 may shield passive components 150, passive components 152, passive components 250, and passive components 252 from integrated device 104, block device 107, passive components 270, and / or passive components 272. Similarly, metal layer 156 may shield integrated device 104, block device 107, passive components 270, and / or passive components 272 from passive components 150, passive components 152, passive components 250, and passive components 252.

[0027] Metal layer 176 laterally surrounds encapsulation layer 174, passive components 170, and integrated device 172. Metal layer 176 may shield passive components 170 and integrated device 172 from integrated device 104, block device 105, passive components 270, and / or passive components 272. Similarly, metal layer 176 may shield integrated device 104, block device 105, passive components 270, and / or passive components 272 from passive components 170 and integrated device 172.

[0028] There are several advantages to the configuration of package 100. First, using block devices with EMI shielding helps improve the performance of the package by reducing and / or eliminating interference between components from package 100 and / or from components external to package 100. Second, using block devices with EMI shielding helps provide a more compact package since components within package 100 can be placed closer to each other within package 100 without necessarily adversely affecting the performance of package 100. Third, using block devices with predefined EMI shielding simplifies the fabrication process during assembly and fabrication of the package.

[0029] The EMI shield (e.g., metal layer 156, metal layer 176, metal layer 109) may be configured as a Faraday cage that provides electrical isolation between different circuit functions within the package. The use of pre-applied compartment shields on these block devices may provide excellent shielding without significantly altering the existing layout of the package. The EMI shield(s) may be a means for shielding (e.g., a means for EMI shielding).

[0030] It should be noted that package 100 may include a different number of block devices, such as one or more block devices. Also, each block device may have a different number of electrical components (e.g., electrical devices, passive components, integrated devices) that are shielded from other components and / or devices of the package. Thus, the configurations of package 100 shown in this disclosure are merely exemplary.

[0031] 3-6 show various views of block device 105. FIG. 3 shows a side view of block device 105 including passive components 150, passive components 152, encapsulation layer 154, and metal layer 156. A plurality of solder interconnects 151 are coupled to passive components 150. A plurality of solder interconnects 153 are coupled to passive components 152. In some implementations, a bottom of passive components 150 and / or a bottom of passive components 152 may be aligned with a bottom of encapsulation layer 154. For example, a bottom surface of passive components 150 and / or a bottom surface of passive components 152 may be aligned with a bottom surface of encapsulation layer 154. In some implementations, passive component 150 and / or passive component 152 may protrude from a bottom surface of encapsulation layer 154 such that a portion of a side of passive component 150 and / or a portion of a side of passive component 152 is not covered by encapsulation layer 154. FIG. 4 shows another side view of block device 105 including passive component 150, passive component 250, encapsulation layer 154, and metal layer 156.

[0032] 5 illustrates a bottom view of block device 105 including passive components 150, 152, 250, 252, encapsulation layer 154, and metal layer 156. A plurality of solder interconnects may be coupled to terminals of passive components 150, 152, 250, and / or 252. FIG. 6 illustrates a top view of block device 105 including metal layer 156. Metal layer 156 is disposed on a surface of encapsulation layer 154.

[0033] 7-10 show various views of block device 107. FIG. 7 shows a side view of block device 107 including passive components 170, integrated device 172, block substrate 175, encapsulation layer 174, and metal layer 176. A plurality of solder interconnects 178 are bonded to block substrate 175. Encapsulation layer 174 is disposed over block substrate 175, passive components 170, and integrated device 172. Metal layer 176 is disposed over a surface of encapsulation layer 174. Block substrate 175 includes at least one dielectric layer 177 and a plurality of interconnects 179. A plurality of solder interconnects 178 are bonded to some of the plurality of interconnects 179. FIG. 8 shows another side view of block device 107 including passive components 170, integrated device 172, block substrate 175, encapsulation layer 174, and metal layer 176.

[0034] 9 shows a bottom view of block device 107 including passive components 170, integrated device 172, block substrate 175 (including at least one dielectric layer 177 and multiple interconnects 179), encapsulation layer 174, and metal layer 176. Multiple solder interconnects may be coupled to some of the multiple interconnects 179. FIG. 10 shows a top view of block device 107 including metal layer 176. Metal layer 176 is disposed on a surface of encapsulation layer 174.

[0035] In some implementations, the block device 107 may be implemented without the block substrate 175. In some implementations, the block device 105 may be implemented with the block substrate 175 as described for the block device 107.

[0036] 11-14 show various views of a block device 1107. The block device 1107 may be implemented in any package (e.g., 100). The block device 1107 may be similar to the block device 107. However, the block device 1107 does not include a block substrate 175. FIG. 11 shows a side view of the block device 1107 including a passive component 170, an integrated device 172, an encapsulation layer 174, and a metal layer 176. A plurality of solder interconnects 171 are coupled to the passive component 170. A plurality of solder interconnects 173 are coupled to the integrated device 172. In some implementations, the passive component 170 and / or the integrated device 172 may protrude from a bottom surface of the encapsulation layer 174 such that a portion of a side of the passive component 170 and / or a portion of a side of the integrated device 172 is not covered by the encapsulation layer 174. In some implementations, the bottom of passive components 170 and / or the bottom of integrated device 172 may be aligned with the bottom of encapsulation layer 174. For example, the bottom surface of passive components 170 and / or the bottom surface of integrated device 172 may be aligned with the bottom surface of encapsulation layer 174. FIG. 12 shows another side view of block device 1107 including passive components 170, integrated device 172, encapsulation layer 174, and metal layer 176.

[0037] 13 shows a bottom view of block device 1107 including passive components 170, integrated devices 172, encapsulation layer 174, and metal layer 176. A plurality of solder interconnects 171 may be coupled to terminals of passive components 170. A plurality of solder interconnects 173 may be coupled to integrated devices 172. FIG. 14 shows a top view of block device 1107 including metal layer 176. Metal layer 176 is disposed over a surface of encapsulation layer 174.

[0038] The integrated device (e.g., 104, 172) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 104, 172) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may be an example of an electrical component and / or an electrical device.

[0039] Having described various packages, several methods for making the packages are now described below.

[0040] Exemplary sequence for creating a package with a block device and a shield In some implementations, making a package includes several processes. Figures 15A and 15B show an example sequence for providing or making a package. In some implementations, the sequence of Figures 15A-15B can be used to provide or make the package 100 of Figure 1. However, the process of Figures 15A-15B can be used to make any of the packages described in this disclosure.

[0041] It should be noted that the sequence of Figures 15A-15B may combine one or more steps to simplify and / or clarify the sequence for providing or making a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0042] As shown in FIG. 15A, stage 1 shows the state after a substrate 102 is provided. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder resist layer 126. Different implementations may use different substrates having different numbers of metal layers. The substrate may include a coreless substrate, a cored substrate, or an embedded trace substrate (ETS). FIGS. 20A-20B illustrate and explain an example of fabricating a substrate.

[0043] Stage 2 illustrates the state after the plurality of solder interconnects 1500 have been coupled to (provided on) the substrate 102. The plurality of solder interconnects 1500 may be coupled to at least some of the plurality of interconnects 122. The plurality of solder interconnects 1500 may represent the plurality of solder interconnects 140, 151, 153, and / or 178.

[0044] Stage 3 shows the state after the integrated device 104, the block device 105, and the block device 107 are coupled to the substrate 102 via a plurality of solder interconnects 1500. The block device 105 may be coupled to the substrate 102 via a plurality of solder interconnects 151 and / or 153. The integrated device 104 may be coupled to the substrate 102 via a plurality of solder interconnects 140. The block device 107 may be coupled to the substrate 102 via a plurality of solder interconnects 178. Different implementations may couple different components and / or devices to the substrate 102. Other components and / or devices may be coupled to the substrate 102. A solder reflow process may be used to couple the integrated device 104, the block device 105, and the block device 107 to the substrate 102.

[0045] Stage 4 shows the state after the encapsulation layer 108 is provided (e.g., formed) on the substrate 102. The encapsulation layer 108 may encapsulate the block device 105, the integrated device 104, and the block device 107. The encapsulation layer 108 may encapsulate other devices and / or components bonded to the substrate 102. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photoetchable. The encapsulation layer 108 may be a means for encapsulation. As shown in stage 4, the encapsulation layer 108 leaves the tops of the block devices 105 and 107 exposed (e.g., not covered by the encapsulation layer 108). In some implementations, the encapsulation layer 108 may be formed such that the encapsulation layer 108 is formed and disposed on and / or around the top of the block device 105 and / or the top of the block device 107.

[0046] Stage 5, as shown in FIG. 15B , illustrates the state after a portion of block device 105 and a portion of block device 107 have been removed. The grinding and / or polishing process may remove a portion of block device 105 and / or a portion of block device 107. In some implementations, an upper portion of metal layer 156 of block device 105 and an upper portion of metal layer 176 of block device 107 may be removed to expose encapsulation layer 154 and encapsulation layer 174. A portion of encapsulation layer 154 and / or a portion of encapsulation layer 174 may also be removed. In some implementations, a portion of encapsulation layer 108 may also be removed (e.g., if encapsulation layer 108 is present over block device 105 and / or block device 107).

[0047] Stage 6 shows the state after metal layer 109 has been formed on the outer surface of encapsulation layer 108. A sputtering process and / or a plating process may be used to form and bond metal layer 109 to encapsulation layer 108. Metal layer 109 may be formed on a top surface of encapsulation layer 108, a surface of encapsulation layer 154, a surface of encapsulation layer 174, a side of encapsulation layer 108, and a side of substrate 102. Metal layer 109 may be bonded to metal layer 156 of block device 105. Metal layer 109 may be bonded to metal layer 176 of block device 107. Metal layer 109 may be configured to be bonded to ground.

[0048] Stage 7 shows the condition after the plurality of solder interconnects 130 have been bonded to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 130 to the substrate 102.

[0049] Placement of the block devices may use surface mount technology (SMT) to place the block devices in the appropriate locations.

[0050] 1 is an exemplary flow diagram of a method for making a package with a block device and a shield; In some implementations, producing a package including a block device and a shield includes several processes. Figure 16 shows an example flow diagram of a method 1600 for providing or producing a package. In some implementations, the method 1600 of Figure 16 may be used to provide or produce the package 100 of Figure 1 described in this disclosure. However, the method 1600 may be used to provide or produce any of the packages (e.g., 100) described in this disclosure.

[0051] It should be noted that the method of Figure 16 may combine one or more processes to simplify and / or clarify the method for providing or making the package. In some implementations, the order of the processes may be changed or modified.

[0052] The method provides (at 1605) a substrate (e.g., 102). The substrate 102 may be provided by a supplier or may be fabricated. A process similar to that shown in FIGS. 20A-20B may be used to fabricate the substrate 102. However, different implementations may use different processes to fabricate the substrate 102. Examples of processes that may be used to fabricate the substrate 102 include semi-additive processes (SAP) and modified semi-additive processes (mSAP). The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder resist layer 126. The substrate 102 may include an embedded trace substrate (ETS). In some implementations, the at least one dielectric layer 120 may include a prepreg layer. Stage 1 of FIG. 15A illustrates and describes an example of providing a substrate.

[0053] The method includes (at 1610) providing a plurality of solder interconnects (e.g., 1500) on the substrate 102. The plurality of solder interconnects 1500 may be coupled to at least some of the plurality of interconnects 122. Stage 2 of Figure 15A illustrates and describes one example of providing solder interconnects.

[0054] The method includes (at 1615) bonding components and / or devices to a first surface of the substrate 102. For example, the integrated device 104 is bonded to the first surface (e.g., top surface) of the substrate 102. The integrated device 104 may be bonded to the substrate 102 via a plurality of solder interconnects 140. The block device 105 may be bonded to the first surface of the substrate 102 via a plurality of solder interconnects 151 and / or 153. The block device 107 may be bonded to the first surface of the substrate 102 via a plurality of solder interconnects 178. A solder reflow process may be used to bond the integrated device 104, the block device 105, and the block device 107 to the substrate 102 via the plurality of solder interconnects. Stage 3 of FIG. 15A illustrates and describes one example of bonding at least components and / or devices to a substrate.

[0055] The method forms (at 1620) an encapsulation layer (e.g., 168) over the substrate (e.g., 102). The encapsulation layer 108 may be provided and formed over and / or around the substrate 102, the integrated device 104, the block device 105, and the block device 107. In some implementations, the tops of the integrated device 104, the block device 105, and / or the block device 107 may be left exposed. The encapsulation layer 108 may encapsulate the integrated device(s), the device(s), and / or the component(s). The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photo-etchable. The encapsulation layer 108 may be a means for encapsulation. Step 4 of FIG. 15A illustrates one example of forming an encapsulation layer.

[0056] The method removes (at 1625) a portion of block device 105 and a portion of block device 107. The grinding and / or polishing process may remove a portion of block device 105 and / or a portion of block device 107. In some implementations, an upper portion of metal layer 156 of block device 105 and an upper portion of metal layer 176 of block device 107 may be removed to expose encapsulation layer 154 and encapsulation layer 174. A portion of encapsulation layer 154 and / or a portion of encapsulation layer 174 may also be removed. In some implementations, a portion of encapsulation layer 108 may also be removed (e.g., if encapsulation layer 108 is present over block device 105 and / or block device 107). Stage 5 of FIG. 15B illustrates and describes one example of grinding to remove a component and / or a portion of an encapsulation layer.

[0057] The method forms (at 1630) a metal layer (e.g., 109) on an outer surface of encapsulation layer 108. A sputtering process and / or a plating process may be used to form and bond metal layer 109 to encapsulation layer 108. Metal layer 109 may be formed on a top surface of encapsulation layer 108, a surface of encapsulation layer 154, a surface of encapsulation layer 174, a side of encapsulation layer 108, and a side of substrate 102. Metal layer 109 may be bonded to metal layer 156 of block device 105. Metal layer 109 may be bonded to metal layer 176 of block device 107. Metal layer 109 may be configured to be coupled to ground.

[0058] The method bonds (at 1635) the plurality of solder interconnects (e.g., 130) to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 130 to the substrate 102. Step 7 of Figure 15B illustrates and describes one example of bonding the solder interconnects to a substrate.

[0059] The packages (eg, 100) described in this disclosure may be fabricated one by one or together as part of one or more wafers and then singulated into individual packages.

[0060] Depending on the design and component requirements, several block assembly configurations may be used, for example, tape-assisted molding may be used with a carrier. Block devices may be bonded using SMT assembly rules and designed to be compatible with tape-and-reel and assembly processes. The height of the block devices may need to be adjusted to account for the target package thickness to allow for electrical connection with an external EMI shield.

[0061] Exemplary sequence for creating a block device with shielding In some implementations, creating a block device includes several processes. Figures 17A-17B show an example sequence for providing or creating a block device. In some implementations, the sequence of Figures 17A-17B may be used to provide or create a block device 105. However, the process of Figures 17A-17B may be used to create any of the block devices described in this disclosure.

[0062] 17A-17B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a block device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0063] Stage 1, as shown in Figure 17A, depicts the state after tape 1700 has been provided. Tape 1700 may include an adhesive. Note that another carrier may be used in place of tape.

[0064] Stage 2 shows the state after a number of passive components 1710 have been mounted and coupled to tape 1700. The number of passive components 1710 may represent any of the passive components described in this disclosure, such as passive components 150, 152, 250, and / or 252. It should be noted that other components and / or devices may also be coupled to tape 1700. For example, an integrated device (e.g., 104) may be mounted and coupled to tape 1700.

[0065] Stage 3 shows the state after encapsulation layer 154 has been formed on tape 1700. Encapsulation layer 154 may encapsulate passive components 1710. Encapsulation layer 154 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form encapsulation layer 154.

[0066] Stage 4 shows the state after the encapsulation layer 154 has been cut and / or diced, creating cut lines 1720 (e.g., cavities) in the encapsulation layer 154. A saw and / or laser may be used to create the cut lines 1720. This creates several individual block devices with the encapsulation layer and several passive components.

[0067] Stage 5, as shown in Figure 17B, shows the state after the individual block devices with encapsulation layer and some passive components have been separated (e.g., removed) from tape 1700 and transferred to a carrier 1750. The individual block devices may be placed and bonded to carrier 1750. Note that transfer to a carrier may be optional.

[0068] Stage 6 shows the state after metal layer 156 has been formed over encapsulation layer 154 of the individual block devices (e.g., over the surface of encapsulation layer 154). A sputtering process and / or a plating process may be used to form metal layer 156.

[0069] Stage 7 shows the state after the carrier 1750 has been separated, leaving behind a number of block devices 105, each having a number of passive components, an encapsulation layer 154, and a metal layer 156. The metal layer 156 may be configured as an EMI shield.

[0070] Exemplary sequence for creating a block device with shielding In some implementations, creating a block device includes several processes. Figures 18A-18C show an example sequence for providing or creating a block device. In some implementations, the sequence of Figures 18A-18C may be used to provide or create a block device 107. However, the process of Figures 18A-18C may be used to create any of the block devices described in this disclosure.

[0071] 18A-18C may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a block device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0072] As shown in FIG. 18A, stage 1 shows the state after a block substrate 175 is provided. The block substrate 175 may include at least one dielectric layer 177 and a plurality of interconnects 179. Different implementations may use different materials for the at least one dielectric layer 177. For example, the at least one dielectric layer 177 may include prepreg, glass, and / or quartz. FIGS. 20A-20B show an example of fabricating a substrate that may be used to fabricate the block substrate 175.

[0073] Stage 2 shows the state after the passive components 170 and the integrated devices 172 have been mounted and bonded to the block substrate 175. Note that other components and / or devices may also be bonded to the block substrate 175. The passive components 170 and the integrated devices 172 may be bonded to the block substrate 175 via solder interconnects (e.g., 171, 173). A solder reflow process may be used to bond the passive components 170 and the integrated devices 172 to the block substrate 175.

[0074] Stage 3 shows the state after encapsulation layer 174 is formed over block substrate 175 and passive components 170 and integrated device 172. Encapsulation layer 174 may encapsulate passive components 170 and integrated device 172. Encapsulation layer 174 may include mold, resin, and / or epoxy. Compression molding, transfer molding, or liquid molding processes may be used to form encapsulation layer 174.

[0075] Stage 4 shows the state after the block substrate 175 , the plurality of passive components 170 , the plurality of integrated devices 172 , and the encapsulation layer 174 are bonded to the carrier 1800 .

[0076] Stage 5, as shown in Figure 18B, shows the state after the encapsulation layer 174 has been cut and / or diced, thereby creating cut lines 1820 (e.g., cavities) in the encapsulation layer 174. A saw and / or laser may be used to create the cut lines 1820, thereby creating several individual block devices with the encapsulation layer and several passive components and / or integrated devices.

[0077] Stage 6 shows the state after the individual block devices with the encapsulation layer and some passive components and / or integrated devices have been separated (e.g., removed) from carrier 1800 and transferred to carrier 1810. The individual block devices may be placed and bonded to carrier 1810. Note that in some implementations, the transfer to another carrier may be optional.

[0078] Stage 7 shows the state after metal layer 176 has been formed over encapsulation layer 174 of the individual block devices (e.g., over the surface of encapsulation layer 174). A sputtering process and / or a plating process may be used to form metal layer 176.

[0079] Stage 8 shows the state after the carrier 1810 has been separated, leaving a plurality of block devices 107, each having a block substrate 175, at least one passive component, at least one integrated device, an encapsulation layer 174, and a metal layer 176. The metal layer 176 may be configured as an EMI shield. At least a portion of the block substrate 175 may be configured as an EMI shield.

[0080] 1 is an exemplary flow diagram of a method for making a package with a block device having a shield; In some implementations, the fabrication of a block device with a shield includes several processes. FIG. 19 shows an example flow diagram of a method 1900 for providing or fabricating a block device. In some implementations, the method 1900 of FIG. 19 may be used to provide or fabricate the block device 107 of FIG. 1 described in this disclosure. The method 1900 is described with respect to fabricating the block device 107. However, the method 1900 may be used to provide or fabricate any of the block devices (e.g., 105, 107) described in this disclosure.

[0081] It should be noted that the method of Figure 19 may combine one or more processes to simplify and / or clarify the method for providing or creating a block device, and in some implementations, the order of the processes may be changed or modified.

[0082] The method may optionally provide (at 1905) a block substrate (e.g., 175). The block substrate 175 may be provided by a supplier or may be fabricated. The block substrate 175 may include at least one dielectric layer 177 and a plurality of interconnects 179. Step 1 of FIG. 18A illustrates and describes one example of providing a block substrate.

[0083] The method provides and couples (at 1910) at least one passive component (e.g., 170) and / or at least one integrated device (e.g., 172). The at least one passive component and / or at least one integrated device may be coupled to a block substrate 175 or may be coupled to a tape or carrier. The at least one passive component and / or at least one integrated device may be examples of electrical components and / or electrical devices. Step 2 of FIG. 18A illustrates and describes one example of providing and / or coupling at least one passive component and / or at least one integrated device.

[0084] The method forms (at 1915) an encapsulation layer (e.g., 174) on the block substrate (e.g., 175), carrier, or tape. The encapsulation layer 174 may be provided and formed on and / or around the block substrate 175 and the integrated device (e.g., 172) and / or passive components (e.g., 170). The encapsulation layer 174 may encapsulate the integrated device(s) and / or components. The encapsulation layer 174 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the encapsulation layer 174. The encapsulation layer 174 may be photoetchable. The encapsulation layer 174 may be a means for encapsulation. Step 4 of FIG. 18A illustrates and describes one example of forming an encapsulation layer.

[0085] The method then dices (at 1920) the encapsulation layer (e.g., 174), thereby creating cut lines 1820 (e.g., cavities) in the encapsulation layer 174. A saw and / or a laser may be used to create the cut lines 1820. This creates several individual block devices having the encapsulation layer, passive component(s), and / or integrated device(s). Step 5 of FIG. 18B illustrates and describes one example of dicing the encapsulation layer. Once dicing is complete, the method may place (e.g., transfer) the individual block devices onto a carrier. Step 6 of FIG. 18B illustrates and describes one example of placing the individual block devices onto a carrier.

[0086] The method forms (at 1925) a metal layer (e.g., 176) on the encapsulation layer 174 of the individual block devices. A metal layer may be formed and bonded to an outer surface of the encapsulation layer 174. A sputtering process and / or a plating process may be used to form the metal layer 176. The metal layer 176 may be configured as an EMI shield. Step 7 of FIG. 18C illustrates and describes an example forming a metal layer. Note that during the process of making the block devices, various components may be separated, transferred, and / or bonded to various tapes and / or carriers. The method may then separate the individual block devices from the carrier. Step 8 of FIG. 18C illustrates and describes an example of separating the block devices from the carrier.

[0087] It should be noted that by using proper design rules and dicing tolerances, the risk of voids occurring during encapsulation of the individual block devices as well as during package encapsulation can be minimized.

[0088] Note that opening the solder mask on the package and proper mold flow can further reduce the risk of mold voids. The block devices can include exposed pads that can be made thinner to increase the standoff during package assembly to further reduce the risk of mold voids.

[0089] Exemplary Sequence for Preparing a Substrate In some implementations, the fabrication of a substrate includes several processes. Figures 20A-20B show an example sequence for providing or fabricating a substrate. In some implementations, the sequence of Figures 20A-20B may be used to provide or fabricate the substrate 102 of Figure 1. However, the process of Figures 20A-20B may be used to fabricate any of the substrates described in this disclosure.

[0090] 20A-20B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0091] Stage 1, as shown in FIG. 20A , depicts the state after a carrier 2000 is provided and a metal layer is formed on the carrier 2000. The metal layer may be patterned to form interconnects 2002. Plating and etching processes may be used to form the metal layer and the interconnects. In some implementations, the carrier 2000 may be provided with a metal layer that is patterned to form the interconnects 2002. In some implementations, there may be a seed layer on the carrier 2000. The seed layer may be disposed between the carrier 2000 and the metal layer that forms the interconnects 2002.

[0092] Stage 2 shows the state after a dielectric layer 2020 has been formed over the carrier 2000 and the interconnects 2002. A deposition and / or lamination process may be used to form the dielectric layer 2020. The dielectric layer 2020 may include polyimide. However, different implementations may use different materials for the dielectric layer.

[0093] Stage 3 shows the state after the cavities 2010 have been formed in the dielectric layer 2020. The cavities 2010 may be formed using an etching process (eg, a photoetching process) or a laser process.

[0094] Stage 4 shows the state after interconnects 2012 have been formed in and on the dielectric layer 2020, including in and on the plurality of cavities 2010. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0095] Stage 5 shows the state after another dielectric layer 2022 is formed on top of the dielectric layer 2020. A deposition and / or lamination process may be used to form the dielectric layer 2022. The dielectric layer 2022 may be the same material as the dielectric layer 2020. However, different implementations may use different materials for the dielectric layer.

[0096] 20B, after a number of cavities 2030 have been formed in the dielectric layer 2022. An etching process or a laser process may be used to form the cavities 2030.

[0097] Stage 7 shows the state after interconnects 2014 have been formed in and over the dielectric layer 2022, including in and over the plurality of cavities 2030. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0098] It should be noted that steps 5-7 may be repeated iteratively to form additional metal and dielectric layers. Some or all of interconnects 2002, 2012, and / or 2014 may define multiple interconnects 122 in substrate 102. Dielectric layers 2020 and 2022 may be represented by at least one dielectric layer 120.

[0099] Stage 8 shows the state after the carrier 2000 has been separated (e.g., removed, polished away) from the at least one dielectric layer 120, leaving the substrate 102 including the at least one dielectric layer 120 and multiple interconnects 122.

[0100] Stage 9 shows the state after solder resist layer 124 and solder resist layer 126 have been formed on substrate 102. A deposition process may be used to form solder resist layer 124 and solder resist layer 126. In some implementations, there may be zero or one solder resist layer formed on at least one dielectric layer 120.

[0101] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer(s). For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0102] 1 is an exemplary flow diagram of a method for fabricating a substrate; In some implementations, the fabrication of a substrate includes several processes. Figure 21 shows an example flow diagram of a method 2100 for providing or fabricating a substrate. In some implementations, the method 2100 of Figure 21 can be used to provide or fabricate the substrate(s) of Figure 1. For example, the method of Figure 21 can be used to fabricate the substrate 102.

[0103] It should be noted that the method 2100 of Figure 21 may combine one or more processes to simplify and / or clarify the method for providing or fabricating a substrate, and in some implementations, the order of the processes may be changed or modified.

[0104] The method provides (at 2105) a carrier 2000. Different implementations may use different materials for the carrier. The carrier may include a seed layer. The carrier may include a substrate, glass, quartz, and / or a carrier tape. Step 1 of Figure 20A illustrates and describes one example of a carrier that is provided.

[0105] The method forms (at 2110) a metal layer on the carrier 2000. The metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier may include a metal layer. The metal layer on the carrier may be patterned to form the interconnects (e.g., 2002). Step 1 of FIG. 20A illustrates and describes one example of a metal layer and interconnects formed on a carrier.

[0106] The method forms (at 2115) a dielectric layer 2020 over the carrier 2000 and the interconnects 2002. A deposition and / or lamination process may be used to form the dielectric layer. The dielectric layer 2020 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 2010) in the dielectric layer 2020. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 2-3 of FIG. 20A illustrate and describe one example of forming the dielectric layer and the cavities in the dielectric layer.

[0107] The method forms (at 2120) interconnects in and on the dielectric layer. For example, interconnects 2012 may be formed in and on the dielectric layer 2020. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects may also include forming the interconnects within cavities in the dielectric layer. Step 4 of FIG. 20A illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0108] The method forms (at 2125) a dielectric layer 2022 over the dielectric layer 2020 and the interconnects. A deposition and / or lamination process may be used to form the dielectric layer. The dielectric layer 2022 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 2030) in the dielectric layer 2022. The plurality of cavities may be formed using an etching process or a laser process. Steps 5-6 of Figures 20A-20B illustrate and describe one example of forming the dielectric layer and the cavities in the dielectric layer.

[0109] The method forms (at 2130) an interconnect in and / or on the dielectric layer. For example, interconnect 2014 may be formed. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer on and in the dielectric layer. Forming the interconnect may also include forming the interconnect within a cavity in the dielectric layer. Step 7 of FIG. 20B illustrates and describes one example of forming an interconnect in and on the dielectric layer.

[0110] The method may form additional dielectric layer(s) and additional interconnects as described at 2125 and 2130.

[0111] Once all the dielectric layer(s) and additional interconnects have been formed, the method may separate (e.g., remove, polish away) the carrier (e.g., 2000) from the dielectric layer 2020 leaving the substrate. In some implementations, the method may form a solder resist layer (e.g., 124, 126) over the substrate.

[0112] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer(s). For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0113] Exemplary Electronic Devices FIG. 22 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 2202, a laptop computer device 2204, a fixed location terminal device 2206, a wearable device 2208, or an automotive vehicle 2210 may include a device 2200 as described herein. The device 2200 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 2202, 2204, 2206, and 2208, and the vehicle 2210 illustrated in FIG. 22 are merely exemplary. Other electronic devices may also feature device 2200, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0114] One or more of the components, processes, features, and / or functions shown in Figures 1-14, 15A-15B, 16, 17A-17B, 18A-18C, and / or 19-22 may be rearranged and / or combined into a single component, process, feature, or function, or may be embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from the present disclosure. It should also be noted that Figures 1-14, 15A-15B, 16, 17A-17B, 18A-18C, and / or 19-22 in this disclosure and their corresponding descriptions are not limited to dies and / or ICs. 1-14, 15A-15B, 16, 17A-17B, 18A-18C, and / or 19-22 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0115] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some examples, the figures may not be to scale. In some examples, for clarity, not all components and / or parts are shown. In some examples, the positions, locations, sizes, and / or shapes of various parts and / or parts in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0116] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, object A and object C may still be considered to be coupled to each other even if they do not directly physically contact each other. Object A that is coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electric current traveling between the two objects. The use of the terms "first", "second", "third" and "fourth" (and / or fifth or more) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The terms "encapsulate", "encapsulating", and / or derivatives thereof, mean that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component placed on top may be placed on top of a component placed on the bottom. A top component may be considered a bottom component and vice versa. As described in this disclosure, a first component placed "on" a second component may mean that the first component is placed above or below the second component, depending on how bottom or top is arbitrarily defined.In another example, a first component may be disposed on (e.g., above) a first surface of a second component, and a third component may be disposed on (e.g., below) a second surface of the second component, the second surface facing the first surface. It is further noted that the term "over" as used herein in the context of one component being disposed over another component may be used to mean a component on and / or within (e.g., on the surface of or embedded in) another component. Thus, for example, a first component being disposed over a second component may mean (1) the first component is disposed over, but not in direct contact with, the second component, (2) the first component is disposed on (e.g., on the surface of) the second component, and / or (3) the first component is disposed within (e.g., embedded in) the second component. A first component that is located "in" a second component may be located partially within the second component or may be located completely within the second component. As used in this disclosure, the term "about 'the value of X'" or "approximately the value of X" means within 10 percent of the "value of X." For example, a value of about 1 or approximately 1 means a value in the range of 0.9 to 1.1.

[0117] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the interconnects.

[0118] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process is terminated when its operations are completed.

[0119] Further examples are described below to facilitate understanding of the present disclosure.

[0120] Aspect 1: A package comprising: a substrate; a first integrated device coupled to the substrate; a first block device coupled to the substrate, the first block device including a first electrical component, a second electrical component, a first encapsulation layer encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer; and a second encapsulation layer at least partially encapsulating the first integrated device and the first block device.

[0121] Aspect 2: The package of aspect 1, further comprising a second metal layer coupled to the second encapsulation layer, the second metal layer being disposed on an outer surface of the second encapsulation layer.

[0122] Aspect 3: The package of aspect 2, wherein the second metal layer is coupled to the first metal layer of the first block device.

[0123] Aspect 4: The package of aspect 2 or 3, wherein the first metal layer and / or the second metal layer are configured as an electromagnetic interference (EMI) shield.

[0124] Aspect 5: The package of aspects 2-4, wherein the first metal layer and / or the second metal layer are configured to be coupled to ground.

[0125] Aspect 6: The package of aspects 1 to 5, wherein the first block device further includes a block substrate, and the first electrical component and the second electrical component are coupled to the block substrate.

[0126] Example 7: The package of Examples 1 to 6, wherein the first electrical component includes a passive component or an integrated device, and the second electrical component includes another passive component or another integrated device.

[0127] Aspect 8: The package of aspects 1-7, wherein the first block device includes three or more electrical components.

[0128] Aspect 9: The package of Aspects 1-8, further comprising a second block device coupled to the substrate, the second block device including a third electrical component, a fourth electrical component, a third encapsulation layer encapsulating the third electrical component and the fourth electrical component, and a third metal layer coupled to the third encapsulation layer, the third metal layer configured as a shield for the second block device.

[0129] Embodiment 10: The package of embodiments 1-9, wherein the first block device is coupled to the substrate via a plurality of solder interconnects.

[0130] Aspect 11: An apparatus comprising: a substrate; a first integrated device coupled to the substrate; a first block device coupled to the substrate, the first block device including a first electrical component, a second electrical component, a first encapsulation means configured to encapsulate the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation means; and a second encapsulation means configured to at least partially encapsulate the first integrated device and the first block device.

[0131] Example 12: The device of Example 11, further comprising a second metal layer coupled to the means for second encapsulation, the second metal layer being disposed on an outer surface of the means for second encapsulation.

[0132] Example 13: The apparatus of example 12, wherein the second metal layer is coupled to the first metal layer of the first block device.

[0133] Example 14: The device of example 12 or 13, wherein the first metal layer and / or the second metal layer are configured as an electromagnetic interference (EMI) shield.

[0134] Example 15: The device of Examples 12-14, wherein the first metal layer and / or the second metal layer are configured to be coupled to ground.

[0135] Aspect 16: An apparatus described in aspects 11 to 15, wherein the first block device further includes a block substrate, and the first electrical component and the second electrical component are coupled to the block substrate.

[0136] Example 17: An apparatus described in Examples 11 to 16, wherein the first electrical component includes a passive component or an integrated device, and the second electrical component includes another passive component or another integrated device.

[0137] Aspect 18: The apparatus of aspects 11-17, wherein the first block device includes three or more electrical components.

[0138] Aspect 19: The apparatus of aspects 11-18, further comprising a second block device coupled to the substrate, the second block device including: a third electrical component, a fourth electrical component, a third encapsulation means configured to encapsulate the third electrical component and the fourth electrical component, and a third metal layer coupled to the third encapsulation means, the third metal layer configured as a shield for the second block device.

[0139] Aspect 20: The apparatus of aspects 11 to 19, wherein the apparatus comprises a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0140] Aspect 21: A method for making a package, the method comprising: providing a substrate; coupling a first integrated device to the substrate; coupling a first block device to the substrate, the first block device including a first electrical component, a second electrical component, a first encapsulation layer encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer; and forming a second encapsulation layer at least partially encapsulating the first integrated device and the first block device.

[0141] Example 22: The method of example 21, further comprising forming a second metal layer on an outer surface of the second encapsulation layer.

[0142] Example 23: The method of example 22, wherein the second metal layer is coupled to the first metal layer of the first block device.

[0143] Example 24: The method of example 22 or 23, wherein the first metal layer and / or the second metal layer are configured as an electromagnetic interference (EMI) shield.

[0144] Aspect 25: The method of any one of aspects 21 to 24, wherein the first block device further includes a block substrate, and the first electrical component and the second electrical component are coupled to the block substrate.

[0145] Various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and is not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0146] 100 packages 102 Substrate 104 Integrated Devices 105 Block Devices 107 Block Devices 108 Encapsulation Layer 109 Metal layer 120 Dielectric layer 122 Interconnection 124 Resist layer 126 Resist layer 130 Interconnection 140 Interconnection 150 Passive Components 151 Interconnection 152 Passive Components 153 Interconnection 154 Encapsulation Layer 156 Metal layer 170 Passive Components 171 Interconnection 172 Integrated Devices 173 Interconnection 174 Encapsulation Layer 175 Block Board 176 Metal layer 177 Dielectric Layer 178 Interconnection 179 Interconnection 250 Passive Components 252 Passive Components 270 Passive Components 272 Passive Components 1107 Block Device 1500 Interconnect 1700 Tape 1710 Passive Components 1720 cutting line 1750 Career 1800 Career 1810 Career 1820 cutting line 2000 Career 2002 Interconnect 2010 hollow 2012 Interconnect 2014 Interconnect 2020 Dielectric layer 2022 Dielectric layer 2030 Cavity 2200 Devices 2202 Mobile Phone Device 2202 Devices 2204 Devices 2206 Devices 2208 Devices 2210 Vehicles

Claims

1. A package comprising: A substrate; a first integrated device coupled to the substrate; a first block device coupled to the substrate via a plurality of solder interconnects between the first block device and the substrate, the first block device comprising: a first electrical component; a second electrical component; and a first encapsulation layer encapsulating the first electrical component and the second electrical component; a first metal layer coupled to and in contact with a side of the first encapsulation layer; the entire first metal layer extends between a top portion of the first encapsulation layer and a bottom portion of the first encapsulation layer; or a first block device further including a block substrate, the first electrical component and the second electrical component being coupled to the block substrate, and the entire first metal layer extending between a top of the first encapsulation layer and a bottom of the block substrate; a second encapsulation layer at least partially encapsulating the first integrated device and the first block device; A package comprising:

2. 10. The package of claim 1, further comprising a second metal layer coupled to the second encapsulation layer, the second metal layer being disposed on an outer surface of the second encapsulation layer.

3. The package of claim 2 , wherein the second metal layer is coupled to the first metal layer of the first block device.

4. The package of claim 2 , wherein the first metal layer and / or the second metal layer are configured as an electromagnetic interference (EMI) shield.

5. The package of claim 2 , wherein the first metal layer and / or the second metal layer are configured to be coupled to ground.

6. the first electrical component comprises a passive component or an integrated device; the second electrical component comprises another passive component or another integrated device; The package of claim 1.

7. The package of claim 1 , wherein the first block device includes three or more electrical components.

8. and a second block device coupled to the substrate, the second block device comprising: a third electrical component; and a fourth electrical component; and a third encapsulation layer encapsulating the third electrical component and the fourth electrical component; a third metal layer coupled to the third encapsulation layer, the third metal layer configured as a shield for the second block device; and The package of claim 1 comprising:

9. An apparatus including a package according to any one of claims 1 to 8, comprising a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

10. 1. A method for making a package, comprising: Providing a substrate; Coupling a first integrated device to the substrate; coupling a first block device to the substrate via a plurality of solder interconnects between the first block device and the substrate, the first block device comprising: a first electrical component; a second electrical component; and a first encapsulation layer encapsulating the first electrical component and the second electrical component; a first metal layer coupled to and contacting a side of the first encapsulation layer; Including, the entire first metal layer extends between a top portion of the first encapsulation layer and a bottom portion of the first encapsulation layer; or the first block device further includes a block substrate, the first electrical component and the second electrical component are coupled to the block substrate, and the entire first metal layer extends between a top of the first encapsulation layer and a bottom of the block substrate; forming a second encapsulation layer at least partially encapsulating the first integrated device and the first block device; A method comprising:

11. The method of claim 10 further comprising forming a second metal layer on an outer surface of the second encapsulation layer.

12. The method of claim 11 , wherein the second metal layer is coupled to the first metal layer of the first block device.

13. The method of claim 11 , wherein the first metal layer and / or the second metal layer are configured as an electromagnetic interference (EMI) shield.

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