Signal power splitter / combiner with resistive and impedance transformer loads.

Abstract

The embodiment relates to a signal power splitter / combiner (700) including a first signal port (P1), a first resistor (RO), a first impedance transformer (710) coupled in series with the first resistor between the first signal port and a first intermediate node (n1), a second impedance transformer (720) coupled between the first intermediate node (n1) and a second signal port (P2), a third impedance transformer (730) coupled between the first intermediate (n1) node and a third signal port (P3), and a second resistor (R2) coupled between the second signal port and the third signal port. The signal power splitter / combiner may further include a fourth impedance transformer (740) coupled between the second impedance transformer (720) and the second signal port, a fifth impedance transformer (750) coupled between the third impedance transformer (730) and the third signal port, and a third resistor (R1) coupled between a third intermediate node (n3) and a second intermediate node (n2), the second intermediate node (n2) being between the second impedance transformer (720) and the fourth impedance transformer (740), and the third intermediate node (n3) being between the third impedance transformer (730) and the fifth impedance transformer (750).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001]

[0001] This patent application claims priority to pending U.S. non-provisional application Ser. No. 17 / 392,005, filed on August 2, 2021, assigned to the assignee of the present application, and expressly incorporated by reference herein for all applicable purposes as if fully set forth below. [Technical field]

[0002] Aspects of the present disclosure relate generally to signal power splitters / combiners, and more particularly to signal power splitters / combiners with resistive and impedance transformer loading for improved performance over wider bandwidths. [Background technology]

[0003]

[0003] A signal power splitter is configured to receive an input signal and power split the input signal to generate a set of output signals. Conversely, a signal power combiner is configured to receive a set of input signals and power combine the input signals to generate an output signal. In general, signal power splitters or combiners have a reciprocity property, where the same device can be used as a power splitter or combiner depending on whether an input signal is received at a single port on one side of the device, or a set of input signals is received at a set of input ports on the other side of the device.

[0004]

[0004] Other characteristics of interest for signal power splitters / combiners include the insertion loss between the input and output ports, the isolation between two or more input or output ports, and the impedance matching or return loss at any of the ports. Summary of the Invention

[0005]

[0005] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0006]

[0006] An aspect of the disclosure relates to an apparatus including a first signal port, a first resistor, a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node, a second impedance transformer coupled between the first intermediate node and a second signal port, a third impedance transformer coupled between the first intermediate node and a third signal port, and a second resistor coupled between the second signal port and the third signal port.

[0007] Another aspect of the disclosure relates to a method, the method including receiving a first signal at a first signal port, propagating the first signal through a first resistor and a first transformer to generate a second signal at a first intermediate node, splitting the second signal at the first intermediate node to generate third and fourth signals, propagating a third signal through the second impedance transformer to a second signal port, propagating the fourth signal through the third impedance transformer to a third signal port, and electrically coupling the second signal port to the third signal port via the second resistor.

[0008] Another aspect of the disclosure relates to an apparatus including means for receiving a first signal at a first signal port, means for propagating the first signal through a first resistor and a first transformer to generate a second signal at a first intermediate node, means for splitting the second signal at the first intermediate node to generate third and fourth signals, means for propagating a third signal through the second impedance transformer to a second signal port, means for propagating a fourth signal through the third impedance transformer to a third signal port, and means for electrically coupling the second signal port to the third signal port via the second resistor.

[0009] Another aspect of the disclosure relates to a method, the method including receiving a first signal at a first signal port, receiving a second signal at a second signal port, electrically coupling the first signal port to the second signal port through a first resistor, propagating the first signal from the first signal port to a first intermediate node through a first impedance transformer, propagating the second signal from the second signal port to the first intermediate node through a second impedance transformer, combining the first and second signals at the first intermediate node to generate a third signal, and propagating the third signal from the first intermediate node to a third signal port through a third impedance transformer and a second resistor.

[0010] Another aspect of the disclosure relates to an apparatus including means for receiving a first signal at a first signal port, means for receiving a second signal at a second signal port, means for electrically coupling the first signal port to the second signal port via a first resistor, means for propagating the first signal from the first signal port to a first intermediate node via a first impedance transformer, means for propagating the second signal from the second signal port to the first intermediate node via a second impedance transformer, means for combining the first and second signals at the first intermediate node to generate a third signal, and means for propagating the third signal from the first intermediate node to a third signal port via the third impedance transformer and the second resistor.

[0011] Another aspect of the present disclosure relates to a wireless communication device including at least one antenna, a set of transceiver chains coupled to the at least one antenna, and a signal power splitter or combiner coupled to the set of transceiver chains, the signal power splitter or combiner including a first signal port, a first resistor, a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node, a second impedance transformer coupled between the first intermediate node and a second signal port, a third impedance transformer coupled between the first intermediate node and a third signal port, and a second resistor coupled between the second signal port and a third signal port.

[0012] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed and the described implementations are intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0013] [Figure 1A]

[0013] FIG. 1 illustrates a schematic diagram of an example signal power splitter in accordance with an aspect of the present disclosure. [Figure 1B]

[0014] 2 illustrates a schematic diagram of an example signal power combiner according to another aspect of the disclosure. [Figure 2A]

[0015] 1C illustrates example specification and response graphs associated with the signal power splitter / combiner of FIG. 1A or 1B in accordance with another aspect of the disclosure. [Figure 2B] 1C illustrates example specification and response graphs associated with the signal power splitter / combiner of FIG. 1A or 1B in accordance with another aspect of the disclosure. [Figure 2C] 1C illustrates example specification and response graphs associated with the signal power splitter / combiner of FIG. 1A or 1B in accordance with another aspect of the disclosure. [Diagram 3]

[0016] 1 illustrates a schematic diagram of another example signal power splitter / combiner in accordance with another aspect of the present disclosure. [Figure 4]

[0017] 1 illustrates a schematic diagram of another example signal power splitter / combiner in accordance with another aspect of the present disclosure. [Figure 5A]

[0018] 5 illustrates example specification and response graphs associated with the signal power splitter / combiner of FIG. 3 or 4 in accordance with another aspect of the disclosure. [Figure 5B] 5 illustrates example specification and response graphs associated with the signal power splitter / combiner of FIG. 3 or 4 in accordance with another aspect of the disclosure. [Figure 5C] 5 illustrates example specification and response graphs associated with the signal power splitter / combiner of FIG. 3 or 4 in accordance with another aspect of the disclosure. [Figure 6]

[0019] 1 illustrates a schematic diagram of another example signal power splitter / combiner in accordance with another aspect of the present disclosure. [Figure 7]

[0020] 1 illustrates a schematic diagram of another example signal power splitter / combiner in accordance with another aspect of the present disclosure. [Figure 8]

[0021] 5 illustrates an example Smith chart of impedances at the signal ports of the signal power splitter / combiner of FIG. 3 or 4 according to another aspect of the disclosure. [Figure 9]

[0022] 8 illustrates an example Smith chart of impedance at the signal ports of the signal power splitter / combiner of FIG. 6 or 7 according to another aspect of the disclosure. [Figure 10A]

[0023] 8 illustrates example specification and response graphs associated with the signal power splitter / combiner of FIG. 6 or 7 according to another aspect of the disclosure. [Figure 10B] 8 illustrates example specification and response graphs associated with the signal power splitter / combiner of FIG. 6 or 7 according to another aspect of the disclosure. [Figure 10C] 8 illustrates example specification and response graphs associated with the signal power splitter / combiner of FIG. 6 or 7 according to another aspect of the disclosure. [Figure 11B]

[0024] 1 illustrates a layout diagram of an example signal power splitter / combiner according to another aspect of the present disclosure. [Figure 12]

[0025] 4 illustrates a flow diagram of an example method for power dividing a signal according to another aspect of the disclosure. [Figure 13]

[0026] 4 illustrates a flow diagram of an example method for power combining signals according to another aspect of the disclosure. [Figure 14]

[0027] 1 illustrates a block diagram of an example wireless communication device according to another aspect of the disclosure. [Figure 15]

[0028] 1 illustrates a block diagram of another example signal power splitter / combiner in accordance with another aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[0029] The detailed description set forth below in conjunction with the attached drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0015]

[0030] FIG. 1A illustrates a schematic diagram of an example signal power splitter 100 according to an embodiment of the present disclosure. The signal power splitter 100 splits an input signal P in Receives the input signal P in to obtain a first output signal P out1 and the second output signal P out2 In this example, the power division is equal or balanced, i.e., the first output signal P out1 The power level of the second output signal P out2 Assuming there is no insertion loss between the input and output of the signal power splitter 100, the power level of the first output signal P out1 and the second output signal P out2 The signal power of each of the input signals P in 3 dB lower than the signal power of

[0016]

[0031] The signal power splitter 100 includes an input signal port 110, a first transmission line 112 coupled between the input signal port 110 and a first output signal port 116, a second transmission line 114 coupled between the input signal port 110 and a second output signal port 118, and a resistor R coupled between the first output signal port 116 and the second output signal port 118. As discussed, the input signal P in is received at the input signal port 110 and a first output signal P out1 and the second output signal Pout2 are generated at the first output port 116 and the second output port 118, respectively.

[0017]

[0032] If the input signal port 110 and the output signal ports 116 and 118 have a particular characteristic impedance Zo at a particular wavelength λ or frequency, then the transmission lines 112 and 114 each have substantially the same impedance Z1, which is substantially

[0018]

number

[0019] Additionally, the transmission lines 112 and 114 each have substantially the same length L1, which may be set to substantially one-quarter wavelength (λ / 4) at a particular frequency. Further, the resistance of the resistor R may be set to substantially 2·Zo.

[0020]

[0033] The transmission lines 112 and 114 may be implemented as microstrip, stripline, coplanar microstrip, suspended microstrip, or otherwise, where the transmission lines 112 and 114 are each implemented as a metallization strip disposed on a dielectric or semiconductor substrate. The resistor R may also be implemented as an appropriately sized thin film material, such as titanium nitride (TiN), disposed on a dielectric or semiconductor substrate.

[0021]

[0034] 1B illustrates a schematic diagram of an example signal power combiner 150 according to another aspect of the disclosure. The previously discussed signal power splitter 100 has a reciprocal property. That is, the signal power splitter 100 can be configured as a signal power combiner by receiving respective input signals at ports 116 and 118 and generating a combined signal at port 110. The signal power combiner 150 is an example where the signal power splitter 100 is used as a power combiner. Due to their reciprocal property, the signal power splitter 100 and the combiner 150 are generally referred to herein as signal power splitters / combiners.

[0022]

[0035] The signal power combiner 150 receives a first input signal P in1 and the second input signal P in2 Receives the input signal P in1 and P in2 The output signal P out In this example, the power combination is equal or balanced, i.e., the output signal P out The power level of the input signal P in1 and P in2 This means that there is no insertion loss between the input and output of the signal power combiner 150, and the input signal P in1 and P in2 have substantially the same power, the output signal P out The power of the input signal P in1 and P in2 3 dB higher than the signal power of each of the

[0023]

[0036] The signal power combiner 150 includes a first input signal port 162, a second input signal port 164, a resistor R coupled between the first input signal port 162 and the second input signal port 164, a first transmission line 166 coupled between the first input signal port 162 and an output signal port 170, and a second transmission line 168 coupled between the second input signal port 164 and the output signal port 170. As discussed, the first input signal P in1 and the second input signal Pin2 are received at a first input signal port 162 and a second input signal port 164, respectively, and an output signal P out is produced at the output signal port 170.

[0024]

[0037] If the input signal ports 162 and 164 and the output signal port 170 each have a particular characteristic impedance Zo at a particular wavelength λ or frequency, then the transmission lines 166 and 168 each have substantially the same impedance Z1, which is substantially

[0025]

number

[0026] Additionally, the transmission lines 166 and 168 each have substantially the same length L1, which may be set to substantially one-quarter wavelength (λ / 4) at a particular frequency. Further, the resistance of the resistor R may be set to substantially 2·Zo.

[0027]

[0038] In effect, the transmission lines 166 and 168 may be implemented as microstrip, stripline, coplanar microstrip, suspended microstrip, or otherwise, where the transmission lines 166 and 168 are each implemented as a metallization strip disposed on a dielectric or semiconductor substrate. The resistor R may also be implemented as an appropriately sized thin film material, such as titanium nitride (TiN), disposed on a dielectric or semiconductor substrate.

[0028]

[0039] 2A-2C illustrate graphs of example specifications and responses associated with a signal power splitter / combiner 100 / 150 according to another embodiment of the disclosure. In each of the graphs, the x-axis or horizontal axis represents frequency from 0 Hertz at the left end to 20 Gigahertz (GHz) at the right end. The y-axis or vertical axis of the graph illustrated in FIG. 2A represents insertion loss in dB between ports 110 / 170 and 116 / 162 (or between ports 110 / 170 and 118 / 164), from -2 dB at the top to -14 dB at the bottom. The y-axis or vertical axis of the graph illustrated in FIG. 2B represents isolation in dB between ports 116 / 162 and 118 / 164, from 0 dB at the top to -30 dB at the bottom. The y-axis or vertical axis of the graph illustrated in FIG. 2C represents the return loss in dB at ports 110 / 170, from 0 dB at the top to −30 dB at the bottom.

[0029]

[0040] With particular reference to FIG. 2A, the graph includes a shaded region that indicates an illustrative specification for insertion loss for a particular application. In particular, the specification indicates an insertion loss of -5 dB or less between frequencies 0-15 GHz, but ideally should be -3 dB across the entire frequency band. Additionally, as discussed, the graph also indicates the insertion loss in dB between ports 110 / 170 and 116 / 162 (or between ports 110 / 170 and 118 / 164). Note that the insertion loss varies between -3 dB and -4 dB between frequencies 0-15 GHz, which meets the illustrative specification for insertion loss.

[0030]

[0041] With particular reference to FIG. 2B, the graph includes a shaded area showing an illustrative specification for the isolation between ports 116 / 162 and 118 / 164 for a particular application. In particular, the specification shows an isolation of -15 dB or better between the frequencies 7-15 GHz. Additionally, as discussed, the graph also shows the isolation between ports 116 / 162 and 118 / 164. Note that the isolation varies between -13 dB and -29 dB within the frequency band 7-15 GHz. From this, in the lower portion of the frequency band 7-15 GHz (e.g., between 7-8 GHz), the isolation between ports 116 / 162 and 118 / 164 does not meet the specification. This is because the length L1 of transmission lines 112 / 166 and 114 / 168 are each set for a particular frequency, such as 13 GHz in this example, where the isolation peaks at -29 dB. In this example, for frequencies further away from the particular frequency where the isolation does not meet the specification below 8.2 GHz, the isolation decreases.

[0031]

[0042] With particular reference to FIG. 2C, the graph includes shaded areas illustrating illustrative specifications for return loss at ports 110 / 170 for a particular application. In particular, the specifications indicate a return loss of -15 dB or less in the lower frequency band 0-1 GHz and in the higher frequency band 7-15 GHz. Additionally, as discussed, the graph also illustrates the return loss at such ports 110 / 170. Note that the return loss varies between -12 dB and -27 dB in the higher frequency band 7-15 GHz. Thus, particularly in the lower portion of the higher frequency band 7-15 GHz (e.g., between 7-9 GHz), the return loss does not meet the specification. Additionally, for the entire lower frequency band 0-1 GHz, the return loss is greater than -5 dB, which does not meet the specification by a large margin. Again, this is because the length L1 of the transmission lines 112 / 166 and 114 / 168 are each set for a particular frequency, such as 13 GHz in this example, where the return loss is best at -29 dB. The return loss increases for frequencies away from the particular frequency, where in this example the return loss does not meet specification below 9 GHz for the higher frequency bands, and does not meet specification for the entire lower frequency band.

[0032]

[0043] 3 illustrates a schematic diagram of another example signal power splitter / combiner 300 according to another aspect of the disclosure. An approach to improve the bandwidth over which a signal power splitter / combiner may be able to meet specifications in terms of insertion loss, isolation, and return loss is to add more stages to the signal power splitter / combiner. The power splitter / combiner 300 is an example of a multi-stage signal power splitter / combiner.

[0033]

[0044] In particular, the signal power splitter / combiner 300 includes a first signal port P1, a first transmission line 312 coupled between the first signal port P1 and a first intermediate node n1, a second transmission line 314 coupled between the first signal port P1 and a second intermediate node n2, and a first resistor R1 coupled between the first intermediate node n1 and the second intermediate node n2. The signal power splitter / combiner 300 further includes a third transmission line 316 coupled between the first intermediate node n1 and a second signal port P2, a fourth transmission line 318 coupled between the second intermediate node n2 and a third signal port P3, and a second resistor R2 coupled between the second signal port P2 and the third signal port P3.

[0034]

[0045] When the signal power splitter / combiner 300 is used as a power splitter, the signal power splitter / combiner 300 receives an input signal P in and receives an output signal P at ports P2 and P3. out1 and P out2 When the signal power splitter / combiner 300 is used as a power combiner, the signal power splitter / combiner 300 generates an input signal P in1 and P in2 and outputs an output signal P out Generate.

[0035]

[0046] When the ports P1, P2, and P3 each have a characteristic impedance Zo at a particular wavelength λ or frequency, the first transmission line 312 and the second transmission line 314 may each have substantially the same impedance Z1 (e.g., Z1=1.32·Zo) and substantially the same length L1 (e.g., λ / 4 at a particular frequency (e.g., 13 GHz)). Furthermore, the resistance of the first resistor R1 may be set to substantially 1.87·Zo. Additionally, the third transmission line 316 and the fourth transmission line 318 may each have substantially the same impedance Z2 (e.g., Z2=1.13·Zo) and substantially the same length L2 (e.g., λ / 4 at a particular frequency (e.g., 13 GHz)). Furthermore, the resistance of the second resistor R2 may be set to substantially 3.11·Zo.

[0036]

[0047] The transmission lines 312, 314, 316, and 318 may be implemented as microstrip, stripline, coplanar microstrip, suspended microstrip, or otherwise, where the transmission lines 312, 314, 316, and 318 are each implemented as a metallization strip disposed on a dielectric or semiconductor substrate. The resistors R1 and R2 may also be implemented as an appropriately sized thin film material, such as titanium nitride (TiN), disposed on a dielectric or semiconductor substrate.

[0037]

[0048] FIG. 4 illustrates a schematic diagram of another example signal power splitter / combiner 400 according to another aspect of the disclosure. The signal power splitter / combiner 400 may be an alternative implementation of the previously discussed signal power splitter / combiner 300. That is, the transmission lines 312, 314, 316, and 318 of the signal power splitter / combiner 300 each operate as an impedance transformer. However, another circuit implementing an equivalent impedance transformer uses discrete devices such as a pi network including shunt capacitors respectively coupled to both ends of a series inductor. By using discrete components instead of transmission lines, the signal power splitter / combiner 400 may be made smaller or more compact compared to the signal power splitter / combiner 300.

[0038]

[0049] The signal power splitter / combiner 400 includes a first signal port P1, a first impedance transformer 420, a second impedance transformer 430, a first resistor R1, a third impedance transformer 440, a fourth impedance transformer 450, a second resistor R2, a second signal port P2, and a third signal port P3. The first impedance transformer 420 is coupled between the first signal port P1 and a first intermediate node n1. The first impedance transformer 420 includes a first shunt capacitor C coupled between the first signal port P1 and a lower voltage rail (e.g., ground). 1A and a series inductor L coupled between the first signal port P1 and the first intermediate node n1. 1A and a second shunt capacitor C coupled between the first intermediate node n1 and a lower voltage rail (e.g., ground). 1B Includes:

[0039]

[0050] The second impedance transformer 430 is coupled between the first signal port P1 and the second intermediate node n2. The second impedance transformer 430 includes a first shunt capacitor C coupled between the first signal port P1 and a lower voltage rail (e.g., ground). 1Cand a series inductor L coupled between the first signal port P1 and the second intermediate node n2. 1B and a second shunt capacitor C coupled between the second intermediate node n2 and a lower voltage rail (e.g., ground). 1D The first resistor R1 is coupled between the first intermediate node n1 and the second intermediate node n2.

[0040]

[0051] The third impedance transformer 440 is coupled between the first intermediate node n1 and the second signal port P2. The third impedance transformer 440 includes a first shunt capacitor C coupled between the first intermediate node n1 and a lower voltage rail (e.g., ground). 2A and a series inductor L coupled between the first intermediate node n1 and the second signal port P2. 2A and a second shunt capacitor C coupled between the second signal port P2 and a lower voltage rail (e.g., ground). 2B Includes:

[0041]

[0052] The fourth impedance transformer 450 is coupled between the second intermediate node n2 and the third signal port P3. The fourth impedance transformer 450 includes a first shunt capacitor C coupled between the second intermediate node n2 and a lower voltage rail (e.g., ground). 2C and a series inductor L coupled between the second intermediate node n2 and the third signal port P3. 2B and a second shunt capacitor C coupled between the third signal port P3 and a lower voltage rail (e.g., ground). 2D Includes:

[0042]

[0053] When the signal power splitter / combiner 400 is used as a power splitter, the signal power splitter / combiner 400 receives an input signal P in and receives an output signal P at ports P2 and P3. out1 and P out2When the signal power splitter / combiner 400 is used as a power combiner, the signal power splitter / combiner 400 generates an input signal P in1 and P in2 and outputs an output signal P out Generate.

[0043]

[0054] If the ports P1, P2, and P3 each have a characteristic impedance Zo at a particular wavelength λ or frequency, the first impedance transformer 420 and the second impedance transformer 430 may be configured to perform substantially the same impedance transformation as the first transmission line 312 and the second transmission line 314, respectively. 1A , C 1B , C 1C , and C 1D , and inductor L 1A and L 1B This can be achieved by setting the capacitance and inductance of the capacitor C 1A , C 1B , C 1C , and C 1D may be substantially the same, and the capacitance of the inductor L 1A and L 1B may have substantially the same inductance.

[0044]

[0055] Similarly, the third impedance transformer 440 and the fourth impedance transformer 450 may be configured to perform substantially the same impedance transformation as the third transmission line 316 and the fourth transmission line 318, respectively. This is achieved by using a capacitor C 2A , C 2B , C 2C , and C 2D , and inductor L 2A and L 2B This can be achieved by setting the capacitance and inductance of the capacitor C 2A , C 2B , C 2C , and C 2Dmay be substantially the same, and the capacitance of the inductor L 2A and L 2B may have substantially the same inductance.

[0045]

[0056] Resistors R1 and R2 of signal power splitter / combiner 400 may be implemented to have substantially the same resistance as resistors R1 and R2 of power splitter / combiner 300, respectively.

[0046]

[0057] 5A-5C illustrate graphs of example specifications and responses associated with the signal power splitter / combiner 300 or 400 according to another aspect of the disclosure. The dimensions, units, and scale of the graphs are the same as those illustrated in FIGS. 2A-2C discussed previously. The graphs also illustrate shaded regions of the same specifications for insertion loss, isolation, and return loss, respectively.

[0047]

[0058] With respect to the insertion loss as illustrated in FIG. 5A, the graph shows that the insertion loss in dB between ports P1 and P2 (or P1 and P3) is still within −3 dB and −4 dB between frequencies 0 and 15 GHz, which meets the illustrative specification for insertion loss. However, due to the power splitter / combiner 300 or 400 having two stages compared to one stage in the power splitter / combiner 100 or 150, the power splitter / combiner 300 or 400 has a roll-off at higher frequencies compared to the roll-off associated with the power splitter / combiner 100 or 150. For example, in the one stage power splitter / combiner 100 or 150, the roll-off begins at about 14 GHz, whereas in the two stage power splitter / combiner 300 or 400, the roll-off begins at 15 GHz.

[0048]

[0059] Regarding the isolation as illustrated in FIG. 5B, the graph shows that the isolation between ports P2 and P3 is greater than −17 dB between frequencies 7-15 GHz, which meets the specification. From this, due to the two-stage power splitter / combiner 300 or 400, the bandwidth or frequency range over which the isolation meets the specification is expanded since the two stages introduce another isolation peak in the frequency range of interest (e.g., 7-15 GHz). For example, the isolation has peaks at 9.5 GHz and 14 GHz.

[0049]

[0060] Regarding the return loss as illustrated in FIG. 5C, the graph shows that the return loss is wider in the higher frequency range of interest (7-15 GHz). However, even in this frequency band, the return loss does not meet the specification for frequencies between 7-9.5 GHz. For the lower frequency range of interest (e.g., 0-1 GHz), the return loss does not meet the specification. From this, it may be possible that the two-stage signal power splitter / combiner 300 or 400 can improve the return loss in the higher frequency band by frequency-broadening the return loss therein. However, the signal power splitter / combiner 300 or 400 is still insufficient to meet the specification for a portion of the higher frequency band and the entire lower frequency band.

[0050]

[0061] FIG. 6 illustrates a schematic diagram of another exemplary signal power splitter / combiner 600 according to another aspect of the disclosure. In summary, to improve return loss specifications within a lower frequency band (e.g., 0-1 GHz) and the lower portion of a higher frequency band (e.g., 7-15 GHz), the signal power splitter / combiner 600 includes a load resistor R0 and an additional impedance transformer 610 coupled in series between the signal port P1 and a first impedance transformer 612 and a second impedance transformer 614. As discussed in more detail herein, the load resistor R0 improves the return loss within the lower frequency band such that the return loss within that frequency band meets the specification within that frequency band. The additional impedance transformer 610 improves the return loss within the lower portion of the higher frequency band such that the return loss across the higher frequency band meets the specification.

[0051]

[0062] In particular, the signal power splitter / combiner 600 includes a first signal port P1, a load resistor R0, a series transmission line 610, a first parallel transmission line 612 and a second parallel transmission line 614, a first resistor R1, a third parallel transmission line 616 and a fourth parallel transmission line 618, a second resistor R2, and a second signal port P2 and a third signal port P3. The load resistor R0 and the series transmission line 610 are coupled in series between the first signal port P1 and a first intermediate node n1. The first parallel transmission line 612 is coupled between the first intermediate node n1 and a second intermediate node n2. The second parallel transmission line 614 is coupled between the first intermediate node n1 and a third intermediate node n3. The first resistor R1 is coupled between the second intermediate node n2 and the third intermediate node n3. The third parallel transmission line 616 is coupled between the second intermediate node n2 and the second signal port P2. The fourth parallel transmission line 618 is coupled between the third intermediate node n3 and the third signal port P3. The second resistor R2 is coupled between the second signal port P2 and the third signal port P3.

[0052]

[0063] Similarly, when the signal power splitter / combiner 600 is used as a power splitter, the signal power splitter / combiner 600 outputs an input signal P in and receives an output signal P at ports P2 and P3. out1 and P out2 When the signal power splitter / combiner 600 is used as a power combiner, the signal power splitter / combiner 600 generates an input signal P in1 and P in2 and outputs an output signal P out The resistances, impedances Z0, Z1, and Z2, and lengths L1, L2, and L3 of resistors R0, R1, and R2 of transmission lines 610, 612 / 614, and 616 / 618 may be optimized to meet specifications for insertion loss, isolation, and return loss over one or more frequency bands of interest, such as those described with reference to FIGS.

[0053]

[0064] Similarly, the transmission lines 610, 612, 614, 616, and 618 may be implemented as microstrip, stripline, coplanar microstrip, suspended microstrip, or otherwise, where the transmission lines 610, 612, 614, 616, and 618 are each implemented as a metallization strip disposed on a dielectric or semiconductor substrate. The resistors R0, R1, and R2 may also be implemented as appropriately dimensioned thin film materials, such as titanium nitride (TiN), disposed on a dielectric or semiconductor substrate.

[0054]

[0065] 7 illustrates a schematic diagram of another example signal power splitter / combiner 700 according to another aspect of the disclosure. The signal power splitter / combiner 700 may be an alternative discrete component implementation of the signal power splitter / combiner 600 previously discussed.

[0055]

[0066] The signal power splitter / combiner 700 includes a signal port P1, a load resistor R0, a series impedance transformer 710, a first parallel impedance transformer 720, a second parallel impedance transformer 730, a first resistor R1, a third parallel impedance transformer 740, a fourth parallel impedance transformer 750, a second resistor R2, a second signal port P2, and a third signal port P3. The load resistor R0 and the series impedance transformer 710 are coupled in series between the first port P1 and a first intermediate node n1. The series impedance transformer 710 includes a first shunt capacitor C1 coupled between the first port P1 and a lower voltage rail (e.g., ground). 0A and a series inductor L coupled between the first port P1 and the first intermediate node n1. 0A and a second shunt capacitor C coupled between the first intermediate node n1 and a lower voltage rail (e.g., ground). 0B Includes:

[0056]

[0067] The first parallel impedance transformer 720 is coupled between the first intermediate node n1 and the second intermediate node n2. The first parallel impedance transformer 720 includes a first shunt capacitor C 1A and a series inductor L coupled between the first intermediate node n1 and the second intermediate node n2. 1A and a second shunt capacitor C coupled between the second intermediate node n2 and a lower voltage rail (e.g., ground). 1B Includes:

[0057]

[0068] The second parallel impedance transformer 730 is coupled between the first intermediate node n1 and the third intermediate node n3. The second parallel impedance transformer 730 includes a first shunt capacitor C 1C and a series inductor L coupled between the first intermediate node n1 and the third intermediate node n3. 1Band a second shunt capacitor C coupled between the third intermediate node n3 and a lower voltage rail (e.g., ground). 1D The first resistor R1 is coupled between the second intermediate node n2 and the third intermediate node n3.

[0058]

[0069] The third parallel impedance transformer 740 is coupled between the second intermediate node n2 and the second port P2. The third parallel impedance transformer 740 includes a first shunt capacitor C 2A and a series inductor L coupled between the second intermediate node n2 and the second port P2. 2A and a second shunt capacitor C coupled between the second port P2 and a lower voltage rail (e.g., ground). 2B Includes:

[0059]

[0070] The fourth parallel impedance transformer 750 is coupled between the third intermediate node n3 and the third port P3. The fourth impedance transformer 750 includes a first shunt capacitor C coupled between the third intermediate node n3 and a lower voltage rail (e.g., ground). 2C and a series inductor L coupled between the third intermediate node n3 and the third port P3. 2B and a second shunt capacitor C coupled between the third port P3 and a lower voltage rail (e.g., ground). 2D Includes:

[0060]

[0071] When the signal power splitter / combiner 700 is used as a power splitter, the signal power splitter / combiner 700 receives an input signal P in and receives an output signal P at ports P2 and P3. out1 and P out2 When the signal power splitter / combiner 700 is used as a power combiner, the signal power splitter / combiner 700 generates an input signal P in1 and P in2and outputs an output signal P out Generate.

[0061]

[0072] If ports P1, P2, and P3 each have a characteristic impedance Zo at a particular wavelength λ or frequency, then the load resistor R0 and the series impedance transformer 710 may be configured to improve the return loss (and / or other characteristic(s)) of the signal power splitter / combiner 700 in one or more desired frequency bands, such as portions of the lower frequency band (e.g., 0-1 GHz) and higher frequency bands (e.g., 7-15 GHz) previously discussed. This is achieved by adjusting the resistance of the load resistor R0 and the capacitor C 0A and C 0B and inductor L 0A This can be achieved by setting the capacitance and inductance of

[0062]

[0073] Similar to the signal power splitter / combiner 600, the first parallel impedance transformer 720 and the second parallel impedance transformer 730 may be configured to perform substantially the same impedance transformation as the first parallel transmission line 612 and the second parallel transmission line 614, respectively. This is achieved by using a capacitor C 1A , C 1B , C 1C , and C 1D , and inductor L 1A and L 1B Similarly, the third parallel impedance transformer 740 and the fourth parallel impedance transformer 750 may be configured to perform substantially the same impedance transformation as the third parallel transmission line 616 and the fourth parallel transmission line 618, respectively. This can be achieved by setting the capacitance and inductance of the capacitors C 2A , C 2B , C 2C , and C 2D , and inductor L 2A and L 2BThis can be achieved by setting the capacitance and inductance, respectively, of the power splitter / combiner 700. The resistors R1 and R2 of the power splitter / combiner 600 can be implemented to have substantially the same resistance as the resistors R1 and R2 of the power splitter / combiner 600, respectively.

[0063]

[0074] 8 illustrates an example Smith chart of impedances at ports of the signal power splitter / combiner 300 or 400 according to another embodiment of the present disclosure. At low frequencies, such as within a lower frequency band (e.g., 0-1 GHz), the impedance transformers 312, 314, 316, and 318, or 420, 430, 440, and 450, have substantially no effect on low frequency signals. This is because at low frequencies, the transmission lines 312, 314, 316, and 318 essentially act as shorts. Similarly, at low frequencies, the capacitors of the impedance transformers 420, 430, 440, and 450 essentially act as opens, and the inductors essentially act as shorts.

[0064]

[0075] From this, the impedance of the signal power splitter / combiner 300 or 400 from the perspective of port P1 is essentially R1 in parallel with R2. For example, if R1 is 1.87·Zo and R2 is 3.11·Zo, then the impedance presented by the power splitter / combiner 300 to port P1 is 0.7·Zo, taking into account the Zo present at ports P2 and P3 as well. From this, as shown in the Smith chart, the impedance at such low frequencies is essentially an electrical resistance with a resistance less than Zo, as represented by the circled number "1" on the Smith chart. This is the reason for the poor return loss at low frequencies. The area shown within the square labeled "2" is the impedance presented by the power splitter / combiner 300 to port P1 at higher frequencies, such as the higher frequency band (e.g., 7-15 GHz), where the return loss is better, but may not meet the specification for the entire higher frequency band, as previously discussed.

[0065]

[0076] 9 illustrates an example Smith chart of impedance at a port of a signal power splitter / combiner 600 or 700 according to another embodiment of the disclosure. The addition of a load resistor R0 into the power splitter / combiner 600 or 700 has the effect of increasing the resistance presented by the power splitter / combiner 600 or 700 to the port P1. Hence, the area indicated by the circled number "3", which represents the low frequency impedance, is closer to Zo than the area of ​​the circled number "1" of the Smith chart associated with the power splitter / combiner 300 or 400. Thus, the addition of a series load resistor R0 improves the impedance match or return loss in the lower frequency band.

[0066]

[0077] The addition of the series load resistor R0 not only improves the impedance match or return loss at lower frequencies, but may also adversely affect the impedance match in the higher frequency band. Thus, to compensate for any adverse effect on the impedance match or return loss in the higher frequency band due to the addition of the load resistor R0, the series impedance transformer 610 or 710 improves the impedance match or return loss in the higher frequency band. The Smith chart illustrates this with the square area numbered "4" compressed around Zo compared to the area "2" of the Smith chart related to the power splitter / combiner 300 or 400. Thus, the addition of the series impedance transformer 610 or 710 improves the impedance match or return loss in the higher frequency band.

[0067]

[0078] 10A-10C illustrate graphs of example specifications and responses associated with a signal power splitter / combiner 600 or 700 according to another aspect of the disclosure. The dimensions, units, and scale of the graphs are the same as those illustrated in FIGS. 2A-2C discussed previously. The graphs also illustrate shaded regions of the same specifications for insertion loss, isolation, and return loss, respectively.

[0068]

[0079] Regarding the insertion loss as illustrated in Figure 10A, the graph shows that the insertion loss in dB between ports P1 and P2 (or P1 and P3) is about 1 dB higher than the corresponding insertion loss of the power splitter / combiner 300 or 400, but is still less than the -5 dB specification between frequencies 0 and 15 GHz. From this, the addition of the load resistor R0 and the series impedance transformer 610 or 710 has a negligible effect on the insertion loss.

[0069]

[0080] Regarding the isolation as illustrated in Fig. 10B, the graph shows that the isolation between ports P2 and P3 is greater than -15 dB between the frequencies of 7 to 15 GHz, which meets the specification. From this, the addition of load resistor R0 and series impedance transformer 610 or 710 to the two-stage signal power splitter / combiner 300 or 400 does not significantly affect the isolation in the higher frequency band (e.g., 7 to 15 GHz).

[0070]

[0081] Regarding the return loss as illustrated in Figure 10C, the graph shows that the addition of the load resistor R0 and the series impedance transformer 610 or 710 greatly improves the impedance match or return loss in the lower and higher frequency bands (e.g., 0-1 GHz and 7-15 GHz), such that the return loss in both bands meets the specification of less than -15 dB.

[0071]

[0082] 11 illustrates a layout diagram of an example signal power splitter / combiner 1100 according to another aspect of the disclosure. The signal power splitter / combiner 1100 is an example layout implementation of the signal power splitter / combiner 700.

[0072]

[0083] The signal power splitter / combiner 1100 includes a signal port P1, a load resistor 1110, and a series impedance transformer including first and second shunt capacitors 1112 and a series inductor 1114. The signal power splitter / combiner 1100 further includes a first parallel impedance transformer including shunt capacitors 1116 and 1124 and a series inductor 1118. It is noted that the shunt capacitor 1116 is shared between the series impedance transformer and the first parallel impedance transformer. Similarly, the signal power splitter / combiner 1100 further includes a second parallel impedance transformer including shunt capacitors 1116 and 1126 and a series inductor 1120. It is also noted that the shunt capacitor 1116 is shared between the series impedance transformer and the second parallel impedance transformer.

[0073]

[0084] The signal power splitter / combiner 1100 further includes a third parallel impedance transformer including shunt capacitors 1124 and 1136 and a series inductor 1130. It is noted that the shunt capacitor 1124 is shared between the first parallel impedance transformer and the third parallel impedance transformer. Additionally, the signal power splitter / combiner 1100 further includes a fourth parallel impedance transformer including shunt capacitors 1126 and 1138 and a series inductor 1132. The shunt capacitor 1126 is shared between the second parallel impedance transformer and the fourth parallel impedance transformer. The signal power splitter / combiner 1100 further includes a first resistor 1128 and a second resistor 1134, and a second signal port P2 and a third signal port P3.

[0074]

[0085] The load resistor 1110 and the series impedance transformer 1112 / 1114 / 1116 are coupled in series between the first port P1 and the first intermediate node n1. The first parallel impedance transformer 1116 / 1118 / 1124 is coupled between the first intermediate node n1 and the second intermediate node n2. The second parallel impedance transformer 1116 / 1120 / 1126 is coupled between the first intermediate node n1 and the third intermediate node n3. The first resistor 1128 is coupled between the second intermediate node n2 and the third intermediate node n3.

[0075]

[0086] The third parallel impedance transformer 1124 / 1130 / 1136 is coupled between the second intermediate node n2 and the second port P2. The fourth parallel impedance transformer 1126 / 1132 / 1138 is coupled between the third intermediate node n3 and the third port P3. The second resistor 1134 is coupled between the second port P2 and the third port P3.

[0076]

[0087] As previously mentioned, resistors 1110, 1128, and 1134 may be implemented as appropriately sized sheets of resistive material such as TiN. Capacitors 1112, 1116, 1124, 1126, 1136, and 1138 may be implemented as metal-insulator-metal (MIM) capacitors. Inductors 1114, 1118, 1120, 1130, and 1132 may be implemented as metallization coiled strips formed on one or more metallization layers.

[0077]

[0088] When the signal power splitter / combiner 1100 is used as a power splitter, the signal power splitter / combiner 1100 receives an input signal P in and receives an output signal P at ports P2 and P3. out1 and P out2 When the signal power splitter / combiner 1100 is used as a power combiner, the signal power splitter / combiner 1100 generates an input signal P in1 and P in2and outputs an output signal P out Generate.

[0078]

[0089] 12 illustrates a flow diagram of an example method 1200 of power splitting a signal according to another aspect of the disclosure. The method 1200 includes receiving a first signal at a first signal port (block 1210). An example of a means for receiving a first signal at a first signal port includes signal ports P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, P36, P37, P38, P39, P40, P41, P42, P43, P44, P45, P46, P47, P48 11 , P 21A , and P 21B This includes any of the following:

[0079]

[0090] The method 1200 further includes propagating the first signal through the first resistor and the first impedance transformer to generate a second signal at the first intermediate node (block 1220). Examples of means for propagating the first signal through the first resistor and the first transformer to generate the second signal at the first intermediate node include any of the load resistors R0 and 1110 and series impedance transformers 610, 710, and 1112 / 1114 / 1116 described herein.

[0080]

[0091] The method 1200 also includes splitting the second signal at the first intermediate node to generate third and fourth signals (block 1230). Examples of means for splitting the second signal at the first intermediate node to generate third and fourth signals include any of the intermediate nodes n1 described herein.

[0081]

[0092] The method 1200 additionally includes propagating the third signal through the second impedance transformer toward the second signal port (Block 1240). Examples of means for propagating the third signal through the second impedance transformer toward the second signal port include any of the impedance transformers 612, 720, and 1116 / 1118 / 1124 described herein.

[0082]

[0093] Further, the method 1200 includes propagating the fourth signal through the third impedance transformer toward the third signal port (Block 1250). Examples of means for propagating the fourth signal through the third impedance transformer toward the third signal port include any of the impedance transformers 614, 730, and 1116 / 1120 / 1126 described herein.

[0083]

[0094] The method 1200 also includes electrically coupling the second signal port to the third signal port through a second resistor (block 1260). An example of a means for electrically coupling the second signal port to the third signal port through a second resistor includes coupling a second resistor R2 or 1134 between the second port P2 and the third port P3.

[0084]

[0095] The method 1200 may further include propagating a third signal from the second intermediate node to the second signal port through a fourth impedance transformer, where the second impedance transformer is coupled between the first intermediate node and the second intermediate node; propagating the fourth signal from the third intermediate node to the third signal port through a fifth impedance transformer, where the third impedance transformer is coupled between the first intermediate node and the third intermediate node; and electrically coupling the second intermediate node to the third intermediate node via a third resistor.

[0085]

[0096] An example of the means for propagating the third signal from the second intermediate node to the second signal port through the fourth impedance transformer includes any of the impedance transformers 616, 740, and 1124 / 1130 / 1136 described herein. An example of the means for propagating the fourth signal from the third intermediate node to the third signal port through the fifth impedance transformer includes any of the impedance transformers 618, 750, and 1126 / 1132 / 1138 described herein. An example of the means for electrically coupling the second intermediate node to the third intermediate node through a third resistor includes coupling a first resistor R1 or 1128 between the second intermediate node n2 and the third intermediate node n3.

[0086]

[0097] Additionally, the method 1200 may include splitting the third signal at the second signal port to generate a fifth and sixth signal. Examples of means for splitting the third signal at the second signal port to generate the fifth and sixth signals include any of the power splitters 1520 and 1530 as described herein. Additionally, the method 1200 may include splitting the fifth signal at the first signal port to generate the first and sixth signals. Examples of means for splitting the fifth signal at the first signal port to generate the first and sixth signals include any of the power splitters 1520 and 1530 as described herein.

[0087]

[0098] 13 illustrates a flow diagram of an example method 1300 of power combining signals according to another aspect of the disclosure. The method 1300 includes receiving a first signal at a first signal port (block 1310). Examples of means for receiving the first signal at the first signal port include any of the signal ports P2 described herein. The method 1300 further includes receiving a second signal at a second signal port (block 1320). Examples of means for receiving the second signal at the second signal port include any of the signal ports P3 described herein.

[0088]

[0099] Additionally, the method 1300 includes electrically coupling the first signal port to the second signal port through a first resistor (block 1330). An example of a means for electrically coupling the first signal port to the second signal port through a first resistor includes coupling a second resistor R2 or 1134 between the second port P2 and the third port P3 described herein.

[0089]

[0100] The method 1300 also includes propagating the first signal from the first signal port to the first intermediate node through the first impedance transformer (block 1340). Examples of means for propagating the first signal from the first signal port to the first intermediate node through the first impedance transformer include any of the impedance transformers 612, 720, and 1124 / 1118 / 1116 described herein.

[0090]

[0101] Further, the method 1300 includes propagating the second signal from the second signal port to the first intermediate node through the second impedance transformer (Block 1350). Examples of means for propagating the second signal from the second signal port to the first intermediate node through the second impedance transformer include any of the impedance transformers 614, 730, and 1126 / 1120 / 1116 described herein.

[0091]

[0102] The method 1300 also includes combining the first and second signals at the first intermediate node to generate a third signal (block 1360). Examples of means for combining the first and second signals at the first intermediate node to generate the third signal include any of the intermediate nodes n1 described herein.

[0092]

[0103] The method 1300 then includes propagating the third signal from the first intermediate node to the third signal port through the third impedance transformer and the second resistor (block 1370). Examples of means for propagating the third signal from the first intermediate node to the third signal port through the third impedance transformer and the second resistor include any of the series impedance transformers 610, 710, and 1116 / 1114 / 1112 and load resistors R0 and 1110 described herein.

[0093]

[0104] The method 1300 may further include propagating a third signal from the second signal port to the second intermediate node via a fourth impedance transformer, where the first impedance transformer is coupled between the first intermediate node and the second intermediate node; propagating a fourth signal from the third signal port to the third intermediate node via a fifth impedance transformer, where the second impedance transformer is coupled between the first intermediate node and the third intermediate node; and electrically coupling the second intermediate node to the third intermediate node via a third resistor.

[0094]

[0105] An example of the means for propagating the third signal from the second signal port to the second intermediate node through the fourth impedance transformer includes any of the impedance transformers 616, 740, and 1136 / 1130 / 1124 described herein. An example of the means for propagating the fourth signal from the third signal port to the third intermediate node through the fifth impedance transformer includes any of the impedance transformers 618, 750, and 1138 / 1132 / 1126 described herein. An example of the means for electrically coupling the second intermediate node to the third intermediate node through the third resistor includes coupling of a first resistor R1 or 1128 between the second intermediate node n2 and the third intermediate node n3.

[0095]

[0106] Additionally, the method 1300 may include combining the third signal with the fourth signal at the third signal port to generate a fifth signal. Means for combining the third signal with the fourth signal at the third signal port to generate the fifth signal include any of the power splitters 1520 and 1530 as described herein. In addition, the method 1300 may include combining the fourth and fifth signals at the first signal port to generate the first signal. Examples of means for combining the fourth and fifth signals at the first signal port to generate the first signal include any of the power splitters 1520 and 1530 as further described herein.

[0096]

[0107] 14 illustrates a block diagram of an example wireless communication device 1400 according to another aspect of the disclosure. The wireless communication device 1400 may be implemented as a smartphone, a tablet device, a laptop computer, a desktop computer, a wearable device (e.g., a smart watch, an activity monitoring device, a health monitoring device, etc.), an Internet of Things (IoT) device, etc.

[0097]

[0108] The wireless communication device 1400 includes at least one antenna 1410 (e.g., a set of antennas, or one or more phased array antennas, etc.), a set of transceiver chains 1420, a signal power combiner 1440, a signal power splitter 1450, and signal processing circuitry 1460. Each of the set of transceiver chains 1420 may include a signal routing circuitry 1422 configured to route signals to and from the at least one antenna 1410, a low noise amplifier (LNA) 1424, a phase shifter 1426, a downconversion mixer 1428 (which receives a local oscillator (LO) signal), and an intermediate frequency (IF) or baseband (BB) filter 1430. These devices are collectively configured to convert RF signals received via the at least one antenna 1410 to received IF or BB signals.

[0098]

[0109] The signal power combiner 1440 includes inputs respectively coupled to outputs of the set of transceiver chains 1420. For example, the inputs of the signal power combiner 1140 may be respectively coupled to outputs of corresponding received IF or BB filters 1430 of the set of transceiver chains 1420. The inputs of the signal power combiner 1140 are configured to receive IF or BB signals from the set of transceiver chains 1420. Considering the previous example, one of the set of transceiver chains 1420 may be configured to generate an IF signal in a higher frequency band (e.g., 7-15 GHz), and another one of the set of transceiver chains 1420 may be configured to generate an IF signal in a lower frequency band (e.g., 0-1 GHz).

[0099]

[0110] The signal power combiner 1440 is configured to combine the received IF or BB signals to generate a combined received IF or BB signal at its output. The signal power combiner 1440 may be implemented by any of the signal power combiners described herein. The output of the signal power combiner 1440 is coupled to an input of the signal processing circuit 1460. The signal processing circuit 1460 is configured to process the combined received IF or BB signal to recover data therefrom.

[0100]

[0111] The signal processing circuit 1460 is configured to generate a combined transmit IF or BB signal including data. The signal processing circuit 1460 includes an output coupled to an input of the signal power splitter 1450, at which the combined transmit IF or BB signal is generated. The signal power splitter 1450 is configured to power split the combined transmit IF or BB signal to generate a set of transmit IF or BB signals. The signal power splitter 1450 may be implemented by any of the signal power splitters described herein. The signal power splitter 1450 includes a set of outputs respectively coupled to inputs of the set of transceiver chains 1420, at which the set of transmit IF or BB signals is generated.

[0101]

[0112] Each of the set of transceiver chains 1420 may further include an upconversion mixer 1432 (receiving an LO signal), a radio frequency (RF) filter 1434, a phase shifter 1436, and a set of one or more amplifiers 1438 (e.g., preamplifiers, power amplifiers (PAs), etc.). These devices are collectively configured to convert the transmit IF or BB signals received from the signal power splitter 1450 to generate transmit RF signals, which are provided to at least one antenna 1410 via the signal routing circuitry 1422 for wireless transmission. The set of transmit IF or BB signals generated by the signal power splitter 1450 are provided to corresponding upconversion mixers 1432 of the set of transceiver chains 1420, respectively.

[0102]

[0113] 15 illustrates a block diagram of another example signal power splitter / combiner 1500 according to another aspect of the disclosure. The power splitter / combiner 1500 may include a hierarchical set of signal power splitters / combiners, each of which may be configured by any of the signal power splitters / combiners previously discussed.

[0103]

[0114] In particular, the signal power splitter / combiner 1500 includes a signal port P11 , P 12 , and P 13 The first hierarchical level signal power splitter / combiner 1510 may be implemented by any of the previously discussed signal power splitters / combiners 600, 700, and 1100, and includes a signal port P 11 , P 12 , and P 13 correspond to signal ports P1, P2, and P3 of signal power splitter / combiners 600, 700, and 1100, respectively.

[0104]

[0115] The signal power splitter / combiner 1500 has a signal port P 21A , P 22A , and P 23A The first second hierarchical level signal power splitter / combiner 1520 may be implemented by any of the previously discussed signal power splitters / combiners 600, 700, and 1100, and includes a signal port P 21A , P 22A , and P 23A correspond to signal ports P1, P2, and P3 of signal power splitter / combiners 600, 700, and 1100, respectively.

[0105]

[0116] The signal power splitter / combiner 1500 has a signal port P 21B , P 22B , and P 23B The second hierarchical level signal power splitter / combiner 1530 may be implemented by any of the previously discussed signal power splitters / combiners 600, 700, and 1100, and includes a signal port P 21B , P 22B , and P 23B correspond to signal ports P1, P2, and P3 of signal power splitter / combiners 600, 700, and 1100, respectively.

[0106]

[0117] When the signal power splitter / combiner 1500 is used as a power splitter, the signal power splitter 1500 is 11 In the input signal P in , and the first hierarchical level splitter 1510 splits the input signal P in Split the power to port P 12 and P 13 In the first hierarchical level output signal P out11 and P out12 The first and second hierarchical level signal power splitters 1520 generate ports P 21A In the first hierarchical level output signal P out11 Receives signal P out11 Split the power to port P 22A and P 23B In the second hierarchical level output signal P out21 and P ou22 The second hierarchical level signal power splitter 1530 generates a port P 21B In the second hierarchical level output signal P out12 Receives signal P out12 Split the power to port P 22B and P 23B In the second hierarchical level output signal P out23 and P out24 It should be appreciated that there may be more than two hierarchical levels of signal power splitters.

[0107]

[0118] When the signal power splitter / combiner 1500 is used as a power combiner, the signal power splitter 1500 is 22A , P 23A , P 22B , and P 23B In the input signal P in1 , P in2 , P in 3, and P in 4. The first and second hierarchical level signal power combiners 1520 receive the input signal P in1 and P in2 The power is combined to port P 21AIn the first hierarchical level input signal P in11 Similarly, the second hierarchical level signal power combiner 1530 generates an input signal P in 3 and P in 4 are power-combined to port P 21B In the second first hierarchical level input signal P in12 The first hierarchical level signal power combiner 1510 generates a 12 and P 13 In the first hierarchical level input signal P in11 and P in12 and receive the signal P in1 1 and P in12 The power is combined to port P 11 At the output signal P out It should be appreciated that there may be more than two hierarchical levels of signal power combiners.

[0108]

[0119] The example shown in Figure 15 is a 1:4 power splitter or a 4:1 power combiner. The maximum signal power division or combination is 2 n where n is the number of hierarchical levels. For example, in this example, n=2. From this, the maximum number of signal splitting or combining is 2 2 or 4. Maximum of 2 for signal splitting or combining n An odd or even number other than 1500 may be achieved by removing one or more power splitters / combiners at the highest hierarchical level. For example, a 1:3 power splitter or a 3:1 power combiner may be achieved using power splitter / combiner 1530 by removing power splitter / combiner 1500. Another example is three hierarchical levels (n=3), where the highest hierarchical level has six power splitters / combiners instead of the maximum of eight.

[0109]

[0120] The following provides a summary of aspects of the present disclosure:

[0110]

[0121] Aspect 1: An apparatus including a first signal port, a first resistor, a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node, a second impedance transformer coupled between the first intermediate node and a second signal port, a third impedance transformer coupled between the first intermediate node and a third signal port, and a second resistor coupled between the second signal port and the third signal port.

[0111]

[0122] Aspect 2: The apparatus of aspect 1, wherein the first impedance transformer includes a first transmission line having a first impedance and a first length.

[0112]

[0123] Aspect 3: The apparatus of aspect 1 or 2, wherein the second impedance transformer includes a second transmission line having a second impedance and a second length.

[0113]

[0124] Aspect 4: The apparatus of any one of Aspects 1 to 3, wherein the third impedance transformer includes a third transmission line having a third impedance and a third length.

[0114]

[0125] Aspect 5: The apparatus of Aspect 4, wherein the second impedance is substantially the same as the third impedance and the second length is substantially the same as the third length.

[0115]

[0126] Aspect 6: An apparatus described in any one of Aspects 1 to 5, wherein the first impedance transformer includes a first shunt capacitor, a first series inductor, and a second shunt capacitor, the first and second shunt capacitors being respectively coupled to both ends of the first series inductor.

[0116]

[0127] Aspect 7: The apparatus of any one of aspects 1 to 6, wherein the second impedance transformer includes a third shunt capacitor, a second series inductor, and a fourth shunt capacitor, the third and fourth shunt capacitors being respectively coupled to both ends of the second series inductor.

[0117]

[0128] Aspect 8: The apparatus of any one of aspects 1 to 7, wherein the third impedance transformer includes a fifth shunt capacitor, a third series inductor, and a sixth shunt capacitor, the fifth and sixth shunt capacitors being respectively coupled to both ends of the third series inductor.

[0118]

[0129] Aspect 9: The apparatus of aspect 9, wherein the third, fourth, fifth, and sixth shunt capacitors have substantially the same capacitance, and the second and third series inductors have substantially the same inductance.

[0119]

[0130] Aspect 10: An apparatus described in any one of aspects 6 to 9, wherein the second impedance transformer includes a second series inductor and a third shunt capacitor, the second shunt capacitor being shared between the first impedance transformer and the second impedance transformer, and the second and third shunt capacitors being respectively coupled to both ends of the second series inductor.

[0120]

[0131] Aspect 11: The apparatus of Aspect 10, wherein the third impedance transformer includes a third series inductor and a fourth shunt capacitor, the second shunt capacitor is shared between the first impedance transformer, the second impedance transformer, and the third impedance transformer, and the second and fourth shunt capacitors are respectively coupled to both ends of the third series inductor.

[0121]

[0132] Aspect 12: The apparatus of any one of aspects 1-11, further including a fourth impedance transformer coupled between the second intermediate node and the second signal port, where the second impedance transformer is coupled between the first intermediate node and the second intermediate node, a fifth impedance transformer coupled between the third intermediate node and the third signal port, and a third resistor coupled between the second intermediate node and the third intermediate node, where the third impedance transformer is coupled between the first intermediate node and the third intermediate node.

[0122]

[0133] Aspect 13: The apparatus of aspect 12, wherein the fourth impedance transformer includes a first transmission line having a first impedance and a first length, and the fifth impedance transformer includes a second transmission line having a second impedance and a second length, wherein the first impedance is substantially the same as the second impedance, and the first length is substantially the same as the second length.

[0123]

[0134] Aspect 14: The apparatus of aspect 12, wherein the fourth impedance transformer includes a first shunt capacitor, a first series inductor, and a second shunt capacitor, the first and second shunt capacitors being respectively coupled to both ends of the first series inductor; the fifth impedance transformer includes a third shunt capacitor, a second series inductor, and a fourth shunt capacitor, the third and fourth shunt capacitors being respectively coupled to both ends of the second series inductor, the first, second, third, and fourth shunt capacitors having substantially the same capacitance, and the first and second series inductors having substantially the same inductance.

[0124]

[0135] Aspect 15: A method comprising: receiving a first signal at a first signal port; propagating the first signal through a first resistor and a first impedance transformer to generate a second signal at a first intermediate node; splitting the second signal at the first intermediate node to generate third and fourth signals; propagating a third signal through the second impedance transformer towards a second signal port; propagating the fourth signal through the third impedance transformer towards a third signal port; and electrically coupling the second signal port to the third signal port via the second resistor.

[0125]

[0136] Aspect 16: The method of aspect 15, wherein the first, second, and third impedance transformers each include a transmission line.

[0126]

[0137] Aspect 17: The method of aspect 15, wherein the first, second, and third impedance transformers each include a first shunt capacitor, a series inductor, and a second shunt capacitor, the first and second shunt capacitors being respectively coupled to both ends of the series inductor.

[0127]

[0138] Aspect 18: The method of any one of claims 15-17, further comprising: propagating a third signal from the second intermediate node to the second signal port through a fourth impedance transformer, where the second impedance transformer is coupled between the first intermediate node and the second intermediate node; propagating a fourth signal from the third intermediate node to the third signal port through a fifth impedance transformer, where the third impedance transformer is coupled between the first intermediate node and the third intermediate node; and electrically coupling the second intermediate node to the third intermediate node via a third resistor.

[0128]

[0139] Aspect 19: The method of any one of aspects 15 to 18, further comprising splitting the third signal at the second signal port to generate fifth and sixth signals.

[0129]

[0140] Example 20: The method of any one of Examples 15 to 19, further splitting the fifth signal to generate the first signal and the sixth signal.

[0130]

[0141] Aspect 21: A method comprising: receiving a first signal at a first signal port; receiving a second signal at a second signal port; electrically coupling the first signal port to the second signal port via a first resistor; propagating the first signal from the first signal port to a first intermediate node via a first impedance transformer; propagating the second signal from the second signal port to the first intermediate node via a second impedance transformer; combining the first and second signals at the first intermediate node to generate a third signal; and propagating the third signal from the first intermediate node to a third signal port via the third impedance transformer and the second resistor.

[0131]

[0142] Aspect 22: The method of aspect 21, wherein the first, second, and third impedance transformers each include a transmission line.

[0132]

[0143] Aspect 23: The method of aspect 21, wherein the first, second, and third impedance transformers each include a first shunt capacitor, a series inductor, and a second shunt capacitor, the first and second shunt capacitors being respectively coupled to both ends of the series inductor.

[0133]

[0144] Aspect 24: The method of any one of aspects 21 to 23, further comprising: propagating a first signal from the first signal port to the second intermediate node via a fourth impedance transformer, where the first impedance transformer is coupled between the first intermediate node and the second intermediate node; propagating a second signal from the second signal port to a third intermediate node via a fifth impedance transformer, where the second impedance transformer is coupled between the first intermediate node and the third intermediate node; and electrically coupling the second intermediate node to the third intermediate node via a third resistor.

[0134]

[0145] Example 25: The method of any one of Examples 21 to 24, further comprising combining the third signal with the fourth signal to generate a fifth signal.

[0135]

[0146] Example 26: The method of any one of Examples 21 to 25, further comprising combining the fourth and fifth signals to generate the first signal.

[0136]

[0147] Aspect 27: A wireless communication device including at least one antenna, a set of transceiver chains coupled to the at least one antenna, and a signal power splitter or combiner coupled to the set of transceiver chains, the signal power splitter or combiner including a first signal port, a first resistor, a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node, a second impedance transformer coupled between the first intermediate node and a second signal port, a third impedance transformer coupled between the first intermediate node and a third signal port, and a second resistor coupled between the second signal port and the third signal port.

[0137]

[0148] Aspect 28: A wireless communication device as described in aspect 27, wherein the first signal port is coupled to an input of a signal processing circuit, and the second and third ports are respectively coupled to inputs of a set of transceiver chains.

[0138]

[0149] Aspect 29: A wireless communication device as described in aspect 27, wherein the second and third signal ports are respectively coupled to outputs of a set of transceiver chains, and the first signal port is coupled to an input of a signal processing circuit.

[0139]

[0150] Aspect 30: A wireless communication device as described in any one of aspects 27 to 29, wherein the signal power splitter or combiner further comprises a fourth impedance transformer coupled between the second intermediate node and the second signal port, where the second impedance transformer is coupled between the first intermediate node and the second intermediate node, a fifth impedance transformer coupled between the third intermediate node and the third signal port, and where the third impedance transformer is coupled between the first intermediate node and the third intermediate node, and a third resistor coupled between the second intermediate node and the third intermediate node.

[0140]

[0151] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

**Claim 1** An apparatus comprising: a first signal port; a first resistor; a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node; a second impedance transformer coupled between the first intermediate node and a second signal port; a third impedance transformer coupled between the first intermediate node and a third signal port; a second resistor coupled between the second signal port and the third signal port. The apparatus as claimed in claim 1. **Claim 2** The apparatus as claimed in claim 1, wherein the first impedance transformer comprises a first transmission line having a first impedance and a first length, the second impedance transformer comprises a second transmission line having a second impedance and a second length, and the third impedance transformer comprises a third transmission line having a third impedance and a third length. **Claim 3** The apparatus as claimed in claim 2, wherein the second impedance is substantially the same as the third impedance, and the second length is substantially the same as the third length. **Claim 4** The apparatus as claimed in claim 1, wherein the first impedance transformer comprises a first shunt capacitor, a first series inductor, and a second shunt capacitor, and the first and second shunt capacitors are respectively coupled to both ends of the first series inductor. **Claim 5** The apparatus as claimed in claim 4, wherein the second impedance transformer comprises a third shunt capacitor, a second series inductor, and a fourth shunt capacitor, and the third and fourth shunt capacitors are respectively coupled to both ends of the second series inductor. **Claim 6** The apparatus as claimed in claim 5, wherein the third impedance transformer comprises a fifth shunt capacitor, a third series inductor, and a sixth shunt capacitor, and the fifth and sixth shunt capacitors are respectively coupled to both ends of the third series inductor, wherein the third, fourth, fifth, and sixth shunt capacitors have substantially the same capacitance, and the second and third series inductors have substantially the same inductance. The apparatus as claimed in claim 5. **Claim 7** The second impedance transformer includes a second series inductor and a third shunt capacitor. The second shunt capacitor is shared between the first impedance transformer and the second impedance transformer. The second and third shunt capacitors are respectively coupled to both ends of the second series inductor. The third impedance transformer includes a third series inductor and a fourth shunt capacitor. The second shunt capacitor is shared between the first impedance transformer, the second impedance transformer, and the third impedance transformer. The second and fourth shunt capacitors are respectively coupled to both ends of the third series inductor. The device according to claim 4.

8. A fourth impedance transformer coupled between the second intermediate node and the second signal port, wherein the second impedance transformer is coupled between the first intermediate node and the second intermediate node. A fifth impedance transformer coupled between the third intermediate node and the third signal port, wherein the third impedance transformer is coupled between the first intermediate node and the third intermediate node. A third resistor coupled between the second intermediate node and the third intermediate node. The device according to claim 1, further comprising the same.

9. The fourth impedance transformer includes a first transmission line having a first impedance and a first length. The fifth impedance transformer includes a second transmission line having a second impedance and a second length. The first impedance is substantially the same as the second impedance, and the first length is substantially the same as the second length. The device according to claim 8.

10. The fourth impedance transformer includes a first shunt capacitor, a first series inductor, and a second shunt capacitor. The first and second shunt capacitors are respectively coupled to both ends of the first series inductor. The fifth impedance transformer includes a third shunt capacitor, a second series inductor, and a fourth shunt capacitor. The third and fourth shunt capacitors are respectively coupled to both ends of the second series inductor. The device according to claim 8, wherein the first, second, third, and fourth shunt capacitors have substantially the same capacitance, and the first and second series inductors have substantially the same inductance.

11. A method comprising: receiving a first signal at a first signal port; propagating the first signal through a first resistor and a first impedance transformer to generate a second signal at a first intermediate node; dividing the second signal at the first intermediate node to generate third and fourth signals; propagating the third signal through a second impedance transformer toward a second signal port; propagating the fourth signal through a third impedance transformer toward a third signal port; electrically coupling the second signal port to the third signal port via a second resistor A method comprising the above steps.

12. propagating the third signal from a second intermediate node to the second signal port through a fourth impedance transformer, wherein the second impedance transformer is coupled between the first intermediate node and the second intermediate node; propagating the fourth signal from a third intermediate node to the third signal port through a fifth impedance transformer, wherein the third impedance transformer is coupled between the first intermediate node and the third intermediate node; electrically coupling the second intermediate node to the third intermediate node via a third resistor The method according to claim 11, further comprising the above steps.

13. The method according to claim 11, further comprising dividing the third signal at the second signal port to generate fifth and sixth signals.

14. The method according to claim 11, further comprising dividing a fifth signal to generate the first signal and a sixth signal.

15. A wireless communication device comprising: at least one antenna; a set of transceiver chains coupled to the at least one antenna; the device according to claim 1 coupled to the set of transceiver chains; A wireless communication device comprising the above components.

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