Mitigating Duty Cycle Distortion Due to Asymmetric Aging

Abstract

The system (305) includes a first park circuit (310) having a signal input (312), an output (314), and a control input (316). The system also includes a first signal path (320) having an input (322) and an output (324), the input of the first signal path being coupled to the output of the first park circuit. The system also includes a second park circuit (330) having a signal input (332), an output (334), and a control input (336), the signal input of the second park circuit being coupled to the output of the first signal path. The system further includes a second signal path (340) having an input (342) and an output (344), the input of the second signal path being coupled to the output of the second park circuit.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 404,919, filed in the United States Patent Office on Aug. 17, 2021, the contents of which are incorporated herein in their entirety as if fully set forth below and for all applicable purposes. [Background technology]

[0002] Field Aspects of the present disclosure relate generally to duty cycle distortion, and more specifically, to mitigating duty cycle distortion.

[0003] background A circuit may suffer from aging effects such as bias temperature instability (BTI), which may degrade the performance of the circuit over time. For example, BTI stress in a signal path (e.g., a clock path) of a circuit during idle mode may cause duty cycle distortion in the signal path over time, which may result in timing problems (e.g., timing violations) in the circuit. Summary of the Invention

[0004] SUMMARY OF THE DISCLOSURE The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This Summary is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] A first aspect relates to a system. The system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, the input of the first signal path being coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, the signal input of the second park circuit being coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, the input of the second signal path being coupled to the output of the second park circuit.

[0006] A second aspect relates to a method for mitigating duty cycle distortion in a system, the system including a first signal path and a second signal path, the method including, in an active mode, transmitting a clock signal from a clock source to a circuit via the first signal path and the second signal path, the method also including, in an idle mode, parking an input of the first signal path at a first logic state and parking an input of the second signal path at a second logic state. [Brief description of the drawings]

[0007] [Figure 1A] 1 illustrates an example of a signal path including a delay buffer in accordance with some aspects of the present disclosure. [Figure 1B] 1 illustrates an example in which the input of a signal path is parked low in idle mode, according to some aspects of the present disclosure. [Figure 1C] 1 illustrates an example of duty cycle distortion in a signal path due to asymmetric aging, in accordance with some aspects of the present disclosure. [Figure 1D] 1 illustrates an example in which the input of a signal path is parked high in idle mode, according to some aspects of the present disclosure. [Figure 1E] 1 illustrates another example of duty cycle distortion in a signal path due to asymmetric aging, in accordance with some aspects of the present disclosure. [Figure 2A]1 illustrates an example of a signal path and clock gating circuit according to some aspects of the present disclosure. [Figure 2B] 1 illustrates an example of logic states in signal paths and clock gating circuits in an idle mode in accordance with some aspects of the present disclosure. [Figure 2C] 1 illustrates an example implementation of a delay buffer in accordance with certain aspects of the present disclosure. [Figure 3A] 1 illustrates an example of a signal path with duty cycle distortion mitigation in accordance with some aspects of the present disclosure. [Figure 3B] 1 illustrates an example of logic states in signal paths in an idle mode in accordance with some aspects of the present disclosure. [Figure 3C] 1 illustrates another example of a signal path with duty cycle distortion mitigation in accordance with some aspects of the present disclosure. [Figure 3D] 3B illustrates an example of an aging path in the signal path of FIG. 3A in accordance with some aspects of the disclosure. [Figure 3E] 3D illustrates an example of an aging path in the signal path of FIG. 3C, according to some aspects of the disclosure. [Figure 4A] 1 illustrates an example implementation of a park-high circuit and a park-low circuit in accordance with some aspects of the present disclosure. [Figure 4B] 1 illustrates another example implementation of park-high and park-low circuits in accordance with some aspects of the present disclosure. [Figure 4C] 1 illustrates yet another example implementation of a park-high circuit and a park-low circuit in accordance with some aspects of the present disclosure. [Figure 5A] 1 illustrates an example implementation of a park-high circuit in accordance with some aspects of the present disclosure. [Figure 5B] 1 illustrates an example implementation of a park-row circuit in accordance with some aspects of the present disclosure. [Figure 6] 1 illustrates an example of a system including a control circuit configured to sequence a park-high circuit and a park-low circuit in accordance with some aspects of the present disclosure. [Figure 7]4 is a flowchart illustrating an example sequence for transitioning a system to an idle mode in accordance with certain aspects of the present disclosure. [Figure 8A] 1 illustrates an example implementation of a per-row circuit with a status output in accordance with some aspects of the present disclosure. [Figure 8B] 1 illustrates an example implementation of a park-high circuit with a status output in accordance with some aspects of the present disclosure. [Figure 9] 6 is a flowchart illustrating another example sequence for transitioning a system to an idle mode in accordance with certain aspects of the present disclosure. [Figure 10] 4 is a flowchart illustrating an example sequence for transitioning a system to an active mode in accordance with some aspects of the present disclosure. [Figure 11] 6 is a flowchart illustrating another example sequence for transitioning a system to an active mode in accordance with certain aspects of the present disclosure. [Figure 12] 1 illustrates an example of a system including multiple clock branches in accordance with some aspects of the present disclosure. [Figure 13A] 1 illustrates an example implementation of a park-low circuit and a park-high circuit in accordance with some aspects of the present disclosure. [Figure 13B] 13B illustrates an example of logic states in a system including the park-low and park-high circuits of FIG. 13A in accordance with some aspects of the present disclosure. [Figure 14A] 1 illustrates an example implementation of a first park high circuit and a second park high circuit in accordance with some aspects of the present disclosure. [Figure 14B] 14B illustrates an example of logic states in a system including the first park-high circuit and the second park-high circuit of FIG. 14A in accordance with some aspects of the disclosure. [Figure 15A] 1 illustrates an example of a system including a first signal path having an even number of delay buffers and a second signal path having an odd number of delay buffers in accordance with some aspects of the present disclosure. [Figure 15B]15B illustrates one embodiment of a park-row circuit coupled between the output of the second signal path of FIG. 15A and the circuit, according to some aspects of the disclosure. [Figure 16] 1 illustrates another example of a system including a first signal path having an even number of delay buffers and a second signal path having an odd number of delay buffers in accordance with some aspects of the present disclosure. [Figure 17] 1 illustrates an example of a system including a first signal path having an odd number of delay buffers and a second signal path having an even number of delay buffers in accordance with some aspects of the present disclosure. [Figure 18A] 1 illustrates an example of a system including a first park circuit and a second park circuit, according to some aspects of the disclosure. [Figure 18B] 18A illustrates an example of one of many circuits that may be included in the exemplary system 1805 shown in FIG. 18A in accordance with some aspects of the disclosure. [Figure 19] 1 illustrates an example of a system including a multiplexer for alternating an input of a signal path between low and high over multiple idle periods in accordance with some aspects of the present disclosure. [Figure 20] 1 is a timing diagram illustrating logic states at the inputs of signal paths over multiple active periods and multiple idle periods in accordance with some aspects of the disclosure. FIG. [Figure 21] 1 illustrates one embodiment of a parkrow circuit coupled between an output of a signal path and a circuit in accordance with some aspects of the present disclosure. [Figure 22] 1 illustrates another example of a system including a multiplexer for alternating an input of a signal path between low and high over multiple idle periods in accordance with some aspects of the present disclosure. [Diagram 23] 1 is a flowchart illustrating a method for mitigating duty cycle distortion in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The detailed description of the present invention, described below in connection with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0009] Aging effects such as bias temperature instability (BTI) can degrade the performance of a circuit over time. For example, BTI stress in a signal path (e.g., a clock path) of a circuit during idle mode can cause duty cycle distortion in the signal path over time, which can result in timing issues (e.g., timing violations) in the circuit. In one example, the signal path can include a high-speed clock path that has tight timing margin(s) (e.g., setup time and / or hold time) and may be more susceptible to timing violations due to duty cycle distortion. In this example, the high-speed clock path can carry a high-speed clock signal that operates at a higher frequency than other clock signals in the system.

[0010] An example of a duty cycle distortion induced by BTI stress will now be described with reference to Figures 1A-1E. Figure 1A shows an example of a signal path 105 that includes multiple delay buffers 120-1-120-8 coupled in series. For example, signal path 105 may be a clock path configured to distribute a timing signal, such as a clock signal, from a clock source to one or more circuits.

[0011] In the embodiment shown in FIG. 1A, each of delay buffers 120-1 through 120-8 is implemented using a respective complementary inverter that includes a first respective transistor 125-1 through 125-8 (e.g., an n-type field effect transistor (NFET)) and a second respective transistor 130-1 through 130-8 (e.g., a p-type field effect transistor (PFET)). However, it should be understood that other types of circuits or logic gates may be used to implement each of delay buffers 120-1 through 120-8.

[0012] In an embodiment in which signal path 105 is a clock path, a clock gating circuit (not shown) may be coupled between the clock source and input 108 of signal path 105. In this embodiment, the clock gating circuit may be configured to pass (i.e., ungate) the clock signal in an active mode and to gate (i.e., block) the clock signal in an idle mode.

[0013] 1B illustrates an embodiment in which signal path input 108 is parked low (i.e., logic 0) in idle mode. FIG. 1B also illustrates the logic state at output 110 of signal path 105, which in this embodiment is low (i.e., logic 0). In this embodiment, transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8 are turned on in idle mode, and transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8 are turned off in idle mode. 1B shows an aging path 140 that passes through transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8 that are turned on in idle mode. As used herein, an "aging path" is a path that passes through transistors that are turned on in idle mode. The transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8 that are turned on in the idle mode are stressed in the idle state, which causes the transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8 to age more than the transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8 that are turned off in the idle mode. Therefore, the aging is different between transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8 stressed in idle mode and transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8, thereby resulting in asymmetric BTI aging in signal path 105.

[0014] In this example, asymmetric aging shifts the threshold voltages of transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8, thereby increasing the falling edge delay at output 110 of signal path 105 relative to the rising edge delay at output 110 of signal path 105. This is because the falling edge propagates to output 110 of signal path 105 via aging path 140 (i.e., transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8 in aging path 140 turn on to propagate the falling edge to output 110), but the rising edge does not propagate to output 110 of signal path 105 via aging path 140. The increase in falling edge delay relative to the rising edge delay causes duty cycle distortion in signal path 105 .

[0015] An example of duty cycle distortion is illustrated in the timing diagram shown in Figure 1C. In the example shown in Figure 1C, a clock signal 150 is input to an input 108 of a signal path 105 (e.g., a clock path) in an active mode. In this example, the clock signal 150 at the input 108 of the signal path has a 50% duty cycle. Figure 1C also shows a clock signal 160 at the output 110 of the signal path 105 after the clock signal 150 has propagated through the signal path 105. The signal path 105 delays the rising edge of the clock signal 160 at the output 110 by a delay T r , so that the falling edge of the clock signal 160 is delayed by a delay T f As shown in Figure 1C, the falling edge delay T f is the delay T of the rising edge due to the asymmetric aging of the transistors in the signal path 105 described above. rThis is because the falling edge propagates through aging path 140 to output 110, but the rising edge does not propagate through aging path 140 to output 110. The longer delay of the falling edge increases the duty cycle of clock signal 160 at output 110 (i.e., results in a duty cycle greater than 50% at output 110). Thus, in this example, the duty cycle distortion due to asymmetric aging increases the duty cycle of the clock signal.

[0016] Asymmetric aging also occurs when input 108 of signal path 105 is parked high in idle mode. In this regard, Figure 1D illustrates an embodiment in which input 108 is parked high (i.e., logic 1) in idle mode. Figure 1D also illustrates the logic state at output 110 of signal path 105, which in this embodiment is high (i.e., logic 1). In this embodiment, transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8 are turned on in idle mode, and transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8 are turned off in idle mode. 1D shows an aging path 175 that passes through transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8 that are turned on in the idle mode. The aging path 175 is the inverse of the aging path 140 shown in FIG. 1B (i.e., the aging path 175 is obtained by inverting the aging path 140). The transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8 that are turned on in the idle mode are stressed, which causes the transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8 to age more than the transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8 that are turned off in the idle mode. Therefore, the aging is different between transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8 stressed in idle mode and transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8, thereby resulting in asymmetric BTI aging in signal path 105.

[0017] In this example, asymmetric aging shifts the threshold voltages of transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8, thereby increasing the rising edge delay at output 110 of signal path 105 relative to the falling edge delay at output 110 of signal path 105. This is because the rising edge propagates to output 110 of signal path 105 via aging path 175 (i.e., transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8 in aging path 175 are turned on to propagate the rising edge to output 110), but the falling edge does not propagate to output 110 of signal path 105 via aging path 175. The increase in rising edge delay relative to the falling edge delay causes duty cycle distortion in signal path 105 .

[0018] An example of duty cycle distortion is illustrated in the timing diagram shown in Figure IE. In the example shown in Figure IE, clock signal 150 is input to input 108 of signal path 105 in active mode. In this example, clock signal 150 at input 108 has a 50% duty cycle. Figure IE also shows clock signal 180 at output 110 of signal path 105 after clock signal 150 has propagated through signal path 105. Signal path 105 delays the rising edge of clock signal 180 by a delay T r , so that the falling edge of the clock signal 180 is delayed by a delay T f As shown in Figure 1E, the rising edge delay T r is the delay T of the falling edge due to the asymmetric aging of the transistors in the signal path 105 mentioned above. f1. This is because the rising edge propagates through aging path 175 to output 110, but the falling edge does not propagate through aging path 175 to output 110. The longer delay of the rising edge reduces the duty cycle of clock signal 180 at output 110 (i.e., results in a duty cycle less than 50% at output 110). Thus, in this example, the duty cycle distortion due to asymmetric aging reduces the duty cycle of the clock signal.

[0019] Thus, asymmetric aging in idle mode causes duty cycle distortion over time. Duty cycle distortion either increases or decreases the duty cycle depending on whether input 108 of signal path 105 is parked low or high in idle mode. In the embodiment shown in Figures 1B-1E, parking input 108 low increases the duty cycle and parking input 108 high decreases the duty cycle. This is because the aging path 140 for park low and the aging path 175 for park high are the inverse of each other (i.e., the transistors 130-1, 125-2, 130-3, 125-4, 130-5, 125-6, 130-7, and 125-8 that are turned on for park low are turned off for park high, and the transistors 125-1, 130-2, 125-3, 130-4, 125-5, 130-6, 125-7, and 130-8 that are turned on for park high are turned off for park low). As a result, the aging path 140 for park low and the aging path 175 for park high move the duty cycle in opposite directions.

[0020] FIG. 2A illustrates one embodiment of a signal path 220 (e.g., a clock path) and a clock gating circuit 210 (also referred to as a clock gating cell) according to some aspects. The clock gating circuit 210 has a clock input 214 configured to receive a clock signal (labeled "CLK"), a control input 212 configured to receive an enable signal (labeled "EN"), and an output 216 coupled to an input 222 of the signal path 220. An output 224 of the signal path 220 may be coupled to one or more circuits (not shown). In this embodiment, the signal path 220 may be configured to distribute a clock signal to one or more circuits, each of which may use the clock signal to time operations within the circuit (e.g., clock a latch within the circuit). The signal path 220 includes a plurality of delay buffers 230-1 to 230-n and 250-1 to 250-m coupled in series. The delay buffers may also be referred to as delay stages, delay elements, delay units, or other terms. The enable signal may also be referred to as a clock enable signal, a control signal, or some other terminology.

[0021] Each delay buffer 230-1 through 230-n and 250-1 through 250-m may be implemented using an inverter or another type of delay buffer (e.g., a NOR gate, a NAND gate, an OR gate, an AND gate, etc.). For example, each of delay buffers 230-1 through 230-n and 250-1 through 250-m may be implemented using a respective complementary inverter. In this regard, FIG. 2C illustrates one embodiment of a delay buffer 275 implemented using a complementary inverter including an NFET 285 and a PFET 290, where the source of NFET 285 is coupled to ground, the gates of NFET 285 and PFET 290 are coupled to an input (labeled “in”) of delay buffer 275, the drains of NFET 285 and PFET 290 are coupled to an output (labeled “out”) of delay buffer 275, and the source of PFET 290 is coupled to supply rail Vdd 277. Each of delay buffers 230-1 through 230-n and 250-1 through 250-m may be implemented using an instance of exemplary delay buffer 275 shown in Figure 2C. However, it should be understood that delay buffers 230-1 through 230-n and 250-1 through 250-m are not limited to this example.

[0022] In this embodiment, the clock gating circuit 210 is configured to gate or ungate the clock signal based on the enable signal. For example, the clock gating circuit 210 may be configured to ungate (i.e., pass) the clock signal when the enable signal is a logic one and gate (i.e., block) the clock signal when the enable signal is a logic zero, or vice versa. The enable signal may be generated by a controller (not shown) configured to manage power for one or more circuits coupled to the output 224 of the signal path 220. In this embodiment, the enable signal may cause the clock gating circuit 210 to pass the clock signal in an active mode and gate the clock signal in an idle mode. In other words, in an embodiment in which the clock gating circuit 210 is configured to ungate the clock signal when the enable signal is a one, the enable signal may be a one in an active mode and a zero in an idle mode. The clock gating circuit 210 may be implemented using one or more logic gates (e.g., an AND gate, a NAND gate, an OR gate, a NOR gate, etc.), one or more clocked latches, a tri-state buffer, or any combination thereof.

[0023] When the clock gating circuit 210 is ungated in the active mode, the clock signal propagates through the signal path 220 to one or more circuits coupled to the output 224 of the signal path 220. When the clock gating circuit 210 is gated in the idle mode, the output 216 of the clock gating circuit 210 parks (i.e., holds) the input 222 of the signal path 220 low or high. FIG. 2B illustrates an example where the clock gating circuit 210 parks the input 222 low in the idle mode. FIG. 2B also illustrates the logic state at the output 224 in the idle mode, which is logic 0 in this example. In this example, parking the input 222 low in the idle mode causes duty cycle distortion over time due to asymmetric aging. In the example of FIG. 2B, the duty cycle distortion increases the duty cycle of the clock signal, as described above with reference to FIG. 1C. The duty cycle distortion can result in timing issues in one or more circuits receiving the clock signal via the signal path 220.

[0024] In systems that are duty cycle sensitive (e.g., long clock paths), duty cycle distortion can result in minimum pulse width violations and / or timing violations in the system. One example of such a system is a double-data rate (DDR) system in which data is captured from a data signal on both the rising and falling edges of a clock signal. In this example, duty cycle distortion due to asymmetric aging can cause the system to fail to capture data from the data signal.

[0025] To address this, various aspects of the present disclosure reduce duty cycle distortion due to aging. In one embodiment, the signal path is divided into segments, and asymmetric aging within a segment causes duty cycle distortion in opposite directions. As a result, duty cycle distortions within a segment cancel each other out, thereby reducing duty cycle distortion across the segment. These and other exemplary features of the present disclosure are further described below.

[0026] 3A illustrates an example of a system 305 with duty cycle distortion mitigation according to some aspects of the disclosure. In this example, the example signal path 220 illustrated in FIG. 2A is split into a first signal path 320 and a second signal path 340, where the first signal path 320 includes serially coupled delay buffers 230-1 through 230-n, and the second signal path 340 includes serially coupled delay buffers 250-1 through 250-m. In this regard, the first signal path 320 may be considered a first segment of the signal path 220, and the second signal path 340 may be considered a second segment of the signal path 220.

[0027] 3A, input 232-1 of delay buffer 230-1 is coupled to input 322 of first signal path 320, and output 234-n of delay buffer 230-n is coupled to output 324 of first signal path 320. Input 252-1 of delay buffer 250-1 is coupled to input 342 of second signal path 340, and output 254-m of delay buffer 250-m is coupled to output 344 of second signal path 340. First signal path 320 and second signal path 340 may have equal numbers of delay buffers (i.e., n=m) or different numbers of delay buffers (i.e., n≠m).

[0028] System 305 also includes clock gating circuit 210, park-high circuit 310, and park-low circuit 330. Park-high circuit 310 has a signal input 312 coupled to output 216 of clock gating circuit 210, a control input 316 configured to receive an enable signal, and an output 314 coupled to input 322 of a first signal path 320. In the embodiment of FIG. 3A, control input 316 of park-high circuit 310 is coupled to control input 212 of clock gating circuit 210. In embodiments in which the signal propagating through signal paths 320 and 340 is a clock signal, signal input 312 may also be referred to as a clock input.

[0029] The park low circuit 330 has a signal input 332 coupled to the output 324 of the first signal path 320, a control input 336 configured to receive an enable signal, and an output 334 coupled to an input 342 of the second signal path 340. In the embodiment of FIG. 3A, the control input 336 of the park low circuit 330 is coupled to the control input 212 of the clock gating circuit 210. In embodiments in which the signal propagating through the signal paths 320 and 340 is a clock signal, the signal input 332 may be referred to as a clock input. An output 344 of the second signal path 340 may be coupled to one or more of the circuits described above with reference to FIG. 2A.

[0030] In one embodiment, the clock gating circuit 210 is configured to ungate (i.e., pass) the clock signal when the enable signal has a first logic value and gate (i.e., block) the clock signal when the enable signal has a second logic value. The first logic value may be 1 and the second logic value may be 0, or vice versa.

[0031] In one embodiment, the park-high circuit 310 is configured to couple (i.e., ungate) the signal input 312 to the output 314 when the enable signal has a first logic value and to park the output 314 high (i.e., logic 1) when the enable signal has a second logic value. For example, the park-high circuit 310 may be implemented using a clock gating circuit configured to ungate when the enable signal has a first logic value and configured to gate and park its output high when the enable signal has a second logic value.

[0032] In one embodiment, the park low circuit 330 is configured to couple (i.e., ungate) the signal input 332 to the output 334 when the enable signal has a first logical value and to park the output 334 low (i.e., logic 0) when the enable signal has a second logical value. For example, the park low circuit 330 may be implemented using a clock gating circuit configured to ungate when the enable signal has a first logical value and configured to gate and park its output low when the enable signal has a second logical value.

[0033] In this embodiment, the enable signal has a first logic value in the active mode. Thus, in the active mode, the clock gate circuit 210 passes the clock signal to a signal input 312 of the park-high circuit 310. The park-high circuit 310 passes the clock signal to an input 322 of a first signal path 320. The clock signal then propagates through the first signal path 320 to a signal input 332 of the park-low circuit 330. The park-low circuit 330 passes the clock signal to an input 342 of a second signal path 340. The clock signal then propagates through the second signal path 340 to one or more circuits coupled to an output 344 of the second signal path 340.

[0034] In this embodiment, the enable signal has a second logic value in the idle mode. Thus, in the idle mode, the clock gating circuit 210 gates the clock signal. The park high circuit 310 parks the input 322 of the first signal path 320 high (i.e., logic 1) and the park low circuit 330 parks the input 342 of the second signal path 340 low (i.e., 0).

[0035] The park-high circuit 310 and the park-low circuit 330 mitigate asymmetric aging in the signal paths 320 and 340. An example of this is shown in FIG. 3B. In this example, each of the signal paths 320 and 340 is assumed to have an even number of delay buffers (i.e., n and m are both even), and each of the delay buffers is implemented using an inverter. However, as further discussed above, it should be understood that the present disclosure is not limited to this example.

[0036] Figure 3B shows the logic state at output 216 of clock gating circuit 210 in idle mode, which in this example is 0. Figure 3B also shows the logic state at input 322 of first signal path 320 and the logic state at output 324 of first signal path 320 in idle mode, which in this example are both logic states are 1. Figure 3B also shows the logic state at input 342 of second signal path 340 and the logic state at output 344 of second signal path 340 in idle mode, which in this example are both logic states are 0.

[0037] In this example, parking the input 322 of the first signal path 320 high in idle mode induces duty cycle distortion in the first signal path 320 due to asymmetric aging, which in this case reduces the duty cycle of the clock signal, as described above with reference to FIG.

[0038] Parking the input 342 of the second signal path 340 low in idle mode induces duty cycle distortion in the second signal path 340 due to asymmetric aging, which in this case increases the duty cycle of the clock signal, as described above with reference to FIG.

[0039] Thus, in this embodiment, the duty cycle distortion in the first signal path 320 and the duty cycle distortion in the second signal path 340 travel in opposite directions, with the duty cycle distortion in the first signal path 320 decreasing the duty cycle of the clock signal and the duty cycle distortion in the second signal path 340 increasing the duty cycle of the clock signal. As a result, the duty cycle distortion in the second signal path 340 offsets at least a portion of the duty cycle distortion in the first signal path 320, thereby reducing the overall duty cycle distortion across signal paths 320 and 340.

[0040] It should be understood that the present disclosure is not limited to the embodiment shown in Figures 3A and 3B. For example, it should be understood that the positions of the park low circuit 330 and the park high circuit 310 can be switched while still achieving a similar asymmetric aging cancellation effect. In this regard, Figure 3C shows an embodiment in which the positions of the park low circuit 330 and the park high circuit 310 are switched. In this embodiment, the signal input 332 of the park low circuit 330 is coupled to the output 216 of the clock gate circuit 210, the output 334 of the park low circuit 330 is coupled to the input 322 of the first signal path 320, the signal input 312 of the park high circuit 310 is coupled to the output 324 of the first signal path 320, and the output 314 of the park high circuit 310 is coupled to the input 342 of the second signal path 340. In the embodiment shown in Figure 3C, the duty cycle distortion in the first signal path 320 increases the duty cycle of the clock signal, and the duty cycle distortion in the second signal path 340 decreases the duty cycle of the clock signal. As a result, the duty cycle distortion in the second signal path 340 cancels at least a portion of the duty cycle distortion in the first signal path 320 .

[0041] In the embodiment shown in FIG. 3B, the output 334 of the park low circuit 330 (coupled to the input 342 of the second signal path 340) has a different logic state (i.e., logic value) in the idle mode than the output 324 of the first signal path 320. More specifically, in the idle mode, the output 324 of the first signal path 320 has a logic state of 1 and the output 334 of the park low circuit 330 has a logic state of 0, thereby inverting the aging path in the second signal path 340 relative to the aging path in the first signal path 320. An example of this is shown in FIG. 3D, which shows an example aging path 380 in the first signal path 320 and an example aging path 385 in the second signal path 340. In the embodiment shown in FIG. 3D, the delay buffers 230-1 to 230-n and 250-1 to 250-m are implemented using the example delay buffers 120-1 to 120-8 shown in FIG. 1A. However, it should be appreciated that the present disclosure is not limited to this example. As shown in FIG. 3D, the aging path 385 in the second signal path 340 is the inversion of the aging path 380 in the first signal path 320. Note that FIG. 3D also shows the aging path 380 in the first signal path 320 extending into the second signal path 340 to show that the aging path 385 in the second signal path 340 is the inversion of the aging path 380 in the first signal path 320. By inverting the aging path, the per-row circuit 330 moves the duty cycle distortion in the second signal path 340 in the opposite direction to the duty cycle distortion in the first signal path 320, thereby canceling at least a portion of the duty cycle distortion in the first signal path 320.

[0042] A similar asymmetric aging cancellation effect is achieved for the embodiment of FIG. 3C. In the embodiment of FIG. 3C, the output 334 of the park-high circuit 310 (coupled to the input 342 of the second signal path 340) has a different logic state (i.e., logic value) than the output 324 of the first signal path 320 in the idle mode. More specifically, in the idle mode, the output 324 of the first signal path 320 has a logic state of 0 and the output 314 of the park-high circuit 310 has a logic state of 1, thereby inverting the aging path in the second signal path 340 relative to the aging path in the first signal path 320. An example of this is shown in FIG. 3E, which shows an example of an aging path 390 in the first signal path 320 and an example of an aging path 395 in the second signal path 340. In the example shown in FIG. 3E, delay buffers 230-1-230-n and 250-1-250-m are implemented using the exemplary delay buffers 120-1-120-8 shown in FIG. 1A. However, it should be appreciated that the present disclosure is not limited to this example. As shown in FIG. 3E, the aging path 395 in the second signal path 340 is the inverse of the aging path 390 in the first signal path 320. Note that FIG. 3E also shows the aging path 390 in the first signal path 320 extending into the second signal path 340 to show that the aging path 395 in the second signal path 340 is the inverse of the aging path 390 in the first signal path 320. By reversing the aging path, the park-high circuit 310 moves the duty cycle distortion in the second signal path 340 in the opposite direction to the duty cycle distortion in the first signal path 320, thereby canceling out at least a portion of the duty cycle distortion in the first signal path 320.

[0043] It should be understood that system 305 may include additional signal paths in addition to first signal path 320 and second signal path 340 shown in Figures 3A-3E. In general, aspects of the present disclosure may be extended to systems including any number of signal paths and to systems having multiple branches. For example, aspects of the present disclosure may be extended to clock distribution systems including multiple clock branches (e.g., clock trees or clock networks), as described further below.

[0044] 4A illustrates an example implementation of the park-high circuit 310 and the park-low circuit 330, according to some aspects. In this example, the park-high circuit 310 includes a first multiplexer 410, and the park-low circuit 330 includes a second multiplexer 430. It should be noted that the delay buffers 230-1 to 230-n in the first signal path 320 and the delay buffers 250-1 to 250-m in the second signal path 340 are not explicitly shown in FIG. 4A for ease of illustration.

[0045] The first multiplexer 410 has a first input 412, a second input 414, a select input 416, and an output 418. The first input 412 is coupled to the signal input 312 of the park high circuit 310, the second input 414 is configured to receive a logic one, and the output 418 is coupled to the output 314 of the park high circuit 310. The select input 416 is coupled to the control input 316 of the park high circuit 310. In one embodiment, the second input 414 can receive a logic one by coupling the second input 414 to a supply rail Vdd 440, as shown in the embodiment of FIG. 4B.

[0046] In one embodiment, the first multiplexer 410 is configured to couple the first input 412 to the output 418 (i.e., select the first input 412) when the enable signal at the selection input 416 has a first logic value (e.g., 1). Thus, when the enable signal has the first logic value in the active mode, the first multiplexer 410 passes the clock signal from the first input 412 to the output 418. The first multiplexer 410 is configured to couple the logic 1 at the second input 414 to the output 418 (i.e., select the second input 414) when the enable signal at the selection input 416 has a second logic value (e.g., 0). Thus, when the enable signal has the second logic value in the idle mode, the first multiplexer 410 parks the output 418 high (i.e., logic 1). In this embodiment, the output 418 of the first multiplexer 410 is coupled to the input 322 of the first signal path 320, so that the first multiplexer 410 parks the input 322 of the first signal path 320 high in idle mode.

[0047] The second multiplexer 420 has a first input 432, a second input 434, a selection input 436, and an output 438. The first input 432 is coupled to the signal input 332 of the park row circuit 330, the second input 434 is configured to receive a logic 0, and the output 438 is coupled to the output 334 of the park row circuit 330. The selection input 436 is coupled to the control input 336 of the park row circuit 330. In one embodiment, the second input 434 can receive a logic 0 by coupling the second input 434 to ground, as shown in the embodiment of FIG. 4B.

[0048] In one embodiment, the second multiplexer 430 is configured to couple the first input 432 to the output 438 (i.e., select the first input 432) when the enable signal at the selection input 436 has a first logic value (e.g., 1). Thus, when the enable signal has the first logic value in the active mode, the second multiplexer 430 passes the clock signal from the first input 432 to the output 438. The second multiplexer 430 is configured to couple a logic 0 at the second input 434 to the output 438 (i.e., select the second input 434) when the enable signal at the selection input 436 has a second logic value (e.g., 0). Thus, when the enable signal has the second logic value in the idle mode, the second multiplexer 430 parks the output 438 low (i.e., logic 0). In this embodiment, the output 438 of the second multiplexer 430 is coupled to the input 342 of the second signal path 340, so that the second multiplexer 430 parks the input 342 of the second signal path 340 low in idle mode.

[0049] The first multiplexer 410 and the second multiplexer 430 may each be implemented with one or more switches, one or more logic gates, or any combination thereof.

[0050] It should be appreciated that in some implementations, the control input 316 of the park-high circuit 310 and the control input 336 of the park-low circuit 330 can be coupled to the control input 212 of the clock gating circuit 210 via an inverter 450, one example of which is shown in FIG. 4C. In this example, an input 452 of the inverter 450 is coupled to the control input 212 of the clock gating circuit 210, and an output 454 of the inverter 450 is coupled to the control input 316 of the park-high circuit 310 and the control input 336 of the park-low circuit 330. The inverter 450 inverts the enable signal and outputs the inverted enable signal to the control input 316 of the park-high circuit 310 and the control input 336 of the park-low circuit 330.

[0051] In this example, the first multiplexer 410 can be configured to select the first input 412 when a second logical value (e.g., 0) is input to the select input 416 and to select the second input 414 when a first logical value (e.g., 1) is input to the select input 416. In this example, an inverted enable signal is input to the select input 416 so that the first multiplexer 410 passes the clock signal when the enable signal has a first logical value (e.g., 1) and parks the input 322 of the first signal path 320 high when the enable signal has a second logical value (e.g., 0).

[0052] In this example, the second multiplexer 430 can be configured to select the first input 432 when a second logical value (e.g., 0) is input to the select input 436 and to select the second input 434 when a first logical value (e.g., 1) is input to the select input 436. In this example, an inverted enable signal is input to the select input 436 so that the second multiplexer 430 passes the clock signal when the enable signal has a first logical value (e.g., 1) and parks the input 342 of the second signal path 340 low when the enable signal has a second logical value (e.g., 0).

[0053] 5A illustrates another exemplary implementation of the park-high circuit 310 according to some aspects. In this example, the park-high circuit 310 includes a park-high gate circuit 505 that includes a synchronizer 510, a latch 520, and a logic gate 530.

[0054] The synchronizer 510 has a control input 512, an output 514, and a timing input 516. The control input 512 is coupled to the control input 316 of the park-high circuit 310, and the timing input 516 is coupled to the signal input 312 (e.g., a clock input) of the park-high circuit 310. The synchronizer 510 is configured to receive a control signal (e.g., an enable signal) at the control input 512 and a clock signal at the timing input 516. The synchronizer 510 is configured to synchronize the control signal with the clock signal and output the synchronized control signal at the output 514. For example, the synchronizer 510 can synchronize the control signal with the clock signal by aligning an edge (i.e., a transition) of the control signal with an edge of the clock signal.

[0055] The latch 520 has a control input 522, an output 524, and a timing input 526. The control input 522 is coupled to the output 514 of the synchronizer 510, and the timing input 526 is coupled to the signal input 312 (e.g., a clock input) of the park-high circuit 310. In the example of FIG. 5A, the control input 522 of the latch 520 is coupled to the output 514 of the synchronizer 510 via an inverter 540, an input 542 of the inverter 540 is coupled to the output 514 of the synchronizer 510, and an output 544 of the inverter 540 is coupled to the control input 522 of the latch 520. Thus, in this example, the inverter 540 inverts the synchronized control signal before inputting the synchronized control signal to the latch 520. However, it should be understood that for some implementations, the inverter 540 may be omitted.

[0056] Latch 520 is configured to receive a synchronized control signal (which may be inverted by inverter 540) at a control input 522 and a clock signal at a timing input 526. Latch 520 is configured to latch the synchronized control signal on a rising edge of the clock signal and output the resulting latched control signal at output 524. Latch 520 may be implemented using a flip-flop (e.g., a positive-edge triggered flip-flop) or another type of clocked latch.

[0057] The logic gate 530 has a first input 532, a second input 534, and an output 536. The first input 532 is coupled to the output 524 of the latch 520, the second input 534 is coupled to the signal input 312 of the park high circuit 310, and the output 536 is coupled to the output 314 of the park high circuit 310. The logic gate 530 is configured to couple the signal input 312 of the park high circuit 310 to the output 314 of the park high circuit 310 (i.e., ungate the park high circuit 310) or park the output 314 of the park high circuit 310 high based on the latched control signal from the latch 520. In the embodiment shown in FIG. 5A, the logic gate 530 includes an OR gate 537. However, it should be understood that the logic gate 530 is not limited to this embodiment and the logic gate 530 can include another type of logic gate capable of parking the output 536 high.

[0058] In this example, the park high circuit 310 couples (i.e., ungates) the signal input 312 to the output 314 when the control signal at the control input 316 is 1 and parks the output 314 high when the control signal at the control input 316 is 0. When the control signal at the control input 316 transitions from 0 to 1, the synchronizer 510 synchronizes the control signal with the clock signal such that the transition from 0 to 1 (i.e., rising edge) is aligned with an edge of the clock signal. The inverter 540 then inverts the 1 of the synchronized control signal to a 0, and the latch 520 latches the 0 on the rising edge of the clock signal. The latched 0 is input to a first input 532 of the logic gate 530, which causes the logic gate 530 (e.g., OR gate 537) to pass the clock signal at the second input 534 to the output 536. In this embodiment, latch 520 helps ensure that logic gate 530 ungates park high circuit 310 when the clock signal is high to help prevent glitches at output 314.

[0059] When the control signal at the control input 316 transitions from 1 to 0, the synchronizer 510 synchronizes the control signal with the clock signal such that the transition from 1 to 0 (i.e., the falling edge) is aligned with an edge of the clock signal. The inverter 540 then inverts the 0 of the synchronized control signal to a 1, and the latch 520 latches the 1 on the rising edge of the clock signal. The latched 1 is input to a first input 532 of a logic gate 530, which causes the output 536 of the logic gate 530 (e.g., OR gate 537) to park high. This is because the 1 at the first input 532 of the logic gate 530 (e.g., OR gate 537) causes the logic gate 530 to output a 1, effectively gate (i.e., block) the clock signal, regardless of the logic value at the second input 534 of the logic gate 530. In this embodiment, latch 520 helps ensure that logic gate 530 parks the output 314 of the park high circuit 310 high when the clock signal is high to help prevent glitches at the output 314.

[0060] It should be understood that latch 520 and / or synchronizer 510 may be omitted if glitching is not an issue. It should also be understood that synchronizer 510 may be omitted if the control signals are already synchronized with the clock signal. In these cases, the control input 522 of latch 520 can be coupled to the control input 316 without synchronizer 510. An advantage of synchronizer 510 is that it allows the incoming control signals to be asynchronous with the clock signal, thereby simplifying the timing of the control signals.

[0061] 5B illustrates another exemplary implementation of the park low circuit 330, according to some embodiments. In this example, the park low circuit 330 is implemented using a park low gate circuit 548 that includes a synchronizer 550, a latch 560, and a logic gate 570.

[0062] The synchronizer 550 has a control input 552, an output 554, and a timing input 556. The control input 552 is coupled to the control input 336 of the park row circuit 330, and the timing input 556 is coupled to the signal input 332 (e.g., a clock input) of the park row circuit 330. The synchronizer 550 is configured to receive a control signal (e.g., an enable signal) at the control input 552 and a clock signal at the timing input 556. The synchronizer 550 is configured to synchronize the control signal with the clock signal and output the synchronized control signal at the output 554. For example, the synchronizer 550 can synchronize the control signal with the clock signal by aligning an edge (i.e., a transition) of the control signal with an edge of the clock signal.

[0063] The latch 560 has a control input 562, an output 564, and a timing input 566. The control input 562 is coupled to the output 554 of the synchronizer 550, and the timing input 566 is coupled to a signal input 332 (e.g., a clock input) of the park row circuit 330. The latch 560 is configured to receive a synchronized control signal at the control input 562 and a clock signal at the timing input 566. The latch 560 is configured to latch the synchronized control signal on a falling edge of the clock signal and output the resulting latched control signal at the output 564. The latch 560 can be implemented using a flip-flop (e.g., a negative edge triggered flip-flop) or another type of clocked latch.

[0064] The logic gate 570 has a first input 572, a second input 574, and an output 576. The first input 572 is coupled to the output 564 of the latch 560, the second input 574 is coupled to the signal input 332 of the park row circuit 330, and the output 576 is coupled to the output 334 of the park row circuit 330. The logic gate 570 is configured to couple the signal input 332 of the park row circuit 330 to the output 334 of the park row circuit 330 (i.e., ungate the park row circuit 330) or park the output 334 of the park row circuit 330 low based on the latched control signal from the latch 560. In the embodiment shown in FIG. 5B, the logic gate 570 includes an AND gate 577. However, it should be understood that the logic gate 570 is not limited to this embodiment and the logic gate 570 can include another type of logic gate capable of parking the output 576 low.

[0065] In this embodiment, the park low circuit 330 couples (i.e., ungates) the signal input 332 to the output 334 when the control signal at the control input 336 is a 1 and parks the output 334 low when the control signal at the control input 336 is a 0. When the control signal at the control input 336 transitions from 0 to 1, the synchronizer 550 synchronizes the control signal with the clock signal such that the 0 to 1 transition is aligned with an edge of the clock signal. The latch 560 latches the 1 of the synchronized control signal on the falling edge of the clock signal. The latched 1 is input to a first input 572 of a logic gate 570, which causes the logic gate 570 (e.g., an AND gate 577) to pass the clock signal at the second input 574 to the output 576. In this embodiment, the latch 560 helps ensure that the logic gate 570 ungates the park low circuit 330 when the clock signal is low to help prevent glitches at the output 334.

[0066] When the control signal at the control input 336 transitions from 1 to 0, the synchronizer 550 synchronizes the control signal with the clock signal such that the transition from 1 to 0 is aligned with an edge of the clock signal. The latch 560 latches the 0 of the synchronized control signal on the falling edge of the clock signal. The latched 0 is input to a first input 572 of a logic gate 570, which causes the output 576 of the logic gate 570 (e.g., AND gate 577) to park low. This is because the 0 at the first input 572 of the logic gate 570 (e.g., AND gate 577) causes the logic gate 570 to output a 0, effectively gate (i.e., block) the clock signal, regardless of the logic value at the second input 574 of the logic gate 570. In this embodiment, the latch 560 helps ensure that the logic gate 570 parks the output 334 of the park low circuit 330 low when the clock signal is low, thereby helping to prevent glitches at the output 576.

[0067] It should be understood that latch 560 and / or synchronizer 550 may be omitted if glitching is not an issue. It should also be understood that synchronizer 550 may be omitted if the control signals are already synchronized with the clock signal. In these cases, control input 562 of latch 560 may be coupled to control input 336 without synchronizer 550. An advantage of synchronizer 550 is that it allows the incoming control signals to be asynchronous with the clock signal, thereby simplifying the timing of the control signals.

[0068] In some aspects, the operation of the clock gating circuit 210, the park high circuit 310, and the park low circuit 330 can be ordered when the system transitions to an idle mode and / or when transitioning to an active mode. This can be done, for example, to prevent glitches at the output 344 of the second signal path 340. In this regard, FIG. 6 illustrates one embodiment of a system 605 with ordering, according to some aspects. In this embodiment, the system 605 includes the clock gating circuit 210, the park high circuit 310, the first signal path 320, the park low circuit 330, and the second signal path 340 described above with reference to FIG. 3A. It should be noted that the delay buffers 230-1 to 230-n in the first signal path 320 and the delay buffers 250-1 to 250-m in the second signal path 340 are not explicitly shown in FIG. 6 for ease of illustration.

[0069] 6 illustrates an embodiment of a circuit 650 coupled to the output 344 of the second signal path 340. The circuit 650 may include a processor, a logic gate, a register, a retention flop, a memory, sequential logic, or any combination thereof. FIGURE 6 also illustrates an embodiment of a clock source 690 having an output 692 coupled to the clock input 214 of the clock gating circuit 210. The clock source 690 is configured to generate a clock signal (labeled "CLK") and output the clock signal at the output 692.

[0070] In one embodiment, the clock source 690 may include a phase locked loop (PLL) 694. However, it should be understood that the disclosure is not limited to this embodiment and that the clock source 690 may be implemented using another type of clock source (also referred to as a clock generator). It should be understood that the clock source 690 may be coupled to the clock gating circuit 210 via a delay buffer (not shown), one or more other clock gating circuits (not shown), and / or one or more multiplexers (not shown). The one or more other clock gating circuits (not shown) may be used, for example, to gate a clock signal upstream of the clock gating circuit 210. The one or more multiplexers (not shown) may be used, for example, to selectively couple the clock input 214 of the clock gating circuit 210 to one or more other clock sources.

[0071] The system 605 also includes a control circuit 610 configured to control the sequencing of the clock gating circuit 210, the park-high circuit 310, and the park-low circuit 330 during transitions to an idle mode and / or transitions to an active mode. As used herein, an "idle mode" is a mode in which a clock signal to the circuit 650 is gated to reduce dynamic power. The idle mode may be triggered, for example, when the circuit 650 is not in use. In the idle mode, logic gates and / or flops in the circuit 650 that receive a clock signal in the active mode may be held in a static state in the idle mode. The idle mode may also be referred to as an idle state, a static state, an inactive state, or another term. As used herein, an "active mode" is a mode in which a clock signal is sent to the circuit 650 via signal paths 320 and 340 to time (i.e., clock) operations in the circuit 650. The active mode may also be referred to as an active state, a functional mode, or another term.

[0072] The control circuit 610 has a first output 614, a second output 616, a third output 618, a first input 612, a second input 620, and a third input 622. The first input 612 is configured to receive a clock gate signal or a clock enable signal, which will be further described below. The first output 614 is coupled to a control input 212 of the clock gate circuit 210 (also called a clock gate cell), the second output 616 is coupled to a control input 316 of the park high circuit 310, and the third output 618 is coupled to a control input 336 of the park low circuit 330.

[0073] 6, the park low circuit 330 also has a status output 630 coupled to the second input 620 of the control circuit 610. In this example, the park low circuit 330 can be configured to output a status signal to the control circuit 610 via the status output 630, which reports the status of the park low circuit 330, as described further below. It should be understood that in some implementations, the status output 630 may be omitted. As used herein, a "status output" is an output of a circuit configured to output a status signal indicative of the status of the circuit.

[0074] 6, the park high circuit 310 also has a status output 635 coupled to the third input 622 of the control circuit 610. In this example, the park high circuit 310 can be configured to output a status signal to the control circuit 610 via the status output 635, the status signal reporting the status of the park high circuit 310, as described further below. It should be understood that in some implementations, the status output 635 may be omitted.

[0075] 7 illustrates an example sequence 700 that may be performed by a system 605 to transition to an idle mode, according to some aspects. Initially, the clock gating circuit 210 may be ungated, and the park-high circuit 310 and the park-low circuit 330 may pass the clock signal. In other words, the system 605 may initially operate in an active mode.

[0076] In block 710, the control circuit 610 receives a clock gate signal at a first input 612 requesting that the clock signal be gated. For example, the clock gate signal can come from a controller (not shown) configured to manage the power state of the circuit 650.

[0077] At block 720, in response to the clock gate signal, the control circuit 610 commands (i.e., causes) the park low circuit 330 to park the output 334 low via the third output 618. For example, the control circuit 610 may output a logic value to the control input 336 of the park low circuit 330 via the third output 618 that causes the park low circuit 330 to park the output 334 low. In this example, the park low circuit 330 may be implemented using the exemplary park low gate circuit 548 shown in FIG. 5B.

[0078] At block 730, the control circuit 610 commands (i.e., causes) the park high circuit 310 to park the output 314 high via the second output 616. For example, the control circuit 610 may output a logic value to the control input 316 of the park high circuit 310 via the second output 616 that causes the park high circuit 310 to park the output 314 high. In this example, the park high circuit 310 may be implemented using the exemplary park high gate circuit 505 shown in FIG. 5A.

[0079] At block 740, the control circuit 610 commands (i.e., causes) the clock gating circuit 210 to gate the clock signal via the first output 614. For example, the control circuit 610 may output a logic value (e.g., a second logic value) to the control input 212 of the clock gating circuit 210 via the first output 614 that causes the clock gating circuit 210 to gate the clock signal. In some aspects, the output 216 of the clock gating circuit 210 may be parked low when the clock signal is gated.

[0080] In one embodiment, the control circuit 610 can instruct the park high circuit 310 to park the output 314 high in block 730 after the park low circuit 330 parks the output 334 low. This helps to prevent the park high at the output 314 of the park high circuit 310 from propagating to the circuit 650 via the second signal path 340. This is because parking the park low circuit 330 low before the park high circuit 310 parks high causes the park low circuit 330 to block the park high at the output 314 of the park high circuit 310 from propagating to the second signal path 340.

[0081] In one embodiment, the control circuit 610 can use a status signal from the park low circuit 330 to help ensure that the park high circuit 310 parks high after the park low circuit 330 parks low. For example, when the park low circuit 330 parks the output 334 low, the park low circuit 330 can be configured to output a park low status signal to the control circuit 610 via the status output 630 indicating that the output 334 has been parked low. In this embodiment, the control circuit 610 can be configured to instruct the park high circuit 310 to park high after the control circuit 610 receives the park low status signal at the second input 620.

[0082] 8A illustrates an example implementation in which the park low circuit 330 is configured to output a status signal at a status output 630, according to some aspects. In this example, the park low circuit 330 includes the example park low gate circuit 548 shown in FIG. 5B. In the example of FIG. 8A, the park low circuit 330 also includes a second latch 810. The second latch 810 has a status input 812 coupled to the output 564 of the first latch 560, a dimming input 816 coupled to the signal input 332, and an output 814 coupled to the status output 630. The second latch 810 may include a flip-flop or another type of latch.

[0083] In this embodiment, the second latch 810 is configured to provide a status signal at the status output 630 by latching the logic value at the output 564 of the first latch 560 at the rising edge of the clock signal and outputting the latched logic value to the status output 630. In this embodiment, the first latch 560 outputs a 0 to the first input 572 of the logic gate 570 (e.g., AND gate 577) to park the output 334 low. Therefore, in this embodiment, the second latch 810 outputs a 0 at the status output 630 to report that the output 334 is parked low (i.e., the above-mentioned park low status signal is 0 in this embodiment). Also, in this embodiment, the first latch 560 outputs a 1 to the first input 572 of the logic gate 570 to ungate the park low circuit 330, so that the second latch 810 outputs a 1 at the status output 630 when the park low circuit 330 is ungated.

[0084] 8B illustrates an exemplary implementation in which the park high circuit 310 is configured to output a status signal at a status output 635, according to some aspects. In this example, the park high circuit 310 includes the exemplary park high gate circuit 505 shown in FIG. 5A. In the example of FIG. 8B, the park high circuit 310 also includes a second latch 820 and a second inverter 830. The second latch 820 has a status input 822 coupled to the output 524 of the first latch 520 via the second inverter 830, an input 832 of the second inverter 830 is coupled to the output 524 of the first latch 520, and an output 834 of the second inverter 830 is coupled to the status input 822 of the second latch 820. The second latch 820 also has a timing input 826 coupled to the signal input 312 and an output 824 coupled to the status output 635. The second latch 820 may include a flip-flop or another type of latch.

[0085] In this embodiment, the second latch 820 is configured to latch the inverse of the logic value at the output 524 of the first latch 520 on the falling edge of the clock signal and output the inverse of the latched logic value to the status output 635, thereby providing a status signal at the status output 635. In this embodiment, the first latch 520 outputs a 1 to the first input 532 of the logic gate 530 (e.g., OR gate 537) to park the output 314 high. Thus, in this embodiment, the second latch 820 outputs a 0 (i.e., the inverse of the 1 output by the first latch 520) at the status output 635 to report that the output 314 is parked high (i.e., the park high status signal described above is a 0 in this embodiment). Also, in this embodiment, the second latch 810 outputs a 1 at the status output 635 when the park high circuit 310 is ungated.

[0086] 9 illustrates another example sequence 900 that may be performed by the system 605 to transition to an idle mode, according to some aspects. Initially, the clock gating circuit 210 may be ungated, and the park high circuit 310 and the park low circuit 330 may pass the clock signal. In other words, the system 605 may initially operate in an active mode.

[0087] In block 910, the control circuit 610 receives a clock gate signal at a first input 612 requesting that the clock signal be gated. For example, the clock gate signal can come from a controller (not shown) configured to manage the power state of the circuit 650.

[0088] At block 920, in response to the clock gate signal, the control circuit 610 instructs (i.e., causes) the clock gating circuit 210 to gate the clock signal via the first output 614. For example, the control circuit 610 may output a logic value (e.g., a second logic value) to the control input 212 of the clock gating circuit 210 via the first output 614 that causes the clock gating circuit 210 to gate the clock signal. In this example, the output 216 of the clock gating circuit 210 may be parked low when the clock signal is gated.

[0089] In block 930, the control circuit 610 commands (i.e., causes) the park low circuit 330 to park the output 334 low via the third output 618. For example, the control circuit 610 can output a logic value to the control input 336 of the park low circuit 330 via the third output 618 that causes the park low circuit 330 to park the output 334 low. In this embodiment, the park low circuit 330 can include the second multiplexer 430 shown in FIG. 4A. In this embodiment, the control circuit 610 can wait until the park low at the output 216 of the clock gate circuit 210 propagates to the park low circuit 330 before commanding the park low circuit 330 to park low such that the park low circuit 330 parks low when the signal input 332 of the park low circuit 330 is low, which helps prevent glitches at the output 334. In this embodiment, the control circuit 610 can delay commanding the park low circuit 330 to park low by a time delay that allows sufficient time for the park low at the output 216 of the clock gate circuit 210 to propagate to the park low circuit 330.

[0090] In block 940, the control circuit 610 commands (i.e., causes) the park high circuit 310 to park the output 314 high via the second output 616. For example, the control circuit 610 can output a logical value to the control input 316 of the park high circuit 310 via the second output 616 that causes the park high circuit 310 to park the output 314 high. In this embodiment, the park high circuit 310 can include the first multiplexer 410 shown in FIG. 4A.

[0091] 9 can be used to help prevent glitches, for example, when the park low circuit 330 does not include internal mechanisms (e.g., synchronizers and / or latches) to prevent glitches. In this example, glitches are prevented by gating the clock signal before parking the park low circuit 330. In this example, the park low circuit 330 can be implemented using a multiplexer (e.g., the second multiplexer 430).

[0092] 10 illustrates an example sequence 1000 that may be performed by system 605 to transition to an active mode, according to some aspects. Initially, clock gating circuit 210 may be gated, park high circuit 310 may be parked high, and park low circuit 330 may be parked low. In other words, system 605 may initially be in an idle mode.

[0093] In block 1010, the control circuit 610 receives a clock enable signal at a first input 612 requesting that the clock signal be ungated (ie, enabled).

[0094] In block 1020, in response to the clock enable signal, the control circuit 610 commands (i.e., causes) the park high circuit 310 to ungate (i.e., couple the signal input 312 to the output 314). As a result, the park high circuit 310 is transparent in the sense that the park high circuit 310 passes the logic value at the signal input 312 to the output 314. In an embodiment in which the output 216 of the clock gating circuit 210 is parked low when the clock signal is gated, the park high circuit 310 passes the park low at the output 216 of the clock gating circuit 210 to the output 314. In some aspects, the control circuit 610 can command the park high circuit 310 to ungate (i.e., couple the signal input 312 to the output 314) by outputting a logic value to the control input 316 of the park high circuit 310 via the second output 616, which causes the park high circuit 310 to ungate.

[0095] At block 1030, the control circuit 610 commands (i.e., causes) the park low circuit 330 to ungate (e.g., couple the signal input 332 to the output 334). In one embodiment, the control circuit 610 can wait until the park low at the output 216 of the clock gating circuit 210 propagates through the park high circuit 310 to the park low circuit 330 before commanding the park low circuit 330 to ungate such that the park low circuit 330 ungates when the signal input 332 of the park low circuit 330 is low, which helps prevent glitches at the output 334. In this embodiment, the control circuit 610 can delay commanding the park low circuit 330 to ungate by a time delay that allows sufficient time for the park low to propagate to the park low circuit 330. In some aspects, the control circuit 610 can instruct the park-row circuit 330 to ungate (i.e., couple the signal input 332 to the output 334) by outputting a logic value to the control input 336 of the park-row circuit 330 via a third output 618 that causes the park-row circuit 330 to be ungated. In this example, the park-row circuit 330 can be implemented using a multiplexer (e.g., the second multiplexer 430).

[0096] At block 1040, the control circuit 610 commands (i.e., causes) the clock gating circuit 210 to ungate via the first output 614. For example, the control circuit 610 may output a logic value to the control input 212 of the clock gating circuit 210 via the first output 614 that causes the clock signal to be ungated.

[0097] It should be understood that aspects of the disclosure are not limited to the example sequence 1000 shown in Figure 10. In this regard, Figure 11 illustrates another example sequence 1100 that may be executed by the system 605 to transition to an active mode, according to some aspects. Initially, the clock gating circuit 210 may be gated, the park high circuit 310 may be parked high, and the park low circuit 330 may be parked low. In other words, the system 605 may initially be in an idle mode.

[0098] In block 1110, the control circuit 610 receives a clock enable signal at a first input 612 requesting that the clock signal be ungated (ie, enabled).

[0099] At block 1120, in response to the clock enable signal, the control circuit 610 commands (i.e., causes) the park high circuit 310 to ungate (i.e., couple the signal input 312 to the output 314). For example, the control circuit 610 can command the park high circuit 310 to ungate (i.e., couple the signal input 312 to the output 314) by outputting a logical value to the control input 316 of the park high circuit 310 via the second output 616 that causes the park high circuit 310 to ungate.

[0100] At block 1130, the control circuit 610 commands (i.e., causes) the clock gating circuit 210 to ungate via the first output 614. For example, the control circuit 610 may output a logic value via the first output 614 to the control input 212 of the clock gating circuit 210 that causes the clock gating circuit 210 to ungate the clock signal.

[0101] In block 1140, the control circuit 610 commands (i.e., causes) the park low circuit 330 to ungate (e.g., couple the signal input 332 to the output 334). For example, the control circuit 610 can command the park low circuit 330 to ungate (i.e., couple the signal input 332 to the output 334) by outputting a logic value to the control input 336 of the park low circuit 330 via the third output 618 that causes the park low circuit 330 to ungate. In this embodiment, the park low circuit 330 can include the park low gate circuit 548 shown in FIG. 5B to prevent glitches at the output 334. In this case, the synchronizer 510 and the latch 520 in the park low gate circuit 548 help ensure that the park low circuit 330 ungates when the clock signal is low to prevent glitches, as described above. By un-gating the clock gating circuit 210 before un-gating the per-row circuit 330, the latency of providing a clock signal to the circuit 650 when the system 605 transitions to the active mode can be reduced.

[0102] As mentioned above, aspects of the disclosure can be extended to a clock distribution system that includes multiple clock branches (e.g., a clock tree or clock network). In this regard, FIG. 12 illustrates one embodiment of a system 1205 that includes multiple branches. For example, the branches may be part of a clock tree used to distribute a clock signal from a clock source 690 (shown in FIG. 6) to multiple circuits. The circuits may include one or more processors, logic gates, registers, retention flops, one or more memories, sequential logic, or any combination thereof.

[0103] In this embodiment, the system 1205 includes the clock gating circuit 210, the park high circuit 310, the first signal path 320, the park low circuit 330, the second signal path 340, and the control circuit 610, as described above with reference to FIG. 6. As described above, the control circuit 610 is configured to command the clock gating circuit 210 to ungate (i.e., pass the clock signal) in the active mode and to command the clock gating circuit 210 to gate the clock signal in the idle mode. The control circuit 610 is also configured to command the park high circuit 310 to ungate in the active mode and to command the park high circuit 310 to park the output 314 high in the idle mode. The control circuit 610 is also configured to command the park low circuit 330 to ungate in the active mode and to command the park low circuit 330 to park the output 334 low in the idle mode. In this embodiment, the first signal path 320, the park-row circuit 330, and the second signal path 340 may be part of a first clock branch configured to distribute a clock signal to the circuit 650. In the following description, the park-row circuit 330 is referred to as the first park-row circuit, and the circuit 650 is referred to as the first circuit.

[0104] The system 1205 also includes a third signal path 1220, a second park low circuit 1230, and a fourth signal path 1240. The second park low circuit 1230 can be implemented using a park low gate circuit (e.g., the park low gate circuit 548), a multiplexer (e.g., the second multiplexer 430), or another circuit. The third signal path 1220 has an input 1222 coupled to the output 314 of the park high circuit 310 and an output 1224. The second park low circuit 1230 has a signal input 1232, an output 1234, a control input 1236, and a status output 1238. The signal input 1232 is coupled to the output 1224 of the third signal path 1220, and the control input 1236 is coupled to the third output 618 of the control circuit 610. The fourth signal path 1240 has an input 1242 coupled to the output 1234 of the second park-row circuit 1230 and an output 1244 coupled to the second circuit 1250. The third signal path 1220 and the fourth signal path 1240 may each include delay buffers coupled in series. In this embodiment, the third signal path 1220, the second park-row circuit 1230, and the fourth signal path 1240 may be part of a second clock branch configured to distribute a clock signal to the second circuit 1250.

[0105] In operation, the control circuit 610 is configured to command the second park low circuit 1230 to ungate (i.e., couple the signal input 1232 and the output 1234) in an active mode and to command the second park low circuit 1230 to park the output 1234 low in an idle mode. In one embodiment, the second park low circuit 1230 can be configured to ungate when a first logical value is input to the control input 1236 and to park low when a second logical value is input to the control input 1236. In this embodiment, the control circuit 610 can command the second park low circuit 1230 to ungate by inputting a first logical value to the control input 1236 via the third output 618 and can command the second park low circuit 1230 to park the output 1234 low by inputting a second logical value to the control input 1236 via the third output 618.

[0106] In this example, an input 322 of the first signal path 320 and an input 1222 of the third signal path 1220 may be coupled to an output 314 of the park-high circuit 310 via a node 1210. The path between the output 314 of the park-high circuit 310 and the node 1210 may include one or more delay buffers 1215 coupled in series.

[0107] Although two clock branches are shown in the example of Figure 12, it should be understood that the system 1205 can include one or more additional clock branches not shown in Figure 12. In other words, aspects of the present disclosure can be extended to systems having more than two clock branches.

[0108] In the embodiment shown in FIG. 12, the system 1205 further includes a first combiner 1270 having a first input 1272, a second input 1274, and an output 1276. The first input 1272 is coupled to the status output 630 of the first park row circuit 330, the second input 1274 is coupled to the status output 1238 of the second park row circuit 1230, and the output 1276 is coupled to an input 620-1 of the control circuit 610. As will be further described below, the first combiner 1270 is configured to combine (i.e., aggregate) the status signals from the status outputs 630 and 1238 of the park row circuits 330 and 1230 into a first combined status signal and input the first combined status signal to the input 620-1 of the control circuit 610. In the embodiment shown in FIG. 12, the first combiner 1270 includes an OR gate 1278. However, it should be understood that the first combiner 1270 is not limited to this embodiment and that the first combiner 1270 can be implemented using other types of logic gates.

[0109] In this example, the first composite status signal is 0 when all of the status signals from the park row circuits 330 and 1230 are 0. Thus, in an example where a status signal having a logic value of 0 indicates that the respective park row circuits are parked low, the first composite status signal is 0 when all of the park row circuits 330 and 1230 are parked low. This allows the control circuit 610 to determine that all of the park row circuits 330 and 1230 are parked low when the first composite status signal is 0. In an alternative implementation, a status signal having a logic value of 0 can indicate that the respective park row circuits are ungated. In this example, the control circuit 610 can determine that all of the park row circuits 330 and 1230 are ungated when the first composite status signal is 0.

[0110] In this embodiment, the system 1205 further includes a second combiner 1280 having a first input 1282, a second input 1284, and an output 1286. The first input 1282 is coupled to the status output 630 of the first park-row circuit 330, the second input 1284 is coupled to the status output 1238 of the second park-row circuit 1230, and the output 1286 is coupled to an input 620-2 of the control circuit 610. As will be explained further below, the second combiner 1280 is configured to combine (i.e., aggregate) the status signals from the status outputs 630 and 1238 of the park-row circuits 330 and 1230 into a second combined status signal and input the second combined status signal to the input 620-2 of the control circuit 610. In the embodiment shown in FIG. 12, the second combiner 1280 includes an AND gate 1288. However, it should be understood that the second combiner 1280 is not limited to this embodiment and that the second combiner 1280 can be implemented using other types of logic gates.

[0111] In this example, the second composite status signal is 1 when all of the status signals from the park row circuits 330 and 1230 are 1. Thus, in an example where a status signal having a logical value of 1 indicates that the respective park row circuits are ungated, the second composite status signal is 1 when all of the park row circuits 330 and 1230 are ungated. This allows the control circuit 610 to determine that all of the park row circuits 330 and 1230 are ungated when the second composite status signal is 1. In an alternative implementation, a status signal having a logical value of 1 can indicate that the respective park row circuits are parked low. In this example, the control circuit 610 determines that all of the park row circuits 330 and 1230 are parked low when the second composite status signal is 1.

[0112] Thus, the control circuit 610 can use the first and second combined status signals to determine when all of the park low circuits 330 and 1230 are parked low or when all of the park low circuits 330 and 1230 are ungated. Although two park low circuits (i.e., the park low circuits 330 and 1230) are shown in the embodiment of Figure 12, it should be understood that the first combiner 1270 and the second combiner 1280 can be extended to a system having more than two park low circuits to determine the status of more than two park low circuits.

[0113] In some aspects, the control circuit 610 can be configured to control the sequencing of the clock gating circuit 210, the park high circuit 310, the first park low circuit 330, and the second park low circuit 1230 during a transition to the idle mode and / or a transition to the active mode. In one embodiment, the control circuit 610 can transition to the idle mode based on an example sequence 700 shown in Figure 7. In this embodiment, in block 720, the control circuit 610 can instruct the first park low circuit 330 to park the output 334 low and the second park low circuit 1230 to park the output 1234 low. 12, the control inputs 336 and 1236 of the park low circuits 330 and 1230 are coupled to the third output 618 of the control circuit 610, so that the control circuit 610 can command all of the park low circuits 330 and 1230 to park low by outputting a logic value at the third output 618 that causes all of the park low circuits 330 and 1230 to park low. In one embodiment, the control circuit 610 can command the park high circuit 310 to park high in block 730 after determining that all of the park low circuits 330 and 1230 are parked low based on the first composite status signal or the second composite status signal, as described above.

[0114] In another embodiment, the control circuit 610 can transition to the idle mode based on the exemplary sequence 900 shown in Figure 9. In this embodiment, in block 930, the control circuit 610 can command the first park row circuit 330 to park the output 334 low and the second park row circuit 1230 to park the output 1234 low. In the embodiment of Figure 12, the control inputs 336 and 1236 of the park row circuits 330 and 1230 are coupled to the third output 618 of the control circuit 610, so that the control circuit 610 can command all of the park row circuits 330 and 1230 to park low by outputting a logic value at the third output 618 that causes all of the park row circuits 330 and 1230 to park low. In one embodiment, the control circuit 610 can instruct the park high circuit 310 to park high in block 940 after determining that all of the park low circuits 330 and 1230 are parked low based on the first composite status signal or the second composite status signal, as described above.

[0115] In one embodiment, the control circuit 610 can transition to the active mode based on an exemplary sequence 1000 shown in Figure 10. In this embodiment, in block 1030, the control circuit 610 can command the first park row circuit 330 to ungate and the second park row circuit 1230 to ungate. In the embodiment of Figure 12, the control inputs 336 and 1236 of the park row circuits 330 and 1230 are coupled to the third output 618 of the control circuit 610, so that the control circuit 610 can command all of the park row circuits 330 and 1230 to ungate by outputting a logic value at the third output 618 that causes all of the park row circuits 330 and 1230 to ungate.

[0116] In one embodiment, the control circuit 610 can transition to the active mode based on the exemplary sequence 1100 shown in Figure 11. In this embodiment, in block 1140, the control circuit 610 can command the first park row circuit 330 to ungate and the second park row circuit 1230 to ungate. In the embodiment of Figure 12, the control circuit 610 can command all of the park row circuits 330 and 1230 to ungate by outputting a logic value at the third output 618 that causes all of the park row circuits 330 and 1230 to ungate, as described above.

[0117] It should be understood that the exemplary sequences 700, 900, 1000, and 1100 are not limited to two clock branches, and that the sequences 700, 900, 1000, and 1100 can be extended to systems including three or more clock branches.

[0118] 13A illustrates an example implementation of the park-high circuit 310 and the park-low circuit 330, according to some aspects. In one embodiment, the signal input 312 of the park-high circuit 310 may be coupled to the output 216 of the clock gating circuit 210 (not shown in FIG. 13A ). In another embodiment, the clock gating circuit 210 may be omitted with the park-high circuit 310 performing the function of the clock gating circuit. The output 344 of the second signal path 340 may be coupled to the circuit 650 described above.

[0119] In this embodiment, the park high circuit 310 includes an OR gate 1310 having a first input 1312 coupled to the control input 316, a second input 1314 coupled to the signal input 312, and an output 1316 coupled to the output 314. In this embodiment, to ungate the park high circuit 310, a logical value of 0 is input to the control input 316. This is because the 0 at the first input 1312 of the OR gate 1310 causes the OR gate 1310 to pass the clock signal at the second input 1314 of the OR gate 1310 to the output 1316 of the OR gate 1310. To park the output 314 of the park high circuit 310, a logical value of 1 is input to the control input 316. This is because the 1 at the first input 1312 of the OR gate 1310 causes the OR gate 1310 to output a 1 at the output 1316 of the OR gate 1310 regardless of the logical value at the second input 1314 of the OR gate 1310.

[0120] In this embodiment, the park row circuit 330 includes an inverter 1320 and a NOR gate 1330. An input 1322 of the inverter 1320 is coupled to a signal input 332. The NOR gate 1330 has a first input 1332 coupled to a control input 336, a second input 1334 coupled to an output 1324 of the inverter 1320, and an output 1336 coupled to the output 334. Thus, in this embodiment, the second input 1334 of the NOR gate 1330 is coupled to the signal input 332 via the inverter 1320. In this embodiment, to ungate the park row circuit 330, a logic value of 0 is input to the control input 336. This is because the 0 at the first input 1332 of the NOR gate 1330 causes the NOR gate 1330 to function as an inverter coupled in series with the inverter 1320. As a result, the inverter 1320 and the NOR gate 1330 pass the clock signal at 332 to the output 334. To park the output 334 of the park low circuit 330, a logical value of 1 is input to the control input 336. This is because a 1 at the first input 1332 of NOR gate 1330 causes NOR gate 1330 to output a 0 at its output 1336, regardless of the logical value at the second input 1334 of NOR gate 1330, thereby effectively gates the park low circuit 330.

[0121] 13B illustrates an example of logic states at various locations of system 305 in idle mode, according to some embodiments. In this example, a 1 is input to control input 316 of park-high circuit 310 to park output 314 of park-high circuit 310 high (i.e., 1), and a 1 is input to control input 336 of park-low circuit 330 to park output 334 of park-low circuit 330 low (i.e., 0). In this example, first signal path 320 includes an even number of delay buffers 230-1 through 230-n, and second signal path 340 includes an even number of delay buffers 250-1 through 250-m, with the total number of delay buffers 230-1 through 230-n and 250-1 through 250-m being an even number. As a result, the logic state (i.e., logic value) at output 324 of first signal path 320 is 1 and the logic state at output 344 of second signal path 340 is 0. However, it should be appreciated that the present disclosure is not limited to this example.

[0122] It should be understood that aspects of the disclosure are not limited to an even number of delay buffers in the first signal path 320 and an even number of delay buffers in the second signal path 340. In this regard, FIG. 14A illustrates an example implementation of a system 1405 that may be used when the number of delay buffers 230-1 through 230-n in the first signal path 320 is odd and the number of delay buffers 250-1 through 250-m in the second delay path 240 is odd. The system 1405 may be used, for example, to distribute a clock signal from a clock source 690 to a circuit 650 (not shown in FIG. 14A ) coupled to an output 344 of the second signal path 340. In this example, the system 1405 includes the park-high circuit 310, the first signal path 320, and the second signal path 340 described above. The system 1405 also includes a second park-high circuit 1430 in place of the park-low circuit 330. In the following description, the park high circuit 310 is referred to as the first park high circuit 310.

[0123] In one embodiment, the signal input 312 of the first park-high circuit 310 may be coupled to the output 216 of the clock gating circuit 210 (not shown in FIG. 14A ). In another embodiment, the clock gating circuit 210 may be omitted with the first park-high circuit 310 performing the function of the clock gating circuit.

[0124] In the example shown in Figure 14A, the first park high circuit 310 includes the OR gate 1310 described above with reference to Figure 13A. However, it should be understood that the first park high circuit 310 is not limited to this example and that the first park high circuit 310 can be implemented using different types of logic gates or another one of the other exemplary implementations described above.

[0125] In this embodiment, the second park high circuit 1430 includes an inverter 1440 and a NAND gate 1450. An input 1442 of the inverter 1440 is coupled to a signal input 1432 of the second park high circuit 1430. The NAND gate 1450 has a first input 1452 coupled to a control input 1436 of the second park high circuit 1430, a second input 1454 coupled to an output 1444 of the inverter 1440, and an output 1456 coupled to an output 1434 of the second park high circuit 1430. Thus, in this embodiment, the second input 1454 of the NAND gate 1450 is coupled to the signal input 1432 through the inverter 1440. In this embodiment, a logical value of one is input to the control input 1436 to ungate the second park high circuit 1430. This is because the 1 at the first input 1452 of NAND gate 1450 causes NAND gate 1450 to function as an inverter coupled in series with inverter 1440. As a result, inverter 1440 and NAND gate 1450 pass the clock signal at signal input 1432 to output 1434. To park output 1434 of second park high circuit 1430 high, a logic value of 0 is input to control input 1436. This is because the 0 at the first input 1452 of NAND gate 1450 causes NAND gate 1450 to output a 1 at output 1456 of NAND gate 1450, regardless of the logic value at second input 1454 of NAND gate 1450, thereby effectively gates second park high circuit 1430.

[0126] In some aspects, the control input 1436 can be coupled to the control circuit 610 to enable the control circuit 610 to control the second park high circuit 1430. In these aspects, the control circuit 610 can ungate the second park high circuit 1430 in the active mode and park the output 1434 of the second park high circuit 1430 high in the idle mode.

[0127] It should be understood that the first park high circuit 310 and the second park high circuit 1430 are not limited to the exemplary implementation shown in Figure 14A. For example, in another implementation, the second park high circuit 1430 can be implemented using an OR gate and / or the first park high circuit 310 can be implemented using an inverter and a NAND gate.

[0128] 14B illustrates an example of logic states at various locations of a system 1405 in an idle mode, according to some embodiments. In this example, a 1 is input to the control input 316 of the first park-high circuit 310 to park the output 314 of the first park-high circuit 310 high (i.e., 1), and a 0 is input to the control input 1436 of the second park-high circuit 1430 to park the output 1434 of the second park-high circuit 1430 high (i.e., 1). In this example, the first signal path 320 has an odd number of delay buffers 230-1 to 230-n, and the second signal path 340 has an odd number of delay buffers 250-1 to 250-m, with the total number of delay buffers 230-1 to 230-n and 250-1 to 250-m being an even number. As a result, the logic state (i.e., logic value) at input 322 of first signal path 320 is 1 and the logic state at output 324 of first signal path 320 is 0. Also, the logic state at input 342 of second signal path 340 is 1 and the logic state at output 344 of second signal path 340 is 0. However, it should be appreciated that the disclosure is not limited to this example.

[0129] In this example, the second park-high circuit 1430 mitigates asymmetric aging by making the logic state at the input 342 of the second signal path 340 different from the logic state at the output 324 of the first signal path 320. In the example of FIG. 14B , the logic state at the input 342 of the second signal path 340 is 1 and the logic state at the output 324 of the first signal path 320 is 0. This inverts the aging path in the second signal path 340 relative to the aging path in the first signal path 320, thereby moving the duty cycle distortion in the second signal path 340 in the opposite direction to the duty cycle distortion in the first signal path 320, thereby canceling at least a portion of the duty cycle distortion in the first signal path 320.

[0130] It should be understood that the second park high circuit 1430 is not limited to the exemplary implementation shown in FIGS. 14A and 14B, and that the second park high circuit 1430 can be implemented using different types of logic gates or another of the other exemplary implementations for the park high circuit described above.

[0131] Aspects of the present disclosure may also be used when the number of delay buffers 230-1-230-n in the first signal path 320 is even, the number of delay buffers 250-1-250-m is odd (i.e., n is even and m is odd), and the total number of delay buffers 230-1-230-n and 250-1-250-m is odd. An example of this is shown in FIG. 15A using the example implementation shown in FIG. 13A. FIG. 15A shows an example of logic states at various locations of the system 1305 in idle mode when the number of delay buffers 230-1-230-n in the first signal path 320 is even, and the number of delay buffers 250-1-250-m is odd. In this embodiment, a 1 is input to the control input 316 of the first park-high circuit 310 to park the output 314 of the park-high circuit 310 high (i.e., 1), and a 1 is input to the control input 336 of the park-low circuit 330 to park the output 334 of the park-low circuit 330 low. In this embodiment, the logic state of the input 322 of the first signal path 320 is 1, and the logic state of the output 324 of the first signal path 320 is also 1. In addition, the logic state of the input 342 of the second signal path 340 is 0, and the logic state of the output 344 of the second signal path 340 is 1. In this embodiment, the number of delay buffers 250-1 to 250-m in the second signal path 340 is odd, so the logic state of the output 344 of the second signal path 340 is 1.

[0132] In this embodiment, the park low circuit 330 mitigates asymmetric aging by making the logic state at the input 342 of the second signal path 340 different from the logic state at the output 324 of the first signal path 320. This inverts the aging path in the second signal path 340 relative to the aging path in the first signal path 320, thereby moving the duty cycle distortion in the second signal path 340 in the opposite direction to the duty cycle distortion in the first signal path 320, thereby canceling at least a portion of the duty cycle distortion in the first signal path 320.

[0133] In this embodiment, the logic state at the output 344 of the second signal path 340 is 1 in the idle mode. In some cases, it is desirable for the clock input of the circuit 650 to be low (i.e., 0) in the idle mode. In these cases, to isolate the circuit 650 from the 1 at the output 344 of the second signal path 340 in the idle mode, a park low circuit 1510 can be inserted between the output 344 of the second signal path 340 and the circuit 650, one embodiment of which is shown in FIG. 15B. The park low circuit 1510 has an input 1512 coupled to the output 344 of the second signal path 340, an output 1514 coupled to the circuit 650, and a control input 1516 that can be coupled to the control circuit 610 (not shown in FIG. 15B). In this embodiment, the control circuit 610 can ungate the park low circuit 1510 in the active mode and park the output 1514 of the park low in the idle mode. The park low circuit 1510 may be implemented using any one of the exemplary implementations of park low circuits described above.

[0134] 16 shows another embodiment in which the number of delay buffers 230-1 to 230-n in the first signal path 320 is even and the number of delay buffers 250-1 to 250-m is odd (i.e., n is even and m is odd). In this embodiment, the positions of the park low circuit 330 and the park high circuit 310 are switched, such that the output 334 of the park low circuit 330 is coupled to the input 322 of the first signal path 320, the signal input 312 of the park high circuit 310 is coupled to the output 324 of the first signal path 320, and the output 314 of the park high circuit 310 is coupled to the input 342 of the second signal path 340. Thus, in this embodiment, the input 322 of the first signal path 320 is parked low in idle mode and the input 342 of the second signal path 340 is parked high in idle mode. The park-low circuit 330 can be implemented using any one of the exemplary implementations described above, and the park-high circuit 310 can be implemented using any one of the exemplary implementations described above.

[0135] In one embodiment, the signal input 332 of the park row circuit 330 may be coupled to the output 216 of the clock gating circuit 210 (not shown in FIG. 16). In another embodiment, the clock gating circuit 210 may be omitted with the park row circuit 330 performing the function of the clock gating circuit. In this embodiment, the signal input 332 of the park row circuit 330 may be coupled to a clock source 690 (shown in FIG. 6). The output 344 of the second signal path 340 may be coupled to the circuit 650 described above.

[0136] 16 illustrates an example of logic states at various locations of system 1605 in idle mode when the number of delay buffers 230-1 through 230-n in first signal path 320 is even and the number of delay buffers 250-1 through 250-m is odd. In this example, the logic state at input 322 of first signal path 320 is 0 and the logic state at output 324 of first signal path 320 is also 0. Also, the logic state at input 342 of second signal path 340 is 1 and the logic state at output 344 of second signal path 340 is 0. In this example, since the number of delay buffers 250-1 through 250-m in second signal path 340 is odd, the logic state at output 344 of second signal path 340 is 0.

[0137] Aspects of the present disclosure may also be used when the number of delay buffers 230-1-230-n in the first signal path 320 is odd, the number of delay buffers 250-1-250-m is even (i.e., n is odd and m is even), and the total number of delay buffers 230-1-230-n and 250-1-250-m is odd. An example of this is shown in FIG. 17 using the exemplary implementation shown in FIG. 14A. FIG. 17 illustrates an example of logic states at various locations of the system 1405 in idle mode when the number of delay buffers 230-1-230-n in the first signal path 320 is odd, and the number of delay buffers 250-1-250-m in the second signal path 340 is even. In this embodiment, a 1 is input to the control input 316 of the first park-high circuit 310 to park the output 314 of the park-high circuit 310 high (i.e., 1), and a 0 is input to the control input 1436 of the second park-high circuit 1430 to park the output 1434 of the park-high circuit 1430 high (i.e., 1). In this embodiment, the logic state at the input 322 of the first signal path 320 is 1, and the logic state at the output 324 of the first signal path 320 is 0. This is because, in this embodiment, the number of delay buffers 230-1 to 230-n in the first signal path 320 is an odd number. The logic state at the input 342 of the second signal path 340 is 1, and the logic state at the output 344 of the second signal path 340 is 1. This is because, in this embodiment, the number of delay buffers 250-1 to 250-m in the second signal path 340 is an even number.

[0138] In this embodiment, the logic state at output 344 of second signal path 340 is 1 in idle mode. If it is desired that the clock input of circuit 650 be low (i.e., 0) in idle mode, then a park-low circuit 1510, shown in FIG. 15B, can be inserted between output 344 of second signal path 340 and circuit 650 to isolate circuit 650 from the 1 at output 344 of second signal path 340 in idle mode, as described above.

[0139] Thus, aspects of the present disclosure mitigate duty cycle distortion due to asymmetric aging by inverting the aging path in the second signal path 340 relative to the aging path in the first signal path 320. This moves the duty cycle distortion in the second signal path 340 in the opposite direction to the duty cycle distortion in the first signal path 320, such that the duty cycle distortion in the second signal path 340 cancels at least a portion of the duty cycle distortion in the first signal path 320. As discussed above, the aging path in the second signal path 340 can be inverted relative to the aging path in the first signal path 320 using various combinations of park-low circuit(s) and / or park-high circuit(s).

[0140] In this regard, FIG. 18A illustrates an example system 1805 that generalizes the example system described above, according to various aspects of the disclosure. The system 1805 includes the first signal path 320, the second signal path 340, the clock source 690, and the circuit 650 described above. The system 1805 also includes a first park circuit 1810 and a second park circuit 1820. As used herein, a "park circuit" is a circuit having a signal input, an output, and a control input, the circuit being configured to receive a control signal at the control input and to ungate (i.e., pass the signal between the signal input and the output) if the control signal has a first value (e.g., a first logical value) and to park the output low or high if the control signal has a second control value (e.g., a second logical value), and vice versa. A "park low circuit" is a "park circuit" configured to park an output low, and a "park high circuit" is a "park circuit" configured to park an output high. Each of the first value and the second value may include one or more bits.

[0141] 18A, it should be understood that in some implementations, the system 1805 can include a park-low circuit (e.g., park-low circuit 1510) between the output 344 of the second signal path 340 and the circuit 650. For example, this can be done if it is desired that the output 344 of the second signal path 340 is 1 in idle mode and the input of the circuit 650 is 0 in idle mode.

[0142] The first parking circuit 1810 has a signal input 1812 coupled to the output 692 of the clock source 690, an output 1814 coupled to the input 322 of the first signal path 320, and a control input 1816. Although not shown in FIG. 18A , it should be understood that in some implementations, the system 1805 can include a clock gating circuit (e.g., the clock gating circuit 210) between the clock source 690 and the first parking circuit 1810. In some aspects, the first parking circuit 1810 is configured to ungate (i.e., couple the signal input 1812 and the output 1814) when the control signal at the control input 1816 has a first value (e.g., a first logical value) and park the output 1814 low or high when the control signal at the control input 1816 has a second value (e.g., a second logical value).

[0143] The second parking circuit 1820 has a signal input 1822 coupled to the output 324 of the first signal path 320, an output 1824 coupled to the input 342 of the second signal path 340, and a control input 1826. In some aspects, the second parking circuit 1820 is configured to ungate (i.e., couple the input signal 1822 and the output 1824) when the control signal at the control input 1826 has a first value (e.g., a first logical value) and park the output 1824 low or high when the control signal at the control input 1826 has a second value (e.g., a second logical value), or vice versa.

[0144] In the examples shown in Figures 3A, 3B, 4A, 4B, 4C, 6, 12, 13A, 13B, 15A, and 15B, the first park circuit 1810 includes the park high circuit 310 and the second park circuit 1820 includes the park low circuit 330. In the examples shown in Figures 14A, 14B, and 17, the first park circuit 1810 includes the park high circuit 310 and the second park circuit includes the second park high circuit 1430. In the examples shown in Figures 3C and 16, the first park circuit 1810 includes the park low circuit 330 and the second park circuit 1820 includes the park high circuit 310. The park high circuit can be implemented using any one of the exemplary implementations described above, and the park low circuit can be implemented using any one of the exemplary implementations described above.

[0145] As described above, the first signal path 320 may include an even number of delay buffers 230-1 to 230-n or an odd number of delay buffers 230-1 to 230-n, and the second signal path 340 may include an even number of delay buffers 250-1 to 250-m or an odd number of delay buffers 250-1 to 250-m.

[0146] As discussed above, the second park circuit 1820 mitigates asymmetric aging by inverting the aging path in the second signal path 340 relative to the aging path in the first signal path 320. To do so, the second park circuit 1820 can be configured to park the output 1824 at a logic value (i.e., state) that is the opposite of the logic value at the output 324 of the first signal path 320. For example, in the embodiment of FIG. 3B, the second park circuit 1820 includes a park low circuit 330 that parks the input 342 of the second signal path 340 low, which in this embodiment is the inverse of the logic value (i.e., 1) at the output 324 of the first signal path 320. In the embodiment of FIG. 14B, the second park circuit 1820 includes a second park high circuit 1430 that parks the input 342 of the second signal path 340 high, which in this embodiment is the inverse of the logical value (i.e., 0) at the output 324 of the first signal path 320.

[0147] 18B illustrates an example of one or more circuits that may be included in circuit 650. In this example, circuit 650 may include at least one of a memory device 1850, a retention flop 1852, or a processor 1854. Memory device 1850 may include dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, or another type of memory. Retention flop 1852 may include a flip-flop configured to retain a logic state in circuit 650 when a clock signal is gated. Processor 1854 may include a central processing unit (CPU) core, a digital processor, or another type of processor.

[0148] In some aspects, the inputs of the signal paths are alternately parked low and high for multiple idle periods to balance the aging of devices (e.g., transistors) in the signal paths and thus mitigate duty cycle distortion due to asymmetric aging. In this regard, FIG. 19 illustrates an example system 1905 in which asymmetric aging is mitigated by alternately parking the inputs of the signal path 220 low and high for multiple idle periods, as described further below.

[0149] System 1905 includes the above-described clock gating circuit 210, park high circuit 310, and signal path 220. In this embodiment, park high circuit 310 may be implemented using a park high gate circuit (e.g., park high gate circuit 505), a multiplexer, or another type of circuit.

[0150] The system 1905 also includes a multiplexer 1920 and a control circuit 1910. The multiplexer 1920 has a first input 1922, a second input 1924, a select input 1926, and an output 1928. In this embodiment, the signal input 312 of the park high circuit 310 is coupled to the output 216 of the clock gating circuit 210, and the output 314 of the park high circuit 310 is coupled to the first input 1922 of the multiplexer 1920. The second input 1924 of the multiplexer 1920 is coupled to the output 216 of the clock gating circuit 210, and the output 1928 of the multiplexer 1920 is coupled to the input 222 of the signal path 220. The output 224 of the signal path 220 can be coupled to the circuit 650. As discussed above, the circuit 650 can include a processor, logic gates, registers, retention flops, memory, sequential logic, or any combination thereof.

[0151] The control circuit 1910 has an input 1912, a first output 1914, a second output 1916, and a third output 1918. The input 1912 can be configured to receive a signal indicating when the circuit 650 is in an idle mode. The signal may come from a controller (not shown) configured to manage the power state of the circuit 650. The first output 1914 is coupled to the control input 212 of the clock gating circuit 210, the second output 1916 is coupled to the park high circuit 310, and the third output 1918 is coupled to a select input 1926 of the multiplexer 1920.

[0152] The control circuit 1910 can be configured to gate the clock gating circuit 210 in an idle mode (e.g., when the signal at the input 1912 indicates an idle mode). The control circuit 1910 can gate the clock gating circuit 210 by outputting a logic value at the first output 1914 that causes the clock gating circuit 210 to be gated. In this example, when gated, the clock gating circuit 210 parks the output 216 low. The control circuit 1910 can also be configured to ungate the clock gating circuit 210 in an active mode (e.g., when the signal at the input 1912 does not indicate an idle mode). The control circuit 1910 can ungate the clock gating circuit 210 by outputting a logic value at the first output 1914 that causes the clock gating circuit 210 to be ungated.

[0153] The control circuit 1910 can be configured to park the output 314 of the park high circuit 310 high in an idle mode (e.g., when the signal at the input 1912 indicates an idle mode). The control circuit 1910 can park the output 314 of the park high circuit 310 high by outputting a logic value at the second output 1916 that causes the park high circuit 310 to be parked high. The control circuit 1910 can also be configured to ungate the park high circuit 310 in an active mode (e.g., when the signal at the input 1912 does not indicate an idle mode). The control circuit 1910 can ungate the park high circuit 310 by outputting a logic value at the second output 1916 that causes the park high circuit 310 to be parked high.

[0154] In operation, the control circuit 1910 can be configured to alternately park the input 222 of the signal path 220 low and high using the multiplexer 1920 to mitigate asymmetric aging in the signal path 220. In this regard, FIG. 20 is a timing diagram illustrating an example where the control circuit 1910 alternately parks the input 222 of the signal path 220 low and high over a number of idle periods (also referred to as idle windows) using the multiplexer 1920. FIG. 20 illustrates the logic values ​​2005 (i.e., logic states) at the input 222 of the signal path 220 over a number of active periods 2010-k through 2020-(k+3) and a number of idle periods 2020-k through 2020-(k+3). Note that the timing diagram begins at the kth active period 2010-k in this example.

[0155] 20, the control circuit 1910 alternately parks the input 222 of the signal path 220 low and high over idle periods 2020-k through 320-(k+3) to balance the aging of the transistors in the signal path 220. The control circuit 1910 can park the input 222 of the signal path 220 low by instructing the multiplexer 1920 to select the second input 1924 (coupled to the output 216 of the clock gating circuit 210) and park the input 222 of the signal path 220 high by instructing the multiplexer 1920 to select the first input 1922 (coupled to the output 314 of the park-high circuit 310). In one embodiment, the control circuit 1910 instructs the multiplexer 1920 to select the first input 1922 by outputting a logical value via the third output 1918 that causes the multiplexer 1920 to select the first input 1922, and instructs the multiplexer 1920 to select the second input 1924 by outputting a logical value via the third output 1918 that causes the multiplexer 1920 to select the second input 1924.

[0156] 20, control circuit 1910 parks input 222 of signal path 220 low during idle periods 2020-k and 2020-(k+2) and parks input 222 of signal path 220 high during idle periods 2020-(k+1) and 2020-(k+3). Idle periods 2020-k and 2020-(k+2) may be even idle periods and idle periods 2020-(k+1) and 2020-(k+3) may be odd idle periods, or vice versa.

[0157] Assuming that the cumulative duration of idle periods during which the input 222 of signal path 220 is parked low is approximately equal to the cumulative duration of idle periods during which the input 222 of signal path 220 is parked high over time, the control circuit 1910 parks the input 222 of signal path 220 low and high for approximately equal durations in idle mode over time. This helps balance the aging of transistors in signal path 220, thereby reducing duty cycle distortion in signal path 220 caused by asymmetric aging.

[0158] In the embodiment of Figure 19, the logic state at output 224 of signal path 220 toggles between high and low over multiple idle periods. This is because control circuit 1910 alternately parks input 222 of signal path 220 low and high to balance aging. In some cases, it may be desirable for the clock input of circuit 650 to be low (i.e., 0) in idle mode. In these cases, to isolate circuit 650 from toggling between low and high at output 224 of signal path 220 in idle mode, a park low circuit 2110 may be inserted between output 224 of signal path 220 and circuit 650, one embodiment of which is shown in Figure 21.

[0159] 21, the park low circuit 2110 has an input 2112 coupled to the output 224 of the signal path 220, an output 2114 coupled to the circuit 650, and a control input 2116 coupled to a fourth output 2120 of the control circuit 1910. The park low circuit 2110 may be implemented using any one of the exemplary implementations of a park low circuit described above.

[0160] In this embodiment, the control circuit 1910 can be configured to ungate the park row circuit 2110 in the active mode and park the output 2114 of the park row circuit 2110 low in the idle mode to isolate the circuit 650 from toggling between low and high at the output 224 of the signal path 220 in the idle mode. For example, the control circuit 1910 can ungate the park row circuit 2110 by outputting a logic value at the fourth output 2120 that causes the park row circuit 2110 to be ungated and park the output 2114 of the park row circuit 2110 low by outputting a logic value at the fourth output 2120 that causes the park row circuit 2110 to be parked low. In one embodiment, the park row circuit 2110 is configured to ungate when the logic value at the control input 2116 has a first logic value and park the output 2114 low when the logic value at the control input 2116 has a second logic value. In this embodiment, the control circuit 1910 can ungate the park low circuit 2110 by outputting a first logic value at the fourth output 2120 and park the output 2114 of the park low circuit 2110 low by outputting a second logic value at the fourth output 2120. The first logic value can be 1 and the second logic value can be 0, or vice versa.

[0161] Figure 22 illustrates an embodiment of a system 1905 in which the park-high circuit 310 is omitted and the first input 1922 of the multiplexer 1920 is configured to receive a logical 1. In the embodiment illustrated in Figure 22, the first input 1922 receives a logical 1 by coupling the first input 1922 to the supply rail Vdd 2200.

[0162] In this embodiment, control circuitry 1910 is configured to instruct multiplexer 1920 to select second input 1924 in active mode to pass the clock signal from clock gating circuitry 210 to signal path 220 in active mode. In idle mode, control circuitry 1910 is configured to instruct multiplexer 1920 to alternately select first input 1922 and second input 1924 for multiple idle periods to alternately park input 222 of signal path 220 between high and low for multiple idle periods. For example, the control circuit 1910 can instruct the multiplexer 1920 to select the second input 1924 during idle periods 2020-k and 2020-(k+2) and park it low during idle periods 2020-k and 2020-(k+2), and to select the first input 1922 during idle periods 2020-(k+1) and 2020-(k+3) and park it high during idle periods 2020-(k+1) and 2020-(k+3). In this embodiment, the output 216 of the clock gating circuit 210 is parked low in the idle mode.

[0163] 23 illustrates a method 2300 for mitigating duty cycle distortion in a system according to some aspects. The system includes a first signal path (e.g., first signal path 320) and a second signal path (e.g., second signal path 340).

[0164] At block 2310, in an active mode, a clock signal is transmitted from a clock source to the circuitry via a first signal path and a second signal path. The clock source may correspond to the clock source 690, and the circuitry may correspond to the circuitry 650. The circuitry may include at least one of a memory device (e.g., the memory device 1850), a retention flop (e.g., the retention flop 1852), or a processor (e.g., the processor 1854). The clock signal may be transmitted from the clock source to the circuitry via the first signal path and the second signal path by the first parking circuit 1810, the second parking circuit 1820, and / or the control circuitry 610.

[0165] In block 2320, in the idle mode, the input of the first signal path is parked at a first logic state (i.e., value). The first logic state may be high (i.e., logic 1) or low (i.e., logic 0). The input of the first signal path may be parked at the first logic state by the first parking circuit 1810 and / or the control circuit 610.

[0166] In block 2330, in the idle mode, the input of the second signal path is parked at a second logic state (i.e., value). The second logic state may be high (i.e., logic 1) or low (i.e., logic 0). The input of the second signal path may be parked at the second logic state by the second parking circuit 1820 and / or the control circuit 610.

[0167] In some aspects, the second logic state is the inverse (ie, opposite) of the logic state at the output of the first signal path (eg, output 324 of first signal path 320).

[0168] The method 2300 may also include coupling an output of the first signal path to an input of the second signal path in the active mode. For example, the output of the first signal path may be coupled to the input of the second signal path by ungating the second park circuit 1820.

[0169] The method 2300 may also include coupling an input of the first signal path to a clock source and coupling an output of the second signal path to a circuit in the active mode. For example, the input of the first signal path may be coupled to the clock source by ungating the first park circuit 1810.

[0170] In some aspects, the first signal path includes a first plurality of delay buffers (e.g., delay buffers 230-1 through 230-n) coupled in series, and the second signal path includes a second plurality of delay buffers (e.g., 250-1 through 250-m) coupled in series.

[0171] In some aspects, the number of delay buffers in the first plurality of delay buffers is odd. In these aspects, the first logic state may be high and the second logic state may be high.

[0172] In some aspects, the number of delay buffers in the first plurality of delay buffers is an even number, in these aspects, the first logic state may be high and the second logic state may be low, or the first logic state may be high and the second logic state may be low.

[0173] The following numbered clauses describe example implementations. 1. a first parking circuit having a signal input, an output, and a control input; a first signal path having an input and an output, the first signal path input being coupled to the output of the first park circuit; a second park circuit having a signal input, an output, and a control input, the signal input of the second park circuit being coupled to the output of the first signal path; a second signal path having an input and an output, the second signal path input being coupled to the output of the second park circuit; A system comprising:

[0174] 2. The second park circuit is receiving a control signal at a control input of the second parking circuit; coupling a signal input of the second parking circuit to an output of the second parking circuit when the control signal has a first value; parking an output of a second parking circuit at a logic value that is the inverse of the logic value at the output of the first signal path when the control signal has a second value. It is configured as follows: 2. A system as described in clause 1.

[0175] 3. The system of clause 2, wherein the first value comprises a first logical value, the second value comprises a second logical value, and the second logical value is the inverse of the first logical value.

[0176] 4. The first park circuit is a park high circuit; The second park circuit is a park low circuit. 4. A system according to any one of clauses 1 to 3.

[0177] 5. A clock gating circuit having a clock input, a control input, and an output, the output of the clock gating circuit being coupled to a signal input of a first park circuit; a control circuit having a first input and a plurality of outputs, the plurality of outputs being coupled to a control input of the clock gating circuit, a control input of the first parking circuit, and a control input of the second parking circuit; 5. The system of claim 4, further comprising:

[0178] 6. The control circuit is receiving a clock gating signal at a first input of the control circuit; in response to the clock gate signal, causing a second parking circuit to park an output of the second parking circuit low via a first output of the plurality of outputs; causing the first parking circuit to park the output of the first parking circuit high via a second output of the plurality of outputs after the output of the second parking circuit is parked low; causing the clock gating circuit to gate the clock signal through a third output of the plurality of outputs; It is configured as follows: 5. A system as described in clause 5.

[0179] 7. The second park circuit has a status output; a control circuit having a second input coupled to the status output; a second park circuit configured to output a park low status signal via the status output when the output of the second park circuit is parked low; The control circuit receiving a parc-low status signal via a second input; in response to the park low status signal, causing the first park circuit to park an output of the first park circuit high via a second output of the plurality of outputs; It is configured as follows: 6. A system as described in clause 6.

[0180] 8. The control circuit is receiving a clock gating signal at a first input of the control circuit; in response to the clock gating signal, causing the clock gating circuit to gate the clock signal through a first output of the plurality of outputs; causing a second parking circuit to park an output of the second parking circuit low via a second output of the plurality of outputs after the clock gating circuit has gated the clock signal; causing the first parking circuit to park the output of the first parking circuit high via a third output of the plurality of outputs after the output of the second parking circuit is parked low; It is configured as follows: 5. A system as described in clause 5.

[0181] 9. The second park circuit has a status output; a control circuit having a second input coupled to the status output; a second park circuit configured to output a park low status signal via the status output when the output of the second park circuit is parked low; The control circuit receiving a parc-low status signal via a second input; in response to the park low status signal, causing the first park circuit to park an output of the first park circuit high via a third output of the plurality of outputs; It is configured as follows: 8. A system as described in clause 8.

[0182] 10. A control circuit receiving a clock enable signal at a first input of the control circuit; in response to the clock enable signal, causing the first parking circuit to ungate via a first output of the plurality of outputs; causing a second parking circuit to ungate via a second output of the plurality of outputs after the first parking circuit is ungated; causing the clock gating circuit to ungate via a third output of the plurality of outputs after the second park circuit is ungated. It is configured as follows: 10. A system according to any one of clauses 5 to 9.

[0183] 11. A control circuit receiving a clock enable signal at an input of the control circuit; in response to the clock enable signal, causing the first parking circuit to ungate via a first output of the plurality of outputs; causing the clock gating circuit to ungate through a second output of the plurality of outputs after the first park circuit is ungated; causing the second park circuit to ungate via a third output of the plurality of outputs. It is configured as follows: 10. A system according to any one of clauses 5 to 9.

[0184] 12. The system of any one of clauses 5 to 11, wherein the clock input of the clock gate circuit is coupled to a clock source.

[0185] 13. The system of claim 12, wherein the clock source comprises a phase-locked loop.

[0186] 14. The first park circuit is a multiplexer having a first input, a second input, a selection input, and an output, the first input coupled to a signal input of a first parking circuit, the second input configured to receive a logical one, the selection input coupled to a control input of the first parking circuit, and the output of the multiplexer coupled to an output of the first parking circuit; Equipped with 14. A system according to any one of clauses 4 to 13.

[0187] 15. The second park circuit a multiplexer having a first input, a second input, a selection input, and an output, the first input coupled to a signal input of a second parking circuit, the second input configured to receive a logic zero, the selection input coupled to a control input of the second parking circuit, and the output of the multiplexer coupled to an output of the second parking circuit; Equipped with 15. A system according to any one of clauses 4 to 14.

[0188] 16. The first park circuit is a logic gate having a first input, a second input, and an output, the first input of the logic gate being coupled to a control input of a first park circuit, the second input of the logic gate being coupled to a signal input of the first park circuit, and the output of the logic gate being coupled to an output of the first park circuit; Equipped with 14. A system according to any one of clauses 1 to 13.

[0189] 17. The system of claim 16, wherein the logic gate comprises an OR gate or a NAND gate.

[0190] 18. The first park circuit is a latch having a control input, a timing input, and an output, the control input of the latch being coupled to the control input of a first parking circuit, the timing input of the latch being coupled to the signal input of the first parking circuit, and the output of the latch being coupled to a first input of a logic gate; Further comprising: 16. A system as described in clause 16.

[0191] 19. The second park circuit a logic gate having a first input, a second input, and an output, the first input of the logic gate being coupled to a control input of a second park circuit, the second input of the logic gate being coupled to a signal input of the second park circuit, and the output of the logic gate being coupled to an output of the second park circuit; Equipped with 17. A system according to any one of clauses 1 to 13, 15 and 16.

[0192] 20. The system of claim 19, wherein the logic gate comprises an AND gate or a NOR gate.

[0193] 21. The second park circuit a latch having a control input, a timing input, and an output, the control input of the latch being coupled to the control input of a second parking circuit, the timing input of the latch being coupled to the signal input of the second parking circuit, and the output of the latch being coupled to a first input of a logic gate; Further comprising: 19. A system as described in clause 19.

[0194] 22. The system of any one of clauses 1 to 21, wherein an output of the second signal path is coupled to at least one of a memory device, a plurality of retention flops, and a processor.

[0195] 23. The system of any one of clauses 1 to 21, further comprising a park-row circuit having a signal input, a control input, and an output, the signal input of the park-row circuit being coupled to the output of the second signal path, and the output of the park-row circuit being coupled to at least one of a memory device, a plurality of retention flops, and a processor.

[0196] 24. A first signal path includes a first plurality of delay buffers coupled in series; the second signal path comprises a second plurality of delay buffers coupled in series; 24. A system according to any one of clauses 1 to 23.

[0197] 25. The system of claim 24, wherein the number of delay buffers in the first plurality of delay buffers is an odd number.

[0198] 26. The first park circuit is a first park high circuit; The second park circuit is a second park high circuit; 25. A system as described in clause 25.

[0199] 27. The system of claim 24, wherein the number of delay buffers in the plurality of delay buffers of 1 is an even number.

[0200] 28. The first park circuit is a park high circuit; The second park circuit is a park low circuit. 27. A system as described in clause 27.

[0201] 29. The first park circuit is a park low circuit; The second park circuit is the park high circuit. 27. A system as described in clause 27.

[0202] 30. A method for mitigating duty cycle distortion in a system, the system including a first signal path and a second signal path, the method comprising: transmitting a clock signal from a clock source to the circuit via a first signal path and a second signal path in an active mode; In idle mode, parking an input of a first signal path at a first logic state; parking an input of a second signal path at a second logic state; A method comprising:

[0203] 31. The method of claim 30, wherein the second logic state is the inverse of the logic state at the output of the first signal path.

[0204] 32. The method of clause 30 or 31, further comprising, in the active mode, coupling an output of the first signal path to an input of the second signal path.

[0205] 33. The method of clause 32, further comprising: in the active mode, coupling an input of the first signal path to a clock source; and coupling an output of the second signal path to the circuit.

[0206] 34. A first signal path includes a first plurality of delay buffers coupled in series; the second signal path comprises a second plurality of delay buffers coupled in series; 34. The method according to any one of clauses 30 to 33.

[0207] 35. The method of claim 34, wherein the number of delay buffers in the first plurality of delay buffers is an odd number.

[0208] 36. The first logic state is high; The second logic state is high. The method described in clause 35.

[0209] 37. The method of claim 34, wherein the number of delay buffers in the first plurality of delay buffers is an even number.

[0210] 38. The first logic state is high; The second logic state is low. The method described in clause 37.

[0211] 39. The first logic state is low; The second logic state is high. The method described in clause 37.

[0212] It should be appreciated that the present disclosure is not limited to the exemplary terminology used above to describe aspects of the present disclosure. For example, a serially coupled delay buffer (e.g., delay buffers 230-1 to 230-n or 250-1 to 250-m) may be referred to as a delay line, a delay chain, a delay buffer chain, or other terminology. In another example, an aging path may be referred to as an aging pattern, a propagation path, a stress pattern, a stress path, or other terminology.

[0213] Each of the control circuits 610 and 1910 may be implemented using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), a state machine, or any combination thereof, designed to perform the functions described herein. The functions described herein may be performed by a processor executing software that contains code for performing those functions. The software may be stored on a computer-readable storage medium, such as a RAM, a ROM, an EEPROM, an optical disk, and / or a magnetic disk.

[0214] Within the scope of this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures. It should also be understood that the term "ground" can refer to a DC ground or an AC ground, and therefore the term "ground" encompasses both possibilities.

[0215] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0216] 105 Signal Path 108 Input 110 Output 120-1~8 Delay Buffer 125-1~8 Transistors 130-1~8 Transistors 140 Aging Pathways 150 Clock Signal 160 Clock Signal 175 Aging Pathways 180 Clock Signal 210 Clock Gate Circuit 212 Control Input 214 Clock Input 216 Output 220 Signal Path 222 Input 224 Output 230 Delay Buffer 232 Input 234 Output 250 Delay Buffers 252-1 Input 254 Output 275 Delay Buffer 277 Supply Rail Vdd 285 NFET 290 PFET 310 First Park High Circuit 312 Signal Input 314 Output 316 Control Input 320 Signal Path 322 Input 324 Output 330 First Park Row Circuit 332 Signal Input 334 Output 336 Control Input 340 Second Signal Path 342 Input 344 Output 380 Aging Path 385 Aging Pathways 390 Aging Path 395 Aging Pathways 410 First Multiplexer 412 First Input 414 Second Input 416 Input 418 Output 420 Second Multiplexer 430 Second Multiplexer 432 First Input 434 Second Input 436 Select Input 438 Output 440 Supply Rail Vdd 450 Inverter 452 Input 454 Output 505 Park Highgate Circuit 510 Synchronizer 512 Control Input 514 Output 516 Timing Input 520 Latch 522 Control Input 524 Output 526 Timing Input 530 Logic Gates 532 First Input 534 Second Input 536 Output 537 OR Gate 540 Inverter 542 Input 544 Output 548 Park Low Gate Circuit 550 Synchronizer 552 Control Input 554 Output 556 Timing Input 560 Latch 562 Control Input 564 Output 566 Timing Input 570 Logic Gates 572 First Input 574 Second Input 576 Output 577 AND Gate 605 System 610 Control circuit 612 First Input 614 First Output 616 Second Output 618 Third Output 620 Second Input 620-1 Input 620-2 Input 622 Third Input 630 Status Output 635 Status Output 650 circuits 690 Clock Source 692 Output 694 Phase Locked Loop 810 Second Latch 812 Status Input 814 Output 816 Dimming Input 820 Second Latch 822 Status Input 824 Output 826 Timing Input 830 Second Inverter 832 Input 834 Output 1210 nodes 1215 Delay Buffer 1220 Third Signal Path 1222 Input 1224 Output 1230 Park Row Circuit 1232 signal input 1234 Output 1236 Control Input 1238 Status Output 1240 4th signal path 1242 Input 1244 Output 1250 Second Circuit 1270 First Combiner 1272 First Input 1274 Second Input 1276 Output 1278 OR Gate 1280 Second Combiner 1282 First Input 1284 Second Input 1286 Output 1288 AND Gate 1305 System 1310 OR Gate 1312 First Input 1314 Second Input 1316 Output 1320 Inverter 1322 Input 1324 Output 1330 NOR Gate 1332 First Input 1334 Second Input 1336 Output 1405 System 1430 Park High Circuit 1432 Signal Input 1434 Output 1436 Control Input 1440 Inverter 1442 Input 1444 Output 1450 NAND Gate 1452 First Input 1454 Second Input 1456 Output 1510 Park Row Circuit 1512 Input 1514 Output 1516 Control Input 1605 System 1805 System 1810 First Park Circuit 1812 Signal Input 1814 Output 1816 Control Input 1820 Second Park Circuit 1822 Signal Input 1824 Output 1826 Control Input 1850 Memory Device 1852 Retention Flop 1854 processor 1905 System 1910 Control circuit 1912 Input 1914 First Output 1916 Second Output 1918 3rd Output 1920 Multiplexer 1922 First Input 1924 Second Input 1926 Select Input 1928 Output 2110 Park Row Circuit 2112 Input 2114 Output 2116 Control Input 2120 4th output

Claims

1. A first park circuit having a signal input, an output, and a control input, wherein in response to a first control signal at the control input of the first park circuit, the first park circuit couples the signal input of the first park circuit to the output of the first park circuit or parks the output of the first park circuit at a first logical value; a first park circuit; A first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit; a first signal path; A second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path, and in response to a second control signal at the control input of the second park circuit, the second park circuit couples the signal input of the second park circuit to the output of the second park circuit or parks the output of the second park circuit at a second logical value; a second park circuit; A second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit; a second signal path; A system comprising the above.

2. The second park circuit is configured to receive the second control signal at the control input of the second park circuit, couple the signal input of the second park circuit to the output of the second park circuit when the second control signal has a first value, park the output of the second park circuit at the second logical value which is the inversion of the logical value at the output of the first signal path when the second control signal has a second value, wherein the first value includes a first logical value, the second value includes a second logical value, and the second logical value is the inversion of the first logical value. The system according to claim 1.

3. The first park circuit is a park high circuit that parks the output of the first park circuit at a high logical value, The second park circuit is a park low circuit that parks the output of the second park circuit at a low logical value. The system according to claim 1.

4. ​ A clock gate circuit having a clock input, a control input, and an output, wherein the output of the clock gate circuit is coupled to the signal input of the first park circuit. A control circuit having a first input and a plurality of outputs, wherein the plurality of outputs are coupled to the control input of the clock gate circuit, the control input of the first park circuit, and the control input of the second park circuit. The system according to claim 3, further comprising the above.

5. The control circuit is Receiving a clock gate signal at the first input of the control circuit, In response to the clock gate signal, causing the output of the second park circuit to be parked low via a first output of the plurality of outputs to the second park circuit, After the output of the second park circuit is parked low, causing the output of the first park circuit to be parked high via a second output of the plurality of outputs to the first park circuit, Gating a clock signal to the clock gate circuit via a third output of the plurality of outputs. Configured as The second park circuit has a status output, The control circuit has a second input coupled to the status output, The second park circuit is configured to output a park low status signal via the status output when the output of the second park circuit is parked low. The control circuit is Receiving the park low status signal via the second input, In response to the park low status signal, causing the output of the first park circuit to be parked high via the second output of the plurality of outputs to the first park circuit. Configured as above. The system according to claim 4.

6. The control circuit is Receiving a clock gate signal at the first input of the control circuit, In response to the clock gate signal, gating a clock signal to the clock gate circuit via a first output of the plurality of outputs, After the clock gate circuit gates the clock signal, causing the output of the second park circuit to be parked low via a second output of the plurality of outputs to the second park circuit. After the output of the second park circuit is parked low, the output of the first park circuit is parked high via a third output of the plurality of outputs to the first park circuit. configured as the second park circuit has a status output, the control circuit has a second input coupled to the status output, the second park circuit is configured to output a park low status signal via the status output when the output of the second park circuit is parked low, the control circuit receives the park low status signal via the second input, and in response to the park low status signal, parks the output of the first park circuit high via the third output of the plurality of outputs to the first park circuit. configured as The system according to claim 4.

7. the control circuit receives a clock enable signal at the first input of the control circuit, in response to the clock enable signal, gates the first park circuit via a first output of the plurality of outputs, a) after the first park circuit is gated, gates the second park circuit via a second output of the plurality of outputs, after the second park circuit is gated, gates the clock gate circuit via a third output of the plurality of outputs, or b) after the first park circuit is gated, gates the clock gate circuit via a second output of the plurality of outputs, and gates the second park circuit via a third output of the plurality of outputs. configured as The system according to claim 4.

8. the clock input of the clock gate circuit is coupled to a clock source, the clock source includes a phase locked loop, The system according to claim 4.

9. [[ID= A multiplexer having a first input, a second input, a selection input, and an output, wherein the first input is coupled to the signal input of the first park circuit, the second input is configured to receive a logic 1, the selection input is coupled to the control input of the first park circuit, and the output of the multiplexer is coupled to the output of the first park circuit, a multiplexer. Comprising The second park circuit A multiplexer having a first input, a second input, a selection input, and an output, wherein the first input is coupled to the signal input of the second park circuit, the second input is configured to receive a logic 0, the selection input is coupled to the control input of the second park circuit, and the output of the multiplexer is coupled to the output of the second park circuit, a multiplexer. Comprising The system according to claim 3.

10. The first park circuit A logic gate having a first input, a second input, and an output, wherein the first input of the logic gate is coupled to the control input of the first park circuit, the second input of the logic gate is coupled to the signal input of the first park circuit, and the output of the logic gate is coupled to the output of the first park circuit, a logic gate, and A latch having a control input, a timing input, and an output, wherein the control input of the latch is coupled to the control input of the first park circuit, the timing input of the latch is coupled to the signal input of the first park circuit, and the output of the latch is coupled to the first input of the logic gate, a latch. Comprising The logic gate includes an OR gate or a NAND gate. The system according to claim 1.

11. The second park circuit A logic gate having a first input, a second input, and an output, wherein the first input of the logic gate is coupled to the control input of the second park circuit, the second input of the logic gate is coupled to the signal input of the second park circuit, and the output of the logic gate is coupled to the output of the second park circuit, a logic gate, and A latch having a control input, a timing input, and an output, wherein the control input of the latch is coupled to the control input of the second park circuit, the timing input of the latch is coupled to the signal input of the second park circuit, and the output of the latch is coupled to the first input of the logic gate. Comprising The logic gate includes an AND gate or a NOR gate The system according to claim 1.

12. The output of the second signal path is coupled to at least one of a memory device, a plurality of retention flip-flops, and a processor. The system further comprises a park-low circuit having a signal input, a control input, and an output, wherein the signal input of the park-low circuit is coupled to the output of the second signal path, and the output of the park-low circuit is coupled to at least one of a memory device, a plurality of retention flip-flops, and a processor. The system according to claim 1.

13. The first signal path comprises a first plurality of delay buffers coupled in series. The second signal path comprises a second plurality of delay buffers coupled in series. The system according to claim 1.

14. a) The number of delay buffers in the first plurality of delay buffers is odd, The first park circuit is a first park-high circuit, The second park circuit is a second park-high circuit. Or b) The number of delay buffers in the first plurality of delay buffers is even, The first park circuit is a park-high circuit that parks the output of the first park circuit at a high logic value, The second park circuit that parks the output of the second park circuit at a low logic value is a park-low circuit. Or The first park circuit is a park-low circuit, The second park circuit is a park-high circuit. The system according to claim 13.

15. A method for reducing duty cycle distortion in a system, the system including a first park circuit, a first signal path, a second park circuit, and a second signal path coupled in a row, the method comprising: In the active mode, transmitting a clock signal from a clock source to the circuit through the first park circuit, the first signal path, the second park circuit, and the second signal path. In the idle mode, parking the input of the first signal path to a first logic state using the first parking circuit; parking the input of the second signal path to a second logic state using the second parking circuit; A method comprising the above.

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