PACKAGE HAVING SUBSTRATE WITH HIGH DIFFERENT INTERCONNECTS - Patent application

Abstract

A package including a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate, the substrate including at least one dielectric layer, a first plurality of high density interconnects disposed within the at least one dielectric layer and through the first surface of the at least one dielectric layer, and a second plurality of high density interconnects disposed within the at least one dielectric layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of non-provisional application Ser. No. 17 / 479,691, filed in the United States Patent Office on September 20, 2021, the entire contents of which are incorporated by reference herein as if fully set forth in its entirety below, and for all applicable purposes.

[0002] Various features relate to a package having a substrate. [Background technology]

[0003] A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing various electrical functions. There is a continuing need to provide better performing packages and to reduce the overall size of the package. Summary of the Invention

[0004] Various features relate to a package having a substrate. [Means for solving the problem]

[0005] One example provides a package including a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes at least one dielectric layer, a first plurality of interconnects disposed within the at least one dielectric layer through the first surface of the at least one dielectric layer, and a second plurality of interconnects disposed within the at least one dielectric layer through the second surface of the at least one dielectric layer. The first plurality of interconnects include a first width and a first spacing. The second plurality of interconnects include a second width and a second spacing. The substrate includes a third plurality of interconnects disposed within the at least one dielectric layer. The third plurality of interconnects include a third width greater than the first width and the second width. The third plurality of interconnects include a third spacing greater than the first spacing and the second spacing.

[0006] Another example provides an apparatus including a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate, the substrate including at least one dielectric layer, a first means for high density interconnects disposed within the at least one dielectric layer through the first surface of the at least one dielectric layer, and a second means for high density interconnects disposed within the at least one dielectric layer through the second surface of the at least one dielectric layer.

[0007] Another example provides a method for manufacturing a substrate. The method provides a first carrier comprising a first seed layer. The method forms a first plurality of high density interconnects on the first seed layer. The method forms a first dielectric layer on the first plurality of high density interconnects. The method forms a plurality of interconnects in and / or on the first dielectric layer. The method provides a second carrier comprising a second seed layer. The method forms a second plurality of high density interconnects on the second seed layer. The method bonds the second carrier comprising the second seed layer and the second plurality of high density interconnects to the first carrier comprising the first seed layer, the first plurality of high density interconnects, the first dielectric layer, and the plurality of interconnects via the second dielectric layer. The method separates the second carrier and the first carrier. The method removes a portion of the first seed layer and a portion of the second seed layer.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] 1 shows a cross-sectional view of a package including a substrate having high density interconnects. [Diagram 2] A detailed view of a package including a substrate with high density interconnects is shown. [Diagram 3] A detailed view of a package including a substrate with high density interconnects is shown. [Figure 4A] 1 illustrates an exemplary sequence for manufacturing a substrate having high density interconnects. [Figure 4B] 1 illustrates an exemplary sequence for manufacturing a substrate having high density interconnects. [Figure 4C] 1 illustrates an exemplary sequence for manufacturing a substrate having high density interconnects. [Diagram 5] 1 illustrates an exemplary sequence for manufacturing a substrate having high density interconnects. [Figure 6A] 1 illustrates an exemplary sequence for manufacturing a package with a substrate having high density interconnects. [Figure 6B] 1 illustrates an exemplary sequence for manufacturing a package with a substrate having high density interconnects. [Figure 7] 1 illustrates an exemplary sequence for manufacturing a package having a substrate with high density interconnects. [Figure 8] Various electronic devices are illustrated that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are described to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a package including a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes at least one dielectric layer, a first plurality of high density interconnects disposed within the at least one dielectric layer through the first surface of the at least one dielectric layer, a second plurality of high density interconnects disposed within the at least one dielectric layer through the second surface of the at least one dielectric layer, and a solder resist layer disposed on the at least one dielectric layer. The use of the first plurality of high density interconnects on a first side of the substrate and the second plurality of high density interconnects on a second side of the substrate helps provide high density and high speed communication for the integrated devices while reducing the overall height and / or size of the package.

[0012] Exemplary Package with Substrate Having High Density Interconnects 1 shows a cross-sectional view of a package 100 including a substrate with high density interconnects. The package 100 includes a substrate 102, an integrated device 104, an integrated device 106, and an encapsulation layer 108.

[0013] The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, a solder resist layer 124, and a solder resist layer 126. The substrate 102 may be a coreless substrate. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). As described further below, the substrate 102 includes a plurality of high density interconnects disposed on a first side (e.g., a top side) of the substrate 102 and a plurality of high density interconnects disposed on a second side (e.g., a bottom side) of the substrate 102. The plurality of interconnects 122 may include a plurality of interconnects 122a, a plurality of interconnects 122b, and a plurality of interconnects 122c. Using high density interconnects on both sides of the substrate 102 may enable more electrical connections (e.g., higher density electrical routing) to / from integrated devices in a smaller space while still reducing the size of the package, enabling high speed communication.

[0014] The plurality of interconnects 122a includes a plurality of high density interconnects. The plurality of interconnects 122a may include interconnects disposed on a top metal layer of the substrate 102, such as an M1 layer (e.g., a first metal layer). The plurality of interconnects 122a may be embedded in at least one dielectric layer 120. The plurality of interconnects 122a may be disposed in a first metal layer embedded in at least one dielectric layer 120. The plurality of interconnects 122a includes a minimum width of about 3-4 micrometers and a minimum spacing of about 3-4 micrometers. The plurality of interconnects 122a may include at least one interconnect having a width of about 3-4 micrometers or more. The plurality of interconnects 122a may include at least one interconnect having a spacing of about 3-4 micrometers or more.

[0015] The plurality of interconnects 122b includes a plurality of high density interconnects. The plurality of interconnects 122b may include interconnects disposed on a metal layer adjacent to a bottom metal layer of the substrate 102 (e.g., a metal layer adjacent to the last metal layer, M3 layer). The plurality of interconnects 122b may be embedded in the at least one dielectric layer 120. The plurality of interconnects 122b may be disposed in a last metal layer embedded in the at least one dielectric layer 120. The plurality of interconnects 122b includes a minimum width of about 3-4 micrometers and a minimum spacing of about 3-4 micrometers. The plurality of interconnects 122b may include at least one interconnect having a width of about 3-4 micrometers or more. The plurality of interconnects 122b may include at least one interconnect having a spacing of about 3-4 micrometers or more.

[0016] The plurality of interconnects 122c may be disposed within the at least one dielectric layer 120. The plurality of interconnects 122c may be disposed on a bottom surface of the at least one dielectric layer 120. The plurality of interconnects 122c may be surrounded by a solder resist layer 126. The plurality of interconnects 122c includes a minimum width of about 8 micrometers and a minimum spacing of about 8 micrometers. The plurality of interconnects 122c may include at least one interconnect having a width of about 8 micrometers or greater. The plurality of interconnects 122c may include at least one interconnect having a spacing of about 8 micrometers or greater.

[0017] 2 and 3 show and explain in more detail various examples of high density interconnects for a substrate.

[0018] As shown in FIG. 1 , the integrated device 104 is coupled to a first surface (e.g., top surface) of the substrate 102. For example, the integrated device 104 is coupled to the plurality of interconnects 122a of the substrate 102 via a plurality of solder interconnects 140 (e.g., a first plurality of solder interconnects, a means for a first solder interconnect) and / or a plurality of pillar interconnects 142 (e.g., a first plurality of pillar interconnects, a means for a first pillar interconnect). An encapsulation layer 108 is coupled to the substrate 102 and the integrated device 104. The encapsulation layer 108 is disposed on the first surface of the substrate 102. The encapsulation layer 108 encapsulates the integrated device 104. The encapsulation layer 108 may be disposed on and / or around the integrated device 104. The encapsulation layer 108 may be a means for encapsulation.

[0019] The integrated device 106 is coupled to a second surface (e.g., a bottom surface) of the substrate 102. For example, the integrated device 106 is coupled to the plurality of interconnects 122b of the substrate 102 via a plurality of solder interconnects 160 (e.g., a second plurality of solder interconnects, a means for a second solder interconnect) and / or a plurality of pillar interconnects 162 (e.g., a second plurality of pillar interconnects, a means for a second pillar interconnect).

[0020] The plurality of solder interconnects 130 may be coupled to the substrate 102. For example, the plurality of solder interconnects 130 may be coupled to the plurality of interconnects 122c. The plurality of solder interconnects 130 may be coupled to interconnects from a final metal layer (e.g., M4 layer) of the substrate 102.

[0021] Figure 2 shows a detailed view of package 100. As shown in Figure 2, package 100 includes a substrate 102, an integrated device 104, and an integrated device 106. Substrate 102 includes a plurality of interconnects 122. The plurality of interconnects 122 includes a plurality of interconnects 122a, a plurality of interconnects 122b, and a plurality of interconnects 122c.

[0022] The integrated device 104 is coupled to the plurality of interconnects 122a via the plurality of solder interconnects 140. The integrated device 104 is coupled to the plurality of interconnects 122a via the plurality of pillar interconnects 142 and / or the plurality of solder interconnects 240 (e.g., a first plurality of solder interconnects, a means for a first solder interconnect). It should be noted that the plurality of solder interconnects 140 and the plurality of solder interconnects 240 may be considered as part of the same group of solder interconnects even if they have different sizes and / or volumes. The plurality of interconnects 122a includes a plurality of high density interconnects. The plurality of interconnects 122a may include interconnects disposed on a top metal layer of the substrate 102, such as an M1 layer (e.g., a first metal layer). The plurality of interconnects 122a may be disposed (e.g., embedded) within at least one dielectric layer 120. The plurality of interconnects 122a may be disposed through a first surface of the at least one dielectric layer 120. For example, the plurality of interconnects 122a may include interconnects disposed (e.g., embedded) within the at least one dielectric layer 120 through a first surface of the at least one dielectric layer 120. At least some of the interconnects of the plurality of interconnects 122a may have interconnect surfaces that lie in a plane with the first surface (e.g., top surface) of the at least one dielectric layer 120. The plurality of interconnects 122a includes a minimum width of about 3-4 micrometers and a minimum spacing of about 3-4 micrometers. The plurality of interconnects 122a may include at least one interconnect having a width of about 3-4 micrometers or more. The plurality of interconnects 122a may include at least one interconnect having a spacing of about 3-4 micrometers or more.

[0023] The integrated device 106 is coupled to the plurality of interconnects 122b via the plurality of solder interconnects 160. The integrated device 106 is coupled to the plurality of interconnects 122b via the plurality of pillar interconnects 162 and / or the plurality of solder interconnects 260 (e.g., a second plurality of solder interconnects, a means for second solder interconnection). It should be noted that the plurality of solder interconnects 160 and the plurality of solder interconnects 260 may be considered as part of the same group of solder interconnects even if they have different sizes and / or volumes. The integrated device 106 is coupled to an interconnect from the M3 layer of the substrate 102. The plurality of interconnects 122b includes a plurality of high density interconnects. The plurality of interconnects 122b may be disposed (embedded) within the at least one dielectric layer 120. The plurality of interconnects 122b may be disposed through a second surface of the at least one dielectric layer 120. For example, the plurality of interconnects 122b may include interconnects embedded in the at least one dielectric layer 120 through a second surface of the at least one dielectric layer 120. At least some of the interconnects of the plurality of interconnects 122b may have an interconnect surface that lies in a plane with the second surface (e.g., bottom surface) of the at least one dielectric layer 120. The plurality of interconnects 122b may include interconnects disposed on a metal layer adjacent to the last metal layer of the substrate 102 (e.g., a metal layer adjacent to the bottom metal layer, M3 layer). The plurality of interconnects 122b may include interconnects disposed on a last metal layer embedded in the at least one dielectric layer 120. The plurality of interconnects 122b may include a minimum width of about 3-4 micrometers and a minimum spacing of about 3-4 micrometers. The plurality of interconnects 122b may include at least one interconnect having a width of about 3-4 micrometers or greater. The plurality of interconnects 122b may include at least one interconnect having a spacing of approximately 3-4 micrometers or greater.

[0024] In some implementations, at least some of the interconnects 122c may be disposed within the at least one dielectric layer 120. In some implementations, at least some of the interconnects 122c may be disposed on a second surface (e.g., bottom surface) of the at least one dielectric layer 120. The interconnects 122c may be surrounded by a solder resist layer 126. The interconnects 122c may be a means for interconnection. The interconnects 122c may include interconnects disposed on the last metal layer (e.g., bottom metal layer, M4 layer) of the substrate 102. It should be noted that the interconnects 122c may include interconnects disposed on other metal layers, such as the M2 layer. At least some of the plurality of interconnects 122c disposed on the second surface of the at least one dielectric layer 120 may have an interconnect surface lying in a plane with the second surface of the at least one dielectric layer 120, and / or another interconnect surface of at least one of the plurality of interconnects 122b disposed through the second surface of the at least one dielectric layer 120. For example, one of the plurality of interconnects 122b (e.g., a high density interconnect, a high density trace interconnect, a high density pad interconnect) may have an interconnect surface facing away from the at least one dielectric layer 120 that lies in a plane with another interconnect surface of one of the plurality of interconnects 122c (e.g., a trace interconnect, a pad interconnect) facing towards the at least one dielectric layer 120, and one of the plurality of interconnects 122c (e.g., a trace interconnect, a pad interconnect) is disposed on the second surface of the at least one dielectric layer 120. The plurality of interconnects 122c includes a minimum width of about 8 micrometers and a minimum spacing of about 8 micrometers. The plurality of interconnects 122c can include at least one interconnect having a width of about 8 micrometers or greater. The plurality of interconnects 122c can include at least one interconnect having a spacing of about 8 micrometers or greater.

[0025] Figure 3 shows a detailed view of package 300. Package 300 is similar to package 100 and may include similar components and / or components configured in a similar manner as package 100. As shown in Figure 3, package 300 includes substrate 102, integrated device 104, and integrated device 106. Substrate 102 includes multiple interconnects 122. Multiple interconnects 122 include multiple interconnects 122a, multiple interconnects 122b, and multiple interconnects 122c.

[0026] The integrated device 106 is coupled to the plurality of interconnects 122c via the plurality of solder interconnects 160. The integrated device 106 is coupled to the plurality of interconnects 122b via the plurality of pillar interconnects 162 and / or the plurality of solder interconnects 260. The integrated device 106 is coupled to the interconnects from the M3 and M4 layers of the substrate 102. The plurality of interconnects 122b includes a plurality of high density interconnects. The plurality of interconnects 122b may be embedded in the at least one dielectric layer 120. The plurality of interconnects 122c may be disposed within the at least one dielectric layer 120 and on a second surface (e.g., a bottom surface) of the at least one dielectric layer 120. FIG. 3 shows that the integrated device 106 may be coupled to the interconnects within the at least one dielectric layer 120 and to the interconnects disposed on the second surface of the at least one dielectric layer 120.

[0027] 1-3 illustrate and explain how high density interconnects may be disposed on both sides and / or both surfaces of a substrate. This allows for providing high speed communication to integrated devices disposed on both sides of the substrate. The high density interconnects disposed on both sides and / or both surfaces of the substrate may be configured to be coupled together via non-high density interconnects. For example, the plurality of interconnects 122a (e.g., a first plurality of high density interconnects) and the plurality of interconnects 122b (e.g., a second plurality of high density interconnects) may be configured to be coupled together via other interconnects (e.g., non-high density interconnects) of the plurality of interconnects 122. As will be further described, the high density interconnects (e.g., 122a, 122b) may be fabricated using an embedded trace substrate (ETS) process. The number of metal layers shown on the substrate 102 is exemplary. Different implementations of the substrate may have different numbers of metal layers. For example, the substrate may include seven metal layers (e.g., M1-M7 layers). In such an example, the plurality of interconnects 122a may include interconnects disposed on an M1 metal layer (e.g., a first metal layer), the plurality of interconnects 122b may include interconnects disposed on an M6 metal layer (e.g., adjacent to a bottom metal layer, adjacent to a last metal layer), and the plurality of interconnects 122c may include interconnects on an M7 metal layer (e.g., a last metal layer, a bottom metal layer). Note that the numbering of the metal layers goes from the top to the bottom of the substrate. However, the numbering of the metal layers may go from the bottom to the top of the substrate. The trace interconnects and / or pad interconnects may be disposed on one or more metal layers of the substrate. The via interconnects may be disposed between metal layers of the substrate. Note that the bottom surface and / or top surface described in this disclosure may be defined arbitrarily. In some implementations, the first surface may be a bottom surface and the second surface may be a top surface. In some implementations, the second surface may be a bottom surface and the first surface may be a top surface.

[0028] 2 and 3 show that the vertical spacing between the interconnects from the M3 layer and the interconnects from the M4 layer is smaller (e.g., closer) than the vertical spacing between the interconnects from the M3 layer and the interconnects from the M2 layer. This configuration may help provide a thinner substrate than other substrates having the same number of metal layers. Note that the widths, spacings, minimum widths, and / or minimum spacings mentioned for the various interconnects are exemplary. In some implementations, the widths, spacings, minimum widths, and / or minimum spacings of the interconnects may vary. In some implementations, different combinations of widths, spacings, minimum widths, and / or minimum spacings of the interconnects may be used for the substrate. Any combination of widths, spacings, minimum widths, and / or minimum spacings used for the interconnects may depend on the design and / or requirements of the package including the integrated device(s) and the substrate. For example, in some implementations, the substrate 102 may include (i) a plurality of interconnects 122a and / or a plurality of interconnects 122b having interconnects with a minimum width of about 6 micrometers and / or a minimum spacing of about 8 micrometers, and (ii) a plurality of interconnects 122c having interconnects with a minimum width of about 10 micrometers and / or a minimum spacing of about 15 micrometers. In some implementations, the substrate 102 may include (i) a plurality of interconnects 122a and / or a plurality of interconnects 122b having interconnects with a width of about 6 micrometers or more and / or spacing of about 8 micrometers or more, and (ii) a plurality of interconnects 122c having interconnects with a width of about 10 micrometers or more and / or a minimum spacing of about 15 micrometers or more.

[0029] As used in this disclosure, a high density interconnect can be an interconnect that has a smaller minimum width and / or a smaller minimum spacing than other interconnects of the substrate. As used in this disclosure, a high density interconnect can be an interconnect that has a smaller width and / or a smaller spacing than other interconnects of the substrate. In some implementations, the high density interconnect of the substrate can be a first plurality of interconnects of the substrate, and the other interconnects of the substrate (e.g., non-high density interconnects) can be a second plurality of interconnects and / or a third plurality of interconnects of the substrate. In some implementations, the high density interconnect of the substrate can be similar to the interconnect of the substrate (e.g., non-high density interconnects), except that the high density interconnect has an improved width and / or spacing that allows for denser routing within the substrate. A plurality of interconnects that includes a particular width and / or a particular spacing can mean that one or more of the interconnects of the plurality of interconnects each have a particular width and / or a particular spacing. A plurality of interconnects including a particular minimum width and / or a particular minimum spacing may mean that one or more of the interconnects in the plurality of interconnects each have a particular minimum width and / or a particular minimum spacing.

[0030] The integrated device (e.g., 104, 106) may include a die (e.g., a semiconductor bare die). The integrated device may include an integrated circuit. The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 104, 106) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may be an example of an electrical component and / or an electrical device.

[0031] The package (e.g., 100, 300) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end package (RFFE). The package (e.g., 100, 300) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 300) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 100, 300) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0032] Having described various packages having substrates, several methods for manufacturing the substrates are now described below.

[0033] Exemplary Sequence for Manufacturing a Substrate In some implementations, manufacturing a substrate includes several processes. Figures 4A-4C show an exemplary sequence for providing or manufacturing a substrate. Figures 4A-4C can be used to provide or manufacture a coreless substrate. In some implementations, the sequence of Figures 4A-4C can be used to provide or manufacture a substrate 102. However, the process of Figures 4A-4C can be used to manufacture any of the substrates described in this disclosure.

[0034] Note that the sequences in FIGS. 4A-4C can combine one or more steps to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the process can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0035] Step 1 shows the state after a first carrier 400 is provided, as shown in FIG. 4A. A first seed layer 401 and interconnects 402 can be disposed on the first carrier 400. The interconnects 402 can be disposed on the first seed layer 401. The interconnects 402 can be formed using an electroplating process or an etching process. In some implementations, the first carrier 400 can be provided with the first seed layer 401 and a metal layer patterned to form the interconnects 402. The interconnects 402 can include high-density interconnects. For example, the interconnects 402 can represent at least some of the high-density interconnects among a plurality of interconnects 122a.

[0036] Step 2 shows the state after a dielectric layer 420 is formed on the first carrier 400, the first seed layer 401, and the interconnects 402. The dielectric layer 420 can be formed using a deposition and / or lamination process. The dielectric layer 420 can include polyimide. However, different implementations can use different materials for the dielectric layer.

[0037] Step 3 shows the state after a plurality of cavities 410 are formed in the dielectric layer 420. The plurality of cavities 410 can be formed using an etching process (e.g., a photolithography etching process) or a laser process.

[0038] Stage 4 shows the state after interconnects 412 have been formed in and on dielectric layer 420, including in and over the plurality of cavities 410. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects. Note that stages 2-4 may be repeated iteratively to form additional dielectric layers and additional interconnects.

[0039] Stage 5, as shown in FIG. 4B , illustrates the state after the second carrier 406 is provided. A second seed layer 407 and interconnects 408 may be disposed on the second carrier 406. The interconnects 408 may be disposed on the second seed layer 407. A plating process or an etching process may be used to form the interconnects 408. In some implementations, the second carrier 406 may be provided with the second seed layer 407 and a metal layer that is patterned to form the interconnects 408. The interconnects 408 may include high density interconnects. For example, the interconnects 408 may represent at least some of the high density interconnects of the plurality of interconnects 122b.

[0040] Step 6 shows the process of bonding the second carrier 406, the second seed layer 407, the interconnect 408, and the dielectric layer 422 to the dielectric layer 420 and the interconnect 412. The dielectric layer 422 may include a prepreg.

[0041] Stage 7 shows the state after the second carrier 406, the second seed layer 407, the interconnects 408, and the dielectric layer 422 have been bonded to the dielectric layer 420, the interconnects 412, the interconnects 402, the first seed layer 401, and the first carrier 400. A lamination process can be used to bond the second carrier 406, the second seed layer 407, the interconnects 408, and the dielectric layer 422 to the dielectric layer 420, the interconnects 412, the interconnects 402, the first seed layer 401, and the first carrier 400.

[0042] Stage 8 shows the condition after the second carrier 406 has been separated (eg, detached, removed) from the second seed layer 407.

[0043] Stage 9, as shown in Figure 4C, shows the state after a number of cavities 430 have been formed in the dielectric layer 422. The cavities 430 can be formed using an etching process or a laser process.

[0044] Stage 10 shows the state after interconnects 414 have been formed in and on dielectric layer 422, including in and over a plurality of cavities 430. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0045] Some or all of the interconnects 402, 408, 412, and / or 414 may define a plurality of interconnects 122 of the substrate 102. For example, the interconnect 402 may be represented by a plurality of interconnects 122a, the interconnect 408 may be represented by a plurality of interconnects 122b, and the interconnects 412 and 414 may be represented by a plurality of interconnects 122c. The dielectric layer 420 and the dielectric layer 422 may be represented by at least one dielectric layer 120. The dielectric layers 420 and / or 422 may include prepreg. In some implementations, the dielectric layer 420 may include Ajinomoto build-up film (ABF) and / or polyimide. In some implementations, the at least one dielectric layer 120 may include at least one layer of prepreg and at least one layer of ABF. In some implementations, the at least one dielectric layer 120 may include at least one layer of prepreg and at least one layer of polyimide.

[0046] Stage 11 shows the state after the first carrier 400 has been separated (e.g., detached, removed, ground) from the at least one dielectric layer 120 and the first seed layer 401, a portion of the first seed layer 401 has been removed (e.g., etched away), and a portion of the second seed layer 407 has been removed (e.g., etched away), leaving behind the at least one dielectric layer 120 and the substrate 102 including a plurality of interconnects 122. The plurality of interconnects 122 includes a plurality of interconnects 122a, a plurality of interconnects 122b, and a plurality of interconnects 122c. The substrate 102 may be a coreless substrate.

[0047] Stage 12 shows the state after solder resist layer 124 and solder resist layer 126 have been formed on substrate 102. A deposition process may be used to form solder resist layer 124 and solder resist layer 126. In some implementations, zero or one solder resist layer may be formed on at least one dielectric layer 120.

[0048] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process to form the metal layer(s). For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0049] 1 is an exemplary flow diagram of a method for manufacturing a substrate; In some implementations, manufacturing a substrate includes several processes. Figure 5 shows an example flow diagram of a method 500 for providing or manufacturing a substrate. In some implementations, the method 500 of Figure 5 can be used to provide or manufacture the substrate(s) of Figures 1-3. For example, the method of Figure 5 can be used to manufacture the substrate 102.

[0050] It should be noted that the method 500 of Figure 5 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate, and in some implementations, the order of the processes may be changed or modified.

[0051] The method provides (at 505) a first carrier (e.g., 400). Different implementations may use different materials for the first carrier 400. The first carrier 400 may include a first seed layer (e.g., 401). The first seed layer 401 may include a metal (e.g., copper). The first carrier may include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 4A illustrates and describes one example of a first carrier having a first seed layer provided.

[0052] The method forms and patterns (at 510) interconnects on the first carrier 400 and the first seed layer 401. A metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and seed layer may include a metal layer. A metal layer is disposed on the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 402). Step 1 of FIG. 4A illustrates and describes one example of an interconnect on a seed layer and a carrier.

[0053] The method forms (at 515) a dielectric layer 420 over the first seed layer 401, the first carrier 400, and the interconnect 402. A deposition and / or lamination process may be used to form the dielectric layer 420. The dielectric layer 420 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 410) in the dielectric layer 420. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 2 and 3 of FIG. 4A illustrate and describe one example of forming a dielectric layer and cavities in the dielectric layer.

[0054] The method forms (at 520) an interconnect in and on the dielectric layer. For example, the interconnect 412 can be formed in and on the dielectric layer 420. A plating process can be used to form the interconnect. Forming the interconnect can include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnect can also include forming the interconnect in a cavity in the dielectric layer. Step 4 of FIG. 4A illustrates and describes one example of forming an interconnect in and on the dielectric layer. It should be noted that some methods may iteratively provide and / or form additional interconnects and additional dielectric layers as described at 515 and 520.

[0055] The method provides (at 525) a second carrier (e.g., 406). Different implementations may use different materials for the second carrier 406. The second carrier may include a second seed layer (e.g., 407). The second seed layer 407 may include a metal (e.g., copper). The second carrier may include a substrate, glass, quartz, and / or a carrier tape. The method may also form and pattern (at 525) an interconnect 408 on the second carrier 406 and the second seed layer 407. A metal layer may be patterned to form the interconnect. A plating process may be used to form the metal layer and the interconnect. Step 5 of FIG. 4B illustrates and describes one example of a second carrier having a second seed layer and an interconnect.

[0056] The method bonds (at 530) the second carrier 406, the second seed layer 407, the interconnect 408, and the dielectric layer 422 to the first carrier 400, the first seed layer 401, the interconnect 402, and the dielectric layer 420. A lamination process can be used to bond the second carrier 406, the second seed layer 407, the interconnect 408, and the dielectric layer 422 to the first carrier 400, the first seed layer 401, the interconnect 402, and the dielectric layer 420. Step 6 of Figure 4B and Figure 7 show and describe one example of bonding an interconnect of one carrier to an interconnect of another carrier.

[0057] The method separates (at 535) the second carrier (e.g., 406) from the second seed layer (e.g., 407). The second carrier 406 may be removed and / or grounded. Step 8 of Figure 4B illustrates and describes one example of carrier separation.

[0058] The method forms (at 540) an interconnect in and / or on the dielectric layer. For example, the interconnect 414 may be formed in and / or on the dielectric layer 422. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer over and within the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity in the dielectric layer. Step 9 of FIG. 4C and FIG. 10 illustrate and describe one example of forming an interconnect in and on a dielectric layer.

[0059] The method separates (at 545) the first carrier (e.g., 400) from the first seed layer (e.g., 401). The first carrier 400 may be removed and / or grounded. The method may also remove (at 545) a portion of the first seed layer (e.g., 401) and a portion of the second seed layer (e.g., 407). An etching process may be used to remove a portion of the first seed layer 401 and a portion of the second seed layer 407. Step 11 of FIG. 4C illustrates and describes one example of separating the carrier and seed layers.

[0060] In some implementations, after removal of the carrier(s) and seed layer(s), the method may form a solder resist layer (e.g., 124, 126) over the substrate. Step 12 of FIG. 4C illustrates and describes one example of forming a solder resist layer.

[0061] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process to form the metal layer(s). For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0062] Exemplary sequence for manufacturing a package with a substrate having high density interconnects In some implementations, manufacturing the package includes several processes. Figures 6A-6B show an example sequence for providing or manufacturing a package including a substrate with high density interconnects. In some implementations, the sequence of Figures 6A and 6B can be used to provide or manufacture package 100. However, the process of Figures 6A-6B can be used to manufacture any of the packages (e.g., 300) described in this disclosure.

[0063] 6A-6B may be combined with one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0064] Stage 1, as shown in FIG. 6A, illustrates the state after a substrate 102 is provided. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, a solder resist layer 124, and a solder resist layer 126. The plurality of interconnects 122 may include a plurality of interconnects 122a, a plurality of interconnects 122b, and a plurality of interconnects 122c. Some of the interconnects may include high density interconnects. For example, as described in FIGS. 1-3, a first plurality of high density interconnects may be disposed on a first side of the substrate and a second plurality of high density interconnects may be disposed on a second side of the substrate. Different implementations may use different substrates having different numbers of metal layers. The substrate 102 may be manufactured using the method described in FIGS. 4A-4C.

[0065] Stage 2 shows the state after the integrated device 106 is bonded to the substrate 102 via the solder interconnects 160, the pillar interconnects 162, and / or the solder interconnects 260. A solder reflow process can be used to bond the integrated device 106 to the substrate 102. The integrated device 106 can be bonded to a second surface (e.g., a bottom surface) of the substrate 102. FIG. 2 shows an example of how the integrated device 106 can be bonded to the substrate 102. Different implementations can bond different components and / or devices to the substrate 102.

[0066] Stage 3 shows the state after the integrated device 104 has been coupled to the substrate 102 via the solder interconnects 140, the pillar interconnects 142, and / or the solder interconnects 240. A solder reflow process can be used to couple the integrated device 104 to the substrate 102. The integrated device 104 can be coupled to a first surface (e.g., a top surface) of the substrate 102. FIG. 2 shows an example of how the integrated device 104 can be coupled to the substrate 102. Different implementations can couple different components and / or devices to the substrate 102.

[0067] Stage 4, as shown in FIG. 6B, depicts the state after an encapsulation layer 108 has been provided (e.g., formed) on the first surface of the substrate 102. The encapsulation layer 108 may encapsulate the integrated device 104. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photoetchable. The encapsulation layer 108 may be a means for encapsulation.

[0068] Stage 5 shows the condition after the plurality of solder interconnects 130 have been bonded to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 130 to the substrate 102. The plurality of solder interconnects 130 may be bonded to the plurality of interconnects 122.

[0069] The packages described in this disclosure (eg, 100, 300) may be manufactured one at a time, or may be manufactured together as part of one or more wafers and then singulated into individual packages.

[0070] 1 is an exemplary flow diagram of a method for manufacturing a package with a substrate having high density interconnects; In some implementations, manufacturing the package includes several processes. Figure 7 shows an example flow diagram of a method 700 for providing or manufacturing a package comprising a substrate having high density interconnects. In some implementations, the method 700 of Figure 7 can be used to provide or manufacture the package 100 described in this disclosure. However, the method 700 can be used to provide or manufacture any of the packages (e.g., 300) described in this disclosure.

[0071] It should be noted that the method of Figure 7 may combine one or more processes to simplify and / or clarify the sequence for providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified.

[0072] The method provides (at 705) a substrate (e.g., 102). The substrate 102 may be provided by a supplier or may be manufactured. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, a solder resist layer 124, and a solder resist layer 126. The plurality of interconnects 122 may include a plurality of interconnects 122a, a plurality of interconnects 122b, and a plurality of interconnects 122c. Some of the interconnects may include high density interconnects. For example, as described in FIGS. 1-3, a first plurality of high density interconnects may be disposed on a first side of the substrate and a second plurality of high density interconnects may be disposed on a second side of the substrate. Different implementations may use different processes to manufacture the substrate 102. FIGS. 4A and 4C illustrate and describe an example of manufacturing a substrate having high density interconnects. Stage 1 of FIG. 6A illustrates and describes an example of providing a substrate having high density interconnects.

[0073] The method includes (at 710) bonding an integrated device (e.g., 106) to the substrate 102. For example, the integrated device 106 is bonded to a second surface (e.g., a bottom surface) of the substrate 102. The integrated device 106 is bonded to the substrate 102 via a plurality of solder interconnects 160, a plurality of pillar interconnects 162, and / or a plurality of solder interconnects 260. A solder reflow process may be used to bond the integrated device 106 to the substrate 102. Stage 2 of FIG. 6A illustrates and describes an example of bonding an integrated device to a substrate.

[0074] The method includes (at 710) bonding an integrated device (e.g., 104) to the substrate 102. For example, the integrated device 104 is bonded to a first surface (e.g., top surface) of the substrate 102. The integrated device 104 is bonded to the substrate 102 via a plurality of solder interconnects 140, a plurality of pillar interconnects 142, and / or a plurality of solder interconnects 240. A solder reflow process may be used to bond the integrated device 104 to the substrate 102. Stage 3 of FIG. 6A illustrates and describes one example of bonding an integrated device to a substrate.

[0075] The method forms (at 715) an encapsulation layer (e.g., 108) on a first surface of a substrate (e.g., 102). The encapsulation layer 108 may be provided and formed on and / or around the substrate 102 and the integrated device 104. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photoetchable. The encapsulation layer 108 may be a means for encapsulation. Step 4 of FIG. 6B illustrates and describes one example of forming an encapsulation layer.

[0076] The method includes (at 720) bonding a plurality of solder interconnects (e.g., 130) to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 130 to the substrate 102. Step 5 of Figure 6B illustrates and describes one example of bonding the solder interconnects to the substrate.

[0077] The packages described in this disclosure (eg, 100, 300) may be manufactured one at a time, or may be manufactured together as part of one or more wafers and then singulated into individual packages.

[0078] Exemplary Electronic Devices FIG. 8 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 802, a laptop computer device 804, a fixed location terminal device 806, a wearable device 808, or an automotive vehicle 810 may include a device 800 as described herein. The device 800 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 802, 804, 806, and 808 and the vehicle 810 illustrated in FIG. 8 are merely exemplary. Other electronic devices may also feature device 800, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous cars), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0079] One or more of the components, processes, features, and / or functions shown in Figures 1-3, 4A-4C, 5, 6A-6B, and / or 7 and 8 may be rearranged and / or combined into a single component, process, feature, or function, or may be implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1-3, 4A-4C, 5, 6A-6B, and / or 7 and 8 in this disclosure and corresponding description thereof are not limited to dies and / or ICs. In some implementations, Figures 1-3, 4A-4C, 5, 6A-6B, and / or 7 and 8 and corresponding description thereof may be used to manufacture, create, provide, and / or generate devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0080] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0081] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even though they are not in direct physical contact with each other. Object A that is coupled to object B can be coupled to at least a portion of object B. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not propagate a current between the two objects. The use of the terms "first," "second," "third," and "fourth" (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The terms "encapsulate," "encapsulating," and / or derivatives thereof, mean that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may also be considered a bottom component, and vice versa.As described in this disclosure, a first component being disposed "over" a second component can mean that the first component is disposed above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be disposed above (e.g., above) a first surface of the second component, and a third component may be disposed above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being disposed above another component, the term "over" when used in this application can be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but not in direct contact with the second component, (2) that the first component is present on (e.g., on a surface of) the second component, and / or (3) that the first component is present within (e.g., embedded within) the second component. A first component that is disposed "in" a second component can be partially disposed within the second component or can be completely disposed within the second component. A value that is about X to XX can mean a value between X and XX, inclusive of X and XX. The value or values ​​between X and XX can be discrete or continuous. As used in this disclosure, the term "about value X" or "approximately value X" means within 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0082] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. There may or may not be one or more interfaces between the interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, the interconnects may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process. The process of forming one or more interconnects may include desmearing, masking, demasking, and / or etching.

[0083] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of steps may be rearranged. A process is terminated when its operations are completed.

[0084] In the following, further examples are described to facilitate understanding of the invention. Aspect 1: A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate comprises at least one dielectric layer, a first plurality of interconnects disposed within the at least one dielectric layer through the first surface of the at least one dielectric layer, and a second plurality of interconnects disposed within the at least one dielectric layer through the second surface of the at least one dielectric layer. The first plurality of interconnects comprises a first width and a first spacing. The second plurality of interconnects comprises a second width and a second spacing. The substrate comprises a third plurality of interconnects disposed within the at least one dielectric layer. The third plurality of interconnects comprises a third width greater than the first width and the second width. The third plurality of interconnects comprises a third spacing greater than the first spacing and the second spacing.

[0085] Aspect 2: The package of aspect 1, wherein a first integrated device is coupled to the first plurality of interconnects and a second integrated device is coupled to the second plurality of interconnects.

[0086] Aspect 3: The package of aspects 1-2, wherein a first plurality of interconnects is disposed on a first metal layer of the substrate and a second plurality of interconnects is disposed on a metal layer adjacent to the last metal layer of the substrate.

[0087] Aspect 4: The package of aspects 1 and 2, wherein a first plurality of interconnects is disposed on a first metal layer within at least one dielectric layer, and a second plurality of interconnects is disposed on a final metal layer embedded in the at least one dielectric layer.

[0088] Aspect 5: The package of Aspects 1-4, wherein the substrate includes a fourth plurality of interconnects disposed over the first surface of the at least one dielectric layer. In some implementations, one high density interconnect of the plurality of interconnects can have an interconnect side facing away from the at least one dielectric layer, the interconnect side lying in a plane with another interconnect side of the one interconnect of the plurality of interconnects facing toward the at least one dielectric layer, the interconnect being disposed over the first surface of the at least one dielectric layer.

[0089] Aspect 6: The package of Aspects 1-4, wherein the substrate includes a fourth plurality of interconnects disposed on the second surface of the at least one dielectric layer. In some implementations, one high density interconnect of the plurality of interconnects can have an interconnect side facing away from the at least one dielectric layer, the interconnect side lying in a plane with another interconnect side of the one interconnect of the plurality of interconnects facing toward the at least one dielectric layer, the interconnect being disposed on the second surface of the at least one dielectric layer.

[0090] Aspect 7: The package of Aspects 1-6, wherein the first plurality of interconnects comprises a first minimum width of about 3-4 micrometers and / or a first minimum spacing of about 3-4 micrometers, and the second plurality of interconnects comprises a second minimum width of about 3-4 micrometers and / or a second minimum spacing of about 3-4 micrometers.

[0091] Aspect 8: The package of Aspects 1-7, wherein the first width is about 3-4 micrometers or more and / or the first spacing is about 3-4 micrometers or more, and the second width is about 3-4 micrometers or more and / or the second spacing is about 3-4 micrometers or more.

[0092] Example 9: The package of Examples 1-8, wherein the first integrated device is coupled to the first plurality of interconnects via the first plurality of solder interconnects and / or the first plurality of pillar interconnects.

[0093] Example 10: The package of Example 9, wherein a second integrated device is coupled to the second plurality of interconnects via the second plurality of solder interconnects and / or the second plurality of pillar interconnects.

[0094] Aspect 11: An apparatus comprising: a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate, the substrate including at least one dielectric layer, a means for a first high density interconnect disposed within the at least one dielectric layer through the first surface of the at least one dielectric layer, and a means for a second high density interconnect disposed within the at least one dielectric layer through the second surface of the at least one dielectric layer.

[0095] Example 12: The apparatus of example 11, wherein the first integrated device is coupled to the means for first high density interconnection and the second integrated device is coupled to the means for second high density interconnection.

[0096] Example 13: The device of examples 11 to 12, wherein a means for a first high density interconnection is disposed on a first metal layer of the substrate, and a means for a second high density interconnection is disposed on a metal layer adjacent to the last metal layer of the substrate.

[0097] Example 14: The device of Examples 11 to 12, wherein a means for a first high density interconnection is disposed on a first metal layer within the at least one dielectric layer, and a means for a second high density interconnection is disposed on a last metal layer embedded in the at least one dielectric layer.

[0098] Embodiment 15: The apparatus of embodiments 11-14, wherein the substrate includes a means for interconnection disposed on the first surface of the at least one dielectric layer.

[0099] Embodiment 16: The apparatus of embodiments 11-14, wherein the substrate includes a means for interconnection disposed on the second surface of the at least one dielectric layer.

[0100] Embodiment 17: The apparatus of embodiments 11-16, wherein the means for the first high density interconnection includes interconnects having a first minimum width of about 3-4 micrometers and / or a first minimum spacing of about 3-4 micrometers, and the means for the second high density interconnection includes interconnects having a second minimum width of about 3-4 micrometers and / or a second minimum spacing of about 3-4 micrometers.

[0101] Embodiment 18: The apparatus of embodiments 11-17, wherein the means for the first high density interconnection includes interconnects having a first width of about 3-4 micrometers or more and / or a first spacing of about 3-4 micrometers or more, and the means for the second high density interconnection includes interconnects having a second width of about 3-4 micrometers or more and / or a second spacing of about 3-4 micrometers or more.

[0102] Example 19: An apparatus of examples 11 to 18, wherein a first integrated device is coupled to a means for a first high density interconnection via a means for a first solder interconnection and / or a means for a first pillar interconnection, and a second integrated device is coupled to a means for a second high density interconnection via a means for a second solder interconnection and / or a means for a second pillar interconnection.

[0103] Aspect 20: The apparatus of aspects 11 to 19, wherein the apparatus comprises a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0104] Aspect 21: A method for manufacturing a substrate. The method provides a first carrier comprising a first seed layer. The method forms a first plurality of high density interconnects on the first seed layer. The method forms a first dielectric layer on the first plurality of high density interconnects. The method forms a plurality of interconnects in and / or on the first dielectric layer. The method provides a second carrier comprising a second seed layer. The method forms a second plurality of high density interconnects on the second seed layer. The method bonds the second carrier comprising the second seed layer and the second plurality of high density interconnects to the first carrier comprising the first seed layer, the first plurality of high density interconnects, the first dielectric layer, and the plurality of interconnects via the second dielectric layer. The method separates the second carrier and the first carrier. The method removes a portion of the first seed layer and a portion of the second seed layer.

[0105] Example 22: The method of Example 21, wherein after separating the second carrier, the method forms a second plurality of interconnects in and on the second dielectric layer.

[0106] Example 23: The method of Examples 21-22, further comprising forming a solder resist layer on the second plurality of interconnects.

[0107] A package comprising: a substrate and a first integrated device coupled to a first surface of the substrate, the substrate including: (i) at least one dielectric layer; (ii) a first plurality of interconnects disposed within the at least one dielectric layer, the first plurality of interconnects comprising first interconnects disposed through the first surface of the at least one dielectric layer, the first plurality of interconnects comprising a first interconnect surface; and (iii) a second plurality of interconnects disposed on the first surface of the at least one dielectric layer, the second plurality of interconnects comprising second interconnects disposed on the first surface of the at least one dielectric layer, the second interconnects having a second interconnect surface that is planar relative to the first interconnect surface.

[0108] Example 25: The package of Example 24, wherein the first plurality of interconnects includes a first plurality of high density interconnects, the first interconnects including a first high density interconnect, the first high density interconnect having a first width smaller than the second width of the second interconnect, and the first high density interconnect having a first spacing smaller than the second spacing of the second interconnect.

[0109] Aspect 26: The package of aspects 24 and 25, wherein the substrate comprises a third plurality of interconnects arranged within the at least one dielectric layer, the third plurality of interconnects being arranged through a second surface of the at least one dielectric layer.

[0110] Example 27: The package of Example 26, further comprising a second integrated device coupled to the second surface of the substrate.

[0111] Example 28: The package of Examples 26 and 27, wherein the third plurality of interconnects includes a third plurality of high density interconnects, the third plurality of high density interconnects includes a third high density interconnect, the third high density interconnect having a third width smaller than the second width of the second interconnect, and the third high density interconnect having a third spacing smaller than the second spacing of the second interconnects.

[0112] Embodiment 29: The package of embodiments 26-28, wherein the first surface is a top surface and the second surface is a bottom surface.

[0113] Embodiment 30: The package of embodiments 26-28, wherein the first surface is a bottom surface and the second surface is a top surface.

[0114] Various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0115] 100, 300 packages 102 Substrate 104, 106 Integrated devices 108 Encapsulation Layer 120, 420, 422 Dielectric layer 122, 402, 408, 412, 414 interconnects 124, 126 Solder resist layer 130, 140, 160, 240, 260 Solder Interconnects 142, 162 Pillar Interconnector 410, 430 cavity

Claims

1. A substrate comprising: at least one dielectric layer including a first dielectric layer and a second dielectric layer; a first plurality of interconnects disposed within the first dielectric layer through a first surface of the at least one dielectric layer, the first plurality of interconnects including a first width and a first spacing; a second plurality of interconnects disposed within the second dielectric layer through a second surface of the at least one dielectric layer, the second plurality of interconnects including a second width and a second spacing; a third plurality of interconnects disposed within and on the at least one dielectric layer; wherein the third plurality of interconnects includes a third width greater than the first width and the second width; wherein the third plurality of interconnects includes a third spacing greater than the first spacing and the second spacing; a first solder resist layer disposed on the first surface of the at least one dielectric layer and on the first plurality of interconnects disposed within the first dielectric layer; a second solder resist layer disposed on the second surface of the at least one dielectric layer and on the third plurality of interconnects disposed within and on the at least one dielectric layer; a first integrated device coupled to the first surface of the substrate; a second integrated device coupled to the second surface of the substrate A package comprising the above.

2. The first integrated device is coupled to the first plurality of interconnects; The second integrated device is coupled to the second plurality of interconnects; The package according to claim 1.

3. The first plurality of interconnects are disposed on a first metal layer of the substrate; The second plurality of interconnects are disposed on a metal layer adjacent to the last metal layer of the substrate; The package according to claim 1.

4. The first plurality of interconnects are disposed on a first metal layer within the at least one dielectric layer; The second plurality of interconnects are disposed on a last metal layer embedded in the at least one dielectric layer; The package according to claim 1.

5. The package according to claim 1, wherein the substrate includes a fourth plurality of interconnects disposed on the first surface of the at least one dielectric layer.

6. The package according to claim 1, wherein the substrate includes a fourth plurality of interconnects disposed on the second surface of the at least one dielectric layer.

7. The first plurality of interconnects includes a first minimum width of about 3 to 4 micrometers and / or a first minimum pitch of about 3 to 4 micrometers, The second plurality of interconnects includes a second minimum width of about 3 to 4 micrometers and / or a second minimum pitch of about 3 to 4 micrometers, The package according to claim 1.

8. The first width is about 3 to 4 micrometers or more, and / or the first pitch is about 3 to 4 micrometers or more, The second width is about 3 to 4 micrometers or more, and / or the second pitch is about 3 to 4 micrometers or more, The package according to claim 1.

9. The package according to claim 1, wherein the first integrated device is coupled to the first plurality of interconnects via a first plurality of solder interconnects and / or a first plurality of pillar interconnects.

10. The package according to claim 9, wherein the second integrated device is coupled to the second plurality of interconnects via a second plurality of solder interconnects and / or a second plurality of pillar interconnects.

11. An apparatus including a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a cellular phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things device, and a device in an automotive vehicle, The apparatus, wherein the device includes the package according to any one of claims 1 to 10.

12. A method for manufacturing a substrate, comprising: providing a first carrier having a first seed layer; forming a first plurality of high density interconnects on the first seed layer; forming a first dielectric layer on the first plurality of high density interconnects; forming a plurality of interconnects within and / or on the first dielectric layer; providing a second carrier having a second seed layer; forming a second plurality of high density interconnects on the second seed layer; Couple the second carrier, which includes the second seed layer and the second plurality of high-density interconnects, to the first carrier, which includes the first seed layer, the first plurality of high-density interconnects, the first dielectric layer, and the plurality of interconnects within and / or on the first dielectric layer, via a second dielectric layer; Separate the second carrier and the first carrier; Remove a portion of the first seed layer and a portion of the second seed layer; After separating the second carrier, form a second plurality of interconnects within and on the second dielectric layer; Form a first solder resist layer on the surface of the first dielectric layer and on the first plurality of high-density interconnects; Form a second solder resist layer on the surface of the second dielectric layer and on the second plurality of interconnects; A method comprising the above.

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