Semiconductor die module package having void-defining portions in metal structure(s) of package substrate to reduce die-to-substrate mechanical stresses, and related methods - Patents.com

Abstract

A semiconductor die module package having void-defining portions in a metal structure(s) of a package substrate to reduce mechanical stress on the die substrate, and related manufacturing methods. A void-defining portion is formed in a metal structure(s) in a metallization layer(s) of a package substrate to reduce die-to-substrate mechanical stress between the package substrate and a die(s) of the die module package. The void-defining portion is formed from one or more cutouts in the metal material of the metal structure in a defined area to reduce stiffness, which also has the effect of reducing the effective coefficient of thermal expansion (CTE) of the package substrate. The metal material remaining between the metal cutouts in the void-defining portion forms a metal interconnect. The die interconnect can be directly bonded to the metal interconnect in the void-defining portion in the metal structure to reduce mechanical stress between the die and the die interconnect to the package substrate.

Description

Claiming priority

[0001] Priority Application

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 470,961, filed September 9, 2021, and entitled "SEMICONDUCTOR DIE MODULE PACKAGES WITH VOID-DEFINED SECTIONS IN A METAL STRUCTURE(S) IN A PACKAGE SUBSTRATE TO REDUCE DIE-SUBSTRATE MECHANICAL STRESS, AND RELATED METHODS," the entire contents of which are incorporated by reference into this specification. [Technical field]

[0002] I. Field of Disclosure The field of the disclosure relates to semiconductor die module packages, such as radio-frequency (RF) front-end module packages, which may include various die components, such as power amplifiers (PAs) and filters, as well as other integrated circuit (IC) chips mounted on a package substrate.

[0003] II. Background

[0003] A semiconductor device is the heart of an electronic device. A semiconductor device is formed in a semiconductor die ("die"). One or more semiconductor dies may be packaged as subcomponents in a module package, also called a "die module package". One type of die module package is a radio frequency (RF) die module package. A die module package includes one or more bare semiconductor dies or includes one or more semiconductor dies in its own chip package, the semiconductor dies being coupled to a package substrate. The package substrate provides a support structure for the die. The package substrate includes one or more metallization layers including metal interconnects (e.g., metal traces, metal lines, vertical interconnect access (vias)) for providing signal routing paths to the semiconductor die. These signal routing paths may include external signal routing paths coupled to package interconnects outside the die module package, as well as die-to-die (D2D) signal routing paths. Die interconnects (e.g., solder bumps) are provided to electrically couple the semiconductor die to the metal interconnects in the package substrate for signal routing, and to couple the die to the metal interconnects in an upper metallization layer of the package substrate.

[0004]

[0004] Different components of a die module package are fabricated from different materials with different coefficients of thermal expansion (CTE), which characterize their thermal expansion and contraction in response to temperature changes. For example, a package substrate formed from a dielectric material and embedded metal (e.g., copper) traces may have a different CTE than the die interconnects used to electrically couple and mount the die to the package substrate. The package substrate may also have a different CTE than the subcomponent die or chip itself. Thus, when the die module package experiences changes in environmental temperature, the different materials of the die module package will experience mechanical stresses due to thermal contraction and thermal expansion. However, the different CTEs (i.e., CTE mismatch) of the different materials of the die module package cause repeated mechanical stresses due to repeated thermal expansion and contraction. For example, these stresses may cause damage to the die interconnects (bumps) that couple the die to the package substrate and / or the die itself, especially due to differences in CTE between the die interconnects, the die, and / or the package substrate. The die interconnects will eventually experience mechanical degradation known as "solder fatigue" due to repeated thermal stress. Furthermore, if the die module package is a bare die module package where an air cavity exists between the die mounted to the package substrate and the package substrate, the presence of the air cavity may make it impossible to place a stress absorbing material between the subcomponent die and the package substrate to relieve mechanical stress. For example, if the die module package includes an acoustic filter, an undermold material placed under the filter between the acoustic filter and the substrate will interfere with the acoustic function of the acoustic filter. Summary of the Invention

[0005]

[0005] Aspects disclosed herein include a semiconductor die module package having void-defining portions in the metal structure(s) of the package substrate to reduce die-to-substrate mechanical stress. Related manufacturing methods are also disclosed. The die module package includes one or more die coupled to a package substrate for support and to provide electrical connectivity to the die. For example, the semiconductor die ("die") module package may be an RF die module package including one or more radio frequency (RF) die subcomponents, such as acoustic filters, mounted to the package substrate, as an example. The package substrate includes at least one metallization layer including one or more metal structures for providing signal routing paths including a ground plane for providing a ground potential connection between the die(s) mounted on the package substrate and electrically coupled to the metal structures. Die interconnects (e.g., solder bumps) electrically couple the die(s) to the metal structures in the package substrate. Because the package substrate may have a different coefficient of thermal expansion (CTE) than the die interconnects and the die, mechanical stresses may be imposed by the package substrate on the die interconnects and then on the die due to changes in the temperature of the die module package environment. This may risk damage to the die interconnects and reliable electrical connection of the die to the package substrate. Thus, in an exemplary embodiment, to reduce die-to-substrate mechanical stresses between the package substrate, the die interconnects, and / or the die of the die module package, a void-defining portion is formed in a metal structure(s) in a metallization layer(s) of the package substrate to reduce the stiffness of the metal structure in the void-defining portion. The void-defining portion is formed from one or more cutouts of the metal material of the metal structure in a defined area to reduce stiffness, which also has the effect of reducing the effective CTE of the package substrate. The metal material remaining between the metal cutouts in the void-defining portion forms the metal interconnects. The metal structure including the void-defining portion may be provided in one, multiple, and / or all metallization layers of the package substrate.For example, to reduce the stiffness of the package substrate, multiple metal structures may be provided in multiple metallization layers parallel to each other such that the metal structures are also parallel to each other in the horizontal direction and share a common vertical plane such that they at least partially overlap each other in the vertical direction within the package substrate. The die or die in the die module package may be oriented on the package substrate such that the die is above the die or die and the void-defining portion is below the die or die. The die interconnects bond (directly or indirectly through metal interconnects in intervening metallization layers) the die to the metal interconnects in the reduced stiffness void-defining portions of the metal structures to buffer and thus reduce mechanical stress between the bonding of the die and the die interconnects to the package substrate.

[0006] In another exemplary aspect, the cutouts in the metal structure that define the void-defining portions in the metal structure can be further optionally filled with a material having a lower CTE than the CTE of the metal material of the ground plane(s) to further reduce the stiffness of the void-defining portions and the effective CTE of the package substrate. By further reducing the stiffness and effective CTE of the void-defining portions where the die interconnects and connections to the die are made, mechanical stresses between the package substrate and the die interconnects and / or die can be further reduced.

[0007]

[0007] In one exemplary aspect, the patterned voids may be arranged in the metal structure of the package substrate to be uniform in all directional axes to provide equal flexibility in all directional axes. In another exemplary aspect, the patterned voids in the metal structure(s) of the package substrate may be biased to be elongated in a particular directional axis to provide enhanced flexibility in the particular directional axis. In another exemplary aspect, the patterned voids in the metal structure(s) of the package substrate may be designed such that vertical interconnect access (vias) extend through one or more of the voids to support vias extending through and connected to the metal structure(s). In another exemplary aspect, the voids in the metal structure(s) of the package substrate may be patterned to be selectively provided adjacent to metal traces and / or other electrical components of the package substrate to provide selective mechanical stress relief to such metal traces and / or other electrical components.

[0008]

[0008] In this regard, in one exemplary aspect, a die module package substrate is provided. The die module package includes a package substrate. The package substrate includes a plurality of metal structures that are parallel to one another in a horizontal direction and share a common vertical plane. Each metal structure of the plurality of metal structures includes a metal material having a first CTE. Each metal structure of the plurality of metal structures also includes a void-defining portion including a plurality of voids disposed within the metal structure. Each metal structure of the plurality of metal structures also includes one or more metal interconnects each formed by a metal material within the metal structure disposed between adjacent ones of the plurality of voids. Each metal structure of the plurality of metal structures also includes a dielectric material having a second CTE disposed within at least one void of the plurality of voids within the void-defining portion. The second CTE of the dielectric material is less than the first CTE of the metal material. The die module package also includes a die disposed adjacent to the package substrate. The die module package also includes at least one die interconnect, each coupled to the die and each coupled to one of the one or more metal interconnects within the void-defining portion of at least one metal structure of the plurality of metal structures.

[0009]

[0009] In another exemplary aspect, a method of manufacturing a die module package is provided. The method includes forming a package substrate. Forming the package substrate includes forming a plurality of metal structures that are horizontally parallel to one another and share a common vertical plane. Each metal structure of the plurality of metal structures includes a metal material having a first CTE, a void-defining portion including a plurality of voids disposed within the metal structure, one or more metal interconnects each formed by the metal material in the metal structure disposed between adjacent voids of the plurality of voids, and a dielectric material having a second CTE disposed within at least one of the plurality of voids in the void-defining portion, the second CTE of the dielectric material being less than the first CTE of the metal material. The method also includes forming at least one die interconnect coupled to at least one of the one or more metal interconnects in the void-defining portion of the at least one metal structure of the plurality of metal structures. The method also includes coupling a die to the at least one die interconnect. [Brief description of the drawings]

[0010] [Figure 1]

[0010] A side view of an exemplary semiconductor die ("die") module package having die interconnects that couple the die to void-defining portions in a metal structure, where the void-defining portions are formed by voids in the metal material of the metal structure(s) to reduce the metal stiffness of the metal structure(s) and reduce die-to-substrate mechanical stresses between the package substrate and the die interconnects and die. [Diagram 2]

[0011] FIG. 2 is a top view of an exemplary substrate layer within a package substrate, such as the package substrate of FIG. 1, the substrate layer including a ground plane having a void-defining portion configured to be coupled to a die interconnect coupled to the die to reduce die-to-substrate mechanical stress between the package substrate and the die interconnect and die. [Diagram 3]

[0012] FIG. 1 is a top view of an exemplary metal structure in a metallization layer of a package substrate having patterned voids that provide void-defining portions in the ground plane to reduce the stiffness of the void-defining portions in the ground plane and to reduce the overall coefficient of thermal expansion (CTE) of the ground plane. [Figure 4A]

[0013] 4 is a graph illustrating an example simulation result of the CTE of the metal structure of FIG. 3. [Figure 4B]

[0014] 4 is a graph showing an example simulation result of the CTE of a metal structure similar to that of FIG. 3 but without the patterned voids. [Diagram 5]

[0015] 4 is a graph showing the effective CTE of the metal structure of FIG. 3 as a function of the volume of various metal materials used to form the metal structure. [Figure 6]

[0016] FIG. 13 is a top view of another example ground plane having patterned voids biased in a directional axis to reduce metal stiffness of a metal structure biased vertically in the directional axis. [Figure 7]

[0017] FIG. 1 is a top view of another example ground plane having patterned voids forming void-defining portions in a metal structure, with vertical interconnect access (vias) selectively placed within the voids to reduce stiffness within the void-defining portions. [Figure 8]

[0018] FIG. 13 is a top view of another example metal structure having elongated patterned voids, voids biased in a directional axis to reduce the stiffness of a ground plane biased perpendicular to the directional axis and forming void-defining portions within the metal structure. [Figure 9A]

[0019] FIG. 13 is a top view of another exemplary metal structure having voids selectively provided adjacent to metal traces and / or other electrical components of a package substrate to form void-defining portions within the metal structure that provide selective mechanical stress relief to such metal traces and / or other electrical components. [Figure 9B]FIG. 13 is a top view of another exemplary metal structure having voids selectively provided adjacent to metal traces and / or other electrical components of a package substrate to form void-defining portions within the metal structure that provide selective mechanical stress relief to such metal traces and / or other electrical components. [Figure 9C] FIG. 13 is a top view of another exemplary metal structure having voids selectively provided adjacent to metal traces and / or other electrical components of a package substrate to form void-defining portions within the metal structure that provide selective mechanical stress relief to such metal traces and / or other electrical components. [Figure 9D] FIG. 13 is a top view of another exemplary metal structure having voids selectively provided adjacent to metal traces and / or other electrical components of a package substrate to form void-defining portions within the metal structure that provide selective mechanical stress relief to such metal traces and / or other electrical components. [Figure 9E] FIG. 13 is a top view of another exemplary metal structure having voids selectively provided adjacent to metal traces and / or other electrical components of a package substrate to form void-defining portions within the metal structure that provide selective mechanical stress relief to such metal traces and / or other electrical components. [Figure 9F] FIG. 13 is a top view of another exemplary metal structure having voids selectively provided adjacent to metal traces and / or other electrical components of a package substrate to form void-defining portions within the metal structure that provide selective mechanical stress relief to such metal traces and / or other electrical components. [Figure 9G] FIG. 13 is a top view of another exemplary metal structure having voids selectively provided adjacent to metal traces and / or other electrical components of a package substrate to form void-defining portions within the metal structure that provide selective mechanical stress relief to such metal traces and / or other electrical components. [Figure 9H]FIG. 13 is a top view of another exemplary metal structure having voids selectively provided adjacent to metal traces and / or other electrical components of a package substrate to form void-defining portions within the metal structure that provide selective mechanical stress relief to such metal traces and / or other electrical components. [Figure 10]

[0020] FIG. 1 is a flowchart illustrating an exemplary manufacturing process for manufacturing a die module package including a package substrate that includes one or more metal structures having void-defining portions formed by voids in the metal material of the metal structure(s) to reduce the metal stiffness of the metal structure(s) to reduce die-to-substrate mechanical stresses between the package substrate and the die interconnects and die. [Figure 11]

[0021] 10 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components that may be provided within respective die module packages, including, but not limited to, the package substrate of FIGS. 1-3 and 6-9H, and including a package substrate including one or more metal structures having void-defining portions formed by voids in the metal material of the metal structure(s) to reduce the metal stiffness of the metal structure(s), according to the exemplary manufacturing process of FIG. [Figure 12]

[0022] 10 is a block diagram of an exemplary processor-based system that may be provided within a respective die module package including, but not limited to, the package substrate of FIGS. 1-3 and 6-9H and including a package substrate including one or more metal structures having void-defining portions formed by voids in the metal material of the metal structure(s) to reduce the metal stiffness of the metal structure(s) according to the exemplary manufacturing process of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0023] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0012]

[0024] Aspects disclosed herein include a semiconductor die module package having void-defining portions in the metal structure(s) of the package substrate to reduce die-to-substrate mechanical stress. Related manufacturing methods are also disclosed. The die module package includes one or more die coupled to a package substrate for support and to provide electrical connectivity to the die. For example, the semiconductor die ("die") module package may be, as an example, an RF die module package including one or more radio frequency (RF) die subcomponents, such as acoustic filters, mounted to the package substrate. The package substrate includes at least one metallization layer including one or more metal structures for providing signal routing paths including a ground plane for providing a ground potential connection between the die(s) mounted on the package substrate and electrically coupled to the metal structures. Die interconnects (e.g., solder bumps) electrically couple the die(s) to the metal structures in the package substrate. Because the package substrate may have a different coefficient of thermal expansion (CTE) than the die interconnects and the die, mechanical stresses may be imposed by the package substrate on the die interconnects and then on the die due to changes in the temperature of the die module package environment. This may risk damage to the die interconnects and reliable electrical connection of the die to the package substrate. Thus, in an exemplary embodiment, to reduce die-to-substrate mechanical stresses between the package substrate, the die interconnects, and / or the die of the die module package, a void-defining portion is formed in a metal structure(s) in a metallization layer(s) of the package substrate to reduce the stiffness of the metal structure in the void-defining portion. The void-defining portion is formed from one or more cutouts of the metal material of the metal structure in a defined area to reduce stiffness, which also has the effect of reducing the effective CTE of the package substrate. The metal material remaining between the metal cutouts in the void-defining portion forms the metal interconnects. The metal structure including the void-defining portion may be provided in one, multiple, and / or all metallization layers of the package substrate.For example, to reduce the stiffness of the package substrate, multiple metal structures may be provided in multiple metallization layers parallel to each other such that the metal structures are also parallel to each other in the horizontal direction and share a common vertical plane such that they at least partially overlap each other in the vertical direction within the package substrate. The die or die in the die module package may be oriented on the package substrate such that the die is above the die or die and the void-defining portion is below the die or die. The die interconnects bond (directly or indirectly through metal interconnects in intervening metallization layers) the die to the metal interconnects in the reduced stiffness void-defining portions of the metal structures to buffer and thus reduce mechanical stress between the bonding of the die and the die interconnects to the package substrate.

[0013]

[0025] In other exemplary aspects, the cutouts in the metal structure that define the void-defining portions in the metal structure may be further optionally filled with a material having a lower CTE than the CTE of the metal material of the ground plane(s) to further reduce the stiffness of the void-defining portions and the effective CTE of the package substrate. By further reducing the stiffness and effective CTE of the void-defining portions where the die interconnects and connections to the die are made, mechanical stresses between the package substrate and the die interconnects and / or die may be further reduced.

[0014]

[0026] In this regard, FIG. 1 is a side view of an exemplary semiconductor die ("die") module package 100 including two semiconductor dies ("dies") 102(1), 102(2) adjacent to and coupled to a package substrate 104. For example, the die module package 100 may be an RF die module package in which the dies 102(1), 102(2) are RF components such as acoustic filters or RF amplifiers. The package substrate 104 may be a coreless substrate or a cored substrate. The package substrate 104 includes metallization layers 106(1)-106(4), each including metal structures 108(1)-108(4) for providing signal routing paths between the dies 102(1), 102(2) of the die module package 100 and external interconnect bumps 110. For example, metal structures 108(1)-108(4) may be formed from a redistribution of metal material or may be formed within metallization layers 106(1)-106(4) that are stacked in a stacking process. Metal structures 108(1)-108(4) provide metal interconnects (e.g., metal lines, metal traces). Metal structures 108(1)-108(4) may also function as ground planes for dies 102(1), 102(2). Metal structures 108(1)-108(4) may provide die-to-die interconnects (D2D) between die 102(1) and die 102(2). Vertical interconnect accesses (vias) 112 are coupled between metal structures 108(1)-108(4) in respective metallization layers 106(1)-106(4) in the package substrate 104 to provide signal routing between the different metallization layers 106(1)-106(4). Die interconnects 114 (e.g., solder bumps) are coupled to the die(s) 102(1), 102(2) and metal structures 108(1) in the top metallization layer 106(1) in the package substrate 104 to electrically couple the die 102(1), 102(2) to the package substrate 104. The die interconnect 114 may also be indirectly coupled to other metal structures 108(2)-108(4) in the underlying metallization layers 106(2)-106(4) due to the interconnectivity between such metal structures 108(2)-108(4) through the vias 112.Several metal structures 108(1)-108(4) can serve as ground planes for ground potential coupling to the dies 102(1), 102(4) through die interconnects 114. The dies 102(1), 102(2) are encapsulated by an overmold material 116 on the package substrate 104.

[0015]

[0027] Mechanical stresses can be imposed by the package substrate 104 on the die interconnects 114 and, in turn, on the dies 102(1), 102(2) due to changes in the environmental temperature of the die module package 100. This is because the package substrate 104 can have a different CTE than the die interconnects 114 and / or the dies 102(1), 102(2). This can pose a risk of damage to the die interconnects 114 and to a reliable electrical connection of the dies 102(1), 102(2) to the package substrate 104. The polymeric material 118 in the package substrate 104 is generally a softer material with a lower CTE compared to the metallic materials used to form the metal structures 108(1)-108(4) and the die interconnects 114 in the package substrate 104. When mechanical forces are applied on the package substrate 104, these mechanical forces may be transferred to the metal structures 108(1)-108(4) of the package substrate 104 and then to the die interconnects 114 and the dies 102(1), 102(2). If these forces are too large, the connectivity between the dies 102(1), 102(2) and the metal structures 108(1)-108(4) may be compromised, thus degrading the electrical connectivity of the die module package 100. For example, these mechanical forces may be due to changes in the environmental temperature experienced by the die module package 100. Due to differences in CTE, the dies 102(1), 102(2), the die interconnects 114, and the metal structures 108(1)-108(4) within the package substrate 104 may thermally contract and expand differently, by different amounts and distances, such as in the X-axis, Y-axis, and Z-axis directions of FIG. 1, based on a given temperature change. These stresses can cause damage, especially to the corners of the die 102(1), 102(2) and / or the die interconnects 114. Although the polymer material 118 of the package substrate 104 can buffer some of the mechanical stresses applied to the package substrate 102, the repeated mechanical stresses due to repeated thermal expansion and contraction can still be significant over time to damage the electrical connections between the die 102(1), 102(2) and the package substrate 104.

[0016]

[0028] Thus, in an exemplary embodiment, to reduce die-to-substrate mechanical stresses between the package substrate 104, the die interconnects 114, and / or the dies 102(1), 102(2) of the die module package, as shown in FIG. 1, in this example, void-defining portions 120 are formed in the metal structures 108(1). This reduces the stiffness of the areas of these metal structures 108(1) to which the die interconnects 114 are coupled, which in turn reduces the transfer of mechanical stresses from the package substrate 104 to the die interconnects 114 and the dies 102(1), 102(2). As described in more detail below, the void-defining portions 120 are formed from one or more cutouts in the metal material of the metal structures 108(1) in the defined areas to reduce stiffness, which also has the effect of reducing the effective CTE of the package substrate 104. In this example, the overall effective CTE of the package substrate 104 is less than the CTE of the metal material of the metal structures 108(1)-108(4). Metal material remaining between the metal cutouts in void-defining portions 120 forms metal interconnects. Void-defining portions 120 may be provided in certain metal structures 108(1)-108(4) in one, more, and / or all of metallization layers 106(1)-106(4) of package substrate 104. Die(s) 102(1), 102(2) in die module package 100 may be oriented on package substrate 104 such that dies 102(1), 102(2) are above dies 102(1), 102(2) and void-defining portions 120 in metal structure 108(1) are below dies 102(1), 102(2). This allows die interconnect 114 to bond die 102(1), 102(2) to the metal interconnect in metal structure 108(1) within reduced stiffness void-defining portion 120 (either directly or indirectly via metal structures 108(2)-108(4) within intervening metallization layers 106(2)-106(4)) to buffer, and therefore reduce, mechanical stress between the bonding of die 102(1), 102(2) and die interconnect 114 to package substrate 104.

[0017]

[0029] It should be noted that if it is desired to further reduce the stiffness of the package substrate 104, one or more of the additional metal structures 108(2)-108(4) may also be provided that include void portions formed from one or more cutouts in the metal material of the respective metal structures 108(2)-108(4). For example, such metal structures 108(2)-108(4) may be aligned to share a common vertical plane PL1 in FIG. 1 such that they are parallel to one another in the horizontal direction (e.g., in the X-axis direction) and at least partially overlap one another in the vertical direction (the Z-axis direction). Thus, the die interconnects 114 coupling the die to the metal interconnects in the metal structure 108(1) will benefit from the reduced stiffness and stress from the package substrate 104 from the other metal structures 108(2)-108(4) below the metal structure 108(1). For example, these other metal structures 108(2)-108(4) may allow metal structure 108(1) to flex more easily, thereby reducing stress on die interconnect 114 and dies 102(1), 102(2).

[0018]

[0030] FIG. 2 is a top view of an exemplary metallization layer 106 that may be provided in the package substrate 104 in the die module package 100 of FIG. 1 as an example. As shown in FIG. 2, the metallization layer 106 includes a metal structure 108 (e.g., a metal plane), which may include a metal structure acting as a ground plane. Note that the metal structure 108 may be provided as any of the metal structures 108(1)-108(4) in the package substrate 104 of FIG. 1. The metallization layer 106 also includes metal traces 200 that are not planar structures like the metal structures 108. The metallization layer 106 of FIG. 2 may be the upper metallization layer 106(1) in the package substrate 104 of FIG. 1 that is directly coupled to and adjacent to the die interconnects 114 in the die module package 100. For example, if the metal structures 108 in the metallization layer 106 of FIG. 2 function as a ground plane, such metal structures 108 acting as a ground plane may be disposed beneath the die interconnects 114 to electrically connect a ground potential to the dies 102(1), 102(2). As shown in FIG. 2, the metal structures 108 in this example each include voids 202 arranged in a pattern to form the void-defining portions 120. In this example, the voids 202 are cut-out portions of the metal material 204 in the metal structure 108. By "patterned" voids, we mean that the voids 202 are arranged in an intended location and design within the metal structure 108 such that the voids 202 are not randomly disposed within the metal structure 108. In this example, the voids 202 form a perimeter 208 of the void-defining portions 120 within the metal structure 108.

[0019]

[0031] The metal material 204 remaining between adjacent voids 202 in the metal structure 108 forms a metal interconnect 206 (e.g., metal line, trace) that may be coupled (directly or indirectly) to the die interconnect 114 or to the via 112 to electrically couple to the metal structure 108. In this manner, the voids 202 disposed within the void-defining portion 120 of the metal structure 108 reduce the stiffness of the metal structure 108 in areas where electrical connections to the metal interconnects 206 can be made, reducing the stress applied from the metal structure 108 to such connections. However, the metal structures 108 still retain their metal material structure and provide the metal interconnects 206 for connectivity. For example, the area of ​​a void 202 within a given void-defining portion 120 may be at least eighty-five percent (85%) of the area of ​​its perimeter 208 within the metal structure 108.

[0020]

[0032] 1 and 2, it is noted that a portion of the die 102(1), 102(2) may be oriented with respect to the package substrate 104 such that the die 102(1), 102(2) at least partially overlap a void-defining portion 120 in the metal structure 108 in the package substrate 104 in a vertical direction, which in this example is the Z-axis direction. This allows the die interconnect 114 to more easily couple the die 102(1), 102(2) to the metal interconnect(s) 206 in the void-defining portion 120 of the metal structure 108 to provide an electrical connection. It is also noted that although the vias 112 are shown separate and apart from the voids 202 in the metal structure 108 in the metallization layer 106 in FIG. 2, some of the voids 202 may be filled with a metal material to form vias 112 that extend through the voids 202. Also, as described in more detail below, voids 202 can be molded and positioned within metal structure 108 defining void-defining portion 120 within metal structure 108 to achieve a uniform reduction in stiffness applied in all directions or biased in the X-axis and Y-axis directions within void-defining portion 120. Alternatively, voids 202 can be molded and positioned within metal structure 108 defining void-defining portion 120 within metal structure 108 to achieve a biased or non-uniform reduction in stiffness applied in no particular direction or only in a particular direction.

[0021]

[0033] In this example, the voids 202 in the metal structure 108 may also be optionally filled with a dielectric material 210, such as a polymeric or laminate material, to further reduce the stiffness of the metal structure 108. The dielectric material 210 may be selected to have a lower CTE than the CTE of the metal material 204 forming the metal structure 108. For example, the CTE of the metal material 204 forming the metal structure 108 may be between 13 parts per million (ppm) per Kelvin (ppm / K) and 24 ppm / K. The metal material 204 may be, for example, aluminum nickel (AlNi) or an alloy thereof. As another example, if the metal material 204 forming the metal structure 108 is, for example, copper, the CTE of the metal material 204 of the metal structure 108 may be, for example, 18_ppm / K. The CTE of the dielectric material 210 disposed in the voids 202 of the metal structure 108 may be, for example, between 4_ppm / K and 18 ppm / K. For example, if the dielectric material 210 filled in the voids 202 is a low CTE glass fiber polymer, the CTE of the dielectric material 210 may be about 6_ppm / K, as another example. Examples of fibers for reinforcement of the dielectric material 210 include carbon fiber and aluminum oxide (Al2O3) spheres. As another example, the voids 202 may be disposed in the metal structure 108 such that the Young's modulus (i.e., stiffness) of the voids 202 in the void-defining portion 120 in the metal structure 108 may be between 100 megapascals (MPa) and 50 gigapascals (GPa). It should be noted that although FIG. 2 shows a view of only one metallization layer 106 of the package substrate 104 of FIG. 1, the void-defining portion 120 may be formed in any of the metal structures 108(1)-108(4) of any of the metallization layers 106(1)-106(4) of the package substrate 104.For example, if the die interconnect 114 is coupled to multiple metal structures 108(1)-108(4) in multiple metallization layers 106(1)-106(4) through a direct connection to a metal structure 108(1) in an upper metallization layer 106(1) and through a via 112 connection to the other metallization layers 106(2)-106(4), the subsequent connection of such via 112 in such other metallization layers 106(2)-106(4) may be a void-defining portion 120 in such metal structure 108(2)-108(4) in such other metallization layers 106(2)-106(4). This may further reduce stress applied by the package substrate 104 to the die interconnect 114 and, in turn, to their coupled dies 102(1), 102(2). Also, as described above, one or more of metal structures 108(1)-108(4) having void portions 120 may be aligned within package substrate 104 to share a common vertical plane PL1 (in the Z-axis and Y-axis directions) such that they are parallel to one another in the horizontal direction (e.g., in the X-axis direction) and at least partially overlap one another in the vertical direction (the Z-axis direction) to support reduced stiffness.

[0022]

[0034] The voids 202 disposed within the metal structure 108 of the metallization layers 106(1)-106(4) in the package substrate 104 of FIG. 1 to form void-defining portions 120 to reduce the metal stiffness within the metal structure 108 may be provided in any design and patterned as desired. For example, FIG. 3 is a top view of an exemplary metal structure 308 having patterned voids 302 in the shape of a honeycomb pattern (i.e., hexagonal shaped voids) to form void-defining portions 300 within the metal structure 308 to reduce the metal stiffness of the metal structure 308. Metal interconnects 306 are formed by the metal material 304 of the metal structure 308 remaining between adjacent voids 302. The metal structure 308 may function as a ground plane within a metallization layer of a package substrate of a die module package, such as, by way of example, the metallization layers 106(1)-106(4) in the package substrate 104 of the die module package 100 of FIG. 1. The metal structure 308 is formed from a metal material 304, such as copper. A dielectric material 310 may be disposed within the patterned voids 302. The patterned voids 302 are uniform within the metal structure 308 in this example, meaning that they have the same shape and orientation as shown in Figure 3. The ratio of the area of ​​the plurality of patterned voids 302 to the area of ​​the metal material 304 within the metal structure 308 may be five percent (5%) or greater to achieve a desired reduction in metal stiffness of the metal structure 308.

[0023]

[0035] The patterned voids 302 are also disposed within the metal structure 308 in a repeating pattern as shown in FIG. 3, meaning that the patterned voids 302 are oriented and disposed within the metal structure 308 in a repeating manner. For example, as shown in FIG. 3, the pattern of the patterned voids 302 is shown within the dashed box 309. In the example of FIG. 3, the patterned voids 302 are completely surrounded by the metal material 304 within the metal structure 308. Also, in this example, the patterned voids 302 disposed within the metal structure 308 may be designed to have a total area that is at least thirty percent (30%) of the total area of ​​the metal structure 308. Each patterned void 302 within a row (e.g., row R1) is offset along a centerline CTR1 between two adjacent patterned voids 302 within an adjacent row (e.g., row R2). Also, each patterned void 302 in a column (e.g., row C1) is offset along a centerline CTR2 between two adjacent patterned voids 302 in an adjacent column (e.g., column C2). Each patterned void 302 has the same first pitch P1 in the X-axis direction. Each patterned void 302 has the same second pitch P2 in the Y-axis direction. The first pitch P1 and the second pitch P2 may be the same pitch or different pitches. The patterned voids 302 have the same shape and orientation and the same pitch P1 in the X-axis direction, which means that the metal structure 308 is uniformly flexible in the X-axis direction. The patterned voids 302 have the same shape and the same pitch P2 in the Y-axis direction, which means that the metal structure 308 is uniformly flexible in the Y-axis direction. If it is desired that the metal structure 308 have the same flexibility in both the X-axis and Y-axis directions, the patterned voids 302 may be formed in the metal structure 308 to have the same pitch P1, P2.

[0024]

[0036] To further illustrate an exemplary effect of disposing patterned voids 302 within the metal structure 308 of FIG. 3, FIG. 4A is provided. FIG. 4A illustrates an exemplary simulation result of the mechanical expansion of a package substrate 404 provided with the metal structure 308 of FIG. 3 at a given temperature given the effect of the patterned voids 302 forming void-defining portions 320 within the metal structure 308. In the example of FIG. 4A, the package substrate 404 includes a plurality of metallization layers 406(1)-406(X), each including a metal structure 308 having a void-defining portion 320 formed by voids 302 disposed between vias 412. The metal structures 308 within the plurality of metallization layers 406(1)-406(X) may be aligned to be parallel to one another in the horizontal direction (e.g., in the X-axis direction) and to share a common vertical plane PL2 to at least partially (i.e., fully or partially) overlap one another in the vertical direction (Z-axis direction). FIG. 4B illustrates an example simulation result of mechanical expansion of a package substrate 424 at a given temperature that is copper filled and includes a metal structure 408 like the metal structure 308 of FIG. 3, but without the voids 302 in the void-defining portion 320. With reference to FIG. 4A, different regions of the metal structure 308 are indicated by color changes of the metal structure 308 in the X-axis, Y-axis, and Z-axis directions. The distance of the color change indicates the mechanical displacement. With reference to FIG. 4B, different regions of the metal structure 408 are also indicated by color changes of the metal structure 408 in the X-axis, Y-axis, and Z-axis directions. The distance of the color change indicates the mechanical displacement. It was found that the overall effective CTE of the metal structure 308 of FIG. 4A is about 20% lower than the effective CTE of the metal structure 408 without the voids providing the void-defining portion of FIG. 4B.

[0025]

[0037] FIG. 5 is a graph 500 showing the effective CTE of a package substrate, which may include the metal structure 308 of FIG. 3, as a function of the volume of various metal materials relative to the overall volume of the package substrate. This further illustrates how the presence of patterned voids in the metal structure of the package substrate, including the ground plane, can reduce the overall CTE of the ground plane. The graph 500 of FIG. 5 shows the effective CTE of the package substrate on the Y-axis as a function of the volume percentage of the copper content in the package substrate on the X-axis, and the volume percentage of copper in the ground plane as a function of the patterned voids. As shown in FIG. 5, a first curve 502 shows the effective CTE of the package substrate for a given volume percentage of the copper content in the package substrate when using a ground plane that does not include a void pattern. A second curve 504 shows the effective CTE of the package substrate for a given volume percentage of the copper content in the package substrate when using a ground plane that includes a void pattern in which the metal material is 60% of the volume of the ground plane. As shown in FIG. 5, the effective CTE in the second curve 504 is less than the effective CTE in the first curve 502 for a given volume percentage of copper content in the package substrate.

[0026]

[0038] FIG. 6 is a top view of another exemplary metal structure 608 that may be provided in a metallization layer 601 having patterned voids 602 elongated in the Y-axis direction to bias a reduction in the metal stiffness of the metal structure 608 based on an applied mechanical force. Similar to the metal structure 308 of FIG. 3, the metal structure 608 of FIG. 6 has patterned voids 602 in a honeycomb pattern shape (i.e., hexagonal shaped voids) to generate void-defining regions 620 in the metal structure 608 to reduce the metal stiffness of the metal structure 608. Metal interconnects 606 are formed in the metal material 604 of the metal structure 608 between adjacent voids 602. The metal structure 608 may function as a ground plane in a package substrate, such as the package substrate 104 in the die module package 100 of FIG. 1, as an example. The metal structure 608 is made from a metal material 604, such as copper. A dielectric material 612 may be disposed in the patterned voids 602. The patterned voids 602 have the same shape and orientation as shown in FIG. 6. The patterned voids 602 are also arranged in the metal structure 608 in a repeating pattern as shown in FIG. 6, meaning that the patterned voids 602 are oriented and arranged in the metal structure in a repeating manner. For example, as shown in FIG. 6, the pattern of the patterned voids 602 is shown in the dashed box 610. Each patterned void 602 in a row (e.g., row R1) is offset along a centerline CTR1 between two adjacent patterned voids 602 in an adjacent row (e.g., row R2). Also, each patterned void 602 in a column (e.g., row C1) is offset along a centerline CTR2 between two adjacent patterned voids 602 in an adjacent column (e.g., column C2). The patterned voids 602 each have the same first pitch P3 in the X-axis direction. Additionally, each of the patterned voids 602 has the same second pitch P4 in the Y-axis direction.

[0027]

[0039] In this example, the first pitch P3 is smaller than the second pitch P4 because the length L1 of the patterned voids 602 in the Y-axis direction is greater than the length L2 in the X-axis direction. Thus, the patterned voids 602 are elongated in the Y-axis direction. This has the effect of making the patterned voids 602 less stiff in the X-axis direction than in the Y-axis direction. This may be desired to bias the direction of the stiffness reduction in the metal structure 608. In the example of FIG. 6, the patterned voids 602 are completely surrounded by the metal material 604 in the metal structure 608. Also, in this example of FIG. 6, the patterned voids 602 disposed within the metal structure 608 may be designed to have a total area that is at least thirty percent (30%) of the total area of ​​the metal structure 608.

[0028]

[0040] It may also be desirable to provide vias distributed and extending through a metal structure having void-defining portions 720 within a subset of its patterned voids, such as metal structure 308 of FIG. 3, to provide interconnections to the metal structure. In this regard, FIG. 7 is a top view of another exemplary metal structure 708 that may be provided within a metallization layer of a package substrate, such as package substrate 104 of FIG. 1. Metal structure 708 of FIG. 7 is similar to metal structure 308 of FIG. 3. Metal interconnects 706 are formed within the metal material 704 of metal structure 708 between adjacent patterned voids 702. However, in FIG. 7, certain patterned voids 702 formed within the metal material 704 of metal structure 708 are not filled with a dielectric material, but rather, vias 712 are disposed within these patterned voids 702 to provide interconnections to adjacent metallization layers adjacent to the metallization layer in which metal structure 708 is disposed. This will change the overall volume of the patterned voids 702 with the dielectric material 714 within the metal structure 708, affecting an overall reduction in the metal stiffness and effective CTE of the metal structure 708. However, a smaller reduction in metal stiffness may be desired as a tradeoff against interconnect routing efficiency by placing the vias 712. Other elements of the metal structure 708 of FIG. 7 that are common to elements within the metal structure 308 of FIG. 3 are shown with common element numbers and labeling between FIG. 3 and FIG. 7. Also, in the example of FIG. 7, the patterned voids 702 are completely surrounded by the metal material 704 within the metal structure 708. Also, in this example, the patterned voids 702 disposed within the metal structure 708 may be designed to have a combined area that is at least thirty percent (30%) of the total area of ​​the metal structure 708.

[0029]

[0041] FIG. 8 is a top view of another exemplary metal structure 808 of metal material 804 that may be provided in a metallization layer of a package substrate, such as metallization layers 106(1)-106(4) in package substrate 104 of FIG. 1, and may include a void-defining portion 820 having patterned voids 802. Metal interconnects 806 are formed in metal material 804 of metal structure 808 between adjacent voids 802. The voids 802 formed in metal structure 808 of FIG. 8 are even more elongated in the Y-axis direction than metal structure 608 of FIG. 6 to bias a reduction in metal stiffness of metal structure 808 based on applied mechanical force. Metal structure 808 of FIG. 8 has patterned voids 802 in the shape of elongated slots in the Y-axis direction to reduce metal stiffness of metal structure 808 in the X-axis direction. Metal structure 808 may function as a ground plane in package substrate 104 of a die module package, such as die module package 100 of FIG. 1, by way of example. The metal structures 808 are made of a metal material 804, such as copper. A dielectric material 814 may be disposed within the patterned voids 802 to further reduce the effective CTE of the void-defining portions 820 and the metal structures 808. The patterned voids 802 have the same shape and orientation. The patterned voids 802 are also disposed within the metal structures 808 in a repeating pattern as shown in FIG. 8, meaning that the patterned voids 802 are oriented and disposed within the metal structures in a repeating manner. For example, as shown in FIG. 8, the pattern of the patterned voids 802 is shown within the dashed box 810. The patterned voids 802 each have the same first pitch P5 in the X-axis direction. Also, the patterned voids 802 each have the same second pitch P6 in the Y-axis direction. In this example, the first pitch P5 is smaller than the second pitch P6 because the length L3 of the patterned voids 802 in the Y-axis direction is longer than the length L4 in the X-axis direction. Thus, patterned voids 802 are elongated in the Y-axis direction, which has the effect of making patterned voids 802 less stiff in the X-axis direction than in the Y-axis direction.This may be desired to bias the direction of stiffness reduction in the ground plane 800. In this example, patterned voids 802 having a length L3 in the Y-axis direction that is much greater than length L4 in the X-axis direction essentially creates a spring within the metal structure 808, providing the metal structure 808 with flexibility in the X-axis direction.

[0030]

[0042] Also, as shown in FIG. 8, some or all of the voids 802 may facilitate through vias 812 to facilitate interconnections between the metal interconnects 806 in the void-defining portion 820 and adjacent metallization layers. The vias 812 may also be disposed within the voids 802 in an alternating manner, either extending in the Z-axis direction to an adjacent metallization layer above (indicated by a dot "." inside the voids 802 in FIG. 8) or extending in the Z-axis direction to an adjacent metallization layer below (indicated by an "X" inside the voids 802 in FIG. 8) to provide stiffness and bending symmetry for the void-defining portion 820. Also, in the example of FIG. 8, the voids 802 are completely surrounded by the metal material 804 within the metal structure 808. Also, in this example, the voids 802 disposed within the metal structure 808 may be designed to have a total area that is at least thirty percent (30%) of the total area of ​​the metal structure 808.

[0031]

[0043] It is also possible to provide unpatterned voids in metal structures in a metallization layer of a package substrate to form void-defining portions in the metal structures. For example, voids may be disposed in metal structures that provide a ground plane in a package substrate. For example, voids may be selectively disposed in metal structures, such as ground planes of a package substrate, adjacent metal lines or traces and / or other electrical components of the package substrate to provide selective mechanical stress relief to such metal lines or traces and / or other electrical components.

[0032]

[0044] 9A-9H are top views of other exemplary metal structures in a metallization layer having patterned voids or cutouts selectively provided adjacent metal traces and / or other electrical components of a package substrate to provide void-defining portions within the metal structures that can be coupled to vias or other interconnects in the package substrate to provide selective mechanical stress relief for such interconnects and electrical components coupled to such interconnects.

[0033]

[0045] 9A is a top view of a metal structure 900 having a void-defining portion 903 formed by a void in a metal material 901 of the metal structure 900, which may be provided in a package substrate 902, such as the package substrate 104 of FIG. 1. A first void 904(1) is disposed in the metal structure 900. A second void 904(2) is also disposed adjacent to the first void 904(1) in the metal structure 900, such that a metal interconnect 906 is formed in the metal structure 900 between the first void 904(1) and the second void 904(2). The second void 904(2) is aligned along the same axis A1 of the first void 904(1). Dielectric material 908 may be disposed within first void 904(1) and / or second void 904(2) such that dielectric material 908 has a lower CTE than the CTE of metal material 901 of metal structure 900. In this manner, the stiffness of metal structure 900 adjacent metal interconnect 906 is reduced, which may reduce or avoid damage to metal interconnect 906 and metal material 901 adjacent voids 904(1), 904(2) in response to an applied stress.

[0034]

[0046] 9B is a top view of a metal structure 910 having a void-defining portion 913 formed by a void in a metal material 912 of the metal structure 910, which may be provided in a package substrate 914, such as the package substrate 104 of FIG. 1. A first void 916(1) is disposed in the metal structure 910. The first void 916(1) includes a first elongated void portion 918(1) aligned lengthwise with a first axis A2 and a second elongated void portion 918(2) aligned lengthwise with a second axis A3 parallel to the first axis A2. A third void portion 918(3) couples the first elongated void portion 918(1) and the second elongated void portion 918(2). The third void portion 918(3) is aligned along its length with a third axis A4 that is orthogonal to the first axis A2 and the second axis A3. The second void 916(2) includes a fourth elongated portion 920(1) that is aligned along its length with the first axis A2 and a fifth elongated void portion 920(2) that is aligned along its length with the second axis A3. The sixth void portion 920(3) connects the fourth elongated void portion 920(1) and the fifth elongated void portion 920(2). The sixth void portion 920(3) is aligned along its length with a fourth axis A5 that is orthogonal to the first axis A2 and the second axis A3. The metal interconnects 922 are formed in the spaces between the respective first and fourth elongated void portions 918(1) and 920(1), the respective second and fifth elongated void portions 918(2) and 920(2), and the respective third and sixth void portions 918(3) and 920(3). The dielectric material 924 may be disposed within the void portions 918(1)-918(3), 920(1)-920(3) such that the dielectric material 924 has a lower CTE than the CTE of the metal material 912 of the metal structure 910. In this manner, the stiffness of the metal structure 910 adjacent the metal interconnects 922 is reduced, which may reduce or avoid damage to the metal interconnects 922 and the metal material 912 adjacent the voids 916(1), 916(2) in response to an applied stress.

[0035]

[0047] 9C is a top view of another metal structure 930 having a void-defining portion 933 formed by a void in a metal material 932 of the metal structure 930, which may be provided in a package substrate 934, such as the package substrate 104 of FIG. 1. A first void 936(1) is disposed in the metal structure 930. The first void 936(1) is aligned in its length direction with a first axis A6. A second void 936(2) is disposed in the metal structure 930 and aligned in its length direction with a second axis A7 that is orthogonal to the first axis A6. A third void 936(3) is disposed in the metal structure 930 between the first void 936(1) and the second void 936(2) and includes elongated void portions 938(1), 938(2) aligned in their length directions along respective first and second axes A6 and A7. In this manner, the voids 936(1)-936(3) form an L-shape within the metal structure 930, and two metal interconnects 940(1), 940(2) are formed between each of the voids 936(1)-936(3). The dielectric material 942 may be disposed within the voids 936(1)-936(3) such that the dielectric material 942 has a lower CTE than the CTE of the metal material 932 of the metal structure 930. In this manner, the stiffness of the metal structure 930 adjacent to the metal interconnects 940(1), 940(2) may be reduced, thereby reducing or avoiding damage to the metal interconnects 940(1), 940(2) and the metal material 932 adjacent to the voids 936(1)-936(3) in response to an applied stress.

[0036]

[0048] 9D is a top view of another metal structure 950 having a void-defining portion 953 formed by a void in a metal material 952 of the metal structure 950, which may be provided in a package substrate 954, such as the package substrate 104 of FIG. 1. A curved void 956 of radius R1 is disposed in the metal structure 950. A dielectric material 958 may be disposed in the void 956 such that the dielectric material 958 has a lower CTE than the CTE of the metal material 952 of the metal structure 950. In this manner, the stiffness of the metal structure 950 adjacent the void 956 is reduced, thereby avoiding damage in response to an applied stress. A metal interconnect 959 is formed adjacent the void 956.

[0037]

[0049] 9E-9H are top views of other respective metal structures 960, 970, 980, 990 having respective void-defining portions 963, 973, 983, 993 formed by voids in the metal material 962 of the metal structures 960, 970, 980, 990 that may be provided in a package substrate, such as the package substrate 104 of FIG. 1. FIG. 9E includes four voids 964(1)-964(4) surrounding a via 966 for forming a metal interconnect 967. A dielectric material 968 may be disposed within the voids 964(1)-964(4) such that the dielectric material 968 has a lower CTE than the CTE of the metal material 962 of the metal structure 960. FIG. 9F is a metal structure 970 including four voids 974(1)-974(4) surrounding a via 966 to provide an interconnect in a different arrangement than FIG. 9E. The dielectric material 968 may be disposed within the voids 974(1)-974(4) such that the dielectric material 968 has a lower CTE than the CTE of the metal material 962 of the metal structure 970. FIG. 9G is a metal structure 980 including four voids 984(1)-984(4) surrounding the via 966 to provide an interconnection in a different arrangement than that of FIG. 9F. The dielectric material 968 may be disposed within the voids 984(1)-984(4) such that the dielectric material 968 has a lower CTE than the CTE of the metal material 962 of the metal structure 980. FIG. 9H is yet another metal structure 990 including two voids 994(1), 994(2) surrounding the via 966 to provide an interconnection in a different arrangement than that of FIG. 9G. The dielectric material 968 may be disposed within the voids 994(1), 994(2) such that the dielectric material 968 has a lower CTE than the CTE of the metal material 962 of the metal structure 990.

[0038]

[0050] FIG. 10 is a flow chart illustrating an exemplary manufacturing process 1000 for manufacturing a die module package, such as the die module package 100 of FIG. 1, including a package substrate including one or more metal structures having void-defining portions formed by voids in the metal material of the metal structure(s). The void-defining portions can reduce the metal stiffness of the metal structure(s) to reduce die-to-substrate mechanical stresses between the package substrate and the die interconnects and die. The exemplary manufacturing process 1000 is described with reference to the die module package 100 of FIGS. 1 and 2. However, it should be noted that the manufacturing process 1000 can also be used to manufacture the metal structures 308, 408, 608, 708, 808, 908, 910, 930, 950, 960, 970, 980, 990 of FIGS. 3, 4, and 6-9H, respectively.

[0039]

[0051] In this regard, referring to FIG. 10, the first step of the process 1000 is to form a package substrate 104 (block 1002 of FIG. 10). The next step of the process 1000 is to form a plurality of metal structures 108 (block 1004 of FIG. 10), each including a metal material 204 having a first CTE, the metal structures 108 sharing common vertical surfaces parallel to one another and overlapping one another in the vertical direction. Then, for each metal structure 108 of the plurality of metal structures 108 (block 1006 of FIG. 10), the next step of the process is to form a void-defining portion 120 in the metal structure 108 (block 1008 of FIG. 10). The process 1000 also includes forming, for each metal structure 108 of the plurality of metal structures 108, a plurality of voids 202 arranged in the metal structure 108 such that one or more metal interconnects 206 are formed between respective adjacent voids 202 of the plurality of voids 202 (block 1010 of FIG. 10). The process 1000 also includes disposing, for each metal structure 108 of the plurality of metal structures 108, a dielectric material 210 having a second CTE in at least one of the plurality of voids 202 in the void-defining portion 120, the second CTE of the dielectric material 210 being less than the first CTE of the metal structure 108 (block 1012 of FIG. 10). The process 1000 also includes forming at least one die interconnect 114 coupled to the at least one of the one or more metal interconnects 206 in the void-defining portion 120 (block 1014 of FIG. 10). The process 1000 also includes coupling the dies 102(1), 102(2) to the at least one die interconnect 114 (block 1016 of FIG. 10).

[0040]

[0052] As used herein, it should be understood that the terms "top," "above," "bottom," and "below" are relative terms and are not meant to limit or imply a precise orientation. An "top" reference element is not always oriented as being above a "bottom" reference element with respect to the ground, and vice versa. An element referenced as "top" or "bottom" may be at the top or bottom with respect to that example only and the particular illustrated example. An element referenced as "above" or "below" another element is not necessarily with respect to the ground, and vice versa. An element referenced as "above" or "below" may be above or below such other referenced element with respect to that example only and the particular illustrated example.

[0041]

[0053] A die module package including a package substrate including one or more metal structures having void-defining portions formed by voids in the metal material of the metal structure(s) to reduce the metal stiffness of the metal structure(s), according to any embodiment disclosed herein, including, but not limited to, the package substrate of Figures 1-3 and 6-9H, according to the exemplary manufacturing process of Figure 10, may be provided or integrated within any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0042]

[0054] In this regard, Figure 11 illustrates an exemplary wireless communication device 1100 that includes an RF component formed from one or more ICs 1102, any of which may be included within an IC package 1103. The IC package 1103 may include die module package(s) including, but not limited to, the package substrates of Figures 1-3 and 6-9H, including a package substrate that includes one or more metal structures having void-defining portions formed by voids in the metal material of the metal structure(s) to reduce the metal stiffness of the metal structure(s), according to the exemplary manufacturing process of Figure 10.

[0043]

[0055] The wireless communication device 1100 may include or be provided within, by way of example, any of the devices referenced above. As shown in FIG. 11, the wireless communication device 1100 includes a transceiver 1104 and a data processor 1106. The data processor 1106 may include memory for storing data and program codes. The transceiver 1104 includes a transmitter 1108 and a receiver 1110 supporting bidirectional communication. In general, the wireless communication device 1100 may include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or a portion of the transceiver 1104 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, and the like.

[0044]

[0056] The transmitter 1108 or the receiver 1110 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages in the receiver 1110, for example, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In the direct-conversion architecture, the signal is frequency converted between RF and baseband in one stage. The super-heterodyne architecture and the direct-conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 1100 in FIG. 11, the transmitter 1108 and the receiver 1110 are implemented with a direct-conversion architecture.

[0045]

[0057] On the transmit path, the data processor 1106 processes data to be transmitted and provides I and Q analog output signals to a transmitter 1108. In the exemplary wireless communication device 1100, the data processor 1106 includes digital-to-analog converters (DACs) 1112(1) and 1112(2) to convert digital signals generated by the data processor 1106 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0046]

[0058] Within the transmitter 1108, low pass filters 1114(1) and 1114(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1116(1), 1116(2) amplify the signals from the low pass filters 1114(1), 1114(2), respectively, and provide I and Q baseband signals. An upconverter 1118 upconverts the I and Q baseband signals using I and Q TX local oscillator (LO) signals from a transmit (TX) local oscillator (LO) signal generator 1122 through mixers 1120(1), 1120(2) to provide an upconverted signal 1124. A filter 1126 filters the upconverted signal 1124 to remove unwanted signals caused by frequency upconversion as well as noise in the received frequency band. A power amplifier (PA) 1128 amplifies the upconverted signal 1124 from filter 1126 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1130 and transmitted via an antenna 1132.

[0047]

[0059] In the receive path, an antenna 1132 receives a signal transmitted by a base station and provides a received RF signal, which is routed through a duplexer or switch 1130 and provided to a low noise amplifier (LNA) 1134. The duplexer or switch 1130 is designed to operate at a particular RX to TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. The received RF signal is amplified by the LNA 1134 and filtered by a filter 1136 to obtain a desired RF input signal. Downconversion mixers 1138(1), 1138(2) mix the output of the filter 1136 with I and Q RX LO signals (i.e., LO_I and LO_Q) from a RX LO signal generator 1140 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1142(1), 1142(2) and further filtered by low pass filters 1144(1), 1144(2) to obtain I and Q analog input signals, which are provided to the data processor 1106. In this example, the data processor 1106 includes analog-to-digital converters (ADCs) 1146(1), 1146(2) to convert the analog input signals to digital signals for further processing by the data processor 1106.

[0048]

[0060] In the wireless communication device 1100 of FIG. 11, a TX LO signal generator 1122 generates an I TX LO signal and a Q TX LO signal used for frequency up-conversion, while a RX LO signal generator 1140 generates an I RX LO signal and a Q RX LO signal used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. A TX phase-locked loop (PLL) circuit 1148 receives timing information from the data processor 1106 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 1122. Similarly, a RX PLL circuit 1150 receives timing information from the data processor 1106 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 1140.

[0049]

[0061] FIG. 12 illustrates an example of a wireless communication device as a processor-based system 1200 that may include, but is not limited to, the package substrate of FIGS. 1-3 and 6-9H, a die module package(s) including a package substrate including one or more metal structures having void-defining portions formed by voids in the metal material of the metal structure(s) to reduce the metal stiffness of the metal structure(s), according to the exemplary manufacturing process of FIG. 10, and according to any aspect disclosed herein. In this example, the processor-based system 1200 may be formed as an IC 1204 in an IC package 1202 and as a system-on-a-chip (SoC) 1206. The processor-based system 1200 includes a central processing unit (CPU) 1208 including one or more processors 1210, which may be referred to as CPU cores or processor cores. The CPU 1208 may have a cache memory 1212 coupled to the CPU 1208 for rapid access to temporarily stored data. CPU 1208 is coupled to a system bus 1214, which may interconnect master and slave devices included within processor-based system 1200. As is well known, CPU 1208 communicates with these other devices by exchanging address, control, and data information via system bus 1214. For example, CPU 1208 may communicate bus transaction requests to memory controller 1216, as an example of a slave device. Although not shown in FIG. 12, multiple system buses 1214 may be provided, with each system bus 1214 constituting a different fabric.

[0050]

[0062] Other master and slave devices may be connected to the system bus 1214. As shown in FIG. 12, these devices may include, by way of example, a memory system 1220 including a memory controller 1216 and memory array(s) 1218, one or more input devices 1222, one or more output devices 1224, one or more network interface devices 1226, and one or more display controllers 1228. Each of the memory system 1220, the one or more input devices 1222, the one or more output devices 1224, the one or more network interface devices 1226, and the one or more display controllers 1228 may be provided in the same or different die module packages 1202. The input device(s) 1222 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output device(s) 1224 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. The network interface device(s) 1226 may be any device configured to enable the exchange of data to and from the network 1230. The network 1230 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The network interface device(s) 1226 may be configured to support any type of communication protocol desired.

[0051]

[0063] CPU 1208 may also be configured to access display controller(s) 1228 via system bus 1214 to control information sent to one or more displays 1232. Display controller(s) 1228 send information to display(s) 1232 to be displayed via one or more video processors 1234, which process the information to be displayed into a format suitable for display(s) 1232. Display controller(s) 1228 and video processor(s) 1234 may be included as ICs in the same or different die module package 1202, as an example, in the same or different die module package 1202 that includes CPU 1208. The display(s) 1232 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0052]

[0064] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of both. The master and slave devices described herein may be employed in any circuit, hardware component, IC, or IC chip, by way of example. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0053]

[0065] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0054]

[0066] Aspects disclosed herein may be embodied in hardware and instructions stored in the hardware and may reside in, for example, a Random Access Memory (RAM), a Flash memory, a Read Only Memory (ROM), a Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0055]

[0067] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and explanations. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that many different modifications may be made to the operational steps shown in the flowchart diagrams, as would be readily apparent to one of ordinary skill in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0056]

[0068] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0057]

[0069] The following numbered clauses describe example implementations. 1. a package substrate, the package substrate comprising: a plurality of metal structures that are horizontally parallel to one another and share a common vertical plane; Each metal structure of the plurality of metal structures is a metallic material having a first coefficient of thermal expansion (CTE); a void-defining portion comprising a plurality of voids disposed within the metal structure; one or more metal interconnects each formed by a metal material in the metal structure disposed between adjacent ones of the plurality of voids; a dielectric material having a second CTE disposed within at least one of the plurality of voids within the void-defining portion, the second CTE of the dielectric material being less than the first CTE of the metallic material; Equipped with a die disposed adjacent to a package substrate; at least one die interconnect, each coupled to the die and each coupled to one of the one or more metal interconnects in a void-defining portion of at least one metal structure of the plurality of metal structures; The die module package comprises: 2. A die module package as described in clause 1, wherein at least a portion of the area of ​​the die is oriented relative to the package substrate such that it at least partially overlaps a void-defining portion in the package substrate in a vertical plane. 3. the package substrate includes a plurality of parallel metallization layers; 3. The die module package of clause 1 or 2, wherein each metal structure of the plurality of metal structures is disposed within a different metallization layer of the plurality of metallization layers. 4. a first metal structure of the plurality of metal structures disposed within a first metallization layer of the plurality of metallization layers; a second metal structure of the plurality of metal structures disposed within a second metallization layer of the plurality of metallization layers different from the first metallization layer; a vertical interconnect access (via) disposed through an individual one of the plurality of voids within the void-defining portion of the first metal structure; each via of the at least one via coupled to one metal interconnect of the plurality of metal interconnects within the void-defining portion of the second metal structure; 4. The die module package of any one of clauses 1 to 3, further comprising: 5. A die module package as described in any one of clauses 1 to 4, wherein each of the multiple voids disposed within the metal structure is completely surrounded by and bonded to the metal material within the metal structure. 6. The die module package of any of clauses 1-5, wherein each metal structure of the plurality of metal structures includes a ground plane. 7. The die module package of any of clauses 1-6, wherein the plurality of voids in each metal structure have an area that is at least thirty percent (30%) of the area of ​​the metal structure. 8. The die module package of any of clauses 1-7, wherein the plurality of voids form a perimeter of a void-defining portion in the metal structure. 9. The die module package of claim 8, wherein the plurality of voids have a first area that is at least eighty-five percent (85%) of a perimeter second area. 10. The die module package of any of clauses 1-9, wherein the void-defining portion of the metal structure has a Young's modulus of 100 megapascals (MPa) to 50 gigapascals (GPa). 11. The die module package of any of clauses 1-10, wherein the first CTE of the metal material of the metal structure is between 13 parts per million (ppm) per Kelvin (K) (ppm / K) and 24 ppm / K. 12. The die module package of claim 11, wherein the second CTE of the dielectric material is between 4 ppm / K and 18 ppm / K. 13. The die module package of any of clauses 1-12, wherein the plurality of voids in at least one of the plurality of metal structures are formed in a repeating pattern in the metal structure. 14. A die module package as described in any of clauses 1 to 13, wherein each of the plurality of voids in at least one of the plurality of metal structures has the same first pitch in a first direction of a first axis and the same second pitch in a second direction of a second axis perpendicular to the first axis. 15. A die module package as described in any of clauses 1-14, wherein each of the plurality of voids in at least one of the plurality of metal structures includes an elongated void having a first length in a first direction of a first axis and a second length in a second direction of a second axis perpendicular to the first axis, the second length being equal to the first length. 16. A die module package as described in any of clauses 1-15, wherein each of the plurality of voids in at least one of the plurality of metal structures includes an elongated void having a first length in a first direction of a first axis and a second length in a second direction of a second axis perpendicular to the first axis, the second length being smaller than the first length. 17. A die module package as described in any of clauses 1-16, wherein at least one metal structure of the plurality of metal structures is uniformly deformable along at least two orthogonal axes. 18. The die module package of clause 17, wherein the voids in at least one metal structure of the plurality of metal structures have the same pitch. 19. The die module package of any of clauses 1-18, wherein a subset of the voids among the plurality of voids in at least one metal structure among the plurality of metal structures are elongated along the same axis. 20. A die module package as described in any of clauses 1-19, wherein the void-defining portion in at least one of the plurality of metal structures is a square-shaped void-defining portion having a plurality of linear voids arranged along a square-shaped perimeter forming a perimeter of the void-defining portion. 21. A die module package as described in any of clauses 1-20, wherein the void-defining portion in at least one of the plurality of metal structures is a circular void-defining portion having a plurality of convex voids arranged along a circular perimeter forming a perimeter of the void-defining portion. 22. For at least one metal structure of the plurality of metal structures, A first void of the plurality of voids is a first elongated void portion aligned with a first axis; a second elongated void portion aligned with a second axis parallel to the first axis; a third void portion connecting the first elongated void portion and the second elongated void portion; Equipped with A second void of the plurality of voids a fourth elongated void portion aligned with the first axis and separated from the first elongated void portion by a first metal void portion in the at least one metal structure; a fifth elongated void portion aligned with the second axis and separated from the first elongated void portion by a second metal void portion in the at least one metal structure; a sixth void portion connecting the fourth elongated void portion and the fifth elongated void portion separated by a third metal void portion in the at least one metal structure; Equipped with the first metal void portion, the second metal void portion, and the third metal void portion are bonded together to form a metal interconnect; 22. A die module package according to any one of clauses 1 to 21. 23. The die module package of any of clauses 1-22 integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter. 24. A method for manufacturing a die module package, comprising: forming a package substrate; and forming the package substrate, forming a plurality of metal structures parallel to one another in a horizontal direction and sharing a common vertical plane, each metal structure of the plurality of metal structures comprising: a metallic material having a first coefficient of thermal expansion (CTE); a void-defining portion comprising a plurality of voids disposed within the metal structure; one or more metal interconnects each formed by a metal material in the metal structure disposed between adjacent ones of the plurality of voids; a dielectric material having a second CTE disposed within at least one of the plurality of voids within the void-defining portion, the second CTE of the dielectric material being less than the first CTE of the metallic material; Equipped with forming at least one die interconnect coupled to at least one metal interconnect of the one or more metal interconnects within a void-defining portion of at least one metal structure of the plurality of metal structures; coupling the die to at least one die interconnect; A method comprising: 25. The method of claim 24, wherein coupling the die to the at least one die interconnect further comprises positioning at least a portion of an area of ​​the die oriented relative to the package substrate such that the area at least partially overlaps in a vertical plane a void-defining portion in at least one metal structure of a plurality of metal structures in the package substrate. 26. disposing at least one vertical interconnect access (via) each passing through a respective one of the plurality of voids in a void-defining portion of a first metal structure of the plurality of metal structures; coupling each via of the at least one via to one metal interconnect of the plurality of metal interconnects within a second void-defining portion of one metal structure of the plurality of metal structures; 26. The method of claim 24 or 25, further comprising: 27. The method of any of clauses 24-26, wherein forming the plurality of metal structures further comprises forming each metal structure of the plurality of metal structures in a different metallization layer of a plurality of parallel metallization layers in the package substrate. 28. The method of any of clauses 24-27, wherein forming a plurality of voids in the metal structure further comprises forming a plurality of voids in the metal structure such that each of the plurality of voids is completely surrounded by and bonded to the metal material in the metal structure. 29. The method of any of clauses 24-28, wherein forming a plurality of voids within the metal structures further comprises forming a plurality of voids within each metal structure such that the voids consume an area within the metal structure that is at least thirty percent (30%) of the area of ​​the metal structure. 30. The method of any of clauses 24-29, wherein the void-defining portion of the metal structure has a Young's modulus of 100 megapascals (MPa) to 50 gigapascals (GPa). 31. The method of any of clauses 24-30, wherein the first CTE of the metallic material is between 13 parts per million (ppm) per Kelvin (K) (ppm / K) and 24 ppm / K. 32. The method of any one of clauses 24 to 31, wherein the second CTE of the dielectric material is between 4 ppm / K and 18 ppm / K.

Claims

1. A package substrate, wherein the package substrate comprises a plurality of metal structures that are parallel to each other in a horizontal direction and share a common vertical plane, each of the plurality of metal structures comprising a metal material having a first coefficient of thermal expansion (CTE), a void-defining portion comprising a plurality of voids disposed within the metal structure, wherein the void-defining portion is part of the metal structure, one or more metal interconnects each formed by the metal material within the metal structure disposed within the void-defining portion between adjacent voids of the plurality of voids, a dielectric material having a second CTE disposed within at least one of the plurality of voids within the void-defining portion, the second CTE of the dielectric material being less than the first CTE of the metal material, and a die disposed adjacent to the package substrate, at least one die interconnect each coupled to the die and each coupled to one of the one or more metal interconnects within the void-defining portion of at least one of the plurality of metal structures, a die module package.

2. The die module package according to claim 1, wherein at least a portion of the area of the die is oriented with respect to the package substrate such that it at least partially overlaps a void-defining portion within the package substrate in a vertical plane.

3. A first metal structure of the plurality of metal structures is disposed within a first metallization layer of the plurality of metallization layers, a second metal structure of the plurality of metal structures is disposed within a second metallization layer of the plurality of metallization layers different from the first metallization layer, a vertical interconnect access (via) disposed through an individual void of the plurality of voids within the void-defining portion of the first metal structure, each via of the at least one via coupled to one of the one or more metal interconnects within the void-defining portion of the second metal structure, The die module package according to claim 1, further comprising.

4. The die module package according to claim 1, wherein each metal structure of the plurality of metal structures includes a ground plane.

5. The plurality of voids form around the void-defining portion within the metal structure, and preferably, the plurality of voids have a first area that is at least 85 percent (85%) of a second area surrounded by the perimeter, the dimodule package according to claim 1.

6. The plurality of voids within at least one of the plurality of metal structures are formed in a repeating pattern within the metal structure, the dimodule package according to claim 1.

7. Each of the plurality of voids within at least one of the plurality of metal structures has the same first pitch in a first direction of a first axis and the same second pitch in a second direction of a second axis orthogonal to the first axis, or Each of the plurality of voids within at least one of the plurality of metal structures includes an elongated void having a first length in a first direction of a first axis and a second length in a second direction of a second axis orthogonal to the first axis, the second length being smaller than the first length, or At least one of the plurality of metal structures is uniformly deformable along at least two orthogonal axes, and preferably, the plurality of voids within at least one of the plurality of metal structures have the same pitch, or a subset of the voids among the plurality of voids within at least one of the plurality of metal structures are elongated along the same axis, or the void-defining portion within at least one of the plurality of metal structures is a square-shaped void-defining portion comprising a plurality of linear voids arranged along a square-shaped perimeter forming around the void-defining portion, or the void-defining portion within at least one of the plurality of metal structures is a circular-shaped void-defining portion comprising a plurality of convex voids arranged along a circular-shaped perimeter forming around the void-defining portion, the dimodule package according to claim 1.

8. For at least one of the plurality of metal structures, a first void among the plurality of voids has a first elongated void portion aligned with a first axis, and a second elongated void portion aligned with a second axis parallel to the first axis, A third void portion that joins the first elongated void portion and the second elongated void portion, comprising, wherein a second void of the plurality of voids is aligned with the first axis and is a fourth elongated void portion separated from the first elongated void portion by a first metal void portion within the at least one metal structure, aligned with the second axis and is a fifth elongated void portion separated from the first elongated void portion by a second metal void portion within the at least one metal structure, a sixth void portion that joins the fourth elongated void portion and the fifth elongated void portion, separated by a third metal void portion within the at least one metal structure, comprising, the first metal void portion, the second metal void portion, and the third metal void portion are joined together to form the metal interconnection, The dimodule package according to claim 1.

9. A method of manufacturing a dimodule package, comprising: forming a package substrate, and forming the package comprises forming a plurality of metal structures that are parallel to each other in a horizontal direction and share a common vertical plane, wherein each metal structure of the plurality of metal structures is a metal material having a first coefficient of thermal expansion (CTE), a void defining portion comprising a plurality of voids disposed within the metal structure, wherein the void defining portion is part of the metal structure, one or more metal interconnections each formed by the metal material within the metal structure disposed within the void defining portion between adjacent voids of the plurality of voids, a dielectric material having a second CTE disposed within at least one of the plurality of voids within the void defining portion, wherein the second CTE of the dielectric material is less than the first CTE of the metal material, comprising, forming at least one die interconnection coupled to at least one of the one or more metal interconnections within the void defining portion of at least one metal structure of the plurality of metal structures, coupling a die to the at least one die interconnection, A method comprising.

10. Coupling the die to the at least one die interconnect further comprises arranging at least a portion of the region of the die oriented with respect to the package substrate so as to at least partially overlap a void defining portion within at least one of the plurality of metal structures within the package substrate in a vertical plane, the method according to claim 9.

11. Arranging at least one vertical interconnect access (via) through which each individual void of the plurality of voids within the void defining portion of the first metal structure of the plurality of metal structures passes; Coupling each via of the at least one via to one metal interconnect of the plurality of metal interconnects within a second void defining portion of one of the plurality of metal structures; The method according to claim 9, further comprising.

12. The void defining portion of the metal structure has a Young's modulus of 100 megapascals (MPa) to 50 gigapascals (GPa), or The first CTE of the metal material is 13 parts per million (ppm) per Kelvin (ppm / K) to 24 ppm / K, or The second CTE of the dielectric material is 4 ppm / K to 18 ppm / K, the die module package according to claim 1 or the method according to claim 9.

13. The package substrate includes a plurality of metallization layers parallel to each other, The die module package according to claim 1 or the method according to claim 9, wherein each of the plurality of metal structures is disposed within a different one of the plurality of metallization layers.

14. Each of the plurality of voids disposed within the metal structure is completely surrounded by and bonded to the metal material within the metal structure, the die module package according to claim 1 or the method according to claim 9.

15. The plurality of voids within each metal structure have an area that is at least 30 percent (30%) of the area of the metal structure, the die module package according to claim 1 or the method according to claim 9.

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