Chalcogenide Processing Techniques and Equipment

Abstract

A layer of chalcogenide material can be etched by providing a wafer having a layer of chalcogenide material in a processing chamber, heating the wafer to a first temperature, flowing a first chemical species comprising a fluoride or chloride over the wafer while the wafer is at the first temperature to modify a surface of the layer of chalcogenide material to produce a modified layer of chalcogenide material, and flowing a second chemical species comprising a compound having a central atom that is aluminum, boron, silicon, or germanium and at least one chlorine over the wafer to remove the modified layer of chalcogenide material without the use of a plasma.

Description

[Technical field]

[0001] <CROSS REFERENCE TO RELATED APPLICATIONS> The PCT application is being filed contemporaneously herewith as a part of this application. Each application to which this application claims benefit or priority as identified in the contemporaneously filed PCT application is hereby incorporated by reference in its entirety for all purposes.

[0002] Fabrication of semiconductor devices involves the formation of memory stacks, which can be difficult to form and are often sensitive to etching processes such as exposure to energetic species, as well as to oxidation, moisture, and additional exposure to energetic species after etching. As a result, some memory stacks may undergo post-etch processing to address damage from etching and environmental exposure, followed by encapsulation of the memory stack prior to subsequent processing. However, some methods of post-etch processing prior to encapsulation, and corresponding apparatus, may not be able to adequately address damage and exposure to the memory stack, which may further damage the memory stack. [Background technology]

[0003] The background description provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors, to the extent described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004] The systems, methods, and devices of the present disclosure each have several innovative aspects, none of which is solely responsible for the desirable properties disclosed herein, including at least the following embodiments, although additional embodiments may be described in the detailed description or may be apparent from the description set forth herein. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 illustrates an example process flow diagram for performing operations in accordance with the disclosed embodiments.

[0006] [Diagram 2] FIG. 2 illustrates a second example process flow diagram for performing operations in accordance with the disclosed embodiments.

[0007] [Diagram 3] FIG. 3 shows an example schematic diagram of atomic layer etching according to a disclosed embodiment.

[0008] [Figure 4] FIG. 4 illustrates a third example process flow diagram for performing operations in accordance with disclosed embodiments.

[0009] [Figure 5A] FIG. 5A illustrates an example gas flow sequence according to various embodiments. [Figure 5B] FIG. 5B illustrates an example gas flow sequence according to various embodiments. [Figure 5C] FIG. 5C illustrates an example gas flow sequence according to various embodiments.

[0010] [Figure 6] FIG. 6 shows an example schematic of an etching process according to a disclosed embodiment.

[0011] [Figure 7] FIG. 7 illustrates an example process flow for etching chalcogenides.

[0012] [Figure 8] FIG. 8 illustrates a flow chart of an example sequence of operations for forming a film of a material on a substrate by an ALD process.

[0013] [Figure 9]FIG. 9 illustrates a third example process flow diagram for performing operations in accordance with disclosed embodiments.

[0014] [Figure 10] FIG. 10 illustrates a first exemplary processing apparatus according to disclosed embodiments.

[0015] [Figure 11] FIG. 11 illustrates yet another example process flow for etching a chalcogenide layer.

[0016] [Figure 12] FIG. 12 illustrates a second exemplary processing apparatus according to disclosed embodiments.

[0017] [Figure 13] FIG. 13 illustrates another technique in accordance with disclosed embodiments.

[0018] [Figure 14] FIG. 14 illustrates yet another technique in accordance with disclosed embodiments.

[0019] [Figure 15] FIG. 15 shows an example process flow for etching two chalcogenides.

[0020] [Figure 16] FIG. 16 illustrates an example of a substrate processing chamber for etching a material in accordance with the present disclosure.

[0021] [Figure 17] FIG. 17 illustrates a cross-sectional side view of an example apparatus according to disclosed embodiments.

[0022] [Figure 18] FIG. 18 shows a top view of a substrate heater with multiple LEDs.

[0023] [Figure 19] FIG. 19 shows an example of a temperature control sequence.

[0024] [Figure 20] FIG. 20 illustrates generally an embodiment of a processing station that may be used for the deposition of material. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. It should be understood that while some disclosed embodiments will be described in conjunction with specific embodiments, it is not intended to be limited to those disclosed embodiments.

[0026] In this application, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will appreciate that the term "partially fabricated integrated circuit" can refer to a silicon wafer during any of the many stages of integrated circuit fabrication on a silicon wafer. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, or 300 mm, or 450 mm. In the following detailed description, it is assumed that the invention is implemented on a wafer. However, the invention is not so limited. Workpieces can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the invention include a variety of printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0027] Introduction and Background: Semiconductor fabrication processes often involve the deposition of silicon nitride materials. In one example, silicon nitride may be used as a diffusion barrier, gate dielectric, sidewall spacer, and encapsulation layer in semiconductor fabrication processes. Conformal silicon nitride layers may also be used in other applications. For example, silicon nitride may be used during the fabrication of memory structures. Some memory structures include metal oxide materials used for bit storage. However, as advanced memory structures continue to be developed to accommodate smaller devices and improve efficiency, new challenges arise. Advanced memory architectures such as magnetoresistive random access memory and phase change random access memory (PCRAM) rely on new materials (other than metal oxides), such as chalcogenides, for bit storage.

[0028] In some memory devices, chalcogenides such as Ovonic Threshold Switching (OTS) are present in the stack. OTS and other chalcogenides can be sensitive to various gases and plasmas. For example, in PCRAM, the phase of the metal chalcogenide determines the bit state. Some examples of chalcogenides include sulfur (S), selenium (Se), and tellurium (Te). These new materials are sensitive to air and moisture and may require an encapsulation layer. These chalcogenides form a phase change layer when combined with an appropriate metalloid ion such as germanium (Ge), antimony (Sb), etc. In some cases, memory devices include a germanium antimony tellurium (GST) material. If the chalcogenide is damaged, it may not function properly, for example, the phase of the phase change layer may not change.

[0029] The use of chalcogenides requires both depositing the chalcogenide and removing a portion of the deposited chalcogenide from the wafer to create a desired structure, such as removing a portion of the chalcogenide from within a trench or via. It is desirable to etch the chalcogenide without damaging and / or changing the composition of the chalcogenide material that is intended to remain on the wafer within a desired non-uniformity tolerance. However, removing some of the chalcogenide from the wafer presents unique and difficult challenges and considerations, and conventional etches cannot remove some of the chalcogenide without damaging and / or changing the composition of the chalcogenide material within a desired non-uniformity tolerance.

[0030] Also, some of the conventional techniques for removing chalcogenides may adversely affect the wafer. For example, reactive ion etching ("RIE") using plasma may in some cases result in poor etch uniformity and may cause unnecessary damage to the chalcogenides, thereby compromising their properties and preventing them from becoming effective PCRAM. Also, the plasma in RIE etching is directional rather than isotropic, thus limiting its capabilities to etching in a direction perpendicular to the substrate surface and preventing etching under ledges or overhangs. For example, the wafer may have "features" such as vias or contact holes, which may be characterized by one or more of narrow and / or recessed openings, constrictions within the feature, and high aspect ratios. One example of a feature is a hole or via in a semiconductor substrate or substrate layer. Other examples include trenches in the substrate or layer, as well as overhangs or ledges that may require etching in places that may not be accessible with the directional ions used in RIE etching.

[0031] Some processes using RIE etching require performing post-etch operations, sometimes referred to as "clean" or "wash" operations, to remove at least a portion of the damaged chalcogenide material. However, these cleaning operations can reduce throughput, increase costs, further damage the wafer, and can be difficult to implement. Some such cleaning operations utilize wet cleaning processes that expose the wafer to a number of liquid chemicals that remove the damaged chalcogenide material from the surface of the wafer. However, wet cleaning processes can damage the wafer in a variety of ways. In some instances, the liquid chemicals themselves can change the composition of some chalcogenide materials, such as GST, thereby further damaging the chalcogenide. In addition, capillary forces exerted by wet cleaning fluids, such as liquids in trenches or vias, on chalcogenide-bearing structures can cause the structures to collapse. Some wet cleaning processes may prevent this collapse by using surface-modifying reactants, but these reactants can remain on the surface of the chalcogenide and adversely affect the chalcogenide or other materials on the wafer. Also, the amount of damage removal depends on the selectivity of the damaged chalcogenide versus the undamaged bulk chalcogenide, thus increasing the challenge and difficulty of removing the damaged chalcogenide.

[0032] Furthermore, the liquids used in wet cleaning processes can require complex liquid storage and delivery systems that can be expensive and difficult to operate and maintain. Furthermore, many etching and post-etching processes (such as deposition of an encapsulation layer on the etched chalcogenide) are performed at vacuum pressure, while wet cleaning operations are performed at atmospheric pressure. Thus, the wafer is transferred from the vacuum environment where the etching is performed to atmospheric pressure for wet cleaning, and then transferred back to the vacuum environment for further post-etching processes. Transferring the wafer between the vacuum and atmospheric environments can increase processing time and reduce throughput, can lead to wafer defects due to particle contamination, and can expose the etched chalcogenide to air, oxygen, or N2, which can oxidize and damage the etched chalcogenide material. Also, wet cleaning processes are typically performed in separate chambers, which require additional space in the fabrication environment along with complex liquid storage and delivery systems. Thus, it increases the footprint of the semiconductor processing tool and prevents the placement of additional tools in the facility, thereby reducing the overall throughput in the facility.

[0033] The present specification provides techniques and apparatus for etching and further processing chalcogenide materials. The techniques use thermal etching (which may include thermal atomic layer etching) to perform cleaning operations of chalcogenide materials after RIE etching or other ion-based etching instead of wet cleaning operations, and / or to etch bulk chalcogenide materials instead of RIE or other ion-based etching. This may include performing thermal etching on a single layer of chalcogenide material, or multiple layers of chalcogenide materials in a stack of materials. As described in more detail below, thermal etching may involve flowing a first chemical species including fluoride or chloride onto the wafer to modify the surface of the layer of chalcogenide material to form a modified layer of chalcogenide material, and flowing a second chemical species including a compound having a central atom that is aluminum, boron, silicon, or germanium, and at least one chlorine onto the wafer to remove the modified layer of chalcogenide material without the use of plasma.

[0034] Atomic layer etching ("ALE") processes remove thin layers of material using a sequence of self-limiting reactions. Generally, an ALE cycle is the minimum set of operations used to perform a single etching process, such as etching a monolayer. An ALE cycle results in etching at least a portion of a film layer on a substrate surface. Typically, an ALE cycle includes a modification operation that forms a reactive layer, followed by a removal operation that removes or etches only the reactive layer. A cycle may include certain auxiliary operations, such as removal of one of the reactants or by-products, as well as cleaning operations that remove accumulated residues on the surfaces of the process chamber. Generally, a cycle includes one instance in a specific sequence of operations.

[0035] By way of example, an ALE cycle may include the following operations: (i) delivery of a first process gas, which is a reactant gas, (ii) purging the reactant gas from the chamber, (iii) delivery of a second process gas, which is a removal gas, and optional plasma, and (iv) purging the chamber. The modification operation (item (ii) above) generally forms a thin reactive surface layer that is less thick than the unmodified material, such as one, two, or three atomic layers thick, or less than a full atomic layer thick in one cycle.

[0036] The etching processes described herein may rely on maintaining the substrate at a particular temperature or temperature range that facilitates chemical reactions in a modification and / or removal operation, which, in conjunction with the chemical reactions, may be considered "thermal ALE" or "thermal etching". In some embodiments, the thermal etching or thermal ALE may be considered an isotropic etch. In some embodiments, one or more layers of the substrate may be modified by chemical adsorption (hereinafter "chemisorption") without the use of plasma while the substrate is maintained at a first temperature, and then one or more modified layers of the substrate may be removed by desorption without the use of plasma while the substrate is at a second temperature. Some implementations may optionally use plasma during the modification operation and not during the removal operation. In some embodiments, the first and second temperatures may be the same, and in some other embodiments, they may differ from one another.

[0037] Chemisorption and desorption are temperature-dependent chemical reactions that may occur at separate temperature regimes, partially overlapping temperature regimes, or the same temperature regime. As such, some thermal etching techniques described herein maintain the temperature of the substrate at the same or substantially the same (e.g., within about 10% or 5% of each other) temperature during the modification and removal operations. Some other embodiments adjust the temperature of the substrate between the modification and removal operations to enable and utilize chemisorption that occurs at one temperature for the modification operation and desorption that occurs at a different temperature for the removal operation.

[0038] In some of the thermal etching processes provided herein, one or more surface layers of a material may be modified by chemisorption while the substrate is maintained at a first temperature, resulting in one or more modified surface layers of the substrate. The substrate includes a layer of material, which may be a uniform layer of material or a non-uniform layer containing different molecules and elements, and an exposed surface. A first process gas having modifying molecules may be flowed over the substrate maintained at a first temperature. In some embodiments, the modifying molecules may include fluorine or chlorine to fluorinate or chlorinate the molecules on the substrate, as described below. The first process gas may also include a carrier gas, such as N2, Ar, He, and Ne. This first temperature allows for chemisorption between the modifying molecules and at least a portion of the molecules in the one or more exposed surfaces of the material.

[0039] The one or more modified surface layers may be removed while the substrate is maintained at the second temperature. In some embodiments, the second temperature alone may allow and cause the modified molecules to desorb from the substrate, thereby removing the modified molecules from the substrate. In some other embodiments, a second process gas having the removal molecules may be flowed over the substrate, including over the exposed surface of the substrate. The second process gas may also include a carrier gas as described above. These removal molecules may react with the modified molecules to form different volatile molecules, which may be considered volatilized molecules. The volatilized molecules may then be removed from the substrate by desorption when the substrate is at the second temperature. In some embodiments, flowing this second process gas may be part of the removal operation or may be a separate operation that occurs before, after, or during heating of the substrate.

[0040] In some embodiments, the thermal ALE may be isotropic and therefore non-directional, in some other embodiments, the thermal ALE is not isotropic when directional ions are used in the etching process, such as in a modification operation.

[0041] Other thermal etches may be performed in which the modifying and removing molecules are flowed at least in parallel over the substrate, thereby partially overlapping the modifying and removing operations. One or more process gases including both the modifying and removing molecules may be flowed simultaneously over the wafer during such processing. In many implementations of this thermal etch, the modifying and removing molecules are limited so that they do not adversely react with each other, and therefore they may be flowed in parallel over the substrate. In some examples, this parallel flow may occur during the entire etch, and in other examples, the parallel flow may occur during only a portion of the etch. In some examples with only partially overlapping flows, the modifying molecules may be flowed over the substrate before the removing molecules are flowed over the substrate, and thereafter both the modifying and removing molecules may be flowed over the substrate at the same time. In some examples, the flow of both the modifying and removing molecules may be stopped substantially at the same time (e.g., within 10% or 5% of each other), and in other examples, the flow of the modifying molecules may be stopped and the removing molecules may be flowed over the substrate.

[0042] The techniques provided herein may also deposit one or more encapsulating materials over the etched chalcogenide. This may include depositing the encapsulating material using chemical vapor deposition ("CVD"), plasma enhanced CVD ("PECVD"), or atomic layer deposition ("ALD") in a process chamber separate from the process chamber where the etching occurs. In some embodiments, the wafer may be transferred between these process chambers without being exposed to atmospheric pressure, such that the wafer remains at vacuum pressure in both process chambers and during transfer between process chambers. In some embodiments, a layer of a first encapsulating material may be deposited over the etched chalcogenide while the wafer remains in the process chamber where the etching occurs, and the first encapsulating material may include aluminum, such as aluminum oxide. After the first encapsulating material is deposited, the wafer may be transferred to another process chamber where additional encapsulating material is deposited on the wafer.

[0043] Thermal Etching and Encapsulation Technology: Aspects of the present disclosure relate to thermal etching of one or more layers of chalcogenide materials. As discussed above, thermal etching processes rely on holding the substrate at a particular temperature or temperature range that promotes chemical reactions in the modification and / or removal operations in conjunction with chemical reactions. In some embodiments, thermal etching or thermal ALE may be considered an isotropic etch, i.e., a non-directional etch. In some embodiments, one or more layers of the substrate may be modified by chemisorption without the use of plasma while the substrate is maintained at a first temperature, and then one or more modified layers of the substrate may be removed by desorption without the use of plasma while the substrate is at a second temperature. Some implementations may optionally use plasma during the modification operation and not during the removal operation. In some embodiments, the first and second temperatures may be the same, and in some other embodiments, they may differ from one another.

[0044] Some of the techniques described herein etch chalcogenide materials by performing a modification operation in which a first species containing fluorine, such as hydrogen fluoride, or chlorine, such as hydrogen chloride, is flowed over the wafer to modify the surface of the chalcogenide layer to form a modified layer of chalcogenide material. The first species having fluoride or chloride may be considered a modifying molecule as described herein. This modification converts the chalcogenide layer to a fluorinated or chlorinated chalcogenide. The modified layer of chalcogenide is reactive and can be removed by flowing a second species over the wafer, the second species containing a compound having a central atom that is aluminum, boron, silicon, or germanium, and at least one chlorine. The second species of compound reacts with the fluorinated or chlorinated chalcogenide to form a volatile molecule that desorbs from the wafer.

[0045] FIG. 1 illustrates an example process flow diagram for operating in accordance with disclosed embodiments. In block 101, a wafer is provided to a process chamber configured to etch the wafer. The wafer may have a layer of chalcogenide deposited thereon, and in some examples, a surface of the chalcogenide layer may be exposed to the process chamber environment. The chalcogenide may also be disposed on the wafer along the sidewalls and / or bottom of holes, vias, or trenches, undersides of ledges or features, and / or on the top surfaces of features. In some such embodiments, isotropic thermal etching, including thermal ALE, is advantageous because it can perform omnidirectional, non-line-of-sight etching to reach high aspect ratio areas and areas that cannot be seen, such as under ledges or overhangs.

[0046] The chalcogenide may be any of those listed herein. In some implementations, the chalcogenide may be a phase change material, such as a germanium (Ge) antimony (Sb) tellurium (Te) (collectively "GST" or "GeSbTe") material. This may also include n-doped GeSbTe compounds (N-GST), Sb2Te, and Sb2Te doped with Ag and In (AIST). As discussed above, phase change materials are advantageous for use in forming memory devices, for example, because the phase of the metal chalcogenide determines the bit state. In some embodiments, the chalcogenide may include those that do not change phase, such as Ovonic Threshold Switching (OTS) materials. Ovonic Threshold Switching (OTS) materials may include, for example, compounds containing germanium, arsenic, and selenium (GeAsSe), or compounds containing germanium, antimony, selenium, and nitrogen (GeSb,Se,N).

[0047] In block 103, the wafer is heated to a first temperature, which may be considered any specific temperature or range of temperatures as described herein. In some embodiments, the first temperature may be, for example, between about 20° C. and about 500° C., between about 20° C. and about 150° C., between about 20° C. and about 80° C., between about 20° C. and about 100° C., between about 100° C. and about 450° C., between about 100° C. and about 400° C., between about 150° C. and about 400° C., between about 200° C. and about 600° C., between about 200° C. and about 500° C., between about 200° C. and about 350° C., or between about 350° C. and about 500° C. As discussed in more detail below, the wafer may be maintained at the first temperature during all or substantially all (e.g., at least 80%, 90%, or 95%) of the etching, modification, and / or removal operations.

[0048] In block 105, a chalcogenide layer on the wafer is etched by flowing a first species comprising a fluoride or chloride over the wafer to modify the surface of the chalcogenide layer to produce a fluorinated or chlorinated chalcogenide, and by flowing a second species comprising a compound having a central atom that is aluminum, boron, silicon, or germanium, and at least one chlorine, to remove the fluorinated or chlorinated chalcogenide layer. Some embodiments may include separate modification and removal operations, which in some instances may be separated by a purge operation. These embodiments may be considered self-limiting etches. Some other embodiments may include at least partially overlapping modification and removal operations, which in some embodiments may be performed by flowing a first species (i.e., modification molecules) and a second species (i.e., removal molecules) over the wafer in parallel.

[0049] The fluoride-bearing first species may include one or more of the following non-limiting examples: hydrogen fluoride such as HF, sulfur fluoride such as sulfur tetrafluoride, sulfur hexafluoride, or sulfuryl fluoride (SO2F2), nitrogen fluoride such as nitrogen trifluoride, and xenon fluoride such as xenon difluoride. The chlorine-bearing first species may include one or more of the following non-limiting examples: hydrogen chloride such as HCI, sulfur chloride such as sulfur dichloride, sulfur tetrachloride, or sulfuryl chloride (SO2Cl2), or nitrogen chloride such as trichloramine (NCl3). The use of these fluorine or chlorine species for surface modification of chalcogenide layers, as opposed to other halogens or molecules, results in unique reactive compounds that enable and allow total removal of the chalcogenide in the presence of removal molecules. This is because fluorine and chlorine bind very strongly to the surface, weakening the bond with the underlying layer. The first chemical species may be flowed over the wafer in vapor form, for example, as part of a process gas that may optionally include a carrier gas, such as nitrogen, argon, helium, or neon.

[0050] The second chemical species comprising a compound having a central atom of aluminum, boron, silicon, or germanium and at least one chlorine may include various compounds. In some embodiments, the compound may optionally include hydrogen, methyl, or ethyl groups. For example, the compound may have an aluminum central atom with chlorine and methyl groups, such as dimethylaluminum chloride (DMAC) or trimethylaluminum (TMA) chloride. In another example, the compound may have a boron center with multiple chlorides, such as boron trichloride (BCl3). In yet another example, the compound may have a silicon center with multiple chlorides, such as silicon tetrachloride (SiCl4).

[0051] The second species of compound reacts with the fluorinated or chlorinated chalcogenide, making the element volatile and desorbing from the wafer. For example, this exchange reaction is energetically favorable, so that the fluorinated or chlorinated chalcogenide can form a volatile compound with the compound, for example, through the transfer of chlorine or through combining to form volatile germanium, antimony, and tellurium compounds, including combinations of fluoride and chloride. The second species can also be flowed over the wafer in vapor form, for example, as part of a process gas that can optionally include a carrier gas, such as nitrogen, argon, helium, or neon.

[0052] In some embodiments, etching of block 105 may be performed under a variety of process conditions to enable such etching. In addition to the temperature ranges described above, in some embodiments, the substrate may be maintained during etching at a temperature between, for example, about 20° C. to about 500° C., about 20° C. to about 150° C., about 20° C. to about 80° C., about 20° C. to about 100° C., about 100° C. to about 450° C., about 100° C. to about 400° C., about 150° C. to about 400° C., about 200° C. to about 600° C., about 200° C. to about 500° C., about 200° C. to about 350° C., or 350° C. to about 500° C. The etch may also be performed while the process chamber is maintained at a pressure between about 20 milliTorr (mTorr) and 760 Torr (1 atm), including, for example, between about 20 mTorr and 600 mTorr, between about 30 mTorr and 500 mTorr, and between about 40 mTorr and 400 mTorr, as well as between about 3 Torr and 8 Torr, between about 4 Torr and 8 Torr, between 2 Torr and 10 Torr, and between 100 Torr and 760 Torr. As discussed in more detail below, in some embodiments, the etch of block 105 is performed at substantially constant process conditions (e.g., with small deviations, such as about 10% or 5% deviations from set conditions), while in other embodiments, one or more process conditions may be varied during the etch.

[0053] Some embodiments may etch chalcogenide materials using separate modification and removal operations. Figure 2 shows a second example process flow diagram for performing operations according to disclosed embodiments, where blocks 201 and 203 are the same as blocks 101 and 103 of Figure 1. In Figure 2, the modification and removal operations of block 105 are performed as separate operations in blocks 205A and 205B, respectively. This may be considered a self-limited etch, as well as ALE or thermal ALE.

[0054] Following block 203, the surface of the chalcogenide layer is modified in block 205A, i.e., this block represents a modification operation. The chalcogenide layer is modified as described above for block 105 of FIG. 1, except that block 205A now includes flowing a first process gas over the wafer, the first process gas including a first chemical species containing fluoride or chloride. As in block 105, flowing the first chemical species over the wafer modifies the surface of the chalcogenide layer to produce a fluorinated or chlorinated chalcogenide. The fluorinated or chlorinated chalcogenide is uniquely removable by exposure to and reaction with a second chemical species. The first chemical species in this first process gas may be any of those provided herein, including one or more of the following non-limiting examples: hydrogen fluoride such as HF, sulfur fluoride such as sulfur tetrafluoride, sulfur hexafluoride, or sulfuryl fluoride, nitrogen fluoride such as nitrogen trifluoride, xenon fluoride such as xenon difluoride, hydrogen chloride such as HCl, sulfur chloride such as sulfur dichloride, sulfur tetrachloride, or sulfuryl chloride, or nitrogen chloride such as trichloramine (NCl3). The first process gas may also be flowed in vapor form over the wafer and may optionally include a carrier gas such as, for example, nitrogen, argon, helium, or neon. The modification operation of block 205A may be stopped by stopping the flow of the first process gas to the wafer.

[0055] In some embodiments, activation energy may be provided to help the modifying molecules overcome the activation barrier and adsorb onto the wafer. This activation energy may comprise thermal energy, radical energy, and / or UV photons, which in some examples may include heating the wafer and / or generating plasma or photons. This adsorption of the modifying molecules onto the first material may be considered chemical adsorption, or "chemisorption", which is an energy-dependent (e.g., temperature-dependent) chemical reaction. In some thermal etching techniques, this chemisorption during the modification operation may only occur at a certain temperature range that allows the molecules in the material layer and the incoming modifying molecules to overcome the activation barrier and allow dissociation and chemical bonding between the molecules and adsorbates in the modifying molecules. Outside this temperature range, chemisorption may not occur or may occur at an undesirable (e.g., slow) rate.

[0056] Thus, some embodiments of block 205A do not use a plasma, but rather use only thermal activation energy to modify the surface layer of chalcogenide. A first process gas is flowed over the wafer maintained at a first temperature that provides activation energy, and the chalcogenide is modified by chemisorption to form a modified layer of chalcogenide. The first temperature can be any temperature or range of temperatures provided herein, such as between about 20°C and about 500°C, about 20°C and about 150°C, about 20°C and about 80°C, about 20°C and about 100°C, about 100°C and about 450°C, about 100°C and about 400°C, about 150°C and about 400°C, about 200°C and about 600°C, about 200°C and about 500°C, about 200°C and about 350°C, or about 350°C and about 500°C. Additionally, the wafer may be maintained at the first temperature for all or substantially all (e.g., at least 80%, 90%, or 95%) of the modification operation. The duration of the modification operation may be a duration for modification to occur for substantially all (e.g., at least 80%, 90%, or 95%) of the desired exposed molecules on the substrate. This may range, for example, from about 0.5 seconds to about 600 seconds, from about 0.5 seconds to about 400 seconds, from about 0.5 seconds to about 300 seconds, from about 0.5 seconds to about 10 seconds, from about 0.5 seconds to about 5 seconds, from about 1 second to about 5 seconds, or from about 5 seconds to about 300 seconds.

[0057] In some implementations, ion energy, such as from a plasma, may be used to facilitate the modification operation of block 205A. In some examples, a plasma may be ignited and fluorine or chlorine may react with the wafer or adsorb onto the surface of the wafer. The species generated from the plasma may be generated directly by forming a plasma in a processing chamber that contains the wafer, or may be generated remotely in a processing chamber that does not contain the wafer and delivered into the processing chamber that contains the wafer.

[0058] After the modification operation of block 205A, the modified chalcogenide, i.e., fluorinated or chlorinated chalcogenide, is removed from the wafer in block 205B. This removal is performed as described above for block 105 of FIG. 1, except that block 205B now includes flowing a second process gas over the wafer, the second species including a compound having a central atom that is aluminum, boron, silicon, or germanium and at least one chlorine. As in block 105, the second species reacts with the fluorinated or chlorinated chalcogenide and desorbs and thus removes the component from the wafer. The second species in the second process gas may be any of those provided herein, such as DMAC, TMA, or BCl3. The second process gas may also include a carrier gas, such as nitrogen, argon, helium, or neon. The removal operation of block 205B may be stopped by stopping the flow of the second process gas to the wafer.

[0059] In desorption, a particular temperature may allow the activation barrier of the modified molecules to be overcome, thereby allowing the release of the modified layer from the wafer. In some instances, the temperature ranges in which chemisorption and desorption occur do not overlap, while in other instances, they may overlap partially or completely. Thus, to remove molecules from a wafer using chemisorption and desorption, in some embodiments, the wafer may be maintained at the same or substantially the same temperature (e.g., within 10% or 5% of each other) during the removal and modification operations. To remove molecules from a wafer using chemisorption and desorption occurring at different temperature regimes, the modification operation of block 205A may occur at a first temperature range, and the removal operation of block 205B may occur at a second, different temperature range that may be higher or lower than the first temperature. Some such embodiments may perform multiple cycles by maintaining the wafer at the same or substantially the same temperature during the removal and modification operations to remove multiple layers of material, while other embodiments may repeatedly heat and cool the wafer between two temperature regimes for chemisorption and desorption.

[0060] In some embodiments using different temperature regimes, the temperature of the wafer may be brought to a second temperature during or before block 205B that is different from the first temperature at which the wafer is maintained during the modification operation of block 205A. In some other embodiments, the second temperature is the same or substantially the same (e.g., within 10% or 5% of each other) as the first temperature. This second temperature may be a temperature at which desorption occurs in one or more modified surface layers. In some embodiments, the second temperature may be higher than the first temperature, and in these embodiments, block 205B may include heating the wafer from the first temperature to the second temperature. In some other embodiments, the second temperature may be lower than the first temperature, and in these embodiments, the wafer may be actively cooled from the first temperature to the second temperature.

[0061] The wafer may be heated using radiative heating, convective heating, solid-to-solid heat transfer, or plasma. In addition, the top, bottom, or both of the wafer may be heated. In some embodiments, the heating of the wafer may also occur nonlinearly, as discussed further below. Also, as described below, the wafer may be actively cooled in various ways. In some examples, the wafer may be heated to two different temperatures by placing the wafer on two separate substrate supports, such as heated pedestals, that are maintained at different temperatures. Thus, the wafer may be heated to two different temperatures by being transferred between and placed on these two different substrate supports.

[0062] In block 205B, the one or more modified layers may be removed while the wafer is maintained at the second temperature, in some embodiments, the second temperature alone may allow and cause the modified molecules to desorb from the wafer, thereby removing the modified molecules from the wafer.

[0063] In some embodiments, the second temperature may be, for example, between about 20°C and about 500°C, about 20°C and about 150°C, about 20°C and about 80°C, about 20°C and about 100°C, about 100°C and about 450°C, about 100°C and about 400°C, about 150°C and about 400°C, about 200°C and about 600°C, about 200°C and about 500°C, about 200°C and about 350°C, or about 350°C and about 500°C. In addition, the wafer may be maintained at that temperature for all or substantially all (e.g., at least 80%, 90%, or 95%) of the removal operation. The duration of the removal operation may be the duration for desorption to occur for substantially all (e.g., at least 80%, 90%, or 95%) of the desired molecules on the wafer. This may be in the range of, for example, about 0.5 seconds to about 600 seconds, about 0.5 seconds to about 400 seconds, about 0.5 seconds to about 300 seconds, about 0.5 to about 10 seconds, about 0.5 seconds to about 5 seconds, about 1 second to about 5 seconds, or about 5 seconds to about 300 seconds.

[0064] The execution of blocks 205A and 205B may be considered a single thermal ALE cycle. In some embodiments, multiple cycles may be performed and blocks 205A and 205B may be repeated to remove monolayers, submonolayers, and multilayers of chalcogenide. Some etch rates may be lower than the lattice constant of the material being etched, so in some embodiments, only a portion of a monolayer is removed in one cycle. This may include, for example, performing about 1 to about 1,000 cycles, about 1 to about 500 cycles, about 1 to about 100 cycles, about 1 to about 30 cycles, or about 1 to about 20 cycles. Any suitable number of ALE cycles may be included to etch a desired amount of chalcogenide film. In some embodiments, the ALE cycles are performed to etch about 1 angstrom (Å) to about 50 Å of the layer surface on the wafer. In some embodiments, the ALE cycle etches between about 2 Å and about 50 Å of the surface of the wafer layer. In some embodiments, each ALE cycle may etch at least about 0.1 Å, 0.5 Å, 1 Å, 2 Å, or 3 Å. As further shown in FIG. 2, blocks 205A and 205B, and in some implementations, the optional purge of block 207, may be repeated for N ALE or etch cycles. Once decision step 209 determines that N ALE cycles have been performed, the etch may end and thus be complete.

[0065] In some operations, an optional purge operation in block 207 may be performed after the modification operation in block 205A and before the removal operation in block 205B. In the purge operation, non-surface-bound active modification molecules, such as fluorine or chlorine species, and / or other residues or particulates may be removed from the process chamber, chamber walls, chamber gas volume, and / or substrate. This may be performed by removing active species or other elements by purging and / or evacuating the process chamber without removing the adsorbed layer. Species generated in the plasma may be removed by stopping the plasma and allowing the remaining species to decay, optionally combined with purging and / or evacuation of the chamber. Purging may be performed using any inert gas, such as N2, Ar, Ne, He, and combinations thereof. Purging may also be performed after any operation, block, or step provided herein, including after the modification operation, after the removal operation, or both. Purging is optional, so some embodiments may not include any purge.

[0066] In some embodiments, the modification and removal operations of blocks 205A and 205B have different processing conditions, such as duration, temperature, and pressure. In some embodiments, blocks 205A and 205B may be performed for substantially the same time (e.g., within 10% or 5% of each other), while in other embodiments, they may be performed for different times. For example, block 205A may be performed for a shorter or longer time than block 205B. The various durations of each block may range, for example, from about 0.5 seconds to about 600 seconds, from about 0.5 seconds to about 400 seconds, from about 0.5 seconds to about 300 seconds, from about 0.5 seconds to about 10 seconds, from about 0.5 seconds to about 5 seconds, from about 1 second to about 5 seconds, or from about 5 seconds to about 300 seconds.

[0067] In some embodiments, the modification operation of block 205A and the removal operation of block 205B may be performed at different pressures. For example, the modification operation of block 205A may be performed at a first pressure or a first pressure range, and the removal operation of block 205B may be performed at a second pressure or a second pressure range that is different from the modification operation of block 205A. Although not shown in FIG. 2, some embodiments may include a pressure adjustment operation that changes the pressure from a first pressure to a second pressure. This pressure adjustment may occur, for example, between blocks 205A and 205B. Similar to above, the first and second pressures may be, for example, between about 20 milliTorr (mTorr) and 760 Torr (1 atm), including between about 20 mTorr and 600 mTorr, between about 30 mTorr and 500 mTorr, and between about 40 mTorr and 400 mTorr, as well as between about 3 Torr and 8 Torr, between about 4 Torr and 8 Torr, between 2 Torr and 10 Torr, and between 100 Torr and 760 Torr. In some other embodiments, both the modification operation of block 205A and the removal operation of block 205B may be performed at substantially the same pressure (e.g., within 10% or 5% of each other), such as any pressure or pressure range described herein.

[0068] Some implementations of the described etches are further illustrated with FIG. 3. FIG. 3 shows a schematic example of an atomic layer etch according to disclosed embodiments. FIGS. 300a-300e show an ALE cycle. At 300a, a wafer having one or more layers of chalcogenide is provided. At 300b, the surface of the chalcogenide is modified. At 300c, preparation for the next operation is performed, which may include flowing a second process gas or purging the chamber. At 300d, the wafer is exposed to a removal molecule that reacts with the modified chalcogenide layer and desorbs and thus removes the modified chalcogenide layer from the wafer. At 300e, the desired material is removed.

[0069] In Figures 302a-302e, a monolayer of chalcogenide material is etched from a wafer. In 302a, a wafer is provided, the wafer having one or more layers of chalcogenide. Each chalcogenide molecule is represented by an unshaded circle. The top layer of chalcogenide may be considered a surface layer 306. In 302b, a first process gas having fluoride or chloride containing modifying molecules 308 (solid circles, some of which are identified by identifier 308) is introduced to the wafer to modify the chalcogenide surface layer 306 to form a fluorinated or chlorinated chalcogenide. In the conceptual diagram of 302b, some of the modifying molecules 308 adsorb onto the chalcogenide molecules 304 of the surface layer 306 to produce a modified surface layer 310 including modifications 312 (one modified molecule 312 is identified within the dashed oval 302b). As mentioned above, the modifying molecules 308 may be fluorine-containing species, such as hydrogen fluoride, or chloride-containing species, such as hydrogen chloride. In addition, the chalcogenide may be any of the materials provided herein, such as GeSbTe or OTS materials. In some thermal ALE techniques, FIG. 302b may occur while the wafer is maintained at a first temperature as described above, for example, that allows for chemisorption of the modifying molecules onto the surface of the chalcogenide material. In some other examples, the modifying operation may be plasma-assisted.

[0070] In FIG. 302c, after the modified molecules 312 and modified surface layer 310 are produced in 302b, the process gas may optionally be purged from the first chamber, as described above and represented in block 207 of FIG. 2.

[0071] In FIG. 302d, the removal molecule 314 is introduced into the process chamber, which in some embodiments may occur by flowing a second process gas having a second species, i.e., the removal molecule 314, over the wafer. The second species may include a compound having a central atom that is aluminum, boron, silicon, or germanium, and at least one chlorine, such as DMAC. The schematic diagram 302d further illustrates that the removal molecule 314, shown as a shaded diamond, reacts with the fluorinated or chlorinated chalcogenide, i.e., modified molecule 312, thereby desorbing and thus removing the chalcogenide 304, as well as the fluoride 308 or chloride 308, from the wafer. In some embodiments, the reaction between the removal molecule 314 and the modified molecule 312 desorbs the modified molecule 308 from the wafer and forms another compound 316 with the removal molecule and the chalcogenide. Another compound 316, illustrated by the combination of the unshaded circles for the chalcogenides 304 and the shaded diamonds for the removal molecules 314, desorbs from the wafer. In some other embodiments, not shown, the removal molecules and the modified molecules together form another compound that desorbs from the wafer.

[0072] In some thermal ALE embodiments, the removal operation may be performed at a second temperature at which desorption of the modified molecules 312 of the modified surface layer 310 from the wafer occurs. In some of these removal operations, a plasma may not be utilized. In some embodiments, the second temperature is the same as or substantially the same as the first temperature (e.g., within 10% or 5% of each other). In other embodiments, the first and second temperatures may be different from each other, and in these embodiments, the temperature may be changed from the first temperature to the second temperature by heating or cooling the substrate. In some examples, the temperature of one or more operations may be ramped up.

[0073] In 302e, the modified molecules 312, and therefore the modified surface layer 310, have been removed from the wafer.

[0074] As mentioned above, some embodiments may have at least partially overlapping flows of the modifying and removing species, such as overlapping flows of HF and BCl3. FIG. 4 shows a third example process flow diagram for operating in accordance with disclosed embodiments, where blocks 401 and 403 are the same as blocks 101 and 103 of FIG. 1. In FIG. 4, at least a portion of the modifying and removing operations of block 105 are performed simultaneously, as seen from blocks 405A and 405B, which are performed simultaneously. The modifying operation of block 405A and the removing operation of block 405B may be the same as those described above in this specification, except for the differences noted above, including the timing and overlap of flowing the first and second species onto the wafer. For example, the first species of block 405A comprises a fluoride or chloride that is flowed onto the surface of the chalcogenide layer to modify the chalcogenide surface to produce a modified surface layer, such as a fluorinated or chlorinated chalcogenide. Additionally, the second species of block 405B includes compounds having a central atom of aluminum, boron, silicon, or germanium and at least one chlorine that react with the modified surface layer of chalcogenide and remove it from the wafer. Other process conditions and embodiments are described below. Additionally, each process gas may include a carrier gas as described above.

[0075] In some embodiments, the modifying operation of block 405A and the removing operation of block 405B overlap for only a portion of the etch. In other embodiments, these blocks 405A and 405B overlap for substantially all of the etch (e.g., within 10% or 5% of each other). Some of these implementations have the first and second species in the same process gas flowed over the wafer, while some other implementations have the species in separate process gases flowed in parallel or simultaneously over the wafer.

[0076] 5A-5C show example gas flow sequences according to various embodiments. In FIG. 5A, a first process gas having a first species and a second process gas having a second species are flowed over the wafer without any overlap, which may be considered as the gas flows described with respect to FIGS. 2 and 3. Here, the first process gas is flowed from time t1 to time t2 and then stopped. This may be considered as the modification operation of block 205A and schematic diagram 302b. In some examples, an optional purge operation may be performed between time t2 and time t3, as in optional block 207 and schematic diagram 302c. At time t3, the second process gas is flowed over the wafer until time t4, when it is stopped. This period may be considered as the removal operation of block 205B and schematic diagram 302d.

[0077] In FIG. 5B, the first and second process gases overlap only for a portion of the etch. At time t1, the first process gas is flowed over the wafer while the second process gas is not flowed over the wafer until time t2. This may also be considered the modification operation of block 205A and schematic diagram 302b. At time t2, the second process gas is flowed over the wafer while the first process gas is simultaneously flowed over the wafer. From time t2 to time t3, both the first and second process gases are flowed over the wafer. This may be considered a period of overlap or parallel flow of the first and second process gases. Referring again to FIG. 4, this overlap period may be considered the simultaneous execution of blocks 405A and 405B. At time t3 in FIG. 5B, the first process gas flow is stopped and the second process gas continues to flow until it is stopped at time t4. This time may also be considered the removal operation of block 205B and schematic diagram 302d.

[0078] In some embodiments, the temperature of the wafer may be adjusted during the etch shown in FIG. 5B. For example, the wafer may be maintained at a first temperature from time t1 to t2, adjusted to a second temperature at time t2, and maintained at the second temperature until time t3 or t4. In some such implementations, the temperature may be adjusted to a third temperature from time t3 to time t4. In some other embodiments, the temperature may be held at the first temperature from time t1 to time t3, and then adjusted to the second temperature. This may be considered a temperature ramp-up or ramp-down sequence in some embodiments, with a second temperature higher or lower than the first temperature, and a third temperature higher or lower than the second temperature, if applicable. These temperatures may be any provided herein. Adjusting the temperature during any of the etches provided herein may allow for additional control and utilization of chemisorption and desorption. In some other embodiments, the wafer may be maintained at a substantially constant temperature (e.g., within about 10% or 5% of the set temperature) during the etch of FIG. 5B.

[0079] Similarly, the temperature of the wafer may be increased or decreased during the modification, removal, or both. For example, referring to FIG. 5A, the wafer temperature may be increased from a first temperature to a higher second temperature or decreased from the first temperature to a lower third temperature during the modification operation between times t1 and t2. Alternatively, or in addition, the wafer temperature may be increased or decreased during the removal operation between times t3 and t4.

[0080] Alternatively or additionally, the chamber pressure may be adjusted during the etch of FIG. 5B. For example, the chamber may be maintained at a first pressure from time t1 to t2, adjusted to a second pressure at time t2, and maintained at the second pressure until time t3 or t4. In some such implementations, the pressure may be adjusted to a third pressure from time t3 to time t4. In some other embodiments, the pressure may be held at the first pressure from time t1 to time t3, and then adjusted to the second pressure. This may be considered a pressure ramp-up or ramp-down sequence in some embodiments, with a second pressure higher or lower than the first pressure, and a third pressure higher or lower than the second pressure, if applicable. These pressures may be any of those provided herein. Adjusting the pressure during any of the etches provided herein may allow for additional control and utilization of chemisorption and desorption, as well as reducing the buildup of unwanted residues in the chamber. In some other embodiments, the pressure may be substantially constant (eg, within about 10% or 5% of the set pressure) during the etch of FIG. 5B.

[0081] Similarly, the chamber pressure may be increased or decreased during the modification, removal, or both. For example, referring to FIG. 5A, the chamber pressure may be increased from a first pressure to a higher second pressure or decreased from the first pressure to a lower second pressure during the modification operation between time t1 and time t2. Alternatively, or in addition, the chamber pressure may be increased or decreased during the removal operation between time t3 and time t4.

[0082] In FIG. 5C, the first and second species are flowed in parallel or simultaneously over the wafer during substantially all of the etch. Due to design, implementation, tolerances, and operational imperfections in the gas delivery system, the gases may be intended to be flowed in parallel at exactly the same time, but in reality, this may not be the case. Here, in FIG. 5C, the first and second species are flowed simultaneously over the wafer from time t1 to t2, and then both are stopped. In some implementations, the first and second species may be in the same process gas that is flowed over the wafer, along with an optional carrier gas. In some other implementations, the first species may be part of a first process gas and the second species may be part of a separate second process gas, as described above, and both of these first and second process gases are flowed in parallel over the wafer from time t1 to time t2.

[0083] In some embodiments, it may be advantageous to keep the first and second species separated until they enter the processing chamber. This may avoid cross-reactions between the first and second species. Thus, the first and second species may be flowed into the chamber through separate lines and separate ports, such as through a dual plenum showerhead or through separate nozzles. This may allow the two chemicals to meet only on the wafer surface.

[0084] In some embodiments, the temperature of the wafer may be adjusted during the etch shown in FIG. 5C and FIG. 4. For example, the wafer may be maintained at a first temperature from time t1 to ta, adjusted to a second temperature at time ta, and maintained at the second temperature until time t2. In some such implementations, the temperature may be adjusted to a third temperature or other temperature throughout the etch. This may be considered in some embodiments as a temperature ramp-up or ramp-down sequence, for example, with a second temperature higher or lower than the first temperature, and a third temperature higher or lower than the second temperature, if applicable. These temperatures may be any provided herein. In some other embodiments, the wafer may be maintained at a substantially constant temperature during the etch of FIG. 5C.

[0085] Alternatively, or in addition, the chamber pressure may be adjusted during the etch of FIG. 5C. For example, the chamber may be maintained at a first pressure from time t1 to t2, adjusted to a second pressure at time t2, and maintained at the second pressure until time t3. This may be considered, in some embodiments, a pressure ramp-up or ramp-down sequence with a second pressure that is higher or lower than the first pressure. These pressures may be any of those provided herein. In some other embodiments, the pressure may be substantially constant during the etch of FIG. 5C.

[0086] Modification and removal operations using overlapping flows are further illustrated in FIG. 6. FIG. 6 shows an example schematic diagram of an etching process according to disclosed embodiments. FIG. 602a corresponds to FIG. 302a described above, where a wafer is provided and has one or more layers of chalcogenide. Each chalcogenide molecule is represented by an unshaded circle. The top layer of chalcogenide may be considered a surface layer 606. In 602b, a first species, namely, modification molecules 608 (solid circles, some of which are identified by identifier 608), and a second species, namely, removal molecules 614, are introduced into the process chamber simultaneously. This may represent parallel flows or simultaneous flows as described above, such as with respect to FIGS. 4, 5B, and 5C.

[0087] Here, some of the modifying molecules 608 adsorb onto the chalcogenide molecules 604 of the surface layer 606 to produce a modified surface layer 610 including modifications 612 (one modified molecule 612 is identified within the dashed oval 602b). As described above, the modifying molecules 608 may include fluorine, such as hydrogen fluoride, or chloride, such as hydrogen chloride. Removal molecules 614 are also flowed in parallel over the wafer, and the second species may include compounds having a central atom that is aluminum, boron, silicon, or germanium, and at least one chlorine, as described above. These removal molecules 614 react with the modified molecules 612, thereby desorbing and thus removing the chalcogenide from the wafer. In some embodiments, the first and second species may be flowed separately into the processing chamber through separate gas lines and / or separate ports (e.g., separate injection nozzles or ports in the same showerhead).

[0088] In some embodiments, an additional layer of chalcogenide may be etched when the first and second species, e.g., modifying and removing molecules, are flowed onto the wafer. For example, diagram 602b shows that the second layer of chalcogenide 622 may be similarly modified to form modified molecule 612a, which may also be removed from the wafer when exposed to and reacted with removal molecule 614.

[0089] FIG. 602b may be considered to be illustrative of an etch during which the first and second species are simultaneously flowed onto the wafer. As discussed above with respect to FIG. 5B, some modification may occur prior to this FIG. 602b, which may be represented in FIG. 302b. Additionally, in some examples such as FIG. 5B, after this parallel flow of FIG. 602b, additional removal may occur without any homogenous modification, which may be represented by FIG. 302d. In some such embodiments, the etch of FIG. 5B may be illustrated by the sequence of FIG. 302b, 602b, and 302d.

[0090] Referring again to FIG. 4, the combined execution of blocks 405A and 405B for a duration may be considered a single ALE cycle. In some implementations, blocks 405A and 405B may be performed multiple cycles, stopped, and then repeated to remove multiple layers of chalcogenide. This may include, for example, performing about 1 to about 1,000 cycles, about 1 to about 500 cycles, about 1 to about 100 cycles, about 1 cycle to about 30 cycles, or about 1 to about 20 cycles. Any suitable number of ALE cycles may be included to etch a desired amount of chalcogenide film. In some embodiments, the ALE cycles are performed to etch about 1 angstrom (Å) to about 50 Å of the layer surface on the wafer. In some embodiments, the ALE cycle etches between about 2 Å to about 50 Å of the layer surface on the wafer. In some embodiments, each ALE cycle may etch at least about 0.1 Å, 0.5 Å, 1 Å, 2 Å, or 3 Å.

[0091] In some of the embodiments provided herein, the flow rate of the first process gas may remain constant and the flow rate of the second process gas may remain constant. In some other embodiments, the first and second process gases may be flowed at the same or different flow rates. In some other embodiments, it may be advantageous to vary the flow rates of the first and / or second process gases. This may include, for example, increasing the flow rate of the second process gas during the removal operation to provide more removal molecules as the removal operation progresses. Some example flow rates include between about 50 sccm and 1000 sccm.

[0092] As discussed above, the thermal etching provided herein may be used for a variety of purposes. In some embodiments, the thermal etching may be used for cleaning operations of the chalcogenide after the chalcogenide has been etched using an RIE etch or other ion-assisted etch. Additionally or alternatively, some embodiments may perform a thermal etch to etch bulk chalcogenides. In some such examples, the thermal etch may be used in place of an RIE etch or other ion-assisted etch.

[0093] We now discuss the aspect of a thermal etch used as a cleaning operation after another etching process, such as an RIE or other ion-assisted etch, has been performed on the chalcogenide. FIG. 7 shows an example process flow for etching a chalcogenide. In this example, FIG. 728a shows that a chalcogenide 732 may be deposited as one or more bulk layers on a wafer 734, and a hard mask 730 may be deposited on the chalcogenide 732. An etching process, such as an RIE etch or other plasma-assisted etch, may be performed to remove a portion of the bulk layer (e.g., areas extending beyond the hard mask 730 and identified by 731) and form the desired surface shape of the chalcogenide. Here, in FIG. 728b, the chalcogenide 732 is etched into columns. However, as discussed above, this RIE or plasma-assisted etch may undesirably damage the chalcogenide and / or oxidize the exposed chalcogenide 732, effects illustrated by damaged and / or oxidized sidewalls 733.

[0094] As mentioned above, a cleaning operation utilizing a thermal etch such as thermal ALE may be performed on the chalcogenide after this RIE or other ion-assisted etch. FIG. 728c shows the chalcogenide 732 after the thermal etch cleaning operation has been performed. As shown, at least a portion of the damaged and / or oxidized sidewalls 733 of the chalcogenide 732 have been removed. This is represented by the chalcogenide 732 having straight sidewalls 733 with a width 735B that is smaller than the width 735B in FIG. 728b. In some embodiments using thermal ALE, the amount of chalcogenide 732 removed can be controlled on a cycle-by-cycle basis, thus removing the chalcogenide at a monolayer or sub-monolayer level. Thus, one or more cycles of thermal ALE can be performed to remove the desired amount of chalcogenide. In some embodiments, some processes may have a tolerance for allowing damaged and / or oxidized chalcogenide to remain on the wafer, so that only a portion of the damaged and / or oxidized portions of the chalcogenide may be removed by thermal etching. This may improve throughput by performing less etching on the wafer, thus reducing wafer processing time. In some other implementations, substantially all of the damaged and / or oxidized portions of the chalcogenide may be removed, as well as, in some instances, an additional layer of bulk chalcogenide.

[0095] Some implementations may further include depositing an encapsulating layer of material after the thermal etch is performed on the chalcogenide. In some embodiments, as shown in FIG. 728d of FIG. 7, an encapsulating layer 736 of material may be deposited on the chalcogenide 732 and the mask 730 after the thermal etch cleaning operation is performed. The encapsulating material may be deposited using a variety of techniques, such as chemical vapor deposition ("CVD"), plasma-enhanced CVD ("PECVD"), atomic layer deposition ("ALD"), low-pressure CVD, ultra-high CVD, physical vapor deposition ("PVD"), and conformal film deposition ("CFD"). Some CVD processes may deposit a film on a wafer surface by flowing one or more gas reactants into a reactor that form a film precursor and by-products. The precursors are transported to the wafer surface where the precursors are adsorbed by the wafer, diffuse into the wafer, and are deposited on the wafer by chemical reactions, including by plasma generation in PECVD. Some other deposition processes involve multiple film deposition cycles, each cycle producing a "distinct" film thickness. ALD is one such film deposition technique, but any technique that deposits thin layers of films and is used in a repeated, sequential manner may be considered to involve multiple deposition cycles.

[0096] As device and feature sizes continue to shrink in the semiconductor industry, and as 3D device structures become more common in integrated circuit (IC) design, the ability to deposit conformal thin films (films of material that have uniform thickness relative to the shape of the underlying structure, even if non-planar) continues to grow in importance. ALD is a film formation technique well suited for depositing conformal films due to the fact that a single ALD cycle deposits only a single thin film of material. The thickness is limited by the amount of one or more film precursor reactants that can adsorb to the substrate surface prior to the film-forming chemical reaction itself (i.e., the formation of an adsorption-limiting layer). Multiple "ALD cycles" may then be used to build up a film of the desired thickness, with each layer being thin and conformal so that the resulting film substantially conforms to the shape of the underlying device structure. In certain embodiments, each ALD cycle includes the following steps: (1) exposure of the substrate surface to a first precursor; (2) purging of the reaction chamber in which the substrate is located, typically activating a reaction on the substrate surface with a plasma and / or a second precursor, and purging of the reaction chamber in which the substrate is located.

[0097] The deposition of a thin film by thermal ALD can include heating a substrate to an elevated temperature, exposing the substrate to a precursor that adsorbs on the surface of the substrate, and exposing the substrate to one or more gaseous reactants to promote a surface reaction between the one or more gaseous reactants and the precursor, thus forming a thin film by thermal ALD.Specifically, the deposition of a first silicon oxide film by thermal ALD can include heating a substrate to an elevated temperature, exposing the substrate to a silicon-containing precursor that adsorbs on the surface of the substrate, and exposing the substrate to an oxygen-containing reactant to promote a reaction between the oxygen-containing reactant and the silicon-containing precursor, thus forming a first silicon oxide film by thermal ALD.

[0098] The duration of each ALD cycle may typically be less than 25 seconds, or less than 10 seconds, or less than 5 seconds. One or more plasma exposure steps of an ALD cycle may be of short duration, such as, for example, 1 second or less. The plasma may have other durations longer than 1 second, such as, for example, 2 seconds, 5 seconds, or 10 seconds.

[0099] 8 shows a flow chart of an example sequence of operations for forming a film of material on a substrate by ALD processing. As can be seen in FIG. 8, item 1 above corresponds to block 858, item 2 above corresponds to block 860, item 3 above corresponds to block 862, and item 4 above corresponds to block 864. The four blocks are cycled N times, after which the process is stopped.

[0100] In some examples, the encapsulation material may include silicon, such as silicon nitride or silicon oxide. In some implementations, the silicon-containing precursor includes a silane, such as an aminosilane. An aminosilane includes at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes include bis(tert-butylamino)silane (BTBAS), N-(diethylaminosilyl)-N-ethylethanamine (SAM-24), tris(dimethylamino)silane (3DMAS), and tetrakis(dimethylamino)silane (4DMAS). In some embodiments, other materials may be deposited for the encapsulation layer. For example, the encapsulation layer described herein may include a nitride or carbide of a group 4 element, either of which may be doped (such as with oxygen) or undoped. In various embodiments, the encapsulation layer may be any of the following chemistries or any combination thereof: silicon nitride (SiN), silicon carbide (SiC), oxygen doped silicon oxide (SiCO), germanium nitride (GeN), germanium carbide (GeC), and oxygen doped germanium carbide (GeCO).

[0101] In some embodiments, operation 862 of FIG. 8 may include flowing a reactant, such as an oxygen-containing reactant, which may include an oxidizer gas, such as oxygen (O2), ozone (O3), hydrogen peroxide (H2O2), water (H2O), or combinations thereof. In some embodiments, exposing the substrate to the oxygen-containing reactant includes flowing hydrogen and oxygen to the substrate to react in situ in the plasma processing chamber to cause an exothermic reaction. In some embodiments, it is believed that water may be generated in situ by the reaction between hydrogen and oxygen. Water vapor may not be flowed into the plasma processing chamber as the initiating reactant and may or may not be generated in situ in the plasma processing chamber. As used herein, flowing "hydrogen" refers to flowing molecular hydrogen and flowing "oxygen" refers to flowing molecular oxygen. Hydrogen and oxygen may be flowed simultaneously toward the substrate in the plasma processing chamber. The exothermic reaction involving hydrogen and oxygen may release energy to promote a surface reaction with the adsorbed silicon-containing precursor to form a first silicon oxide film.

[0102] During the ALD cycle of FIG. 8, the wafer may be exposed to an oxygen-containing reactant and exposed to an elevated temperature for a suitable duration during the cycle, such as during the thermal oxidation of operation 862. The duration of operation 862 may be between about 0.1 seconds and about 6 seconds, between about 0.2 seconds and about 4 seconds, or between about 0.5 seconds and about 3 seconds. The substrate may be exposed to the oxygen-containing reactant and simultaneously operated at an elevated temperature. In some embodiments, the elevated temperature may be between about 150° C. and about 750° C., between about 150° C. and about 500° C., between about 500° C. and about 650° C., or between about 550° C. and about 650° C. The substrate may be exposed to an increased chamber pressure, such as about 7 Torr or more, about 10 Torr or more, about 12 Torr or more, or between about 10 Torr and about 20 Torr, during one or more of these operations in FIG. 8.

[0103] In some ALD processes using plasma to induce reactions on adsorbed precursors, the chamber pressure in the plasma processing chamber may be relatively low, between about 10 mTorr and about 200 mTorr, or relatively high, between about 1 Torr and about 7 Torr. An RF field is applied to the plasma processing chamber to generate ions and radicals of the oxygen-containing reactant. In various embodiments, the RF frequency used to generate the plasma may be at least about 13.56 MHz, at least about 27 MHz, at least about 40 MHz, or at least about 60 MHz, although other frequencies may be used. In some embodiments, the RF power may be several hundred watts, for example, about 500 W or less, about 400 W or less, or about 300 W or less, although it will be understood that other RF powers may be provided depending on the substrate area. In some embodiments, the duration of the plasma exposure phase may be between about 0.1 seconds and about 120 seconds, or between about 1 second and about 60 seconds.

[0104] We now discuss cleaning operations after RIE etching or other ion-assisted etching, as well as additional etching techniques for chalcogenides that may be used to etch bulk chalcogenide materials. FIG. 9 illustrates a third example process flow diagram for performing operations according to disclosed embodiments. Blocks 901, 903, and 905 are the same as blocks 101, 103, and 105, respectively, in FIG. 1 described above. The operations of blocks 901 through 905 may be performed to etch one or more layers of bulk chalcogenide materials after or in place of an RIE etching or other ion-assisted etching. The etching of block 905 may be performed in any manner provided herein, including separate modification and removal operations separated by a purge operation, as the two shown in FIG. 2. Also, the etching of block 905 may represent a cleaning operation by thermal etching as described above. Here, in FIG. 9, after a thermal etch is performed on the wafer, an encapsulant material is deposited on the wafer in block 911. This encapsulation may be performed by any method provided herein, including by ALD, and the material may include silicon, such as silicon nitride or silicon oxide.

[0105] In some embodiments, the etching operations, including thermal etching and thermal ALE, may occur in one or more etching chambers, while the encapsulation deposition occurs in another processing chamber, such as a deposition chamber configured to deposit material on the wafer. Thus, as represented in optional block 913 of FIG. 9, the wafer may be transferred from one or more etching chambers to a deposition processing chamber. In some embodiments, the wafer may be transferred between chambers while the wafer and the chambers, including the destination chamber, are maintained at vacuum or low pressure, for example, between about 1 mTorr and about 10 Torr, such that the wafer is not exposed to atmospheric pressure during this transfer.

[0106] For example, one or more etch chambers and deposition chambers may be maintained at vacuum or other low pressure, and the wafer may be transferred from one or more etch chambers to the deposition chambers via one or more transfer chambers that are also maintained at vacuum or other low pressure. During this transfer, the wafer and etched chalcogenide are not exposed to atmospheric pressure. Transferring the wafer in this manner advantageously reduces the time that the etched chalcogenide is exposed to air, oxygen, or other environmental gases, thereby reducing or preventing unwanted oxidation of the chalcogenide. This transfer also advantageously increases the throughput of processed wafers by eliminating pump-down steps and additional transfers that occur when the wafer is transferred between vacuum and atmospheric pressure.

[0107] Wafer transport is further described with reference to FIG. 10. FIG. 10 illustrates a first exemplary processing apparatus according to disclosed embodiments. Additional features of the tool 1000 are discussed in more detail below, and various features of some of the described techniques are discussed here. The tool 1000 includes a first processing chamber 1002, a second processing chamber 1004, and a third processing chamber 1006. In some implementations, the first processing chamber 1002 is configured to perform an etching operation on the wafer, including etching of bulk chalcogenides, such as RIE or other ion-assisted etching. The second processing chamber 1004 is configured to perform thermal etching, including thermal ALE. The second processing chamber 1004 also includes multiple processing stations (four stations 1080A-D), each of which may process a wafer. The first and second processing chambers 1002 and 1004 may be considered etching chambers. The third processing chamber 1006 is configured to perform deposition on the wafer, and may be considered a deposition chamber. Additionally, the third processing chamber 1006 may include multiple processing stations (four stations 1082A-D), each of which may process a wafer. The second and third processing chambers 1004 and 1006 may be considered a multi-station processing chamber.

[0108] The tool 1000 also includes a wafer transport unit configured to transport one or more wafers within the tool 1000. For example, after a wafer is etched in the first processing chamber 1002, the wafer transport unit can transport the wafer from the first processing chamber 1002 to a second processing chamber 1004 where a thermal etch as described herein may be performed on the one or more wafers. Following the thermal etch in the second processing chamber 1004, the wafer transport unit can transport the one or more wafers from the second processing chamber 1004 to a third processing chamber 1006 where one or more layers of an encapsulating material may be deposited on the one or more wafers.

[0109] In the example illustrated in FIG. 10, the wafer transport unit includes a first robot arm unit 1008 in a first wafer transport module 1010 and a second robot arm unit 1012 in a second wafer transport module 1014. The first robot arm unit 1008 is configured to transport wafers between the first processing chamber 1002 and the second robot arm unit 1012. The second robot arm unit 1012 is configured to transport wafers between the first robot arm unit 1008, the second processing chamber 1004, and the third processing chamber 1006. In one embodiment, each of the robot arm units 1008 and 1012 may have one arm, and in another embodiment, each of the robot arm units may have two arms, each arm may have an end effector 1224 to grip a substrate for transport. An atmospheric transfer module (ATM) 1022, for example a front end robot 1020 in an equipment front end module (EFEM), may be used to transfer substrates from a cassette or front opening integrated pod (FOUP) to the airlock 1018.

[0110] The first and second wafer transfer modules may each be a vacuum transfer module (VTM). An airlock 1018 (also known as a loadlock or transfer module) is shown and may be individually optimized for carrying out various fabrication processes. The tool 1000 also includes a pressure unit 1016 configured to reduce the pressure of the tool 1000 to a vacuum or low pressure, for example, between about 1 mTorr and about 10 Torr, and to maintain the tool 1000 at this pressure. This includes maintaining the first, second, and third processing chambers 1002-1006, the first wafer transfer module 1010, and the second wafer transfer module 1012 at a vacuum or low pressure.

[0111] When the wafer is transferred throughout the tool, the wafer can be in a range of environments that are maintained at vacuum or low pressure. For example, when the wafer is transferred from the first processing chamber 1002, into the first wafer transfer module 1010, to the second wafer transfer module 1014, to the second processing chamber 1004, the wafer is exposed to and maintained at vacuum or low pressure and is therefore not exposed to atmospheric pressure. Similarly, when the wafer is transferred from the second processing module 1004, to the second wafer transfer module 1014, and to the third processing module 1006, the wafer is maintained at vacuum or low pressure and is not exposed to atmospheric pressure.

[0112] In a further example, a substrate is placed in one of the FOUPs 1024 and the front-end robot 1020 transfers the substrate from the FOUP 1024 to an aligner, thereby allowing the substrate to be properly centered before being etched or deposited on or otherwise processed. After being aligned, the substrate is moved into the airlock 1018 by the front-end robot 1020. The airlock module has the ability to match the environment between the ATM and the VTM, so that the substrate can be moved between the two pressure environments without damage. The substrate is moved by the first robot arm unit 1008 from the airlock module 1018 through the first wafer transfer module 1010 or the VTM 1010 into the first processing chamber 1002. To accomplish this substrate movement, the first robot arm unit 1008 uses an end effector on its respective arm.

[0113] In some embodiments using the tool 1000 of FIG. 10, an etching operation may be performed in two or more processing chambers. For example, an etching operation such as RIE or other ion-assisted etching may be performed in processing chamber 1002, while a thermal etch such as thermal ALE may be performed in a different processing chamber, such as a second processing chamber 1004. The use of two different etch processing chambers may allow different etching techniques to be used on the wafer. For example, a bulk chalcogenide etch may be performed in a first processing chamber 1002, and a thermal etch cleaning operation may be performed in a second processing chamber 1004.

[0114] In some embodiments, instead of using an RIE etch or other ion-assisted etch to remove the chalcogenide, a thermal etch may be used to etch the bulk chalcogenide. Techniques for thermal etching of the bulk chalcogenide may be the same as those described above, such as in FIGS. 1-6, 8, and 9, except that a cleaning operation may not be required because an RIE or ion-assisted etch is not performed. For example, referring again to FIG. 9, block 901 may include providing a wafer to a processing chamber configured for a thermal etch, such as a thermal ALE. Thereafter, blocks 903 and 905 may be performed to etch the bulk chalcogenide, which may include performing multiple thermal ALE cycles as described above and shown in FIGS. 1-6. Following the thermal etch of block 905, the wafer may be transferred to a deposition chamber in block 913, where an encapsulant material is deposited on the wafer in block 911.

[0115] To etch the bulk chalcogenide as well as to etch portions of the damaged and / or oxidized chalcogenide, some thermal etches provided herein may include multi-layer etching, such as etching multiple layers of chalcogenide simultaneously. This may include multiple layers of chalcogenide located in a stack of materials. For example, a wafer may have multiple trenches, holes, or vias, each of which has multiple layers of material and sidewalls with different surface topography. To form a variety of devices, chalcogenide materials may be deposited in these trenches, holes, or vias with the isotropic nature of the thermal etches described herein. Chalcogenide materials can be etched in a variety of structures.

[0116] Etching multiple layers of chalcogenide material is illustrated in FIG. 11, which shows yet another example process flow for etching chalcogenide layers. Here, a partial cross-sectional view of a feature 1152 of a wafer 1134 is shown, which may be, for example, a trench, hole, or via. Each of sidewalls 1150A and 1150B of feature 1152 includes multiple materials, such as metal 1154 (shown in cross-hatching) and dielectric 1156. A layer of chalcogenide material 1158 (shown in shading) is deposited within feature 1152 and on the surfaces of materials 1154 and 1156 of sidewalls 1150A and 1150B.

[0117] A thermal etch of the bulk chalcogenide material 1158 may be performed to remove multiple layers of chalcogenide material 1158, including simultaneously etching multiple layers of chalcogenide material 1158. Because the thermal etch is isotropic and non-directional, the thermal etch of the chalcogenide material 1158 may etch in areas, overhangs, recesses, and other shaped areas of the feature 1152. In FIG. 1128a, the thermal etch may remove multiple layers of chalcogenide 1158 in gaps 1164 of the feature 1152, which may include a layer of bulk, monolithic chalcogenide 1158. Once the chalcogenide 1158 is removed from the gaps 1164, the chalcogenide may exist as separate and separate portions of material in various areas of the feature. For example, in FIG. 1128a, areas 1160A, 1160B, and 1160C enclosed within the dotted rectangles each have a separate portion of chalcogenide 1158 therein. A directional etch, such as an RIE etch, is unable to etch the chalcogenide in these areas. However, thermal etching techniques can reach and simultaneously etch each layer of chalcogenide 1158 in these areas. In FIG. 1128b, the chalcogenide 1158 has been etched back in each area, involving etching multiple layers simultaneously. In some examples, each portion of chalcogenide 1158 in each area may be considered to be a layer of chalcogenide 1158.

[0118] As above, after the chalcogenide material 1158 is etched, an encapsulating material 1162 (shown in dark shading) is deposited thereon using ALD, as shown in Fig. 1128c. Because ALD is a conformal deposition, the encapsulating material 1162 can be deposited over a variety of surface topographies within the feature 1152.

[0119] A variety of apparatus may be used to perform the thermal etching of bulk chalcogenides. For example, the tool 1000 of FIG. 10 may use the second processing chamber 1004 for the thermal etching and the third processing chamber 1006 for the deposition of the encapsulant material. In another example, an apparatus with two processing chambers may be used. FIG. 12 illustrates a second example processing apparatus according to disclosed embodiments. The tool 1200 includes a first processing chamber 1202 and a second processing chamber 1204. This tool 1200 does not include the first processing chamber 1000 of FIG. 10. The first processing chamber 1202 may include multiple processing stations (four stations 1280A-D), each of which may process a wafer. The first processing chamber 1202 is configured to perform thermal etching operations on the wafer, including thermal etching, such as thermal ALE, of the bulk chalcogenide material. The second processing chamber 1204 is configured to perform deposition on the wafer and may be considered a deposition chamber. Additionally, the second processing chamber 1204 may include multiple processing stations (four stations 1282A-D), each of which may process a wafer. The first and second processing chambers 1202 and 1204 may be considered a multi-station processing chamber. In some embodiments, the processing chambers 1202 and 1204 may be the same as the processing chambers 1004 and 1006 of FIG.

[0120] The tool 1200 also includes a wafer transport unit configured to transport one or more wafers within the tool 1200. Additional features of the tool 1200 are discussed in more detail below, and various features related to some of the described techniques are discussed here. In the illustrated example, the wafer transport unit includes a first robot arm unit 1208 in a first wafer transport module 1210 and a second robot arm unit 1212 in a second wafer transport module 1214, which may be considered an equipment front-end module (EFEM) configured to receive a container for wafers, such as a front-opening integrated pod (FOUP) 1216. The first robot arm unit 1208 is configured to transport wafers between the first processing chamber 1202 and the second processing chamber 1204, as well as between the second robot arm unit 1212. The second robot arm unit 1212 is configured to transport wafers between the FOUP and the first robot arm unit 1208. After the wafer is etched in the first processing chamber 1202 using a thermal etch, such as thermal ALE, the wafer transport unit can transport the wafer from the first processing chamber 1202 to a second processing chamber 1204 where one or more layers of encapsulating material can be deposited on the one or more wafers.

[0121] As above, the first transfer module 1210 may be a vacuum transfer module (VTM). An airlock 1220 (also known as a loadlock or transfer module) is shown and may be individually optimized for carrying out various fabrication processes. The tool 1200 also includes a pressure unit 1216 configured to reduce the pressure of the tool 1200 to a vacuum or low pressure, for example, between about 1 mTorr and about 10 Torr, and to maintain the tool 1200 at this pressure. This includes maintaining the first and second processing chambers 1202 and 1204, as well as the first wafer transfer module 1210, at a vacuum or low pressure. The second wafer transfer module 1214 may be at a different pressure, such as atmospheric pressure. When transferring the wafer throughout the tool 1200, the wafer is thus maintained at a vacuum or low pressure. For example, when the wafer is transferred from the first processing chamber 1202 into the first wafer transfer module 1210 and to the second processing chamber 1204, the wafer is maintained at vacuum or low pressure and is not exposed to atmospheric pressure.

[0122] In a further example, the substrate is placed in one of the FOUPs 1218 and the second robot arm unit 1212 or the front-end robot transfers the substrate from the FOUP 1218 to the aligner, thereby allowing the substrate to be properly centered before being etched or deposited on it or otherwise processed. After being aligned, the substrate is moved into the airlock 1220 by the front-end robot 1212. The airlock module has the ability to match the environment between the ATM and the VTM so that the substrate can be moved between the two pressure environments without damage. The substrate is moved by the first robot arm unit 1208 from the airlock module 1220 through the first wafer transfer module 1210 or the VTM 1210 into the first processing chamber 1202. To accomplish this substrate movement, the first robot arm unit 1208 uses an end effector on its respective arm.

[0123] The deposition of the encapsulating material may be done in different ways, some of which are described here. Referring again to FIG. 9, for example, the encapsulating material may be deposited on the wafer per block 911 while the wafer is in a deposition chamber, such as the third processing chamber 1006 of tool 1000 or the second processing chamber 1204 of tool 1200. In some implementations, before this encapsulating material is deposited, another encapsulating material may be deposited on the wafer while the wafer is in a thermal etch chamber, such as the second processing chamber 1004 of tool 1000 or the first processing chamber 1202 of tool 1200.

[0124] Figure 13 illustrates another technique according to disclosed embodiments, where blocks 1301, 1303, and 1305 are the same as blocks 901, 903, and 905 of Figure 9, and blocks 101, 103, and 105 of Figure 1. It will be understood that the etch of block 1305 may be performed in any manner provided herein, including as separate modification and removal operations separated by a purge operation, as the two shown in Figure 2. Also, the etch of block 1305 may represent a cleaning operation by thermal etching as described above.

[0125] In block 1315, after the thermal etch and while the wafer remains in the etch chamber, a first encapsulation material is deposited on the wafer. The deposition may use one or more additional components along with one of the first or second chemical species used in the etch to deposit the first encapsulation material. In some embodiments, at least some of the process conditions, such as the wafer temperature or the process chamber pressure, may remain the same as those used in the etch. In some embodiments, a first encapsulation material including aluminum may be deposited, which may provide good protection for the underlying chalcogenide, such as GST. The first encapsulation material may include, for example, aluminum oxide or aluminum fluoride.

[0126] In one example, the etching in operation 1305 may include a second species including DMAC. The depositing in operation 1315 may flow a second species having DMAC and a third species, such as water vapor, onto the wafer to deposit aluminum oxide. The water vapor and process conditions cause the conversion of the DMAC to aluminum oxide, which further deposits the aluminum oxide onto the wafer by ALD. In another example, the second species may include TMA that is flowed onto the wafer with a third species, such as water vapor, onto the wafer to deposit aluminum oxide. The water vapor converts the TMA into aluminum oxide, which is also deposited onto the wafer by ALD. The activation energy for the deposition is provided by the thermal energy of the wafer and the process chamber without the use of a plasma. An ALD deposition that uses thermal energy rather than a plasma may be considered thermal ALD. Thus, some implementations of block 1315 deposit the first encapsulating material using thermal ALD.

[0127] After the first encapsulant material is deposited in the chamber where the etching takes place, blocks 1313 and 1311 may be performed to transfer the wafer to a deposition processing chamber where further deposition may take place.

[0128] In some embodiments, two different chalcogenides may be etched on a wafer. FIG. 14 illustrates yet another technique in accordance with disclosed embodiments. In block 1401, a wafer is provided to a processing chamber including two different chalcogenides, and once placed in the chamber, in block 1403, the wafer is heated to a first temperature as described with respect to block 103 of FIG. 1. In block 1405, the process includes modifying a surface of the first chalcogenide using a first species having a fluoride or chloride, thus producing a first layer of fluorinated or chlorinated chalcogenide, and removing the first layer of fluorinated or chlorinated chalcogenide using a second species containing a compound having a central atom that is aluminum, boron, silicon, or germanium, and at least one chlorine, to etch the first chalcogenide as described herein. It will be appreciated that the etch of block 1405 may be performed in any manner provided herein, including removal in multiple cycles, with separate modification and removal operations separated by purge operations, as the two shown in Figure 2. The etch of block 1405 may also represent the thermal etch cleaning operation described above.

[0129] After etching in block 1405, the wafer is transferred from the processing chamber to a deposition chamber in block 1407. This transfer may be the same as that described above, such as with respect to block 913 of Figure 9, as well as shown in Figure 10. Once in the deposition chamber, a first encapsulant material is deposited on the wafer with the wafer in the deposition chamber in block 1409, similar to that described above, such as with respect to block 911 of Figure 9.

[0130] After this deposition, the wafer may be returned to the processing chamber for further etching, as shown in block 1411. In some other embodiments, the wafer may be transferred to one or more other processing chambers for different processing, after which the wafer may be transferred to the processing chamber for etching. Once in the processing or etching chamber, in block 1413, the wafer is heated to a first temperature, similar to block 1403, and the second chalcogenide layer is etched, as shown in block 1415. In some embodiments, another RIE or other ion-assisted etch may be performed, and the etch of block 1415 may be a cleaning operation, while in other implementations the etch may be an etch of a bulk chalcogenide material.

[0131] The etch of block 1415 includes modifying the surface of the second chalcogenide with a first species having a fluoride or chloride, thus producing a first layer of fluorinated or chlorinated chalcogenide, and removing the second layer of fluorinated or chlorinated chalcogenide with a second species containing a compound having a central atom that is aluminum, boron, silicon, or germanium, and at least one chlorine. It will be understood that the etch of block 1415 may be performed in any manner provided herein, including multiple cycles of removal, as well as separate modification and removal operations separated by purge operations, as the two shown in FIG. 2. The etch of block 1415 may also represent a cleaning operation by thermal etching as described above.

[0132] In some embodiments, a first temperature, a first chemical species, and a second chemical species may be used to etch both the first and second chalcogenide materials. In some other embodiments, one or more of these items may be different in the etching of the first and second chalcogenides. For example, the first species used to etch the first chalcogenide may include fluorine, while the first species used to etch the second chalcogenide may include chlorine. In another example, the second species used to etch the first chalcogenide may include DMAC, while the second species used to etch the second chalcogenide may include TMA.

[0133] After block 1415, the wafer may be transferred back from the processing chamber to a deposition chamber in block 1417 for another deposition of a second encapsulating material on the wafer in block 1419. The encapsulating deposition may be the same as provided herein. In some embodiments, the encapsulating materials deposited on the first chalcogenide and the second chalcogenide may be the same, while in other embodiments they may be different.

[0134] The technique of FIG. 14 is further illustrated in FIG. 15, which shows an example process flow for etching two chalcogenides. In this example, FIG. 1528a includes a wafer 1534 having a stack of materials including a hard mask 1530. The hard mask 1530 is deposited on a first chalcogenide 1532, which is deposited on another layer of material 1538, which may be another mask, followed by a second chalcogenide 1540. This FIG. 1528a and FIG. 15 are illustrative of concepts herein and are not intended to include all layers of a stack of materials. FIG. 1528a may correspond to block 1401 of FIG. 14. In FIG. 1528b, the first chalcogenide 1532 has been etched, which may correspond to blocks 1403 and 1405 of FIG. 14. The etch is also illustrated as a decrease in width 1535A of first chalcogenide material 1532 occurring between views 1528a and 1528b, with width 1535B being smaller in view 1528b. Following this etch of first chalcogenide material 1532, a layer of first encapsulant material 1536 is deposited over hard mask 1530 and first chalcogenide 1532, as described with respect to block 1409.

[0135] After this first encapsulation material 1536 is deposited, another etching process may be performed to etch the second chalcogenide 1540, as shown in FIG. 1528d and described with respect to blocks 1413 and 1415. The etching is also illustrated as a decrease in width 1527A of the second chalcogenide material 1540 occurring between FIG. 1528c and 1528d, with a smaller width 1527B in FIG. 1528d. A second encapsulation layer 1542 is then deposited over the etched second chalcogenide material 1540, as well as over the first encapsulation material 1536 in some examples, as shown in FIG. 1528e. The second encapsulation material 1442 is indicated by shading with a dotted border. FIG. 1528e corresponds to block 1419 of FIG.

[0136] The techniques and apparatus described herein provide numerous benefits and advantages. For example, the use of thermal etching to perform cleaning operations after RIE etching or other ion-based etching allows for the elimination of wet cleaning operations, thereby providing numerous benefits. Some of these benefits include not transporting the wafer from a vacuum environment to atmosphere for wet cleaning and back again, thus keeping the wafer in vacuum and preventing or reducing unwanted oxidation of the chalcogenides, as well as increasing wafer throughput by reducing processing time. Additionally, the apparatus does not require a liquid delivery system for the wet cleaning operation, thus reducing the tool footprint, reducing system maintenance, and reducing costs by not requiring such systems and liquids. Additional benefits include reducing or eliminating damage that can occur to the chalcogenides and wafers due to wet cleaning operations, such as structural collapse due to liquid surface tension, and not requiring surface modification reactants.

[0137] Additionally, the thermal techniques provided herein allow for etching at the monolayer or submonolayer scale to remove precise amounts of chalcogenide, thereby providing a uniform etch. As noted above, these thermal etching techniques are isotropic, and therefore complex surface topography may be etched without the need for line-of-sight or directional etching.

[0138] Additionally, the apparatus provided herein allows for processing of wafers including etching and deposition of encapsulating material in a multi-station chamber, thereby reducing complexity and increasing wafer throughput.

[0139] Additional equipment: The present disclosure includes the apparatus described above as well as herein below. Referring now to FIG. 16, an example of a substrate processing chamber for etching a material according to the present disclosure is shown. Although a particular substrate processing chamber is shown and described, the methods described herein may be implemented on other types of substrate processing systems. FIG. 16 shows an example apparatus 1620 for semiconductor processing according to disclosed embodiments including thermal atomic layer etching. The apparatus 1620 includes a processing chamber 1622, a process gas unit 1624, a substrate heating unit 1626, and a substrate cooling unit 1628. The processing chamber 1622 has a chamber wall 1630 that at least partially bounds and defines a chamber interior 1632 (which may be considered a plenum volume).

[0140] The process gas unit 1624 is configured to flow a process gas, which may include liquids and / or gases, such as reactants, modifying, transforming, or removing molecules, onto the substrate 1634 in the chamber interior 1632. The process gas unit 1624 also includes one or more flow features 1642, such as holes, nozzles (two of which are shown), or showerheads, configured to flow a first process gas onto the substrate 1634. The one or more flow features 1642 may be located above, below, to the side, or a combination of locations within the chamber interior 1632, such as on the walls, top, and bottom of the processing chamber. The process gas unit 1624 may include a mixing vessel for preparing and / or conditioning the process gas for delivery to the chamber interior 1632. One or more mixing vessel inlet valves may control the introduction of the process gas into the mixing vessel.

[0141] The process gas unit 1624 may include a first process gas source 1636, a first process liquid source 1638, a vaporization point (not shown) where the first liquid may be vaporized into a gas, and a carrier gas source 1640. Some reactants may be kept in liquid form prior to vaporization and after delivery to the processing chamber 1622. In some embodiments, the first process gas may include chlorine or fluorine configured to modify one or more layers of material on the substrate without the use of a plasma. The second process gas may include a compound having a central atom that is aluminum, boron, silicon, or germanium and at least one chlorine on the wafer in the second processing chamber as described above.

[0142] In some implementations, the vaporization point may be a heated liquid injection module. In some other implementations, the vaporization point may be a heated vaporizer. In some other embodiments, the vapor may be generated by applying a vacuum above a vessel containing the liquid reagent. In still other implementations, the vaporization point may be excluded from the processing station. In some implementations, a liquid flow controller (LFC) may be provided upstream of the vaporization point to control the liquid mass flow rate for vaporization and delivery to the chamber interior 1632. The carrier gas source 1640 includes one or more carrier gases or liquids that may be flowed with the process gas, which may be inert gases such as N2, Ar, Ne, He. The apparatus 1620 may also include a vacuum pump 1633 configured to pump the chamber interior to a low pressure, such as a vacuum having a pressure of 1 mTorr or 10 Torr.

[0143] The chamber interior 1632 includes substrate support features 1635 configured to support and thermally float the substrate 1634 within the chamber. The substrate support features 1635 may include, for example, clamps, horizontal pins or supports, vertical pins or supports, and semicircular rings that support the substrate 1634 within the chamber interior 1632. These features are configured to support the substrate 1634 such that the thermal mass of the substrate 1634 is reduced as much as possible to the thermal mass of the substrate alone. Thus, each substrate support feature 1635 may have minimal contact with the substrate 1634 and may be the minimum number of features required to adequately support the substrate during processing (e.g., to support the weight of the substrate and prevent inelastic deformation of the substrate). For example, the surface area of ​​one substrate support feature 1635 in contact with the substrate may be less than about 1%, 0.5%, 0.1%, 0.05%, or 0.01% of the total surface area of ​​the backside of the substrate. Also, for example, 2, 3, or 4 features may be utilized.

[0144] In one example, the support feature 1635 may include two or more vertical pins having grooves wound or spiraled along a perpendicular longitudinal axis and offset from the longitudinal axis at different distances and configured to support a substrate. When the vertical pin rotates along its longitudinal axis such that an edge of the substrate is positioned within the groove, the edge of the groove, and therefore the edge of the substrate, moves away from the longitudinal axis. When multiple vertical pins are used to support a substrate, rotation of the vertical pins causes the grooves to exert a support force on the substrate perpendicular to the longitudinal axis.

[0145] In some embodiments, the chamber 1622 may include a wafer support pedestal including substrate lift pins. During thermal ALE processing, the lift pins may support and position the substrate away from the pedestal such that there is substantially no thermal energy transfer between the pedestal and the substrate (e.g., less than 10%, 5%, 1%, 0.5%, or 0.1% of the energy transfer between the two). In some other embodiments, the chamber 1622 may not have a pedestal. In some embodiments, an electrostatic chuck (ESC) including a substrate heating unit 1626 configured to heat the substrate to a temperature provided herein, such as between about 20° C. and 500° C., may be used.

[0146] The substrate heating unit 1626 is configured to heat the substrate to multiple temperatures and maintain such temperatures for, e.g., at least 1 second, 5 seconds, 10 seconds, 30 seconds, 1 minute, 2 minutes, or 3 minutes. In some embodiments, the substrate heating unit 1626 is configured to heat the substrate between at least two temperature ranges, a first range being between about 20° C. and 150° C. and a second range being between about 200° C. and 600° C., and configured to maintain the substrate at a temperature within these ranges for, e.g., at least 1 second, 5 seconds, or 10 seconds. Additionally, in some embodiments, the substrate heating unit 1626 is configured to heat the substrate from the first temperature range to the second temperature range in, e.g., less than about 250 milliseconds, 150 milliseconds, 100 milliseconds, or 50 milliseconds.

[0147] The substrate heating unit 1626 may utilize radiative heating, convective heating, laser heating, plasma heating, solid-to-solid heat transfer (e.g., transferring heat generated by one or more heating elements in a heated electrostatic chuck or pedestal to a substrate supported by or on the chuck or pedestal), or a combination of these items. In radiative heating, the substrate heating unit 1626 may be used for radiative light heating, ultraviolet heating, microwave heating, radio frequency heating, and inductive heating. For example, the substrate heating unit 1626 may include a light emitting diode (LED) that emits visible light having a wavelength that may include a range between 400 nanometers (nm) and 800 nm. It may also include, for example, a heat lamp, a light emitting diode (e.g., LED), a ceramic heater, a quartz heater, or a plurality of gradient index (GRIN) lenses connected to an optical energy source. The GRIN lens is configured to uniformly deliver thermal energy (heat or light) from the optical energy source to the substrate. The light source may be a laser or high intensity light source that transmits thermal energy to the GRIN lens through a conduit such as a fiber optic cable. The heating elements utilized by the substrate heating unit 1626 may be located above, below, to the side, or a combination thereof, of the substrate 1634, and may be located inside, outside, or both of the chamber interior 1632. In FIG. 16, the heating elements utilized by the substrate heating unit 1626 include multiple LEDs 1626A located both above and below the substrate 1634. The lower heating element is located inside the chamber interior 1632, and the upper heating element is located outside the chamber interior 1632. In some embodiments, for some of the heating elements located outside the chamber 1622, the chamber 1622 may have a window 1654 that allows radiation to be transmitted into the chamber interior 1632 and onto the substrate 1634. In some embodiments, this window 1654 may be an optical grade quartz plate, and in other embodiments, it may be a transparent indium tin oxide (ITO) window.In some embodiments, the substrate heating unit 1626 includes multiple LEDs 1626A, which may be positioned only below the substrate 1634, which may include within a base or ESC that may include a window, and light emitted by the LEDs may pass through the window to reach the back surface of the substrate.

[0148] In solid-to-solid heat transfer, the substrate heating unit 1626 may have one or more heating surfaces configured to contact and heat the substrate inside the chamber. In some embodiments, the substrate heating unit 1626 may have a heating platen, such as a flat surface or a substrate pedestal surface, configured to contact and heat the backside of the substrate. The heating platen may have heating elements, such as heating coils, heating fluids, or radiative heating as described above, that may heat the surface of the heating platen. The substrate may be heated when the backside of the substrate is in direct contact with the heating platen, or when it is offset from the heating platen but close enough to receive thermal energy from the heating platen. When this solid-to-solid heat transfer is used to heat the substrate, the substrate is moved away from the heating platen when cooling the substrate. Some conventional ALE devices may have a substrate pedestal that includes both heating and cooling elements. However, these devices cannot cycle between temperatures of the thermal ALE quickly (e.g., less than 250 milliseconds) due to the large thermal mass of the pedestal that is repeatedly heated and cooled. For example, it may take multiple seconds or minutes to heat the pedestal from a first temperature range (e.g., 20°C-100°C) to a second temperature range (e.g., 200°C-500°C) and to cool the pedestal from the second temperature range to a lower temperature that allows the substrate to cool to the first temperature range. Thus, after using this solid-to-solid heating technique, the heating platen and substrate are separated from each other, which may be achieved, for example, by moving the substrate and / or heating platen away from each other. Without this separation, cooling occurs for the thermal mass of both the substrate and heating platen, thereby increasing the cooling time and reducing the substrate throughput. In some embodiments, an ESC or pedestal having a substrate heating unit and Peltier elements for cooling may allow for short heating and cooling times (e.g., about 30 seconds to cool the substrate to the desired temperature). In some embodiments, this may be done at low pressures, such as, for example, less than 1 Torr, including less than 50 mTorr.

[0149] The substrate cooling unit 1628 of FIG. 16 is configured to actively cool the substrate. In some embodiments, the substrate cooling unit 1628 flows a cooling gas over the substrate 1634 to actively cool the substrate 1634. The substrate cooling unit 1628 may include a cooling fluid source 1648 that may include a cooling fluid (gas or liquid) and a cooler 1650 configured to cool the cooling fluid to a desired temperature, such as 0° C., −50° C., −100° C., −150° C., −170° C., −200° C., −250° C., or lower. The substrate cooling unit 1628 has tubes and a coolant flow feature 1652, such as a nozzle or hole, configured to flow the coolant fluid to the chamber interior 1632. In some embodiments, the fluid may be in liquid form when flowed into the chamber 1622 and in gas form when it reaches the chamber interior 1632, for example, when the chamber interior 1632 is at a low pressure, such as 1 Torr. The cooling fluid may be an inert element such as nitrogen, argon, helium, etc. In some embodiments, the flow rate of the cooling fluid into the chamber interior 1632 may be, for example, at least 10 liters per second, 50 liters per second, 100 liters per second, 150 liters per second, 200 liters per second, 250 liters per second, and 300 liters per second.

[0150] Various factors can increase the ability of the cooling fluid to cool the substrate. Through various experiments, it has been found that the higher the flow rate of the cooling fluid, the faster the substrate cools. In one example experiment, a cooling gas at about -196°C flowed over the substrate at a flow rate of 1 liter per second was found to reduce the temperature of the substrate from about 220°C to about 215°C in about 5,000 milliseconds, while a flow rate of 10 liters per second of the same cooling gas reduced the temperature of the substrate from about 220°C to about 195°C in about 5,000 milliseconds. Additionally, the gap between the substrate and the top of the chamber (1786 in FIG. 17) can also affect the cooling of the substrate, with a smaller gap found to provide greater cooling. In one example, it was found that a substrate separated from the top of the chamber by a gap of about 50 micrometers was cooled from about 220° C. to about 215° C. in about 5,000 milliseconds using cooling gas at about −196° C., while a substrate separated from the top of the chamber by a gap of about 5 millimeters was cooled from about 220° C. to about 209° C. in about 5,000 milliseconds using the same cooling gas. Thus, it was found that the higher the flow rate, as well as the smaller the gap, the faster the substrate was cooled.

[0151] In some embodiments, the substrate cooling unit 1628 may actively cool the substrate 1634 using solid-to-solid heat transfer. In some of these embodiments, a cooling platen, such as a flat, cooled surface, may be used to contact the bottom of the substrate to cool it. The platen may be cooled by flowing a cooling fluid over, through, or under the platen. When using this solid-to-solid cooling, similar to the solid-to-solid heating described above, the substrate is separated from the cooling platen during heating of the substrate, such as by moving the substrate away from the cooling platen by lifting the substrate with lift pins. Without this separation, the thermal mass of both the substrate and the cooling platen would cool and require more cooling, resulting in increased processing time and reduced throughput. In some embodiments, radiative heating of the top of the substrate or plasma heating of the bottom of the substrate may be used in combination with solid-to-solid cooling.

[0152] In some embodiments, the substrate cooling unit 1628 may use laser cooling to cool the substrate. This allows the substrate, which includes thulium molecules on at least the exposed surface of the substrate, to be cooled using the inverse Navier-Stokes reaction. For example, the temperature of the substrate is manifested in phonons, and the laser cooling emits phonons at the substrate surface, which interact with and pick up the phonons of the thulium, and then leave the substrate with the phonons from the thulium at a higher energy level. The removal of these phonons results in a reduction in the substrate temperature. To enable this laser cooling, the substrate may be doped with thulium on the surface, which may be incorporated into the techniques described above, such as before or after any operation, such as a removal operation.

[0153] As described above, some embodiments of the apparatus may include a plasma source configured to generate a plasma inside the chamber, which may be a capacitively coupled plasma (CCP), an inductively coupled plasma (ICP), a remote plasma above, and a remote plasma below.

[0154] In some embodiments, the apparatus described herein may include a controller configured to control various aspects of the apparatus to perform the techniques described herein. For example, in FIG. 16, the apparatus 1620 includes a controller 1666 (which may include one or more physical or logical controllers) communicatively coupled to the process chamber and controlling some or all operations of the process chamber. The system controller 1666 may include one or more memory devices 1668 and one or more processors 1670. In some embodiments, when the disclosed embodiments are performed, the apparatus includes a switching system for controlling, for example, flow rates and durations, substrate heating units, substrate cooling units, substrate loading and unloading in the chamber, substrate thermal floating, and process gas units. In some embodiments, the apparatus may have a switching time of up to about 500 ms or up to about 1650 ms. The switching time may depend on the flow chemistry, the selected recipe, the reactor architecture, and other factors.

[0155] In some implementations, the controller 1666 is part of an apparatus or system, which may be part of the examples described above. Such a system or apparatus may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (gas flow systems, substrate heating units, substrate cooling units, etc.). These systems may be integrated with electronics to control the operation of those systems before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as a "controller" and may control various components or subparts of one or more systems. The controller 1666 may be programmed to control any of the processes described herein depending on the process parameters and / or type of system. The processes include delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operation settings, and transfer of wafers into and out of the tool and into other transfer tools and / or load locks connected or interfaced to the particular system.

[0156] In general terms, the controller 1666 may be defined as electronics having various integrated circuits, logic, memory, and / or software that, for example, receive instructions, issue instructions, control operations, enable cleaning operations, and enable endpoint measurements. The integrated circuits may include chips in firmware form that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute the program instructions (e.g., software). The program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), which define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, the operational parameters may be part of a recipe defined by a process engineer to accomplish one or more processing operations during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of the wafer.

[0157] In some embodiments, the controller 1666 may be part of or coupled to a computer that is integrated, coupled, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or be all or part of a fab host computer system, thereby enabling remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a fabrication operation, examine the history of past fabrication operations, examine trends or performance metrics across multiple fabrication operations, modify parameters of a current process, set up processing operations following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller 1666 receives instructions in the form of data that specify parameters for each processing operation to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller 1666 may be distributed, such as by including one or more discrete controllers networked together and operating toward a common purpose, such as the process and control described herein. An example of a distributed controller for such a purpose would be one or more integrated circuits on the chamber that are located remotely (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that cooperate to control the process on the chamber.

[0158] As described above, depending on the processing operation or operations being performed by the apparatus, the controller 1666 may communicate with one or more of other apparatus circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from wafer containers to tool locations and / or load ports within a semiconductor manufacturing factory.

[0159] Also as described above, the controller may be configured to perform any of the techniques described above. For example, with reference to the apparatus 1620 of FIG. 16 and the techniques of FIG. 1, in some embodiments, the controller 1666 is configured to bring the wafer 1634 located on the substrate support feature 1635 to a first temperature (i.e., heat) by the substrate heating unit 1626 and to flow a first process gas to the wafer 1634 by the process gas unit 1624. As described above, the first process gas is configured to modify one or more surface layers of chalcogenide on the wafer 1634 by chemisorption, in some embodiments without the use of plasma, while the wafer is maintained at the first temperature. The controller 1666 may further be configured to flow a second process gas by the process gas unit onto the wafer 1634 to remove the modified layer of chalcogenide, as described herein. Some implementations include the controller 1666 depositing one or more layers of encapsulant material onto the wafer 1634, as provided herein.

[0160] As mentioned above, some etches performed herein may be a function of temperature controlled processing chambers, e.g., their sidewalls, top, and / or bottom, as well as showerheads and gas delivery systems. FIG. 17 shows a cross-sectional side view of an example apparatus according to disclosed embodiments. As described in more detail below, the apparatus 1700 can rapidly and precisely control the temperature of a substrate, including performing thermal etching operations. The apparatus 1700 includes a processing chamber 1702, a pedestal 1704 having a substrate heater 1706 and a plurality of substrate supports 1708 configured to support a substrate 1718, and a gas distribution unit 1710.

[0161] The processing chamber 1702 includes a sidewall 1712A, a top 1712B, and a bottom 1712C, which at least partially define a chamber interior 1714, which may be considered a plenum volume. As described herein, in some embodiments, it may be desirable to actively control the temperature of the walls 1712A, top 1712B, and bottom 1712C of the processing chamber to prevent unwanted condensation on their surfaces. In some emerging semiconductor processing operations, vapors such as water and / or alcohol vapors are flowed over a substrate, where the vapors adsorb onto the substrate, but may also adsorb undesirably on the interior surfaces of the chamber. This can lead to unwanted deposition and etching on the interior chamber surfaces, which can damage the chamber surfaces and cause particulate matter to flake off onto the substrate, resulting in substrate defects. To reduce and prevent unwanted condensation on the interior chamber surfaces, the temperatures of the walls, top, and bottom of the chamber may be maintained at temperatures that do not cause condensation of chemicals used in the processing operations.

[0162] This active temperature control of the chamber surfaces may be achieved by heating the chamber walls 1712A, the top 1712B, and the bottom 1712C with heaters. As illustrated in FIG. 17, the chamber heater 1716A is disposed on the chamber wall 1712A and configured to heat the chamber wall 1712A, the chamber heater 1716B is disposed on the top 1712B and configured to heat the top 1712B, and the chamber heater 1716C is disposed on the bottom 1712C and configured to heat the bottom 1712C. The chamber heaters 1716A-1716C may be resistive heaters configured to generate heat when a current is passed through a resistive element. The chamber heaters 1716A-1716C may also be fluid conduits through which a heat transfer fluid, such as a heating fluid that may include heated water, may flow. In some examples, the chamber heaters 1716A-1716C may be a combination of both heated fluid and resistive heaters. The chamber heaters 1716A-1716C are configured to generate heat to bring the interior surfaces of the chamber walls 1712A, top 1712B, and bottom 1712C, respectively, to a desired temperature. The desired temperature may range, for example, between about 80° C. and about 130° C., about 90° C., or between about 40° C. and about 150° C., including about 120° C. It has been found that under some conditions, water and alcohol vapors do not condense on surfaces maintained at about 90° C. or above.

[0163] Additionally, the chamber walls 1712A, top 1712B, and bottom 1712C may be constructed of a variety of materials capable of withstanding chemicals used in processing techniques. These chamber materials may include, for example, aluminum, anodized aluminum, aluminum with a polymer such as plastic, a metal or metal alloy with a yttria coating, a metal or metal alloy with a zirconia coating, and a metal or metal alloy with an aluminum oxide coating. In some examples, the coating material may be a blend or layer of a combination of different materials, such as alternating layers of aluminum oxide and yttria, or aluminum oxide and zirconia. These materials are configured to withstand chemicals used in processing techniques, such as anhydrous HF, water vapor, methanol, isopropyl alcohol, chlorine, fluorine gas, nitrogen gas, hydrogen gas, helium gas, and mixtures thereof.

[0164] Additionally, the apparatus 1700 may be configured to perform processing operations at or near a vacuum, such as at a pressure between about 0.1 Torr and about 100 Torr, or between about 20 Torr and about 200 Torr, or between about 0.1 Torr and about 10 Torr, which may include a vacuum pump 1784 configured to pump the chamber interior 1714 to a low pressure, such as a vacuum having a pressure between about 0.1 Torr and about 100 Torr, including between about 0.1 Torr and about 10 Torr, and between about 20 Torr and about 200 Torr, or between about 0.1 Torr and about 10 Torr.

[0165] Various features of the pedestal 1704 will now be described. The pedestal 1704 includes a heater 1722 (enclosed in a dashed rectangle in FIG. 17) having a plurality of LEDs 1724 configured to emit visible light having wavelengths of 400 nm or more and 800 nm or less, including 450 nm. The heater LEDs emit visible light onto the backside of the substrate that heats the substrate. Visible light having a wavelength of about 400 nm to 800 nm can quickly and efficiently heat a silicon wafer, for example, from an ambient temperature of about 20° C. to about 600° C. This is because silicon absorbs light in this range. In contrast, radiative heating, including infrared radiation, may heat silicon inefficiently at temperatures up to about 400° C. because silicon tends to be transparent to infrared radiation at temperatures below about 400° C. Conventional "hot plate" heaters that rely on solid-to-solid heat transfer between the substrate and a heated platen, such as a pedestal with a heating coil, have relatively slow heating and cooling rates and result in uneven heating that can result from substrate warping or inconsistent contact with the heated platen. For example, it can take multiple minutes to heat a conventional pedestal to a desired temperature, as well as to heat the pedestal from a first temperature to a second, higher temperature, and to cool the pedestal to a lower temperature.

[0166] The heater's LEDs may be arranged, electrically connected, and electrically controlled in various ways. Each LED may be configured to emit visible blue light and / or visible white light. In certain embodiments, white light (generated with a wavelength range in the visible region of the EM spectrum) is used. In some semiconductor processing operations, white light can reduce or prevent unwanted thin film interference. For example, some substrates have backside films that reflect different light wavelengths in different amounts, thus resulting in uneven and potentially inefficient heating. Using white light can reduce this unwanted reflection variation by averaging out the thin film interference across the broad visible spectrum provided by white light. In some examples, depending on the material on the backside of the substrate, it may be advantageous to use visible non-white light, such as blue light with a wavelength of 450 nm, to provide a single or narrow band of wavelengths. A single or narrow band of wavelengths may provide more efficient, powerful, and direct heating of some substrates that may better absorb narrow band wavelengths than white light.

[0167] Various types of LEDs may be employed. Examples include chip-on-board (COB) LEDs or surface-mounted diode (SMD) LEDs. In SMD LEDs, the LED chip may be fused with a printed circuit board (PCB) that may have multiple electrical contacts that allow control of each diode on the chip. For example, a single SMD chip is typically limited to having three diodes (e.g., red, blue, or green) that can be individually controlled to produce different colors. SMD LED chips may have sizes ranging from 2.8×2.5 mm, 3.0×3.0 mm, 3.5×2.8 mm, 5.0×5.0 mm, and 5.6×3.0 mm. In COB LEDs, each chip may have four or more diodes, such as 9, 12, tens, hundreds, or more, printed on the same PCB. Typically, COB LED chips have one circuit and two contacts regardless of the number of diodes, thus providing a simple design and efficient monochromatic applications. The ability and performance of the LEDs to heat the substrate may be measured by the watts of heat each LED emits, which may contribute directly to heating the substrate.

[0168] FIG. 18 shows a top view of a substrate heater with multiple LEDs. The substrate heater 1722 includes a printed circuit board 1726 and multiple LEDs 1724, some of which are labeled. The LEDs shown include approximately 1,300 LEDs. External connections 1728 are connected by traces and provide power to the multiple LEDs 1724. As shown in FIG. 18, the LEDs may be arranged along multiple arcs that are radially offset from a center 1730 of the substrate heater 1722 by different radii. In each arc, the LEDs may be equally spaced from one another. For example, one arc 1732 is enclosed in a partially shaded dotted shape and is a portion of a circle having a radius R that includes 16 LEDs 1724 and extends around the center 1730. The 16 LEDs 1724 may be considered to be equally spaced from one another along the arc 1732.

[0169] In some embodiments, the plurality of LEDs may include at least about 1,000 LEDs, including, for example, more than about 1,200, 1,500, 2,000, 3,000, 4,000, 5,000, or 6,000. In some examples, each LED may be configured to use 4 watts or less at 100% power, including 3 watts at 100% power and 1 watt at 100% power. The LEDs may be arranged in individually controllable zones and electrically connected to allow for temperature adjustment and fine tuning across the substrate. In some examples, the LEDs may be grouped into, for example, at least 20 individually controllable zones, including, for example, at least about 25, 50, 75, 80, 85, 90, 95, or 100 zones. The zones may allow for radial and azimuthal (i.e., angular) temperature adjustment. The zones may be arranged in a defined pattern, such as a rectangular grid, a hexagonal grid, or other pattern suitable for generating a desired temperature profile. The zones may also have various shapes, such as square, trapezoid, rectangle, triangle, oval, ellipse, circle, annular (e.g., ring), partial annular (i.e., annular sector), arc, arc, and sector that may have a radius of less than or equal to the full radius of the PCB of the substrate heater centered on the center of the heater. These zones can adjust the temperature at multiple locations across the wafer to generate a desired temperature profile, such as a higher temperature near the edge of the substrate than the center of the substrate, with a more even temperature distribution. Individual control of these zones may also include the ability to control the power output of each zone. For example, each zone may have at least 15, 20, or 25 adjustable power outputs. In some examples, each zone may have one LED, thereby allowing for individual control and adjustment of each LED, thus allowing for a more uniform heating profile on the substrate. Thus, in some embodiments, each of the multiple LEDs in the substrate heater may be individually controllable.

[0170] In certain embodiments, the substrate heater 1722 is configured to heat the substrate to multiple temperatures and maintain each such temperature for various durations. These durations may include the following non-limiting examples: at least about 1 second, at least about 5 seconds, at least about 10 seconds, at least about 30 seconds, at least about 60 seconds, at least about 90 seconds, at least about 120 seconds, at least about 150 seconds, or at least about 180 seconds. The substrate heater may be configured to heat the substrate to between about 50° C. and 150° C., including about 130° C., or between about 150° C. and 350° C., for example. The substrate heater may be configured to maintain the substrate at a temperature within these ranges for various durations, including the following non-limiting examples: at least about 1 second, at least about 5 seconds, at least about 10 seconds, at least about 30 seconds, at least about 60 seconds, at least about 90 seconds, at least about 120 seconds, at least about 150 seconds, or at least about 180 seconds. Additionally, in some embodiments, the substrate heater 1722 is configured to heat the substrate at any temperature within these ranges, for example, for less than about 60 seconds, less than about 45 seconds, less than about 30 seconds, or less than about 15 seconds. In certain embodiments, the substrate heater 1722 is configured to heat the substrate at one or more heating rates, such as, for example, between at least about 0.1° C. / sec and at least about 20° C. / sec.

[0171] The substrate heater may increase the temperature of the substrate by causing the LEDs to emit visible light at one or more power levels, including at least about 80%, at least about 90%, at least about 95%, or at least about 100% power. In some embodiments, the substrate heater is configured to emit between about 10 W and 4000 W, including at least about 10 W, at least about 30 W, at least about 0.3 kilowatts (kW), at least about 0.5 kW, at least about 2 kW, at least about 3 kW, or at least about 4 kW. The apparatus is configured to provide between about 0.1 kW and 9 kW of power to the pedestal. A power source is connected to the substrate heater through the pedestal, not shown. During the temperature increase, the substrate heater may operate at a high power and may operate at a lower power level (including, for example, between about 5 W and about 0.5 kW) to maintain the temperature of the heated substrate.

[0172] Also, in some embodiments, the substrate heater may include a pedestal cooler thermally connected to the LEDs such that heat generated by the LEDs can be transferred from the LEDs to the pedestal cooler. This thermal connection allows heat to be conducted from the LEDs to the pedestal cooler along one or more heat flow paths between these components. In some examples, the pedestal cooler is in direct contact with one or more elements of the substrate heater, while in other examples, other conductive elements, such as a thermally conductive plate (e.g., including metal), are interposed between the substrate heater and the pedestal cooler. Referring again to FIG. 17, the substrate heater includes a pedestal cooler 1736 in direct contact with the bottom of the PCB 1726. Heat is configured to flow from the LEDs to the PCB 1726 and to the pedestal cooler 1736. The pedestal cooler 1736 also includes a number of fluid conduits 1738 configured to allow a heat transfer fluid, such as water, to flow therethrough to receive heat and cool the LEDs in the substrate heater 1722. The fluid conduit 1738 may be connected to a tank and pump (not shown) located outside the chamber. In some examples, the pedestal cooler may be configured to flow chilled water, such as at between about 5° C. and 20° C.

[0173] As provided herein, it may be advantageous to actively heat the exterior surface of the processing chamber 1702. In some examples, it may be advantageous to heat the exterior surface of the pedestal 1704 to prevent unwanted condensation and deposition on the exterior surface as well. As shown in FIG. 17, the pedestal 1704 may further include a pedestal heater 1744 configured to heat the exterior surface of the pedestal 1704, including its sidewalls 1742A and bottom 1742B, within the interior of the pedestal 1704. The pedestal heater 1744 may include one or more heating elements, such as one or more resistive heating elements, and a fluid conduit configured to have a heated fluid flow therethrough. In some examples, both the pedestal cooler and the pedestal heater may have fluid conduits fluidly connected to each other such that the same heat transfer fluid may flow through both the pedestal cooler and the pedestal heater. In these embodiments, the fluid may be heated to between 50° C. and 130° C., including between about 90° C. and 120° C.

[0174] The pedestal may also include a window to protect the substrate heater including the LEDs from damage due to exposure to process chemicals and pressures used during processing operations. As shown in FIG. 17, a window 1750 may be disposed above the substrate heater 1722 and sealed against the sidewall 1749 of the pedestal 1704 to create a plenum volume within the pedestal that is fluidly isolated from the chamber interior. This plenum volume may also be considered to be within the recess 1746. The window may be composed of one or more materials that are optically transparent to visible light emitted by the LEDs, including light having wavelengths in the range of 400 nm to 800 nm. In some embodiments, the material may be quartz, sapphire, quartz with a sapphire coating, or calcium fluoride (CaF). The window may also be free of any holes or openings therein. In some embodiments, the heater may have a thickness of 15 to 30 mm, including 20 mm and 25 mm.

[0175] As shown in FIG. 17, the substrate support 1708 of the pedestal 1704 is configured to support the substrate 1718 above and offset from the window 1750 and the substrate heater 1722. In certain embodiments, the temperature of the substrate can be rapidly and accurately controlled by thermally floating or thermally isolating the substrate in the chamber. Heating and cooling of the substrate targets both the thermal mass of the substrate and the thermal mass of other components in contact with the substrate. For example, if the substrate is in thermal contact with a large object, such as when the entire backside of the substrate rests on a large surface of a pedestal or electrostatic chuck, as in many conventional etching apparatus, this object acts as a heat sink for the substrate, which affects the ability to accurately control the substrate temperature and reduces the rapidity of heating and cooling of the substrate. It is therefore desirable to position the substrate such that a minimum of thermal mass is heated and cooled. This thermal floating is configured to position the substrate such that the thermal contact (including direct and radiative) between the substrate and other objects in the chamber is minimized.

[0176] Thus, in some embodiments, the pedestal 1704 is configured to support the substrate 1718 by thermally floating or thermally isolating the substrate in the chamber interior 1714. The substrate supports 1708 of the pedestal 1704 are configured to support the substrate 1718 such that the thermal mass of the substrate 1718 is reduced as much as possible to the thermal mass of the substrate 1718 alone. Each substrate support 1708 may have a substrate support surface 1720 that is in minimal contact with the substrate 1718. The number of substrate supports 1708 may range from at least three, such as at least six or more. Additionally, the surface area of ​​the support surface 1720 may be the minimum area required to adequately support the substrate during processing operations (e.g., to support the weight of the substrate and prevent inelastic deformation of the substrate). In some embodiments, the surface area of ​​one support surface 1720 may be, for example, less than about 0.1%, less than about 0.075%, less than about 0.05%, less than about 0.025%, or less than about 0.01%.

[0177] The substrate support is also configured to prevent the substrate from contacting other elements of the pedestal, including the surface of the pedestal and features below the substrate. Additionally, the substrate 1718 is offset from the substrate heater 1722 (as measured from the top surface of the substrate heater 1722, which in some examples may be the top surface of the LEDs 1724) by a distance that can affect many aspects of heating the substrate 1718.

[0178] As described above, the substrate supports 1708 are configured to support the substrate 1718 above the window. In some embodiments, these substrate supports are stationary and fixed in place, and they may not be lift pins or support rings. In some embodiments, at least a portion of each substrate support 1708, including the support surface 1720, may be constructed of a material that is transparent to at least the light emitted by the LEDs 1724. In some examples, this material may be quartz or sapphire. The transparency of these substrate supports 1708 may allow visible light emitted by the LEDs of the substrate heater 1722 to pass through the substrate supports 1708 and reach the substrate 1718, so that the substrate supports 1708 do not block this light and the substrate 1718 can be heated within the area where it is supported. This may provide more uniform heating of the substrate 1718 compared to using a substrate support that includes a material that is opaque to visible light. In some other embodiments, the substrate supports 1708 may be constructed of a non-transparent material, such as zirconium dioxide (ZrO2).

[0179] 17, in some embodiments, the pedestal is also configured to move vertically. This may include moving the pedestal such that the gap 1786 between the faceplate 1776 of the gas distribution unit 1710 and the substrate 1718 can range between 2 mm and 70 mm. As provided in further detail below, moving the pedestal vertically may enable active cooling of the substrate and fast cycle times for processing operations including flowing gases and purging due to the low volume formed between the gas distribution unit 1710 and the substrate 1718. This movement may also enable the formation of a small processing volume between the substrate and the gas distribution unit, which can result in smaller purge and processing volumes, thus reducing purge and gas transfer times and increasing throughput.

[0180] The gas distribution unit 1710 is configured to flow process gases, which may include liquids and / or gases, such as reactants, modifying, transforming, or removing molecules, to a substrate 1718 in the chamber interior 1714. As seen in FIG. 17, the gas distribution unit 1710 includes one or more fluid inlets 1770 that are fluidly connected to one or more gas sources 1772 and / or one or more vapor sources 1774. In some embodiments, the gas lines and mixing chamber may be heated to prevent unwanted condensation of vapors and gases flowing therethrough. The lines may be heated to at least about 40° C., at least about 80° C., at least about 90° C., at least about 120° C., at least about 130° C., or at least about 150° C. The one or more vapor sources may include one or more sources of gas and / or liquid to be vaporized. Vaporization may be a direct injection vaporizer, a flow-over vaporizer, or both. The gas distribution unit 1710 also includes a faceplate 1776 that includes a number of through-holes 1778 that fluidly connect the gas distribution unit 1710 to the chamber interior 1714. The through-holes 1778 are fluidly connected to one or more fluid inlets 1770 and further extend through a front surface 1777 of the faceplate 1776, which is configured to face the substrate 1718. In some embodiments, the gas distribution unit 1710 may be considered a top plate, and in some other embodiments, a showerhead.

[0181] The through-holes 1778 may be configured in a variety of ways to deliver a uniform flow of gas over the substrate. In some embodiments, the through-holes may all have the same outer diameter, such as between about 0.03 inches and 0.05 inches, including about 0.04 inches (1.016 mm). Additionally, the faceplate through-holes may be positioned across the faceplate to create a uniform flow from the faceplate.

[0182] 17, the gas distribution unit 1710 may include a unit heater 1780 thermally connected to the faceplate 1776 to allow for heat transfer between the faceplate 1776 and the unit heater 1780. The unit heater 1780 may include a fluid conduit through which a heat transfer fluid may flow. As above, the heat transfer fluid may be heated to a temperature range of, for example, about 20° C. and 120° C. In some examples, the unit heater 1780 may be used to heat the gas distribution unit 1710 to prevent unwanted condensation of vapors and gases, and in some such examples, this temperature may be at least about 90° C. or 120° C.

[0183] In some embodiments, the gas distribution unit 1710 may include a second unit heater 1782 configured to heat the faceplate 1776. The second unit heater 1782 may include one or more resistive heating elements, fluid conduits for flowing a heated fluid, or both. The use of two heaters 1780 and 1782 in the gas distribution unit 1710 may enable different heat transfer within the gas distribution unit 1710. This may include heating the faceplate 1776 by using the first unit heater 1780 and / or the second unit heater 1782 to provide a temperature controlled chamber, as described above, for the purpose of reducing or preventing unwanted condensation on the elements of the gas distribution unit 1710.

[0184] The apparatus 1700 may also be configured to cool the substrate. This may include flowing a cooling gas over the substrate, bringing the substrate close to the faceplate to allow heat transfer between the substrate and the faceplate, or both. Actively cooling the substrate allows for more precise temperature control and faster transitions between temperatures, thereby reducing processing time and improving throughput. In some embodiments, a first unit heater 1780 that flows a heat transfer fluid through a fluid conduit may be used to cool the substrate 1718 by transferring heat transferred from the substrate 1719 away from the faceplate 1776. The substrate 1718 may thus be cooled by being placed in close proximity to the faceplate 1776, such as by a gap 1786 of 5 mm or 2 mm or less, such that heat from the substrate 1718 is transferred to the faceplate 1776 by radiation and transferred away from the faceplate 1776 by the heat transfer fluid in the first unit heater 1780. The faceplate 1776 may therefore be considered a heat sink for the substrate 1718 for cooling the substrate 1718 .

[0185] In some embodiments, the apparatus 1700 may further include a cooling fluid source 1773 that may include a cooling fluid (gas or liquid) and a cooler (not shown) configured to cool the cooling fluid to a desired temperature, such as at least about 90° C., at least about 70° C., at least about 50° C., at least about 20° C., at least about 10° C., at least about 0° C., at least about −50° C., at least about −100° C., at least about −150° C., at least about −190° C., at least about −200° C., or at least about −250° C. or lower. The apparatus 1700 includes a tube for delivering the cooling fluid to the one or more fluid inlets 1770 and a gas distribution unit 1710 configured to flow the cooling fluid over the substrate. In some embodiments, the fluid may be in liquid form when flowed into the chamber 1702 and in gas form when it reaches the chamber interior 1714, for example, when the chamber interior 1714 is at a low pressure, such as between about 0.1 Torr and 10 Torr, or between about 0.1 Torr and 100 Torr, or between about 20 Torr and 200 Torr, as described above. The cooling fluid may be an inert element, such as nitrogen, argon, or helium. In some examples, the cooling fluid may include or have only a non-inert element or mixture, such as hydrogen gas. In some embodiments, the flow rate of the cooling fluid into the chamber interior 1714 may be, for example, at least about 0.25 liters per minute, at least about 0.5 liters per minute, at least about 1 liter per minute, at least about 5 liters per minute, at least about 10 liters per minute, at least about 50 liters per minute, or at least about 100 liters per minute. In certain embodiments, the apparatus may be configured to cool the substrate at one or more cooling rates, such as at least about 5° C. / sec, at least about 10° C. / sec, at least about 15° C. / sec, at least about 20° C. / sec, at least about 30° C. / sec, or at least about 40° C. / sec.

[0186] In some embodiments, the apparatus 1700 may actively cool the substrate by both bringing the substrate close to the faceplate and flowing a cooling gas over the substrate. In some examples, active cooling may be more effective by flowing a cooling gas while the substrate is close to the faceplate. Also, the effectiveness of the cooling gas may depend on the type of gas used.

[0187] Thus, the apparatus provided herein can rapidly heat and cool the substrate. FIG. 19 provides an example of a temperature control sequence. At time 0, the substrate is approximately 20 or 25° C., and the LEDs of the substrate heater provided herein emit visible light having a wavelength between 400 nm and 800 nm to raise the substrate temperature to approximately 400° C. in approximately 30 seconds. This heating was achieved using between 1 kW and 2 kW of heating power, provided by a power supply of approximately 9 kW to the substrate heater. From approximately 30 seconds to approximately 95 seconds, the substrate heater 1722 held the substrate at 400° C. using less power, such as 0.3 to approximately 0.5 kW of heating power, provided by a power supply of approximately 2 kW. From approximately 30 to 60 seconds, the substrate was actively cooled using both a cooling gas (e.g., hydrogen or helium) flowed over the substrate and heat transfer to the faceplate. Once cooled, the substrate heater heated the substrate using between about 10-30 W of heating power provided by a power supply of about 100 W, and maintained its temperature at approximately 70° C. Various processing techniques may use this type of sequence once or repeatedly to process the substrate.

[0188] In some embodiments, the apparatus 1700 may include a mixing plenum to prepare and / or condition the process gases for delivery before reaching the fluid inlet 1770. One or more mixing plenum inlet valves may control the introduction of the process gases into the mixing plenum. In some other embodiments, the gas distribution unit 1710 may include one or more mixing plenums within the gas distribution unit 1710. The gas distribution unit 1710 may also include one or more annular channels fluidly connected to the through-holes 1778, which may distribute the received fluids equally to the through-holes 1778 to provide a uniform flow onto the substrate.

[0189] Apparatus 1700 includes a controller 1731, which may be the same as controller 1666 and may include one or more physical or logical controllers communicatively coupled to the process chambers and capable of controlling the operation of some or all of the process chambers and performing any of the processes described herein.

[0190] FIG. 20 illustrates generally an embodiment of a processing station 2000 that may be used to deposit materials using atomic layer deposition (ALD) and / or chemical vapor deposition (CVD), both of which may be plasma enhanced. For simplicity, the processing station 2000 is illustrated as a stand-alone processing station having a processing chamber body 2002 for maintaining a low pressure environment. However, it will be understood that multiple processing stations 2000 may be included within a common processing tool environment. Additionally, it will be understood that in some embodiments, one or more hardware parameters of the processing station 2000, including those discussed in detail below, may be programmatically adjusted by one or more computer controllers.

[0191] The processing station 2000 is in fluid communication with a reactant delivery system 2001 for delivering process gases to a distribution showerhead 2006. The reactant delivery system 2001 includes a mixing vessel 2004 for formulating and / or conditioning process gases for delivery to the showerhead 2006. One or more mixing vessel inlet valves 2020 may control the introduction of process gases into the mixing vessel 2004. Similarly, a showerhead inlet valve 2005 may control the introduction of process gases to the showerhead 2006.

[0192] Some reactants, such as BTBAS, may be maintained in a liquid state prior to vaporization during and after delivery to the processing station. For example, the embodiment of FIG. 20 includes a vaporization point 2003 for vaporizing liquid reactants provided to the mixing vessel 2004. In some embodiments, the vaporization point 2003 may be a heated vaporizer. The reactant vapor generated by such a vaporizer may condense in the downstream delivery tube. Exposure of incompatible gases to the condensed reactants may generate small particles. These small particles may, for example, clog the tubes, interfere with the operation of valves, or contaminate the substrate. Some approaches to address these issues include sweeping and / or evacuating the delivery tube to remove residual reactants. However, sweeping the tubes may increase the cycle time of the processing station and reduce the throughput of the processing station. Thus, in some embodiments, the delivery tube downstream of the vaporization point 2003 may be heat traced. In some examples, the mixing vessel 2004 may also be heat traced. In one non-limiting example, the pipe downstream of the vaporization point 2003 has an increasing temperature profile from approximately 100° C. to approximately 150° C. at the mixing vessel 2004 .

[0193] In some embodiments, the reactant liquid may be vaporized in a liquid injector. For example, the liquid injector may inject a pulse of liquid reactant into the carrier gas stream upstream of the mixing vessel. In one scenario, the liquid injector may vaporize the reactant by flushing the liquid from high pressure to low pressure. In another scenario, the liquid injector may atomize the liquid into spray droplets that are then vaporized in a heated delivery tube. It will be appreciated that smaller droplets may be vaporized faster than larger droplets, reducing the delay between liquid injection and full vaporization. Faster vaporization may reduce the length of the tube downstream of the vaporization point 2003. In one scenario, the liquid injector may be attached directly to the mixing vessel 2004. In another scenario, the liquid injector may be attached directly to the showerhead 2006.

[0194] In some embodiments, a liquid flow controller upstream of the vaporization point 2003 may be provided to control the mass flow rate of liquid for vaporization and delivery to the processing station 2000. For example, the liquid flow controller (LFC) may include a thermal mass flow meter (MFM) disposed downstream thereof. The plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electronic communication with the MFM. However, stabilizing the liquid flow rate using feedback control may take more than a second. This may prolong the time to dose the liquid reactant. Thus, in some embodiments, the LFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, the LFC may be dynamically switched from a feedback control mode to a direct control mode by disabling the sensing tube and the PID controller of the LFC.

[0195] The showerhead 2006 distributes process gases to the substrate 2012. In the embodiment shown in Figure 20, the substrate 2012 is shown disposed below the showerhead 2006 and resting on a pedestal 2008. It will be understood that the showerhead 2006 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gases to the substrate 2012.

[0196] In some embodiments, a microvolume 2007 is located below the showerhead 2006. By performing ALD and / or CVD processes in the microvolume rather than in the entire volume of the processing station, one can, for example, reduce reactant exposure and sweep times, reduce time to change processing conditions (e.g., pressure, temperature, etc.), and limit exposure of processing station robotics to process gases. Examples of microvolume sizes include, but are not limited to, volumes between 0.1 liters and 2 liters. This microvolume also impacts productivity throughput. While the deposition rate per cycle is reduced, cycle time is also reduced at the same time. In certain cases, the latter effect is dramatic enough to improve the overall throughput of the module for a given target film thickness.

[0197] In some embodiments, the pedestal 2008 may be raised or lowered to expose the substrate 2012 to the micro-volume 2007 and / or to change the volume of the micro-volume 2007. For example, during a substrate transfer phase, the pedestal 2008 may be lowered to allow the substrate 2012 to be loaded onto the pedestal 2008. During a deposition process, the pedestal 2008 may be raised to position the substrate 2012 within the micro-volume 2007. In some embodiments, the micro-volume 2007 may completely surround the substrate 2012 as well as a portion of the pedestal 2008 to form a region of high flow impedance during the deposition process.

[0198] Optionally, the pedestal 2008 may be lowered and / or raised during portions of the deposition process to adjust process pressure, reactant concentration, etc., within the micro-volume 2007. In one scenario where the process chamber body 2002 remains at a base pressure during the deposition process, lowering the pedestal 2008 may allow evacuation of the micro-volume 2007. Example ratios of the micro-volume to the process chamber volume include, but are not limited to, volume ratios between 1:2000 and 1:10. It will be appreciated that in some embodiments, the pedestal height may be programmatically adjusted by a suitable computer controller.

[0199] In another scenario, adjustment of the height of the pedestal 2008 may allow for variation of plasma density during plasma activation and / or processing cycles involved in a deposition process. At the end of the deposition processing stage, the pedestal 2008 may be lowered in a separate substrate transfer stage to allow removal of the substrate 2012 from the pedestal 2008.

[0200] While the micro-volume modifications described herein refer to a height adjustable pedestal, it will be understood that in some embodiments the position of the showerhead 2006 may be adjusted relative to the pedestal 2008 to vary the volume of the micro-volume 2007. Additionally, it will be understood that the vertical position of the pedestal 2008 and / or the showerhead 2006 may be altered by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 2008 may include a rotation axis for rotating the orientation of the substrate 2012. It will be understood that in some embodiments, one or more of these adjustments may be programmatically performed by one or more suitable computer controllers.

[0201] In some embodiments, the process chamber of FIG. 2000 does not use plasma for ALD deposition and therefore does not have plasma-related equipment. In some other embodiments, plasma may be used or the reactor may have such plasma-related equipment. For example, as shown in FIG. 20, the showerhead 2006 and pedestal 2008 are in electrical communication with an RF power supply 2014 and a matching network 2016 to power the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 2014 and the matching network 2016 may be operated at any suitable power to generate a plasma having a desired composition of radical species. Examples of suitable powers are given above. Similarly, the RF power supply 2014 may provide RF power of any suitable frequency. In some embodiments, the RF power supply 2014 may be configured to control the high frequency RF power source and the low frequency RF power source independently of each other. Examples of low frequency RF frequencies include, but are not limited to, frequencies between 50 kHz and 2000 kHz. Examples of high frequency RF frequencies include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz. It will be understood that any suitable parameters may be discretely or continuously adjusted to provide plasma energy for surface reactions. In one non-limiting example, plasma power may be provided in an intermittent pulsed manner to reduce ion bombardment on the substrate surface compared to a continuously powered plasma.

[0202] In some embodiments, the plasma may be monitored in-situ by one or more plasma monitors. In one scenario, the plasma power may be monitored by one or more voltage, current sensors (e.g., VI probes). In another scenario, the plasma density and / or process gas concentration may be measured by one or more optical emission spectroscopy (OES) sensors. In some embodiments, one or more plasma parameters may be programmatically adjusted based on measurements from such in-situ plasma monitors. For example, OES sensors may be used in a feedback loop to provide programmatic control of the plasma power. It will be appreciated that in some embodiments, other monitors may be used to monitor the plasma or other process characteristics. Examples of such monitors include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

[0203] In some embodiments, the plasma may be controlled via input / output control (IOC) sequence instructions. In one example, instructions for setting plasma conditions for a plasma processing step may be included in a corresponding plasma activation recipe step in a deposition processing recipe. In some cases, steps in a process recipe may be sequenced such that all instructions for a deposition processing step are executed simultaneously with that processing step. In some embodiments, instructions for setting one or more plasma parameters may be included in a recipe step that precedes a plasma process step. For example, a first recipe step may include instructions for setting flow rates of inert and / or reactant gases, instructions for setting a plasma generator to a power setting, and a time delay instruction for the first recipe step. A subsequent second recipe step may include instructions for enabling the plasma generator and a time delay instruction for the second recipe step. A third recipe step may include instructions for disabling the plasma generator and a time delay instruction for the third recipe step. It will be appreciated that these recipe steps may be further subdivided and / or repeated in any suitable manner within the scope of the present disclosure.

[0204] In some deposition processes, the plasma strike lasts for durations on the order of a few seconds or more. In certain implementations, much shorter plasma strikes may be used. These may be on the order of 10 ms to 1 second, typically about 20 to 80 ms, with one specific example being 50 ms. Such very short RF plasma strikes require very rapid stabilization of the plasma. To achieve this, the plasma generator may be configured such that the impedance match is preset to a particular voltage while the frequency is allowed to vary. Conventionally, high frequency plasmas are generated with an RF frequency of about 13.56 MHz. In various embodiments disclosed herein, the frequency is allowed to vary to values ​​different from this standard value. By allowing the frequency to vary while the impedance match is fixed at a predetermined voltage, the plasma can stabilize more quickly, a result that can be important when using very short plasma strikes associated with certain deposition cycles.

[0205] In some embodiments, the pedestal 2008 may be temperature controlled via a heater 2010. In some embodiments, the heater 2010 may be the same as the heater unit described above and shown in FIGS. 16-18, such as a heater unit including multiple LEDs used to heat the wafer. Additionally, in some embodiments, pressure control for the deposition processing station 2000 may be provided by a butterfly valve 2018. As shown in the embodiment of FIG. 20, the butterfly valve 2018 throttles and regulates the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the processing station 2000 may be adjusted by varying the flow rate of one or more gases introduced to the processing station 2000.

[0206] Although FIG. 20 is illustrated as a single station, it will be understood that a processing chamber may have multiple such stations sharing a gas delivery system or other equipment. For example, as shown in FIGS. 10 and 12, chambers 1004, 1006, 1202, and 1204 include four processing stations. Each station may include any and all of the features described with respect to the single stations in FIGS. 16-18, and 20. The stations of chambers 1004 and 1202 may be used for etching, and the stations of chambers 1006 and 1204 may be used for depositing material onto a wafer. For example, each station of chambers 1004 and 1202 may be used to perform thermal etching, such as thermal ALE, on a wafer held in a wafer holder, such as a pedestal, at the particular processing station. Similarly, each station of chambers 1006 and 1204 may be used to perform deposition, such as ALD and thermal ALD, on a wafer held in a wafer holder, at the particular processing station. Other similar multi-station processing apparatus may have more or fewer processing stations depending on the implementation and, for example, the desired level of parallel wafer processing, size / space constraints, cost constraints, and the like.

[0207] In each of several processing chambers, such as deposition chambers 1006 and 1204 in FIGS. 10 and 12, RF subsystems 1090 and 1290 may generate and deliver RF power to integrated circuit fabrication chambers 1006 and 1204 via a radio frequency input port. In certain embodiments, integrated circuit fabrication chambers 1006 and 1204 may include input ports in addition to the radio frequency input port. Thus, integrated circuit fabrication chambers 1006 and 1204 may utilize eight RF input ports. In certain embodiments, processing stations 1082A-D and 1282A-D of integrated circuit fabrication chambers 1006 and 1204 may utilize first and second input ports, respectively, where the first input port may deliver a signal having a first frequency and the second input port may deliver a signal having a second frequency. The use of dual frequencies may result in enhanced plasma characteristics.

[0208] As mentioned above, a system controller may be employed for the tools described herein to control process conditions during etching and / or deposition. The controllers 1029 of FIG. 10, 1229 of FIG. 12, and 1666 of FIG. 16, for example, typically include one or more memory devices and one or more processors. The controller 1029 may control all of the operations of the tools 1000 and / or 1200. In some implementations, the controller 1029 and / or 1229 is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal and gas flow systems). These systems may be integrated with electronics to control the operation of those systems before, during, and after processing of a semiconductor wafer or substrate.

[0209] The controller is configured to perform any of the techniques described above. For example, referring to the apparatus 1000 of FIG. 10 or the apparatus 1200 of FIG. 12 and the technique of FIG. 1, in some embodiments, the controller 1029 and / or 1229 is configured to bring (i.e., heat) a wafer located on the substrate support feature to a first temperature by the substrate heating unit and to flow a first process gas to the wafer by the process gas unit. As described above, the first process gas is configured to modify one or more surface layers of chalcogenide on the wafer by chemisorption, in some embodiments without the use of plasma, while the wafer is maintained at the first temperature. The controller is further configured to flow a second process gas onto the substrate by the process gas unit to remove the modified layer of chalcogenide, as described herein. Some implementations include the controller depositing one or more layers of encapsulant material onto the wafer, as described herein. The controller is further configured to control a wafer transport unit, including any of the robotic arms, to transport the wafer between any of the processing stations, and to control pressure units 1016 and 1216, which may include one or more vacuum pumps, to control the pressure within the tools and chambers.

[0210] Although the subject matter disclosed herein has been particularly described with respect to the illustrated embodiments, it will be understood that various changes, modifications, and adaptations may be made based on this disclosure and are intended to be within the scope of the invention. It will be understood that the description is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the scope of the claims.

Claims

1. 1. A method comprising: providing a wafer having a layer of chalcogenide material in a processing chamber; heating the wafer to a first temperature; while the wafer is at the first temperature, etching the layer of chalcogenide material by flowing a first chemical species over the wafer comprising a fluoride or a chloride to modify a surface of the layer of chalcogenide material to produce a modified layer of the chalcogenide material, and flowing a second chemical species over the wafer comprising a compound having a central atom that is aluminum, boron, silicon, or germanium and at least one chlorine to remove the modified layer of chalcogenide material without the use of a plasma; A method comprising:

2. 10. The method of claim 1, The method, wherein the chalcogenide material comprises a phase change material.

3. 10. The method of claim 1, The method wherein the chalcogenide material comprises germanium antimony tellurium.

4. 10. The method of claim 1, The method, wherein the first chemical species comprises hydrogen fluoride, nitrogen fluoride, sulfur fluoride, xenon fluoride, hydrogen chloride, sulfur chloride, or nitrogen chloride.

5. 10. The method of claim 1, The method, wherein the compound further comprises one or more of hydrogen, a methyl group, an ethyl group, or a plurality of chlorine atoms.

6. 10. The method of claim 1, The method wherein the compound comprises one of dimethylaluminum chloride and trimethylaluminum.

7. 7. The method of any one of claims 1 to 6, The method further comprising, after said etching, depositing an encapsulant material over said etched layer of chalcogenide material.

8. 7. The method of any one of claims 1 to 6, the wafer further comprises a plurality of layers of chalcogenide material; the etching step includes flowing the first chemical species onto the wafer while the wafer is at the first temperature to modify a surface of the multiple layers of chalcogenide material to produce a modified layer of the chalcogenide material, and flowing the second chemical species onto the wafer to remove the modified layer of chalcogenide material without the use of a plasma, thereby simultaneously etching the multiple layers of chalcogenide material.

9. 7. The method of any one of claims 1 to 6, the modifying includes flowing a first process gas containing the first chemical species; the removing includes flowing a second process gas containing the second chemical species; method.

10. 7. The method of any one of claims 1 to 6, The method, wherein the etching includes flowing a process gas containing both the first chemical species and the second chemical species over the wafer.

11. 7. The method of any one of claims 1 to 6, The method, wherein said modifying comprises using a plasma.

12. 12. The method of claim 11, The method, wherein the plasma is a remote plasma.

13. 12. The method of claim 11, The method wherein the plasma is generated in the processing chamber.

14. 7. The method of any one of claims 1 to 6, The modifying step does not use plasma.

15. 7. The method of any one of claims 1 to 6, The method, wherein said modifying and said removing occur while said wafer is maintained at substantially the same temperature.

16. 7. The method of any one of claims 1 to 6, the modifying occurs while the wafer is maintained at the first temperature; the removing occurs while the wafer is maintained at a second temperature different from the first temperature. method.

17. 17. The method of claim 16, The method further comprising, after said modifying, heating said wafer from said first temperature to said second temperature, said second temperature being higher than said first temperature.

18. 17. The method of claim 16, The method further comprising, after said modifying, cooling said wafer from said first temperature to said second temperature, said second temperature being lower than said first temperature.

19. 7. The method of any one of claims 1 to 6, the modifying occurs while the processing chamber is maintained at a first pressure; the removing occurs while the processing chamber is maintained at a second pressure different from the first pressure. method.

20. 1. An apparatus for semiconductor processing, comprising: a first processing chamber including a first interior and a first processing station, the first processing station having a first wafer support configured to support a wafer in the first interior and a first wafer heating unit configured to heat the wafer supported by the first wafer support; 1. A process gas unit comprising: flowing a first chemical species comprising a fluoride or a chloride onto the wafer at the first processing station in the first processing chamber; a process gas unit configured to flow a second chemical species onto the wafer at the first processing station within the first processing chamber, the second chemical species including a compound having a central atom that is aluminum, boron, silicon, or germanium and at least one chlorine atom; A controller having instructions, the instructions comprising: providing the wafer having a layer of chalcogenide material to the first processing station within the first processing chamber; causing the first wafer heating unit to heat the wafer to a first temperature; a controller configured to etch the layer of chalcogenide material on the wafer by causing the process gas unit to flow the first chemical species onto the wafer at the first processing station within the first processing chamber while the wafer is at the first temperature, thereby modifying a surface of the layer of chalcogenide material to produce a modified layer of chalcogenide material, and causing the process gas unit to flow the second chemical species onto the wafer at the first processing station within the first processing chamber, thereby removing the modified layer of chalcogenide material without the use of a plasma; An apparatus comprising:

21. 21. The apparatus of claim 20, the first processing chamber further includes a second processing station within the first interior, the second processing station having a second wafer support configured to support a wafer within the first interior and a second wafer heating unit configured to heat the wafer supported by the second wafer support; The controller is further configured with instructions, the instructions comprising: providing a second wafer having a layer of chalcogenide material in the second processing station within the first processing chamber; causing the second wafer heating unit to heat the second wafer to a first temperature; while the wafer is at the first temperature, the second processing station within the first processing chamber is configured to modify a surface of the layer of chalcogenide material to produce a modified layer of chalcogenide material by causing the process gas unit to flow the first chemical species onto the second wafer at the second processing station within the first processing chamber, and to remove the modified layer of chalcogenide material without the use of a plasma by causing the process gas unit to flow the second chemical species onto the wafer at the second processing station within the first processing chamber. Device.

22. 22. The apparatus of claim 21, The etching of the layer of chalcogenide material on the wafer and the etching of the layer of chalcogenide material on the second wafer are performed simultaneously.

23. 21. The apparatus of claim 20, a second processing chamber including a second interior, a second wafer support configured to support a wafer in the second interior, and a second wafer heating unit configured to heat the wafer supported by the second wafer support; a wafer transfer unit configured to transfer the wafer between the first processing chamber and the second processing chamber; Furthermore, the process gas unit is further configured to flow a third chemical species comprising a precursor onto the wafer in the second processing chamber; The controller further includes instructions, the instructions comprising: causing the wafer transfer unit to transfer the wafer from the first processing chamber to the second processing chamber; configured to deposit an encapsulant material on the wafer in the second processing chamber by causing the process gas unit to flow the precursor over the wafer; Device.

24. 21. The apparatus of claim 20, the process gas unit is further configured to flow a third chemical species comprising hydrogen and oxygen over the wafer in the first processing chamber; the controller further includes instructions configured to deposit an encapsulant material on the wafer in the first processing chamber by causing the process gas unit to flow the second chemical species and the first chemical species over the wafer. Device.

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