Modeling thermal donor formation and target resistivity for single crystal silicon ingot production

Abstract

A method for manufacturing a single crystal silicon ingot is disclosed. The method may include modeling the formation of thermal donors and target resistivity during downstream annealing processes, such as during subsequent device fabrication, such as fabrication of an interposer device. The model may output a target range of wafer resistivity before annealing. The manufacturing process of the single crystal silicon ingot may be modeled to determine a counter doping schedule to achieve the target range of wafer resistivity before annealing over a longer length of the ingot body.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 254,337, filed October 11, 2021, which is incorporated by reference in its entirety. [Technical field]

[0002] The field of the disclosure relates to methods for producing single crystal silicon ingots, and in particular to methods for modeling the formation of thermal donors and changes in resistivity during downstream annealing steps. [Background technology]

[0003] An interposer is a mechanical platform that connects circuitry between adjacent active devices. Interposer technology has enabled a cost-effective solution for 2.5D integration in integrated circuits and packaging. Interposers reduce interconnect lengths for increased device speed via through-silicon vias (TSVs), reduce package form factors, and enable heterogeneous device integration.

[0004] Single crystal silicon is commonly used as the substrate for interposers because it has a relatively small thermal expansion coefficient mismatch with silicon-based device components. Thermomechanical stresses generated during silicon processing are small, and via technology in silicon is well established. Passive devices such as radio frequency (RF) circuits can be integrated relatively easily.

[0005] Single crystal silicon is commonly prepared by the so-called Czochralski (CZ) process: a seed crystal is immersed in molten silicon and grown by slowly pulling an ingot out of the melt. The resulting ingot may then be sliced ​​into wafers that can be used as interposer substrates.

[0006] Silicon interposer applications such as RF involve p-type silicon substrates with high resistivity (e.g., >75 Ω·cm, >300 Ω·cm, or even >1000 Ω·cm). Maintaining a relatively high resistivity for RF can be difficult if the device undergoes downstream low-temperature processes (e.g., annealing at 300°C to 500°C). Oxygen incorporated into the wafer can form electrically active oxygen clusters called “thermal double donors” (TDD) or simply “thermal donors” (TD) in this temperature range. The rate of thermal donor generation is highly dependent on both the temperature and the interstitial oxygen concentration. Depending on the temperature and time range over which the interposer is fabricated, oxygen-related thermal donors can shift resistivity beyond acceptable limits or even cause type shift (i.e., from P-type to N-type). In some cases, the productivity of the crystal (measured by prime usable length) can be affected to ensure that resistivity remains within specifications even with longer downstream anneal times.

[0007] A need exists for a method of adjusting single crystal silicon ingot production to increase the prime portion of the ingot and / or to account for downstream resistivity shifts due to the formation of thermal donors.

[0008] This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to better understand the various aspects of the present disclosure. As such, it should be understood that these descriptions are read in this light, and not as admissions of prior art. Summary of the Invention

[0009] One aspect of the disclosure relates to a method for producing a single crystal silicon ingot from a silicon melt held in a crucible. A target resistivity after annealing of a wafer sliced ​​from the ingot is determined. Thermal donors generated during subsequent annealing of the wafer sliced ​​from the ingot are modeled to determine a target range of wafer resistivity before annealing. A dopant profile of the melt during ingot growth is modeled and a counterdoping schedule is determined such that at least a portion of the ingot falls within the target wafer resistivity range before annealing. Polycrystalline silicon is added to the crucible. The polycrystalline silicon is heated to form a silicon melt in the crucible. A first dopant is added to the crucible. The first dopant is p-type or n-type. The melt is contacted with a seed crystal. The seed crystal is pulled from the melt to form a single crystal silicon ingot. A second dopant is added to the silicon melt while forming the single crystal silicon ingot based on the counterdoping schedule. The second dopant is p-type or n-type and is of a different type than the type of the first dopant.

[0010] There are various refinements of the features noted in relation to the above-mentioned aspects of the disclosure. Additional features may be incorporated into the above-mentioned aspects of the disclosure as well. These refinements and additional features may exist individually or in any combination. For example, the various features described below in relation to any of the illustrated embodiments of the disclosure may be incorporated alone or in any combination into any of the above-mentioned aspects of the disclosure. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of a method for producing a single crystal silicon ingot. [Diagram 2] FIG. 1 is a schematic side view of a pulling apparatus for forming a single crystal silicon ingot. [Diagram 3] 2 is a block diagram of a computing device for use in the method of FIG. 1. [Figure 4]1 is a graph showing final resistivity as a function of starting resistivity for a 5 hour 350° C. anneal for wafers having various oxygen concentrations. [Diagram 5] 1 is a graph showing final resistivity as a function of starting resistivity for a 10 hour 350° C. anneal for wafers having various oxygen concentrations. [Figure 6] 1 is a graph showing final resistivity as a function of starting resistivity for a 20 hour 350° C. anneal for wafers having various oxygen concentrations. [Figure 7] 1 is a graph showing final resistivity as a function of starting resistivity for a 40 hour 350° C. anneal for wafers having various oxygen concentrations. [Figure 8] 1 is a graph showing final resistivity as a function of starting resistivity for a 5 hour 400° C. anneal for wafers having various oxygen concentrations. [Figure 9] 1 is a graph showing final resistivity as a function of starting resistivity for a 10 hour 400° C. anneal for wafers having various oxygen concentrations. [Figure 10] 1 is a graph showing final resistivity as a function of starting resistivity for a 20 hour 400° C. anneal for wafers having various oxygen concentrations. [Figure 11] 1 is a graph showing final resistivity as a function of starting resistivity for a 40 hour 400° C. anneal for wafers having various oxygen concentrations. [Figure 12] 1 is a graph showing final resistivity as a function of starting resistivity for a 5 hour 450° C. anneal for wafers having various oxygen concentrations. [Figure 13] 1 is a graph showing final resistivity as a function of starting resistivity for a 10 hour 450° C. anneal for wafers having various oxygen concentrations. [Figure 14] 1 is a graph showing final resistivity as a function of starting resistivity for a 20 hour 450° C. anneal for wafers having various oxygen concentrations. [Figure 15]1 is a graph showing final resistivity as a function of starting resistivity for wafers having various oxygen concentrations annealed at 450° C. for 40 hours. [Figure 16] 1 is a graph showing the variation of resistivity (Ω·cm) over the length of the ingot body for a p-type boron doped ingot. [Figure 17] 1 is a graph showing final resistivity as a function of starting resistivity for 8 nppma wafers annealed at 400° C. for 5, 10, 20, and 40 hours. [Figure 18] 1 is a graph showing the change in resistivity over the length of the ingot body for p-type boron doped ingots of 100, 150, and 200 Ω·cm seeded end ingots. [Figure 19] 1 is a graph showing the change in resistivity over the length of the ingot body for a p-type boron doped ingot with a seed end resistivity of 100 Ω·cm due to two phosphorus counterdoping cycles. [Figure 20] 1 is a graph showing the final resistivity as a function of starting resistivity for wafers annealed for 5 hours, 10 hours, and 40 hours (6 nppma, 5 nppma, 4 nppma, respectively). [Figure 21] 1 is a graph showing the change in resistivity over the length of the ingot body for p-type boron doped ingots with seed end oxygen of 320, 380 and 420 Ω·cm. [Figure 22] 1 is a graph showing the change in resistivity over the length of the ingot body for a p-type boron doped ingot with a seed end resistivity of 340 Ω·cm that has been subjected to three phosphorus counterdoping cyclos.

[0012] Corresponding reference characters indicate corresponding parts throughout the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Provisions of the present disclosure relate to a method for producing a monocrystalline silicon ingot. Wafers sliced ​​from the ingot are annealed downstream, such as during device fabrication (e.g., during the formation of an interposer device). An exemplary method of the present disclosure includes determining a target resistivity after annealing of the wafer sliced ​​from the ingot. The target resistivity after annealing is the desired resistivity of the silicon wafer (or chips, if the wafer is cut into chips before annealing) on ​​which the devices are built. Thermal donors (also referred to herein as "thermal dual donors") created during subsequent annealing of the wafer sliced ​​from the ingot are modeled to determine the target resistivity (pre-anneal resistivity) of the wafer formed from the ingot. The melt may then be systematically doped (e.g., counter-doped) so that a greater portion of the ingot has the target resistivity before annealing.

[0014] One embodiment of the method of the present disclosure is shown in FIG. 1. In a first step 100, a target resistivity after annealing of a wafer sliced ​​from an ingot is determined. The target resistivity may be the desired resistivity at which a subsequent device will operate (i.e., of the single crystal silicon substrate portion of the device). The target resistivity is the resistivity after one or more anneals of the wafer have been performed, such as during device fabrication. The target resistivity may be a minimum resistivity, a maximum resistivity, or a range of resistivities. In some embodiments, such as an interposer device, the desired resistivity of the device (i.e., after fabrication heat treatments) may be at least 75 Ω·cm, at least 300 Ω·cm, or at least 1,000 Ω·cm (e.g., 75 Ω·cm to 5,000 Ω·cm, or 100 Ω·cm to 1,500 Ω·cm). In other embodiments, even higher resistivities may be used, such as up to 20,000 Ω·cm.

[0015] In a second step 200, the amount of thermal donors generated during subsequent annealing of wafers sliced ​​from the ingot is modeled. By modeling the thermal donors (which act as electron donors similar to n-type dopants), the change in resistivity caused by thermal donor generation during subsequent annealing can be determined. Knowing the change in resistivity during subsequent annealing can determine the target range of resistivity (e.g., minimum resistivity, maximum resistivity, or range of resistivity) for the wafer before annealing. For example, for a p-type substrate, the target resistivity before annealing is equal to the target resistivity after annealing minus the increase in resistivity due to thermal donor formation during annealing. For an n-type substrate, the target resistivity before annealing is equal to the target resistivity after annealing plus the decrease in resistivity due to thermal donor formation during annealing.

[0016] Any suitable model can be used to determine the change in resistivity due to the generation of thermal donors during annealing. For example, the model is described in Voronkov et al., "Properties of Fast-Diffusing Oxygen Species in Silicon Deduced from the Generation Kinetics of Thermal Donors", Solid State Phenomena, Vols. 156-158 (2010), pp.115-122. Calculations may be based on other published studies of thermal donor formation, such as Londos et al., "Effect of Oxygen Concentration on the Kinetics of Thermal Donor Formation in Silicon at Temperatures between 350 and 500° C.", Applied Physics Letters, Vol. 62, 1525 (1993), which is also incorporated herein by reference for all relevant consistent purposes. In some embodiments, the model may be based on empirical data regarding the change in resistivity that occurs during annealing.

[0017] In some embodiments, anneal and / or substrate related inputs 210 can be input into the model to determine the change in resistivity that occurs during thermal donor formation and / or annealing. For example, suitable inputs 210 include the oxygen concentration of the ingot / wafer (which may be based on customer specifications and the capabilities of the ingot growth system), anneal temperature, anneal time, and starting resistivity and type. The model can output the number of thermal donors created, which can be used to determine the change in resistivity and type caused by annealing. Alternatively or additionally, the model can output the change in resistivity during annealing, or the final resistivity and type after annealing. The change in resistivity due to annealing is used to determine the target range of wafer resistivity before annealing.

[0018] In accordance with embodiments of the present disclosure, the details of the downstream anneal input into the model can be selected based on the manufacturing method of the downstream device (e.g., an interposer device). In some embodiments, the subsequent anneal is at a temperature of at least 300° C., at least 350° C., at least 400° C., at least 450° C., at least 500° C., or between 300° C. and 500° C. The length of the anneal can be at least 5 hours, at least 10 hours, or at least 20 hours (e.g., 5-40 hours).

[0019] In step 300, the dopant profile of the melt during ingot growth is modeled. The dopant profile is modeled to determine a counterdoping schedule that maximizes the length of the ingot body that has a resistivity within a target range of the wafer resistivity before annealing. For example, in a p-type doped region using boron as a dopant, the resistivity of the melt may decrease over time due to the accumulation of boron in the melt due to the segregation coefficient of boron. By modeling the dopant profile, the counterdoping schedule may be determined. In some embodiments (e.g., interposer applications), the counterdoping schedule consists of adding an amount of an n-type dopant, such as phosphorus, to the melt during ingot growth to compensate for the accumulation of boron. For example, phosphorus may be added in one, two, three, four, or five or more cycles during ingot growth. The model used to determine the counterdoping schedule may be based on a known relationship between dopant amount and resistivity. Resistivity is expressed as a function of the concentration of the dopant element by the following relationship: Resistivity=1 / (nqu) (Equation 1) where n is the number of charge carriers, q is the elementary Coulomb charge, and u is the mobility of the charge carriers. Typically, the dopants are considered to be fully ionized, and n can be taken to be equal to the concentration of the desired dopant.

[0020] Since more than one element can be present as a donor or acceptor, the net majority of carriers can be calculated as an absolute value as follows: n net =|n donors -n acceptors | (Equation 2). When the number of donors exceeds the number of acceptors, the resistivity is calculated as follows: Resistivity=(n net qu e’ ) (Formula 3) Here, e’is the mobility of electrons. Conversely, if the number of donors is less than the number of acceptors, the resistivity is calculated as Resistivity=1 / (n net qu h° ) (Equation 4) Here, u h° is the mobility of holes.

[0021] Inputs 310 to the model for determining the counterdoping schedule include the amount of primary or "first" dopant (e.g., boron) in the melt, melt impurities (e.g., background impurities from charge), initial silicon charge, selected counter dopant, counter dopant feed rate (e.g., as a function of body length), top and taper weights, and body diameter.

[0022] The models used in step 200 to determine the amount of thermal donors generated during the subsequent anneal and / or the change in resistivity during anneal, and the models used in step 300 to determine the dopant profile of the melt during ingot growth and to determine the counterdoping schedule, may each be executed by a computing system, such as a computer system including a processor and a memory.

[0023] As used herein, a processor may include any programmable system, including systems that use microcontrollers, reduced instruction set circuits (RISC), application specific integrated circuits (ASICs), logic circuits, and other circuits or processors capable of performing the functions described herein. The above examples are illustrative and thus are not intended to limit in any way the definition and / or meaning of the term "processor."

[0024] A database associated with the model may be stored in memory. As used herein, the term "database" may refer to a body of data, a relational database management system (RDBMS), or both. As used herein, a database may include any collection of data including hierarchical databases, relational databases, flat file databases, object-relational databases, object-oriented databases, and any other structured collection of records or data stored in a computer system. The above examples are illustrative and do not limit the definition or meaning of the term database. Examples of RDBMS include, but are not limited to, Oracle® Database, MySQL®, IBM® DB2, Microsoft® SQL Server, Sybase® PostgreSQL, and the like. However, any database that enables the systems and methods described herein may be used. (Oracle is a registered trademark of Oracle Corporation, Redwood Shores, California; IBM is a registered trademark of International Business Machines Corporation, Armonk, New York; Microsoft is a registered trademark of Microsoft Corporation, Redmond, Washington; and Sybase is a registered trademark of Sybase, Dublin, California.)

[0025] In another embodiment, a computer program is provided, the program being embodied on a computer readable medium. In an exemplary embodiment, the system runs on a single computer system without requiring connection to a server computer. In a further exemplary embodiment, the system runs on a Windows environment (Windows is a registered trademark of Microsoft Corporation, Redmond, Washington). In yet another embodiment, the system runs on a mainframe environment and a UNIX server environment (UNIX is a registered trademark of X / Open Company Limited, Reading, Berkshire, England). In a further embodiment, the system runs on an iOS environment (iOS is a registered trademark of Cisco Systems, Inc., San Jose, California). In yet another embodiment, the system runs on a Mac OS environment (Mac OS is a registered trademark of Apple Inc., Cupertino, California). In yet another embodiment, the system runs on an Android OS (Android is a registered trademark of Google, Inc., Mountain View, California). In another embodiment, the system runs on a Linux OS (Linux is a registered trademark of Linus Torvalds, Boston, Massachusetts). The application is flexible and designed to run in a variety of different environments without compromising its primary functionality. In some embodiments, the system includes multiple components distributed across multiple computing devices. One or more components are in the form of computer-executable instructions embodied in a computer-readable medium. The system and process are not limited to the specific embodiments described herein. In addition, each system component and each process can be implemented separately and independently from other components and processes described herein. Each component and each process can also be used in combination with other assembly packages and processes.

[0026] The systems and processes are not limited to the specific embodiments described herein. Furthermore, each system component and each step can be performed separately and independently from other components and steps described herein. Each component and each step can also be used in combination with other assembly packages and steps.

[0027] In some embodiments, each model used in steps 200, 300 (FIG. 1) executes on an exemplary computing device 400 (FIG. 3). Computing device 400 includes a processor 402, memory 404, media output components 406, input devices 408, and a communications interface 410. Other embodiments include different components, additional components, and / or do not include all of the components shown in FIG. 3. Computing device 400 can be used, for example, to receive and process data (e.g., inputs 210, 310 described herein) and perform thermal donor and / or crystal growth simulations.

[0028] The processor 402 is configured to execute instructions. In some embodiments, the executable instructions are stored in the memory 404. The processor 402 may include one or more processing units (e.g., a multi-core configuration). The term processor, as used herein, refers to a central processing unit, a microprocessor, a microcontroller, a reduced instruction set circuit (RISC), an application specific integrated circuit (ASIC), a programmable logic circuit (PLC), and any other circuit or processor capable of performing the functions described herein. The above is exemplary and thus is not intended to limit the definition and / or meaning of the term "processor."

[0029] The memory 404 stores non-transient, computer-readable instructions for carrying out the techniques described herein. Such instructions, when executed by the processor 402, cause the processor 402 to carry out at least a portion of the methods described herein. In some embodiments, the memory 404 stores computer-readable instructions for providing a user interface to a user via the media output component 406 and receiving and processing input from the input device 408. The memory 404 may include, but is not limited to, random access memory (RAM), such as dynamic RAM (DRAM) or static RAM (SRAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and non-volatile RAM (NVRAM). Although illustrated as separate from the processor 402, in some embodiments the memory 404 is combined with the processor 402, such as in a microcontroller or microprocessor, but may still be referred to separately. The above memory types are exemplary and therefore not limiting of the types of memory that can be used to store a computer program.

[0030] The media output component 406 is configured to present information to a user (e.g., an operator of a device). The media output component 406 is any component capable of conveying information to a user. In some embodiments, the media output component 406 includes an output adapter, such as a video adapter and / or an audio adapter. The output adapter is operably connected to the processor 402 and operably connected to an output device, such as a display device (e.g., a liquid crystal display (LCD), a light emitting diode (LED) display, an organic light emitting diode (OLED) display, a cathode ray tube (CRT), an "electronic ink" display, one or more light emitting diodes (LEDs)) or an audio output device (e.g., a speaker or headphones).

[0031] The computing device 400 includes or is connected to an input device 408 (e.g., inputs 210, 310 shown in FIG. 1) for receiving input from a user. The input device 408 is any device that allows the computing device 400 to receive analog and / or digital commands, instructions, or other input from a user, including visual, voice, touch, button presses, stylus taps, and the like. The input device 408 may include, for example, a variable resistor, an input dial, a keyboard / keypad, a pointing device, a mouse, a stylus, a touch-sensitive panel (e.g., a touchpad or touch screen), a gyroscope, an accelerometer, a position detector, a voice input device, or any combination thereof. A single component, such as a touch screen, may function as both an output device and an input device 408 for the media output component 406.

[0032] The communication interface allows the computing device 400 to communicate with remote devices and systems, such as remote sensors, remote databases, remote computing devices, and may include multiple communication interfaces for interacting with multiple remote devices or systems. The communication interface may be a wired or wireless communication interface that allows the computing device 400 to communicate with remote devices and systems directly or over a network. The wireless communication interface may include a radio frequency (RF) transceiver, a Bluetooth adapter, a Wi-Fi transceiver, a ZigBee transceiver, a near field communication (NFC) transceiver, an infrared (IR) transceiver, and / or any other device and communication protocol for wireless communication. (Bluetooth is a registered trademark of the Bluetooth Special Interest Group, Kirkland, Washington, and ZigBee is a registered trademark of the ZigBee Alliance, San Ramon, California). The wired communication interface may use any suitable wired communication protocol for direct communication, including, but not limited to, USB, RS232, I2C, SPI, analog, and proprietary I / O protocols. In some embodiments, the wired communication interface includes a wired network adapter that enables the computing device 400 to be coupled to a network, such as the Internet, a local area network (LAN), a wide area network (WAN), a mesh network, and / or any other network for communicating with remote devices and systems over the network.

[0033] The computer systems discussed herein may include additional, fewer, or alternative functionality, including those discussed elsewhere herein. The computer systems discussed herein may include or be implemented via computer-executable instructions stored on a non-transitory computer-readable medium or media.

[0034] In an exemplary embodiment for performing step 200, the computer device 400 includes a model (e.g., simulation) of resistivity change due to thermal donor formation for a range of annealing temperatures and lengths. In an exemplary embodiment for performing step 300, the computer device 400 includes a model (e.g., simulation) of resistivity of an ingot formed from a silicon melt based on initial doping amount (e.g., p-type such as boron) and / or various counter doping amounts.

[0035] Once the counter-doping schedule has been determined, an ingot may be grown in accordance with the counter-doping schedule, step 400. According to an embodiment of the present disclosure, and referring to Figure 2, the ingot is grown by the so-called Czochralski process, in which the ingot is pulled from a silicon melt 44 held in a crucible 22 of an ingot puller 23.

[0036] The ingot puller 23 includes a housing 25 that defines a crystal growth chamber 16 and a pull chamber 20 having a smaller lateral dimension than the growth chamber. The growth chamber 16 has a generally dome-shaped upper wall 45 that transitions from the growth chamber 16 to the narrowed pull chamber 20. The ingot puller 23 includes an inlet port 7 and an outlet port 11 that can be used for the introduction and removal of process gases into and from the housing 25 during crystal growth.

[0037] A crucible 22 in the ingot pulling apparatus 23 contains a silicon melt 44 from which a silicon ingot is pulled. The silicon melt 44 is obtained by melting polycrystalline silicon charged in the crucible 22. The crucible 22 is mounted on a turntable 31 for rotating the crucible about a central longitudinal axis X of the ingot pulling apparatus 23.

[0038] A heating device 39 (e.g., an electrical resistance heater 39) surrounds the crucible 22 to melt the silicon charge to produce a melt 44. The heater 39 may also extend below the crucible as shown in U.S. Pat. No. 8,317,919. The heater 39 is controlled by a control system (not shown) to precisely control the temperature of the melt 44 throughout the pulling process. Insulation (not shown) surrounding the heater 39 can reduce the amount of heat lost through the housing 25. The ingot pulling apparatus 23 can also include a heat shield assembly (not shown) above the melt surface to shield the ingot from the heat of the crucible 22 to increase the axial temperature gradient at the solid-melt interface.

[0039] A pulling mechanism (not shown) is attached to a pull wire 24 that extends downwardly from the mechanism. The mechanism can raise and lower the pull wire 24. The ingot puller 23 may have a pull shaft rather than a wire, depending on the type of puller. The pull wire 24 terminates in a pulling assembly 58 that includes a seed chuck 32 that holds a seed crystal 6 used to grow a silicon ingot. When growing an ingot, the pulling mechanism lowers the seed crystal 6 until it contacts the surface of the silicon melt 44. Once the seed crystal 6 begins to melt, the pulling mechanism slowly pulls the seed crystal through the growth chamber 16 and the pulling chamber 20 to grow a single crystal ingot. A control system controls the rate at which the pulling mechanism rotates the seed crystal 6 and the rate at which the pulling mechanism pulls the seed crystal (i.e., the pull speed v).

[0040] Process gas is introduced into the housing 26 through inlet port 7 and withdrawn through outlet port 12. The process gas creates an atmosphere within the housing, and the melt and the atmosphere form a melt-gas interface. The outlet port 12 is in fluid communication with the ingot puller exhaust system (not shown).

[0041] In this regard, the ingot pulling apparatus 23 shown in FIG. 1 and described herein is exemplary, and other crystal pulling apparatus configurations and arrangements may be used to pull single crystal silicon ingots from a melt, unless otherwise specified.

[0042] According to an embodiment of the present disclosure, polycrystalline silicon is added to a crucible 22. The polycrystalline silicon is heated to liquefy the silicon and form a molten liquid within the crucible. A dopant (e.g., p-type, such as boron) is added to the crucible (either before or after the polycrystalline silicon is melted).

[0043] The methods of the present disclosure provide a method for forming a semiconductor device in which the first dopant is a p-type dopant (e.g., boron, but may also be gallium, aluminum, or indium) and the counterdopant or "second" dopant is an n-type dopant (e.g., in other embodiments, the primary dopant may be one or more n-type dopants and the counterdopant may be a p-type dopant (i.e., the first dopant is p-type or n-type and the second dopant is a type different from the type of the first dopant). If phosphorus is added, any suitable source of phosphorus may be used.

[0044] Counterdoping to achieve a desired pre-anneal resistivity can be used to increase the length of the constant diameter portion or "body" of the ingot that is within the target pre-anneal resistivity range (i.e., the "prime" portion). For example, at least 50% of the length of the constant diameter portion is within the pre-anneal wafer resistivity target range, or at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, or the entire constant diameter portion of the ingot is within the pre-anneal wafer resistivity target range.

[0045] In some embodiments, after the ingot is grown, wafers are sliced ​​from portions of the ingot that are within the pre-anneal wafer resistivity target range. A device, such as an interposer device, is built on the wafer that has been subjected to the thermal treatments described above as part of the device fabrication process. The device may be any device in which a thermal donor is formed as part of the device fabrication process. In some embodiments, the device is an interposer. In some embodiments, the device is any device that includes through silicon via connections (TSVs).

[0046] Compared to traditional methods of forming ingots, the disclosed method has several advantages. By modeling the change in resistivity due to downstream annealing, the target resistivity range before annealing can be determined. This allows a counterdoping schedule to be developed to increase the prime portion of the ingot. This allows the ingot process to be adjusted based on the subsequent anneal temperature and time. This is particularly advantageous for substrates used in interposer devices, since interposer devices are fabricated using methods that involve relatively long anneals (e.g., 5-40 hours) at temperature ranges that can form thermal donors (e.g., 350-500°C). This method allows customers to better define ingot growth specification ranges for improved in-line performance and allows downstream line performance to be tied to wafer integration.

[0047] Working Example The processes of the present disclosure are further illustrated by the following examples, which should not be construed in a limiting sense.

[0048] Example 1: Effect of thermal donors on final resistivity Figures 4-7 show the effect of a 350°C thermal anneal on thermal donor generation in p-type (boron) wafers and the resulting change in resistivity for a given starting resistivity for 5, 10, 20 and 40 hours of annealing (each ingot and wafer of Examples 1 and 2 is p-type and doped with boron). As shown in Figures 4-7, there is little effect on resistivity after annealing, except for the high oxygen wafer (8 nppma) after 40 hours (Figure 7).

[0049] At 400°C (Figures 8-11), more thermal donors are generated, causing type changes in some wafers. Longer anneal times result in resistivity changes even in wafers with lower oxygen content. The post-anneal target resistivity of 300 Ω·cm to 1000 Ω·cm is more constrained at 400°C (vs. 350°C) for a wider oxygen content range. As anneal times increase, viable starting resistivities are suppressed above 4 ppma oxygen, as shown in Figures 8-11. In many cases, the final resistivity not only increases by at least 1,000 Ω·cm, but actually type flips. To avoid resistivity rise and type flip, the usable oxygen window and starting resistivity window are significantly narrower, which may impact the length of the prime portion of the ingot body.

[0050] At 450° C. (FIG. 12-15), more thermal donors are generated, and the starting resistivity and oxygen process window shrink further.

[0051] Example 2: Post-anneal resistivity targets and crystal windows for various oxygen concentrations and annealing and counterdoping techniques As shown in Figures 4-7, for 350 °C, with a target resistivity after annealing (40 hours) of 75-300 Ω·cm, the crystal window is unconstrained down to 6 nppma, but with a final target resistivity of 300-1000 Ω·cm, it is constrained at ~700 Ω·cm at 6 nppma and ~550 Ω·cm at 8 nppma. In either case, if the seed end target is kept below 550 or 700 Ω·cm, the entire crystal can be grown as shown in Figure 16.

[0052] At 400 °C (Fig. 17), it can be seen that for an Oi of 8 nppma, the upper limit of the crystal resistivity after annealing is 75-300 Ω·cm, with 5 h annealing giving ∼200 Ω·cm, 10 h annealing giving ∼150 Ω·cm, 20 h annealing giving ∼100 Ω·cm, and there being virtually no window after 40 h annealing.

[0053] Figure 18 shows the resistivity profiles as a function of solidification fraction (g value) for typical seed-end targets of 100, 150, and 200 Ω·cm for P-type boron-doped crystals. In Figure 18, the upper limit is set to 300 Ω·cm, and the lower limit is set to 75 Ω·cm. Also, as shown in Figure 18, for a seed-end target of 100 Ω·cm (the upper limit for a 400°C 20-hour anneal), the crystal prime length is limited to 72% of the solidification fraction.

[0054] Vapor-phase counterdoping with phosphorus can be used to reset resistivity and ensure full prime length during mid-growth of the ingot, as shown in Figure 19. In this case, vapor-phase phosphorus is counterdoped into the melt close to the crystal growth interface during crystal growth at solidification rates of 46% and 67%. This prophetic example shows that intermittent doping with phosphorus can maintain resistivity within the 75-100 Ω·cm range required to maintain resistivity below 300 Ω·cm after annealing at 400 °C for 20 hours.

[0055] A representative example of the upper crystal resistivity limit as a function of oxygen and time for 450°C is shown in Figure 20. The upper limit of the crystal resistivity after annealing, between 300-1000 Ω·cm, is strongly affected by oxygen and time. As shown in Figure 20, the upper resistivity limit of 6 nppmaOi after 5 hours of annealing is ~380 Ω·cm, the upper resistivity limit of 5 nppmaOi after 10 hours of annealing is ~420 Ω·cm, and the upper resistivity limit of 4 nppmaOi after 40 hours of annealing is ~340 Ω·cm.

[0056] Figure 21 shows the corresponding resistivity profiles (320, 380, and 420 Ω·cm seed ends) of boron-doped crystals grown with normal segregation, including prime lengths (arrows) where the crystal is below the specification limit of 300 Ω·cm.

[0057] Figure 22 shows that gas-phase counterdoping with phosphorus can be effectively used to maintain the resistivity of 4nppmaOi between 340 Ω·cm and the lower limit of 300 Ω·cm when annealed at 450°C for 40 hours. In this example, the prime length is extended from about 32% solidification fraction to nearly the entire n length.

[0058] As used herein, the terms "about," "substantially," "essentially," and "about" when used in conjunction with a range of dimensions, concentrations, temperatures, or other physical or chemical properties or characteristics, are meant to cover variations that may exist at the upper and / or lower limits of the range of the property or characteristic, including, for example, variations due to rounding, measurement methodology, or other statistical variations.

[0059] When introducing elements of the disclosure or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. The use of specific directional terms (e.g., "top," "bottom," "side," etc.) is for convenience of description and does not require a particular orientation of the items described.

[0060] Since various changes may be made in the above structures and methods without departing from the scope of the present disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawings be interpreted as illustrative and not in a limiting sense.

Claims

1. 1. A method for producing a single crystal silicon ingot from a silicon melt held in a crucible, comprising: determining a target resistivity after annealing for wafers sliced ​​from the ingot; modeling thermal donors generated during subsequent annealing of wafers sliced ​​from the ingot to determine a target range for resistivity of the wafers before annealing; modeling the dopant profile of the melt during ingot growth to determine a counterdoping schedule that will result in at least a portion of the ingot being within a target range of resistivity for the wafer before annealing; adding polycrystalline silicon to the crucible; heating the polycrystalline silicon to form a silicon melt in the crucible; adding a first dopant to the crucible, the first dopant being p-type or n-type; contacting the melt with a seed crystal; Pulling the seed crystal from the melt to form a single crystal silicon ingot; and adding a second dopant to the silicon melt during formation of the single crystal silicon ingot according to a counter-doping schedule, the second dopant being p-type or n-type and different from the type of the first dopant; A method comprising:

2. 10. The method of claim 1, wherein modeling thermal donors generated during subsequent annealing of wafers sliced ​​from the ingot includes inputting the temperature of the anneal and the length of the anneal into the model.

3. 3. The method of claim 2, wherein modeling thermal donors generated during subsequent annealing of wafers sliced ​​from the ingot includes inputting the oxygen content of the wafers into the model.

4. 3. The method of claim 2, wherein the annealing is at a temperature of at least 300°C.

5. The method of claim 2, wherein the annealing is at a temperature of at least 450°C.

6. 3. The method of claim 2, wherein the length of the anneal is at least 5 hours.

7. The method of claim 2, wherein the length of the annealing is at least 20 hours.

8. The method of claim 2 , wherein the annealing is part of a device manufacturing process.

9. The method of claim 8 , wherein the device manufacturing process includes forming an interposer device.

10. 10. The method of claim 1, wherein the first dopant is p-type.

11. 11. The method of claim 10, wherein the first dopant is selected from the group consisting of boron, gallium, aluminum, and indium.

12. 11. The method of claim 10, wherein the first dopant is boron.

13. 11. The method of claim 10, wherein the second dopant is n-type and is selected from the group consisting of phosphorus, antimony, and arsenic.

14. 11. The method of claim 10, wherein the second dopant is n-type and is phosphorus.

15. 10. The method of claim 1, wherein the ingot has a constant diameter portion, and at least 50% of the length of the constant diameter portion is within the pre-anneal wafer resistivity target range.

16. The method of claim 1, wherein the ingot has a constant diameter portion, and the entire constant diameter portion of the ingot is within the target range of pre-anneal wafer resistivity.

17. The method of claim 1 , wherein the target resistivity after annealing comprises a minimum resistivity, a maximum resistivity, or a range of resistivities.

18. 20. The method of claim 17, wherein the target resistivity after annealing is at least 75 ohm-cm.

19. Modeling thermal donors generated during subsequent annealing of wafers sliced ​​from the ingot to determine a pre-anneal wafer resistivity target range includes: storing in a memory of a computer system a model for determining a pre-anneal wafer resistivity target range for wafers sliced ​​from the ingot; and running the model using the oxygen content of the wafer, the length of the anneal, and the temperature of the anneal as inputs; 10. The method of claim 1, comprising:

20. modeling the dopant profile of the melt during ingot growth to determine a counterdoping schedule that will result in the ingot being within a pre-anneal wafer resistivity target range; storing the model in a memory of a computer system for determining the dopant profile of the melt during ingot growth; and running the model using the initial doping amount of the melt and the target range of pre-anneal wafer resistivity; 10. The method of claim 1, comprising:

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