Multi-Die Stacking Inductors

Abstract

A microelectronic device having a stacked electromagnetic coil is disclosed. In one example, the microelectronic device can include a first semiconductor element and a second semiconductor element disposed on the first semiconductor element. The microelectronic device can also include an electromagnetic coil. A first portion of the electromagnetic coil and a second portion of the electromagnetic coil can be spaced apart by the first semiconductor element. A first conductive via through the first semiconductor element can connect the first and second portions of the electromagnetic coil. Methods of forming such microelectronic devices are also disclosed.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 262,733, filed October 19, 2021, the contents of which are incorporated by reference in their entirety and for all purposes.

[0002] The field relates to microelectronics, including integrated passive components. [Background technology]

[0003] Passive electronic components such as capacitors, resistors, and inductors play an important role in electronic systems, for example by helping to transform signals and improving the performance of active elements in the system. Summary of the Invention [Problem to be solved by the invention]

[0004] However, when using passive components, it may be necessary to reduce power consumption and undesired coupling. Furthermore, the on-chip integration of passive electronic components may face shape or wiring design constraints. Therefore, there is a continuous need to improve the design of passive electronic components in integrated electronic systems.

[0005] Specific implementations are described below with reference to the drawings, which are given by way of example and not limitation. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of an example embodiment of an electromagnetic coil embedded in a microelectronic device including multiple stacked semiconductor elements. [Diagram 2] 1 is a schematic cross-sectional view of another example embodiment of an electromagnetic coil embedded in a microelectronic device including multiple stacked semiconductor elements. [Diagram 3] 1 is a schematic cross-sectional view illustrating another example embodiment of an electromagnetic coil embedded in a microelectronic device including multiple stacked semiconductor elements. [Figure 4] FIG. 2 is a schematic perspective view of an autotransformer embedded in a microelectronic device including multiple stacked semiconductor elements as shown in FIG. 1, with portions of the structure surrounding the autotransformer coil removed for ease of illustration. [Diagram 5] FIG. 1 is a schematic perspective view of a transformer formed with a primary electromagnetic coil and a secondary electromagnetic coil embedded in a microelectronic device including multiple stacked semiconductor elements. [Figure 6] FIG. 1 is a schematic cross-sectional view of an example embodiment of two electromagnetic coils in a series and parallel arrangement embedded in a microelectronic device including three stacked semiconductor elements. [Figure 7] 1 is a schematic cross-sectional view illustrating the distance between adjacent coils and the thickness of the coil metal wire of an example embodiment of an electromagnetic coil embedded in a microelectronic device including multiple (e.g., four) stacked semiconductor elements. [Figure 8] 2 is a schematic cross-sectional view illustrating the distance between adjacent coils and the thickness of the coil metal wire of an example embodiment of an electromagnetic coil embedded in a single semiconductor element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] On-chip inductors or electromagnetic coils used in integrated circuit technology can be fabricated in the back end of line (BEOL) layers of active devices. Such inductors and / or electromagnetic coils can be formed of thin metal lines, e.g., metal lines having a thickness of about 0.2 μm. Furthermore, in such inductors, the distance between adjacent coil sections is very small because each coil section is formed in a single BEOL layer. Thus, such inductors can suffer from low efficiency due to high electrical resistance caused by the thin metal lines and high self-capacitive coupling between the coil sections, i.e., so-called parasitic capacitance, due to the coil sections being closely packed together. Thus, there is a continuing need for improved on-chip inductor designs.

[0008] Microelectronics including integrated inductors or electromagnetic coils that can achieve high Q (quality factor), low resistance and / or low self-coupling capacitance are disclosed. In one embodiment, an electromagnetic coil is disclosed that spans, for example vertically, multiple back-end (BEOL) layers of a stacked chip. For example, a microelectronic system can include an electromagnetic coil embedded in at least two chips or semiconductor devices, where at least one semiconductor device or semiconductor substrate of the chip is disposed between two adjacent coil portions of the electromagnetic coil. In the context of the present disclosure, a back-end (BEOL) layer can include one or more conductive material layers that provide electrical features and can further include one or more dielectric material layers that insulate the conductive features. In some embodiments, the BEOL layer can be fabricated as part of a wafer fabrication that includes an outermost layer (or a layer close to the outermost layer) in which the coil portion is embedded. In some embodiments, the BEOL layer formed in the wafer fabrication does not include the coil portion, and the coil portion can be added later as part of a routing layer or bonding layer. Thus, in various embodiments, the coil portion(s) can be embedded in any suitable metallization or wiring layer. The dielectric material of the BEOL layer(s) may include inorganic dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like.

[0009] Referring to the figures, Figure 1 is a schematic cross-sectional view of an example microelectronic device 1 having multiple (e.g., three) stacked semiconductor elements (e.g., dies / chips) including a first semiconductor element 10, a second semiconductor element 20, and a third semiconductor element 30. As shown in Figure 1, an inductor or electromagnetic coil 101 has a first metal coil portion 12, a second metal coil portion 22, and a third metal coil portion 32 disposed in a first BEOL layer 16, a second BEOL layer 26, and a third BEOL layer 36, respectively, which are disposed on semiconductor substrates 18, 28, 38 (also referred to herein as semiconductor substrate layers) of the first semiconductor element 10, the second semiconductor element 20, and the third semiconductor element 30, respectively. The semiconductor substrates 18, 28, 38 may comprise any suitable type of semiconductor, such as silicon, and the active sides of the semiconductor elements 10, 20, 30 may have devices (e.g., active circuitry) patterned thereon. Although various embodiments illustrated herein include three semiconductor elements in the stack, any suitable number of semiconductor elements may be provided in the stack (e.g., two, four, five or more).

[0010] In Figure 1, a first semiconductor device 10 disposed at the bottom of the stack has, on a front or active side of the semiconductor device 10, BEOL layers 16 disposed on a first semiconductor substrate layer 18 with a first coil feature 12 disposed in the BEOL layers 16. A second semiconductor device 20 sandwiched in the middle of the stack has, on a front side of the semiconductor device 20, BEOL layers 26 disposed on a second semiconductor substrate layer 28 with a second coil feature 22 disposed in the second BEOL layers 26. A third semiconductor device 30 disposed at the top of the stack may have, on a front side of the semiconductor device 30, BEOL layers 36 disposed on a third semiconductor substrate layer 38 with a third coil feature 32 disposed in the third BEOL layers 36.

[0011] The second semiconductor device 20 further includes a bonding layer 25 disposed on the second BEOL layer 26 on the front side of the device. In various embodiments, the bonding layer 25 can be part of the second BEOL layer 26, such as the outermost layer of the BEOL layer 26. The bonding layer 25 can be directly bonded to the first substrate layer 18 of the first semiconductor device 10 to form a bonding interface 23. The bonding layer 25 can have conductive contact features and nonconductive field regions surrounding the conductive contact features. Each nonconductive field region of the bonding layer 25 can be directly bonded to a nonconductive region of the substrate 18, either to the semiconductor material of the substrate or to a nonconductive bonding layer (not shown) on the substrate. The conductive contact features can be directly bonded to corresponding conductive features of the substrate 18.

[0012] Similarly, the third semiconductor device 30 further includes a bonding layer 35 disposed on a third BEOL layer 36 on a front side of the third device 30. The bonding layer 35 may be directly bonded to the second semiconductor substrate 28 of the second semiconductor device 20 to form a bonding interface 33. The bonding layer 35 may have conductive contact features and non-conductive field regions surrounding the conductive contact features, and each non-conductive field region of the bonding layer 35 may be directly bonded to a non-conductive region of the substrate 28, either to the semiconductor material of the substrate or to a non-conductive bonding layer (not shown) on the substrate. The conductive contact features may be directly bonded to corresponding conductive features of the substrate 28. Although FIG. 1 does not explicitly show a metallization layer on the back side of each semiconductor device 10, 20, 30, it is understood that while a multi-layer BEOL metallization is formed on the front or active side of each device, one or more metallization layers may also be formed on the back side of the device. Also, a bonding layer can be formed on the backside metallization layer(s), or the top backside metallization layer can be a bonding layer having a dielectric material surrounding metal contact features ready to bond directly to the bonding layer of the semiconductor device located directly above. Additionally, although Figure 1 shows the active sides of the devices facing down, it should be understood that the semiconductor devices can be oriented in any suitable manner such that the active side of any semiconductor device faces up or down.

[0013] As shown in FIG. 1 , a first coil portion 12 of an electromagnetic coil 101 having a plurality of metal wires shown in cross section and a second coil portion 22 of the electromagnetic coil 101 having a plurality of metal wires also shown in cross section can be separated by approximately the thickness of the first semiconductor element 10. For example, the first coil portion 12 and the second coil portion 22 can be separated by the thickness of the first semiconductor element 10 plus the thickness of a bonding layer 25 of the second semiconductor element 20. In some embodiments, the thickness of the bonding layer 25 can be substantially less than the thickness of the first substrate 18. A conductive via 14 that passes through the first semiconductor element 10, which can be formed as a through substrate via (TSV), connects the first coil portion 12 of the electromagnetic coil 101 to the second coil portion 22. The electrical connection between the conductive via 14 and the second coil portion 22 can be achieved by directly bonding the first semiconductor element 10 to the second semiconductor element 20 along a bonding interface 23.

[0014] Similarly, the second coil portion 22 and the third coil portion 32 may be spaced apart by approximately the thickness of the second semiconductor element 20. A conductive via 24, which may be formed as a through substrate via (TSV), through the second semiconductor element 20 connects the second coil portion 22 to the third coil portion 32 of the electromagnetic coil 101. An electrical connection between the conductive via 24 and the third coil portion 32 may be made by directly bonding the second semiconductor element 20 to the third semiconductor element 30 along a bonding interface 33. The conductive via 34 may extend through the second semiconductor element 20 and the first semiconductor element 10 to the bottom surface of the semiconductor element 10. The conductive via 34 may be formed as a through substrate via (TSV) in each of the semiconductor elements 10 and 20 and connected together during direct bonding. However, in other embodiments, the conductive via 34 may also be formed by a via last process, for example after the three semiconductor elements of the microelectronic device 1 are directly bonded. A metal contact pad 31 may be provided at the bottom end of via 34. As shown, coil portion 12, coil portion 22 and coil portion 32 may be connected in series to form an inductor or electromagnetic coil embedded in microelectronic device 1. As shown in FIG. 1, current may be input to device 1 via contact pad 11. Current may pass through first coil portion 12, conductive via 14, second coil portion 22, conductive via 24, third coil portion 32 and conductive via 34. Current may be output from device 1 by contact pad 31.

[0015] Because the coil portions of the electromagnetic coil 101 span multiple BEOL layers and are spaced apart by semiconductor elements, the coupling capacitance between the coil portions can be significantly reduced to significantly increase the performance, or Q factor, of the electromagnetic coil. In some embodiments, a ground plane, such as a conductive plane configured to be connected to an electrical ground, can be disposed between the first coil portion 12 and the second coil portion 22 of the electromagnetic coil 101. For example, a metallization layer disposed between the first coil portion 12 and the second coil portion 22 of the electromagnetic coil 101 can be used as the ground plane. The ground plane can capacitively decouple the first coil portion 12 and the second coil portion 22 of the electromagnetic coil 101 to further increase the performance of the electromagnetic coil. Similarly, a ground plane can be disposed between the second coil portion 22 and the third coil portion 32 to perform a similar function.

[0016] Forming the electromagnetic coil on the outermost metallization layer or on the first few layers of the BEOL stack allows for the use of successively thicker metal wires in successive outer layers in the BEOL layers, thereby lowering the electrical resistance of the electromagnetic coil. Thus, in FIG. 1, it is advantageous to place the first coil portion 12 on the outer (e.g., outermost) metallization layer of the first BEOL layer 16, and place the second coil portion 22 and the third coil portion 32 on layers directly below the respective bonding layers 25 and 35. In other embodiments, the coil portions 22, 32 can be placed on the respective bonding layers 25, 35 (e.g., the outermost metallization layers of the BEOL structure). In some embodiments, the active side of the first BEOL layer 16 of the first semiconductor device 10 can be directly bonded to an external substrate, such as a wafer, die, or integrated device.

[0017] FIG. 2 illustrates another embodiment of the microelectronic device 1 shown in FIG. 1, here illustrating a schematic cross-sectional view of an example embodiment of a microelectronic device 2. Similar to the semiconductor device shown in FIG. 1, FIG. 2 also illustrates multiple semiconductor devices, such as a first semiconductor device 40, a second semiconductor device 50, and a third semiconductor device 60 stacked together. The first semiconductor device 40 includes, from the front side to the back side, a first BEOL layer 46 connected to a first semiconductor substrate layer 48. The second semiconductor device 50 includes, from the front side to the back side, a bonding layer 55, a second BEOL layer 56, and a second semiconductor substrate layer 58. The third semiconductor device 60 can include, from the front side to the back side, a bonding layer 65, a third BEOL layer 66, and a third semiconductor substrate layer 68.

[0018] 1, microelectronic device 2 also includes an inductor or electromagnetic coil 102 having a first metal coil portion 42 disposed on a first semiconductor element 40, a second metal coil portion 52 disposed on a second semiconductor element 50, and a third metal coil portion 62 disposed on a third semiconductor element 60. One difference between microelectronic device 2 of FIG. 2 and microelectronic device 1 of FIG. 1 is that second coil portion 52 and third coil portion 62 are disposed in outermost bonding layers 55 and 65, respectively, instead of the respective underlying BEOL layers 56 and 66.

[0019] As mentioned above, being present on the outermost layer (or outer layer) has the advantage of wider and thicker metal feature dimensions, thus lowering electrical resistance and self-coupling capacitance. Similar to the electromagnetic coil 101 of FIG. 1, the first coil portion 42 and the second coil portion 52 of the electromagnetic coil 102 can also be connected by conductive vias 44 that are spaced apart by approximately the thickness of the first semiconductor element 40 and can be formed as through-substrate vias (TSVs). Additionally, the second coil portion 52 and the third coil portion 62 can be connected by conductive vias 54 that are spaced apart by approximately the thickness of the second semiconductor element 50 and can be formed as TSVs. The third conductive via 64 can extend through the second semiconductor element 50 and the first semiconductor element 40 to the underside of the semiconductor element 40. The conductive vias 64 can be formed as TSVs in each of the semiconductor elements 40 and 50 and connected together when directly bonded. Alternatively, the conductive vias 64 can be formed by a via-last process, for example after the three semiconductor elements of the microelectronic device 2 are directly bonded together.

[0020] As shown in FIG. 2, coil portion 42, coil portion 52, and coil portion 62 can be connected in series to form an inductor or electromagnetic coil 102 embedded in microelectronic device 2. Current flows into first coil portion 42 at conductive contact pad 41, through conductive via 44 to second coil portion 52, then through conductive via 54, third coil portion 62, conductive via 64, and finally out at contact pad 61. Metallized bonding layer 55 of second semiconductor element 50 can be directly bonded to first semiconductor substrate layer 48 of first semiconductor element 40 to form bonding interface 53. First substrate 48 of first semiconductor element 40 can have a bonding layer thereon that includes conductive contact pads and surrounding dielectric material that are directly bonded to the contact pads and surrounding dielectric material of second coil portion 52 disposed on metallized bonding layer 55 of second semiconductor element 50, respectively. Similarly, the bonding layer 65 of the third semiconductor element 60 is preferably directly bonded to the second semiconductor substrate layer 58 of the second semiconductor element 50 to form a bonding interface 63. Also, the second substrate 58 of the second semiconductor element 50 may have a metallized bonding layer thereon including conductive contact pads and surrounding dielectric material that are directly bonded to the contact pads and surrounding dielectric material, respectively, of the third coil portion 62 disposed on the metallized bonding layer 55 of the third semiconductor element 60. Since adjacent coil portions of the electromagnetic coil 102 are spaced apart by at least the thickness of the semiconductor element, the coupling capacitance between the coil portions can be significantly reduced to significantly enhance inductor performance.

[0021] 3 illustrates yet another embodiment of the microelectronic device 1 of FIG. 2, where an example embodiment of the microelectronic device 3 includes multiple stacked semiconductor elements (e.g., dies / chips), such as a first semiconductor element 70, a second semiconductor element 80, and a third semiconductor element 90. The first semiconductor element 70 includes, from the front side to the back side, a first BEOL layer 76 and a first substrate layer 78. The second semiconductor element 80 includes, from the front side to the back side, a metallized bonding layer 85, a second BEOL layer 86, and a second substrate layer 88. The third semiconductor element 90 includes, from the front side to the back side, a metallized bonding layer 95, a third BEOL layer 96, and a third substrate layer 98. The microelectronic device 3 also includes an inductor or electromagnetic coil 103 having a first metal coil portion 72 disposed on the first semiconductor element 70, a second metal coil portion 82 disposed on the second semiconductor element 80, and a third metal coil portion 92 disposed on the third semiconductor element 90.

[0022] The microelectronic device 3 of FIG. 3, like the microelectronic device 2 of FIG. 2, has all three coil portions 72, 82, and 92 of the electromagnetic coil 103 disposed within the outermost metallization layer. It should be understood that the bonding layers 85, 95 can be part (e.g., the outermost layers) of the BEOL layers 86, 96, as described above. In the illustrated embodiment, the second coil portion 82 and the third coil portion 92 can be embedded in the bonding layers 85, 95, respectively. As described above, providing the coil portions 72, 82, and 92 in the outermost layers can provide the advantage of utilizing wider and thicker metal feature dimensions, thus lowering electrical resistance and self-coupling capacitance. The first coil portion 72 and the second coil portion 82 of the electromagnetic coil 103 can be spaced apart by approximately the thickness of the first semiconductor element 70. Also, the second coil portion 82 and the third coil portion 92 can be spaced apart by approximately the thickness of the second semiconductor element 80. Additionally, two conductive vias 74 and 94 may pass through the first semiconductor element 70 and the second semiconductor element 80 to connect the three coil portions 72, 82 and 92 to the underside of the semiconductor element 70. The two conductive vias 74 and 94 may be first formed as through-substrate vias (TSVs) in the semiconductor elements 70 and 80 and then joined during direct bonding of the three semiconductor elements. Alternatively, the vias may be formed as via-last TSVs as described above.

[0023] As shown in FIG. 3, the three coil portions 72, 82, 92 can be connected in parallel. As shown in FIG. 3, current can enter the device through contact pad 71 and pass through the three coil portions 72, 82, and 92 in parallel. Vias 74 can provide a parallel electrical connection between the first, second, and third coil portions 72, 82, 92. The current can then travel along conductive vias 94 and leave the device 3 through contact pad 91. The bonding layer 85 of the second semiconductor element 80 can be directly bonded to the first substrate layer 78 of the first semiconductor element 70, on which a bonding layer can be disposed. Similarly, the metallized bonding layer 95 of the third semiconductor element 90 can be directly bonded to the second substrate layer 98 of the second semiconductor element 90, on which a bonding layer can be disposed. The direct bonding of the three semiconductor elements 70, 80, and 90 forms two bonding interfaces 83 and 93, respectively, between two adjacent elements. Vias 74 and 94, if they are through-substrate vias (TSVs), are bonded to contact pads 82a and 82b, respectively, of second coil portion 82 at bonding interface 83 during direct bonding, and are bonded to contact pads 92a and 92b, respectively, of third coil portion 92 at bonding interface 93. If vias 74 and 94 are via-last TSVs, connections to the three coil portions can be made during the via-last process. Because adjacent coil portions of electromagnetic coil 103 are spaced apart by at least the thickness of the semiconductor device, the coupling capacitance between the coil portions can be significantly reduced, significantly improving inductor performance.

[0024] In various embodiments, the coil portions may be present in a layer at or near the surface of an overlying or underlying semiconductor element. For example, in FIG. 1, the second coil portion 22 of the electromagnetic coil 101 between the first semiconductor element 10 and the second semiconductor element 20 may be disposed in the second BEOL layer 22 of the second semiconductor element 20. Alternatively, the second coil portion 22 may be disposed in a metallization layer of the first semiconductor element 10 on the top side of the first semiconductor element 10 facing the second semiconductor element 20. In either arrangement, the first coil portion 12 and the second coil portion 22 of the electromagnetic coil 101 may be separated by at least the substrate layer 18 of the first semiconductor element 10. Similarly, the second coil portion 22 and the third coil portion 32 of the electromagnetic coil 101 may be separated by at least the substrate layer 28 of the first semiconductor element 20.

[0025] In some embodiments, stacked semiconductor elements can be bonded directly to each other without the use of an intervening adhesive. In some embodiments, BEOL layers associated with a semiconductor element can be deposited on the semiconductor element. In some embodiments, a bonding layer (e.g., top or bottom) of a BEOL layer of a semiconductor element can be bonded directly to an adjacent (e.g., lower or upper) semiconductor element. For example, bonding layer 25 of second semiconductor element 20 of FIG. 1 can be bonded directly to, e.g., a bonding layer of first semiconductor element 10. In some embodiments, a conductive via that passes through a semiconductor element can be bonded directly to a coil portion disposed on another semiconductor element. For example, in FIG. 3, conductive via 74 and coil portion 82 of electromagnetic coil 102 disposed on bonding layer 85 of semiconductor element 80 can be bonded directly without the use of an adhesive. In other embodiments, a conductive via such as 74 that passes through a semiconductor element such as 70 and is electrically connected to one or more metallization layers on the backside of semiconductor element such as 70 can be bonded directly to a coil portion such as 82 of an electromagnetic coil disposed on another semiconductor element such as 80. In further embodiments, a coil portion of an electromagnetic coil on the backside of a first semiconductor element is connected to a coil portion on the front side of a second semiconductor element. In some examples, the coupling is performed using only one contact pad, such as 92a, with one coil portion, such as 82, formed in a metallization layer of a first element, such as 80, and another coil portion, such as 92, formed in a metallization layer of a second element, such as 90. In other examples, multiple contact pads can be used to couple multiple metal coil portions of an electromagnetic coil, such as by bonding two coils of two elements together to form one thick homogenous coil.

[0026] In some embodiments, a bonding layer, such as a non-conductive bonding layer, can be used to bond the BEOL layers of a semiconductor device to a substrate, such as another semiconductor device, a carrier, or a package substrate on which the die stack is mounted.

[0027] In some embodiments, the bonding layer is configured for room temperature, atmospheric pressure direct bonding, such as the ZIBOND® and DBI® processes available from Adeia, Inc., San Jose, Calif. In other embodiments, the bonding layer is configured for low temperature die-to-wafer or die-to-die hybrid bonding techniques, such as the DBI® Ultra process available from Adeia, Inc., San Jose, Calif. In other embodiments, the bonding layer is configured for adhesive bonding.

[0028] FIG. 4 is a schematic perspective view illustrating an example embodiment of a microelectronic device 4 with a portion of the surrounding structure removed to expose a portion of the metal lines. The microelectronic device 4 of FIG. 4 includes a first semiconductor element 110, a second semiconductor element 120, and a third semiconductor element 130, similar to the microelectronic device 1 of FIG. 1. The microelectronic device 4 also includes an electromagnetic coil 104 having a first metal coil portion 112, a second metal coil portion 122, and a third metal coil portion 132 disposed in corresponding BEOL layers (e.g., outermost bonding or buried layers of a BEOL stack) of the first semiconductor element 110, the second semiconductor element 120, and the third semiconductor element 130, respectively. The first coil portion 112 and the second coil portion 122 can be spaced apart by at least a substrate layer of the second semiconductor element 120. The second coil portion 122 and the third coil portion 132 can be spaced apart by at least a substrate layer of the third semiconductor element 130. Therefore, the coupling capacitance between the coil portions can be significantly reduced to significantly enhance the performance of the electromagnetic coil. The semiconductor element in the electromagnetic device 4 of FIG. 4 can have an active surface facing upwards compared to the semiconductor element in the device 1 of FIG. 1. Furthermore, the first conductive via (e.g., TSV) 114 connecting the first coil portion 112 to the second coil portion 122 and the second conductive via (e.g., TSV) 124 connecting the second coil portion 122 to the third coil portion 132 can be disposed in different vertical planes. FIG. 4 further illustrates that the electromagnetic coil 104 can have a rectangular spiral winding structure disposed in a BEOL layer or a bonding layer.

[0029] FIG. 4 shows that the electromagnetic coil 101 described in relation to FIG. 1 can be used to form an autotransformer. In FIG. 4, multiple (e.g., three) tapping points (access points) are provided on the electromagnetic coil 104, such as a first tapping point 117, a second tapping point 127, and a third tapping point 137. As shown in FIG. 4, a current can flow in a direction from an input 131 located at the end of the third coil portion 132 to an output 111 located at the end of the first coil portion 112. When an input voltage V0 is applied across the input 131 and the output 111, and the output voltage is tapped at the first tapping point 117, the second tapping point 127, or the third tapping point 137, different output voltages can be obtained between the tapping points and the output 111. For example, when the first tapping point 117 is accessed for output, the output voltage can be close to but less than ⅓ of the input voltage V because this point is located on the first coil portion 112 and close to the conductive via 114. When the second tapping point 127 is accessed for output, the output voltage can be close to but less than ⅔ of the input voltage V because this point is located on the second coil portion 122 and close to the second conductive via 124. In this manner, an autotransformer can be provided to produce different voltages.

[0030] FIG. 5 shows a schematic diagram of a transformer including multiple (e.g., two) electromagnetic coils stacked on top of each other, with surrounding structures removed for ease of illustration. The transformer includes a primary electromagnetic coil 106 and a secondary electromagnetic coil 105. As shown in FIG. 5, the coil portion of the primary electromagnetic coil 106 can be inter-stacked with the coil portion of the secondary electromagnetic coil 105. For example, the first coil portion 155 of the primary electromagnetic coil 106 is inter-stacked between the first coil portion 145 and the second coil portion 146 of the secondary electromagnetic coil 105. The second coil portion 156 of the primary electromagnetic coil 106 is inter-stacked between the second coil portion 146 and the third coil portion 147 of the secondary electromagnetic coil 105. The third coil portion 157 of the primary electromagnetic coil 106 is inter-stacked between the third coil portion 147 and the fourth coil portion 148 of the secondary electromagnetic coil 105.

[0031] The schematic perspective view of Figure 5 also shows conductive vias connecting the metal coil layers of the primary electromagnetic coil 106. For example, a first conductive via 153A connects the first coil portion 155 and the second coil portion 156 of the primary electromagnetic coil 106. A second conductive via 153B connects the second coil portion 156 and the third coil portion 157 of the primary electromagnetic coil 106. And a third conductive via 153C connects the third coil portion 157 and the fourth coil portion 158 of the primary electromagnetic coil 106. At this perspective angle, the conductive vias connecting the metal coil layers of the secondary electromagnetic coil 105 are not visible. According to the schematic perspective view shown in FIG. 5, when a voltage is applied to the primary electromagnetic coil 106 across the input 154 and output 152, the secondary electromagnetic coil 105 provides a current across the input 144 and output 142 with a voltage determined by the coil turns ratio between the two associated electromagnetic coils 105 and 106.

[0032] FIG. 6 is a schematic cross-sectional view of an example microelectronic device 6 having multiple (e.g., three) stacked semiconductor elements (e.g., dies / chips), such as a first semiconductor element 160, a second semiconductor element 170, and a third semiconductor element 180. The microelectronic device 6 of FIG. 6 also includes multiple (e.g., two) electromagnetic coils, such as a first electromagnetic coil 107 and a second electromagnetic coil 108, arranged stacked on top of each other. In one example, each of the two electromagnetic coils has coil portions disposed in multiple BEOL layers or bonding layers of the stacked semiconductor elements. Adjacent coil portions of each electromagnetic coil can be spaced apart by a substrate of the semiconductor elements. Conductive vias through the semiconductor elements can connect different coil portions of the electromagnetic coils.

[0033] 6, for the first electromagnetic coil 107, the first coil portion 162 is disposed on a first BEOL layer 166 of the first semiconductor element 160, the second coil portion 172 is disposed on a bonding layer 175 of the second semiconductor element 170, and the third coil portion 182 is disposed on a third BEOL layer 186 of the third semiconductor element 180. A plurality of conductive vias 164 and 165 may extend through the first semiconductor element 160 and the second semiconductor element 170 to connect the coil portions 162, 172, and 182 of the first electromagnetic coil 107 such that the three coil portions are connected in parallel. The conductive vias 164, 165 may be individual TSVs formed in the semiconductor elements 160, 170 and are bonded together at a bonding interface 171 and to a contact pad of the third coil portion 182 of the first electromagnetic coil 107 at a bonding interface 181 if direct bonding is performed. Alternatively, the conductive vias 164, 165 may be formed by via-last TSVs that are formed after the three semiconductor elements 160, 170 and 180 of the microelectronic device 6 are directly bonded together.

[0034] Further, for the second electromagnetic coil 108, a first coil portion 173 is disposed on a second BEOL layer 176 of the second semiconductor element 170, and a second coil portion 183 is disposed on a bonding layer 185 of the third semiconductor element 180. A conductive via 161 passes through the semiconductor element from the underside of the first semiconductor element 160 to connect the first coil portion 173. A second conductive via 177 passes through the second semiconductor element 170 to connect the first coil portion 173 to a second coil portion 183 of the second electromagnetic coil 108. A third conductive via 179 passes through the second semiconductor element 170 and the first semiconductor element 160 to connect the second coil portion 183 to the underside of the first semiconductor element 160. Again, conductive vias 161, 177 and 179 may be formed in semiconductor elements 160 and 170 and then bonded at bonding interfaces 171 and 181 if direct bonding of the stacked elements is performed. Alternatively, via 179 may be formed by a via-last process after direct bonding of the three semiconductor elements 160, 170 and 180, for example.

[0035] In each of the second and third semiconductor elements 170 and 180, the metallization layer having coil portions 172 and 182 for the first electromagnetic coil 107 and the metallization layer having coil portions 173 and 183 for the second electromagnetic coil 108 may be separated by at least another layer formed of dielectric material(s) or another metallization layer. When a current flows into the input 191 and exits through the first electromagnetic coil 107 at the output 193, a current may be induced in the second electromagnetic coil 107 and flow from the input 195 to the output 197. Alternatively, two electromagnetic coils performing unique functions may be operated.

[0036] 1, 2, 3, 4, and 6 show example electromagnetic coils spanning three dies or semiconductor elements, it should be understood that the disclosed electromagnetic coils can span more than two or three semiconductor elements in a multi-die stack. In some embodiments, two or more separate electromagnetic coils or inductors can be disposed within the same die stack, where each electromagnetic coil / inductor can span multiple semiconductor elements / dies in the die stack, for example.

[0037] 7 and 8 show the reduction of capacitive coupling and increase of Q value of an electromagnetic coil or inductor by stacked and bonded semiconductor elements shown in FIGS. 1-5. FIG. 6 is a schematic cross-sectional view showing multiple (e.g., four) semiconductor elements stacked on each other, including a first semiconductor element 210 having a first BEOL layer 216 and a first substrate layer 218, a second semiconductor element 220 having a second BEOL layer 226 and a second substrate layer 228, a third semiconductor element 230 having a third BEOL layer 236 and a third substrate layer 238, and a fourth semiconductor element 240 having a fourth BEOL layer 246 and a fourth substrate layer 248. The four semiconductor elements 210, 220, 230, and 240 are directly bonded. Each of the BEOL layers can have a coil portion of an electromagnetic coil disposed therein. In the illustrated example embodiment, there are a total of four coil portions including a first coil portion 212, a second coil portion 222, a third coil portion 232, and a fourth coil portion 242. Each adjacent coil portion of the electromagnetic coil is separated by at least a distance d by respective substrates 218, 228, 238, 248 of the semiconductor device. m In FIG. 6, the thickness of the metal wire forming the coil portion can be set to t m Shown as:

[0038] In comparison, Figure 8 illustrates multiple (e.g., four) sections of an electromagnetic coil, including a first coil section 261, a second coil section 262, a third coil section 263, and a fourth coil section 264, disposed in a BEOL stack layer 266 of a single semiconductor device 260 having a substrate layer 268. In Figure 8, the distance between adjacent coil sections is referred to as D sand the thickness of each metal coil layer is t s In the microelectronic device 7 of FIG. 7, the distance d from one coil section to the next is m In contrast, the coil portion distance d s is the order of a single BEOL layer separating adjacent coil sections, and the coil section distance ratio d between the stacked die / chip arrangement and the single die / chip arrangement m / d s can range from 10 to 50. In contrast, in the microelectronic device 7 of FIG. 7, each coil portion can be fabricated in one of the outer BEOL layers (e.g., including the bonding layer(s)) that have thicker, wider metal lines. In the single semiconductor element 260 of FIG. 8, the coil portions of the electromagnetic coil can be formed in many BEOL layers. Thus, the thickness ratio t m / t s is generally in the range of 5 to 10.

[0039] The capacitive coupling C and quality factor Q of an inductor or electromagnetic coil can be determined by the following equations: JPEG2024536563000002.jpg6170 JPEG2024536563000003.jpg11170Here, E0 and E r is the dielectric constant, R0 is the resistivity, μ is the magnetic permeability, N is the number of turns in the coil, l is the length of one layer of wire, w is the width of the inductor line, d is the spacing between adjacent coils.

[0040] To compare an electromagnetic coil disposed in a microelectronic device including multi-stacked semiconductor elements as described in the disclosed embodiments with an electromagnetic coil disposed in a single semiconductor element, the above question expresses the ratio of the capacitive coupling C and quality factor Q of the two electromagnetic coils. By rearrangement and factor elimination, the Q-ratio and C-ratio can be shown as follows: JPEG2024536563000004.jpg11170 JPEG2024536563000005.jpg11170

[0041] The above-mentioned d m / d s and t m / t s By applying the data ranges, the Q ratio and C ratio can be calculated. Thus, the Q factor of an electromagnetic coil embedded in a microelectronic device having a multi-stacked semiconductor element as disclosed herein can be about 25 to 100 times the Q factor of an electromagnetic coil formed in a single semiconductor element. Also, in a C factor comparison, the same electromagnetic coil in a multi-stacked semiconductor element as disclosed herein can be about 0.02 to 0.1 of an electromagnetic coil formed in a single semiconductor element.

[0042] Electronic Devices Die can refer to any suitable type of integrated device die. For example, an integrated device die can include electronic components such as integrated circuits (such as a processor die, a controller die, or a memory die), a microelectromechanical system (MEMS) die, an optical device, or any other suitable type of device die. In some embodiments, the electronic components can include passive devices such as capacitors, inductors, or other surface mount devices. In various embodiments, circuitry (such as active components such as transistors) can be patterned at or near the active surface of the die. The active surface can be on the side of the die opposite the back surface of the die. The back surface can include or not include any active circuitry or passive devices.

[0043] The integrated device die may include a bonding surface and a back surface opposite the bonding surface. The bonding surface may have a plurality of conductive bond pads including conductive bond pads and a non-conductive material adjacent to the conductive bond pads. In some embodiments, the conductive bond pads of the integrated device die may be directly bonded to corresponding conductive pads of the substrate or wafer without the use of an intervening adhesive, and the non-conductive material of the integrated device die may be directly bonded to a portion of the corresponding non-conductive material of the substrate or wafer without the use of an intervening adhesive. Direct bonding without the use of adhesive is described in U.S. Pat. Nos. 7,126,212, 8,153,505, 7,622,324, 7,602,070, 8,163,373, 8,389,378, 7,485,968, 8,735,219, 9,385,024, 9,391,143, 9,485,968 ... Nos. 9,431,368, 9,953,941, 9,716,033, 9,852,988, 10,032,068, 10,204,893, 10,434,749, and 10,446,532, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0044] Examples of direct bonding methods and direct bonding structures Various embodiments disclosed herein relate to direct bonding structures that allow two elements to be directly bonded together without the use of an intervening adhesive. Two or more electronic elements, which may be semiconductor elements (such as integrated device dies, wafers, etc.), may be stacked or bonded together to form a bonded structure. The conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements may be stacked in the bonded structure. The contact pads may include metal pads formed within the non-conductive bonded regions and may be connected to an underlying metallization such as a redistribution layer (RDL).

[0045] In some embodiments, the elements are directly bonded to each other without the use of adhesive. In various embodiments, the non-conductive or dielectric material of the first element can be directly bonded to the corresponding non-conductive or dielectric field area of ​​the second element without the use of adhesive. The non-conductive material can be referred to as the non-conductive bonding area or bonding layer of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-dielectric bonding techniques. For example, the dielectric-dielectric bond can be formed without the use of adhesive using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes. Suitable dielectric materials for direct bonding can include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or carbon such as silicon carbide, silicon oxynitride, silicon carbonitride, or diamond-like carbon. In some embodiments, the dielectric material does not include a polymeric material such as an epoxy, resin, or molding compound.

[0046] In various embodiments, a hybrid direct bond can be formed without the use of an intervening adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to plasma and / or etchants to activate the surfaces. In some embodiments, the surfaces can be terminated with chemical species after or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces, and the termination process can provide additional chemical species at the bonding surfaces that increase the bond energy during direct bonding. In some embodiments, activation and termination are performed in the same process, such as activating and terminating the surfaces with plasma or wet etchants. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the terminating species can include nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there can be one or more fluorine peaks near the layers and / or bonding interface. Thus, in a direct bonding structure, the bond interface between the two dielectric materials can include a very smooth interface with a high nitrogen content and / or fluorine peak at the bond interface. Further examples of activation and / or termination processes are described in U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0047] In various embodiments, the conductive contact pads of a first component can also be directly bonded to corresponding conductive contact pads of a second component. For example, hybrid bonding techniques can be used to provide conductor-conductor direct bonds along a bonding interface that includes a covalently directly bonded dielectric-dielectric surface prepared as described above. In various embodiments, conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds can be formed using direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0048] For example, the dielectric bonding surfaces can be prepared as described above and bonded directly to each other without the use of an intervening adhesive. The conductive contact pads (which can be surrounded by a non-conductive dielectric field region) can also be bonded directly to each other without the use of an intervening adhesive. In some embodiments, each contact pad can be recessed downward from the outer surface (e.g., top surface) of the dielectric field region or the non-conductive bonding region by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, within a range of 2 nm to 20 nm, or within a range of 4 nm to 10 nm. In some embodiments, the non-conductive bonding regions can be bonded directly to each other without the use of an adhesive at room temperature in a bonding tool described herein, and the bonded structure can then be annealed. The annealing can be performed in a separate apparatus. Upon annealing, the contact pads can expand and contact each other to form a direct metal-metal bond. The use of hybrid bonding technologies such as Direct Bond Interconnect or DBI®, commercially available from Adeia, San Jose, Calif., can advantageously allow for a high density of connected pads across the direct bond interface (e.g., small or fine pitch for regular arrays). In some embodiments, the pitch of the bond pads, or the pitch of the conductive trace embedded in the bonding surface of one of the bonded elements, can be less than 40 microns, or less than 10 microns, or even less than 2 microns. In some applications, it is desirable for the ratio of the bond pad pitch to one of the bond pad dimensions to be less than 5 or less than 3, and in some cases less than 2. In other applications, the width of the conductive trace embedded in the bonding surface of one of the bonded elements can range from 0.3 to 3 microns. In various embodiments, the contact pads and / or traces can include copper, although other metals may be suitable.

[0049] Thus, in a direct bonding process, the first element can be directly bonded to the second element without the use of an intervening adhesive. In some configurations, the first element can include a singulated element, such as a singulated integrated device die. In other configurations, the first element can include a carrier or substrate (e.g., a wafer) that includes multiple (e.g., tens, hundreds, or more) element regions that, upon singulation, form multiple integrated device dies. In the embodiments described herein, the first element, whether a die or a substrate, can be considered a host substrate and mounted on a support within a bonding tool to receive the second element from a pick-and-place or robotic end effector. The second element in the illustrated embodiment includes a die. In other configurations, the second element can include a carrier or substrate (e.g., a wafer).

[0050] As described herein, the first and second elements can be directly bonded to each other without the use of adhesive, which is distinct from a deposition process. In one application, the width of the first element in the bonded structure can be similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure can be different from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% greater than the width or area of ​​the smaller element. Thus, the first and second elements can include non-deposited elements. Furthermore, the direct bonded structure, unlike a deposition layer, can include defect regions along the bond interface where nanovoids exist. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonded surface. As discussed above, the bond interface can include concentrations of materials from the activation and / or last chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, nitrogen peaks can be formed at the bond interface. In embodiments utilizing oxygen plasma for activation, oxygen peaks can be formed at the bond interface. In some embodiments, the bond interface can include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond can include a covalent bond that is stronger than van der Waals bonds. The bond layer can also include a highly smoothly planarized polished surface. For example, the bond layer can have a surface roughness of less than 2 nm root mean square (RMS) or less than 1 nm RMS.

[0051] In various embodiments, the metal-metal bond between the contact pads can be bonded such that the copper grains grow together across the bond interface. In some embodiments, the copper can have grains oriented along 111 crystal planes to enhance diffusion of copper across the bond interface. The bond interface can extend substantially completely to at least a portion of the bonded contact pads such that there are substantially no gaps between the non-conductive bonded regions at or near the bonded contact pads. In some embodiments, a barrier layer (which can include, for example, copper) can be provided below the contact pads. However, in other embodiments, there can be no barrier layer below the contact pads, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated herein by reference in its entirety for all purposes.

[0052] In one aspect, a microelectronic device is disclosed. The microelectronic device may include a first semiconductor element. The microelectronic device may also include a second semiconductor element disposed on the first semiconductor element. The microelectronic device may also include an electromagnetic coil. A first portion of the electromagnetic coil and a second portion of the electromagnetic coil are spaced apart by the first semiconductor element. A first conductive via through the first semiconductor element connects the first and second portions of the electromagnetic coil.

[0053] In one embodiment, an electromagnetic coil is configured to act as an inductor.

[0054] In one embodiment, the electromagnetic coil is configured to operate as an autotransformer.

[0055] In one embodiment, the electromagnetic coil is configured to operate as part of a transformer.

[0056] In one embodiment, the second semiconductor element is bonded directly to the first semiconductor element without the use of an intervening adhesive.

[0057] In one embodiment, the interface between the first and second semiconductor elements includes conductor-conductor and dielectric-dielectric direct bonds.

[0058] In one embodiment, a first portion of the electromagnetic coil is disposed in a back-end (BEOL) layer associated with a first semiconductor device.

[0059] In one embodiment, a first portion of the electromagnetic coil is disposed in an outermost metallization layer of a back-end (BEOL) layer associated with a first semiconductor device.

[0060] In one embodiment, a first semiconductor device is disposed on a surface of a substrate and a first portion of an electromagnetic coil is disposed in a metallization layer on the surface of the substrate.

[0061] In one embodiment, a first portion of the electromagnetic coil is disposed on a first bonding layer that bonds an associated BEOL layer of the first semiconductor device to a substrate.

[0062] In one embodiment, the associated BEOL layer of the first semiconductor device is bonded directly to the substrate without the use of an intervening adhesive.

[0063] In one embodiment, the first tie layer comprises an adhesive.

[0064] In one embodiment, the first portion of the electromagnetic coil has a rectangular spiral winding.

[0065] In one embodiment, a second portion of the electromagnetic coil is disposed in a back-end (BEOL) layer associated with the second semiconductor device.

[0066] In one embodiment, a second portion of the electromagnetic coil is disposed in an outermost metallization layer of a back-end (BEOL) layer associated with a second semiconductor device.

[0067] In one embodiment, the second semiconductor element is disposed on a surface of the first semiconductor element and a second portion of the electromagnetic coil is disposed in a metallization layer on the surface of the first semiconductor element.

[0068] In one embodiment, a second portion of the electromagnetic coil is disposed on a second bonding layer that bonds an associated BEOL layer of the second semiconductor device to the first semiconductor device.

[0069] In one embodiment, the associated BEOL layer of the second semiconductor device is bonded directly to the first semiconductor device without the use of an intervening adhesive.

[0070] In one embodiment, the second tie layer comprises an adhesive.

[0071] In one embodiment, the second portion of the electromagnetic coil has a rectangular spiral winding.

[0072] In one embodiment, the microelectronic device further includes a third semiconductor element disposed on the second semiconductor element, the third portion of the electromagnetic coil being spaced from the second portion of the electromagnetic coil by the second semiconductor element, and a second conductive via through the second semiconductor element connecting the second and third portions of the electromagnetic coil.

[0073] In one embodiment, the first semiconductor device includes an integrated device die.

[0074] In one embodiment, the second semiconductor device includes an integrated device die.

[0075] In one embodiment, the electromagnetic coil comprises a metal wire, the metal wire having a minimum diameter of at least 0.5 μm.

[0076] In one embodiment, the spacing between the first portion of the electromagnetic coil and the second portion of the electromagnetic coil is at least 5 μm.

[0077] In one embodiment, a metallization layer configured to be connected to an electrical ground is disposed between the first and second portions of the electromagnetic coil.

[0078] In one embodiment, the electromagnetic coil includes at least three access points configured for electrical connection.

[0079] In one embodiment, the electromagnetic coil is configured to operate as an autotransformer.

[0080] In one embodiment, the microelectronic device further comprises a further electromagnetic coil.

[0081] In one embodiment, the electromagnetic coil and the further electromagnetic coil are configured to operate as a transformer.

[0082] In one embodiment, two portions of the further electromagnetic coil are separated by at least one of the semiconductor elements.

[0083] In one embodiment, a portion of the additional electromagnetic coil is disposed in a back-end (BEOL) layer associated with one of the semiconductor devices.

[0084] In one embodiment, a portion of the additional electromagnetic coil is disposed in an outermost metallization layer of a back-end (BEOL) layer associated with one of the semiconductor devices.

[0085] In one embodiment, a portion of the additional electromagnetic coil is disposed in the bonding layer between the semiconductor elements.

[0086] In one embodiment, a portion of the further electromagnetic coil has a rectangular spiral winding.

[0087] In one embodiment, the further electromagnetic coil comprises a metal wire, the metal wire having a minimum diameter of at least 0.5 μm.

[0088] In one embodiment, the spacing between the two portions of the further electromagnetic coil is at least 5 μm.

[0089] In one aspect, a microelectronic device is disclosed. The microelectronic device may include a first semiconductor element. The microelectronic device may also include a second semiconductor element disposed on the first semiconductor element. The microelectronic device may also include a first electromagnetic coil adjacent to the first semiconductor element. The microelectronic device may also include a second electromagnetic coil adjacent to the second semiconductor element. The first electromagnetic coil and the second electromagnetic coil are spaced apart by the first semiconductor element. At least one of the first electromagnetic coil and the second electromagnetic coil is disposed on a layer configured for direct coupling.

[0090] In one embodiment, a first electromagnetic coil is disposed on a first bonding layer that directly bonds an associated BEOL layer of a first semiconductor device to a substrate.

[0091] In one embodiment, the associated BEOL layer of the first semiconductor device is bonded directly to the substrate without the use of an intervening adhesive.

[0092] In one embodiment, a second electromagnetic coil is disposed on a second bonding layer that directly bonds an associated BEOL layer of the second semiconductor device to the first semiconductor device.

[0093] In one embodiment, a second electromagnetic coil is disposed in a back-end (BEOL) layer associated with the second semiconductor device.

[0094] In one embodiment, a second electromagnetic coil is disposed in an outermost metallization layer of a back-end (BEOL) layer associated with a second semiconductor device.

[0095] In one embodiment, the first electromagnetic coil has a rectangular spiral winding.

[0096] In one embodiment, the second electromagnetic coil is disposed on a bonding layer that directly bonds an associated BEOL layer of the second semiconductor device to the first semiconductor device.

[0097] In one embodiment, the associated BEOL layer of the second semiconductor device is bonded directly to the first semiconductor device without the use of an intervening adhesive.

[0098] In one embodiment, the first electromagnetic coil is disposed in a layer that directly bonds an associated BEOL layer of the first semiconductor device to the substrate without the use of an intervening adhesive.

[0099] In one embodiment, a first electromagnetic coil is disposed in a back-end (BEOL) layer associated with a first semiconductor device.

[0100] In one embodiment, a first electromagnetic coil is disposed in an outermost metallization layer of a back-end (BEOL) layer associated with a first semiconductor device.

[0101] In one embodiment, the second electromagnetic coil has a rectangular spiral winding.

[0102] In one embodiment, the first semiconductor device includes an integrated device die.

[0103] In one embodiment, the second semiconductor device includes an integrated device die.

[0104] In one embodiment, the first electromagnetic coil comprises a metal wire, the metal wire having a minimum diameter of at least 0.5 μm.

[0105] In one embodiment, the second electromagnetic coil comprises a metal wire, the metal wire having a minimum diameter of at least 0.5 μm.

[0106] In one embodiment, the spacing between the first and second electromagnetic coils is at least 5 μm.

[0107] In one embodiment, the first electromagnetic coil and the second electromagnetic coil are configured to operate as a transformer.

[0108] In one aspect, a method of forming a microelectronic device is disclosed. The method can include providing a first semiconductor element and a first coiled structure adjacent to the first semiconductor element. A first conductive via passes through the first semiconductor element. The method can also include providing a second semiconductor element and a second coiled structure adjacent to the second semiconductor element. The method can also include bonding the second semiconductor element to the first semiconductor element such that the first coiled structure and the second coiled structure are connected by the first conductive via. The first coiled structure and the second coiled structure are spaced apart by the first semiconductor element.

[0109] In one embodiment, the second semiconductor element is bonded directly to the first semiconductor element without the use of an intervening adhesive.

[0110] Unless the context clearly requires otherwise, words such as "comprise, comprising, include, including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to," rather than an exclusive or exhaustive sense. The word "coupled," as generally used herein, means two or more elements that may be connected directly or through one or more intermediate elements. Similarly, the word "connected," as generally used herein, means two or more elements that may be connected directly or through one or more intermediate elements. Additionally, when the application uses words such as "herein," "above," "below," and words of similar import, these words are intended to refer to the application as a whole and not to any particular portion of the application. Furthermore, when a first element is described herein as being "on" or "over" a second element, the first element can be directly on or over the second element such that the first and second elements are in direct contact with each other, or indirectly on or over the second element such that there are one or more intervening elements between the first and second elements. Words using the singular or plural in the above detailed description can also include the plural or singular, respectively, where the context allows. The word "or" when referring to a list of two or more items covers all interpretations of the word, such as any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0111] Additionally, as used herein, inter alia, conditional terms such as "can, could, might, may" and "eg, for example, such as" are generally intended to convey that some embodiments include certain features, elements and / or conditions and other embodiments do not include them, unless expressly stated otherwise or understood otherwise within the context of use. Thus, such conditional terms are generally not intended to imply that features, elements and / or conditions are in any way required for one or more embodiments.

[0112] Although several embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, method and system described herein may be embodied in various other forms, and various omissions, substitutions and modifications of the forms of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, although blocks are shown in a given arrangement, another embodiment may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. 1. A microelectronic device comprising: a first semiconductor device having a first substrate; a second semiconductor device having a second substrate disposed on the first semiconductor device; An electromagnetic coil; a first coil portion of the electromagnetic coil and a second coil portion of the electromagnetic coil are separated by at least the first substrate of the first semiconductor element, and a first conductive via passing through the first semiconductor element connects the first and second coil portions of the electromagnetic coil. Microelectronic devices.

2. the electromagnetic coil is configured to operate as an inductor; The microelectronic device of claim 1 .

3. the electromagnetic coil is configured to operate as an autotransformer; The microelectronic device of claim 1 .

4. the electromagnetic coil is configured to operate as part of a transformer; The microelectronic device of claim 1 .

5. the second semiconductor element is directly bonded to the first semiconductor element without the use of an intervening adhesive; The microelectronic device of claim 1 .

6. the interface between the first and second semiconductor elements comprises conductor-conductor and dielectric-dielectric direct bonds; The microelectronic device of claim 1 .

7. the first coil portion of the electromagnetic coil is disposed in a back-end of the line (BEOL) layer associated with the first semiconductor device. The microelectronic device of claim 1 .

8. the first coil portion of the electromagnetic coil is disposed in an outermost metallization layer of a back-end-of-the-line (BEOL) layer associated with the first semiconductor device. The microelectronic device of claim 1 .

9. the first semiconductor element is disposed on a surface of the first substrate, and the first coil portion of the electromagnetic coil is disposed in a metallization layer on the surface of the substrate. The microelectronic device of claim 1 .

10. the first coil portion of the electromagnetic coil is disposed on a first bonding layer that bonds an associated BEOL layer of the first semiconductor device to an external substrate. The microelectronic device of claim 1 .

11. the associated BEOL layer of the first semiconductor device is directly bonded to the external substrate without the use of an intervening adhesive; The microelectronic device of claim 10.

12. the first bonding layer comprises an adhesive; The microelectronic device of claim 10.

13. the first coil portion of the electromagnetic coil has a rectangular spiral winding; The microelectronic device of claim 1 .

14. the second coil portion of the electromagnetic coil is disposed in a back-end of the line (BEOL) layer associated with the second semiconductor device. The microelectronic device of claim 1 .

15. the second coil portion of the electromagnetic coil is disposed in an outermost metallization layer of a back-end of the line (BEOL) layer associated with the second semiconductor device. The microelectronic device of claim 1 .

16. the second semiconductor element is disposed on a surface of the first semiconductor element, and the second coil portion of the electromagnetic coil is disposed in a metallization layer on the surface of the first semiconductor element. The microelectronic device of claim 1 .

17. the second coil portion of the electromagnetic coil is disposed on a second bonding layer that bonds an associated BEOL layer of the second semiconductor device to the first semiconductor device. The microelectronic device of claim 1 .

18. the associated BEOL layer of the second semiconductor device is directly bonded to the first semiconductor device without the use of an intervening adhesive; 20. The microelectronic device of claim 17.

19. the second bonding layer comprises an adhesive; 20. The microelectronic device of claim 17.

20. the second coil portion of the electromagnetic coil has a rectangular spiral winding; The microelectronic device of claim 1 .

21. further comprising a third semiconductor element disposed on the second semiconductor element, wherein a third coil portion of the electromagnetic coil is spaced from the second coil portion of the electromagnetic coil by at least the second substrate of the second semiconductor element, and a second conductive via passing through the second semiconductor element connects the second and third coil portions of the electromagnetic coil. The microelectronic device of claim 1 .

22. the first semiconductor device comprises an integrated device die; The microelectronic device of claim 1 .

23. the second semiconductor element comprises an integrated device die; The microelectronic device of claim 1 .

24. the electromagnetic coil comprises a metal wire, and the minimum diameter of the metal wire is at least 0.5 μm; The microelectronic device of claim 1 .

25. a metallization layer disposed between the first and second coil portions of the electromagnetic coil and configured to be connected to an electrical ground; The microelectronic device of claim 1 .

26. the electromagnetic coil includes at least three access points configured for electrical connection; The microelectronic device of claim 1 .

27. the electromagnetic coil is configured to operate as an autotransformer; 27. The microelectronic device of claim 26.

28. further comprising a further electromagnetic coil; The microelectronic device of claim 1 .

29. the electromagnetic coil and the further electromagnetic coil are configured to operate as a transformer.

30. The microelectronic device of claim 28.

30. two coil portions of the further electromagnetic coil are spaced apart by at least one substrate of the semiconductor element; 30. The microelectronic device of claim 28.

31. a coil portion of the further electromagnetic coil disposed in a back-end-of-the-line (BEOL) layer associated with one of the semiconductor elements; 30. The microelectronic device of claim 28.

32. a coil portion of the further electromagnetic coil disposed in an outermost metallization layer of a back-end-of-the-line (BEOL) layer associated with one of the semiconductor elements; 30. The microelectronic device of claim 28.

33. a coil portion of the further electromagnetic coil is disposed on a bonding layer between the semiconductor elements; 30. The microelectronic device of claim 28.

34. a coil portion of the further electromagnetic coil having a rectangular spiral winding; 30. The microelectronic device of claim 28.

35. the further electromagnetic coil comprises a metal wire, the minimum diameter of the metal wire being at least 0.5 μm; 30. The microelectronic device of claim 28.

36. 1. A microelectronic device comprising: a first semiconductor device having a first substrate; a second semiconductor device having a second substrate disposed on the first semiconductor device; a first electromagnetic coil adjacent to the first substrate of the first semiconductor device; a second electromagnetic coil adjacent to the second substrate of the second semiconductor device; Equipped with the first electromagnetic coil and the second electromagnetic coil are spaced apart by at least the first substrate of the first semiconductor element; at least one of the first electromagnetic coil and the second electromagnetic coil is disposed on a layer configured for direct coupling; Microelectronic devices.

37. the first electromagnetic coil is disposed on a first bonding layer that directly bonds an associated BEOL layer of the first semiconductor device to an external substrate; 37. The microelectronic device of claim 36.

38. the associated BEOL layer of the first semiconductor device is directly bonded to the external substrate without the use of an intervening adhesive; 38. The microelectronic device of claim 37.

39. the second electromagnetic coil is disposed on a second bonding layer that directly bonds an associated BEOL layer of the second semiconductor device to the first semiconductor device; 38. The microelectronic device of claim 37.

40. the second electromagnetic coil is disposed in a back-end of the line (BEOL) layer associated with the second semiconductor device; 38. The microelectronic device of claim 37.

41. the second electromagnetic coil is disposed in an outermost metallization layer of a back-end of the line (BEOL) layer associated with the second semiconductor device; 38. The microelectronic device of claim 37.

42. the first electromagnetic coil has a rectangular spiral winding; 37. The microelectronic device of claim 36.

43. the second electromagnetic coil is disposed on a bonding layer that directly bonds an associated BEOL layer of the second semiconductor device to the first semiconductor device; 37. The microelectronic device of claim 36.

44. the associated BEOL layer of the second semiconductor device is directly bonded to the first semiconductor device without the use of an intervening adhesive; 44. The microelectronic device of claim 43.

45. the first electromagnetic coil is disposed in a layer that directly bonds an associated BEOL layer of the first semiconductor device to an external substrate without the use of an intervening adhesive; 44. The microelectronic device of claim 43.

46. the first electromagnetic coil is disposed in a back-end of the line (BEOL) layer associated with the first semiconductor device; 44. The microelectronic device of claim 43.

47. the first electromagnetic coil is disposed in an outermost metallization layer of a back-end of the line (BEOL) layer associated with the first semiconductor device; 44. The microelectronic device of claim 43.

48. the second electromagnetic coil has a rectangular spiral winding; 37. The microelectronic device of claim 36.

49. the first semiconductor device comprises an integrated device die; 37. The microelectronic device of claim 36.

50. the second semiconductor element comprises an integrated device die; 37. The microelectronic device of claim 36.

51. the first electromagnetic coil includes a metal wire, and the minimum diameter of the metal wire is at least 0.5 μm; 37. The microelectronic device of claim 36.

52. the second electromagnetic coil includes a metal wire, and the minimum diameter of the metal wire is at least 0.5 μm; 37. The microelectronic device of claim 36.

53. the first electromagnetic coil and the second electromagnetic coil are configured to operate as a transformer.

37. The microelectronic device of claim 36.

54. 1. A method of forming a microelectronic device, comprising: providing a first semiconductor element and a first coiled structure adjacent to the first semiconductor element, with a first conductive via passing through the first semiconductor element; providing a second semiconductor element and a second coiled structure adjacent to the second semiconductor element; coupling the second semiconductor element to the first semiconductor element such that the first coiled structure and the second coiled structure are connected by the first conductive via to form an electromagnetic coil, and the first coiled structure and the second coiled structure are spaced apart by the first semiconductor element; A method comprising:

55. the second semiconductor element is directly bonded to the first semiconductor element without the use of an intervening adhesive; 55. The microelectronic device of claim 54.

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