Multi-channel device stacking

Abstract

A stacked electronic device is disclosed. The stacked electronic device may have a first stacked assembly including a first plurality of integrated device dies. The first plurality of integrated device dies may include a first integrated device die. A second stacked assembly is deposited on the first integrated assembly. The second stacked assembly may include a second plurality of integrated device dies, the second plurality of integrated device dies may include a second integrated device die. A first channel may extend at least partially through the first stacked assembly. The first integrated device die may have a first circuit, the first channel connected to the first circuit. A second channel may extend through and bypass the first stacked assembly, the second channel extending at least partially through the second stacked assembly. The second integrated device die may have a second circuit, the second channel connected to the second circuit.

Description

[Technical field]

[0001] The technical field relates to multi-channel device stacking.

[0002] [Citation to Related Applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 263,612, filed November 5, 2021 (titled MULTI-CHANNEL DEVICE STACKING), which is incorporated by reference in its entirety and incorporated herein by reference for all purposes. [Background technology]

[0003] Multi-layer semiconductor devices (e.g., integrated device dies) may be stacked on top of each other in various applications, such as processors, high bandwidth memory (HBM) devices, or other devices that utilize vertical integration. The stacked devices can communicate electrically with each other. Signals and power can be transmitted through the die via through substrate vias (TSVs). Summary of the Invention

[0004] According to one aspect of the present invention, there is provided an electronic device comprising: a first stacked assembly including a first plurality of integrated device dies, the first plurality of integrated device dies including a first integrated device die; a second stacked assembly including a second plurality of integrated device dies, the second stacked assembly being attached to the first integrated assembly, the second plurality of integrated device dies including the second integrated device die; a first integrated device die having a first channel extending at least partially through the first stacked assembly, the first integrated device die having a first circuit, the first channel being connected to the first circuit; An electronic device is provided having a second channel extending through and bypassing the first stacked assembly, the second channel extending at least partially through the second stacked assembly, and a second integrated device die having a second circuit, the second channel being connected to the second circuit.

[0005] According to another aspect of the invention, there is provided an electronic device comprising: a first integrated device assembly; a second integrated device assembly attached to the first integrated device assembly; a first channel connected to a first circuit of a first integrated device assembly; An electronic device is provided having a first channel and a second channel different from the first channel, the second channel bypassing the first integrated device assembly, and the second channel being connected to a second circuit of the second integrated device assembly.

[0006] According to yet another aspect of the present invention, there is provided an electronic device comprising: a first plurality of integrated device dies; a second plurality of integrated device dies, the first and second plurality of integrated device dies being stacked on top of one another; a first channel extending at least partially through the first and second plurality of integrated device dies, the first channel connecting to circuitry in the second plurality of integrated device dies and bypassing circuitry in the first plurality of integrated device dies; An electronic device is provided having a second channel extending at least partially through the first and second plurality of integrated device dies, the second channel connected to a circuit arrangement in the first plurality of integrated device dies.

[0007] According to yet another aspect of the present invention, there is provided an integrated device assembly comprising: a first integrated device die having a first circuit; a second integrated device die having a second circuit, the second integrated device die being attached to the first integrated device die; a carrier, a first integrated device die attached to the carrier; a first channel coupled between the carrier and the first circuit, the first channel extending at least partially through the first integrated device die; An integrated device assembly is provided that includes a second channel coupled between the carrier and a second circuit, the second channel extending through the first integrated device die and at least partially through the second integrated device die, the second channel being electrically isolated from the first channel and the first circuit. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional side view of multiple integrated device dies, a carrier, and multiple through-substrate vias (TSVs) including a single channel stacked on top of one another according to one embodiment. [Diagram 2] 1 is a schematic cross-sectional side view of a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly attached to the first stacked assembly and including a second plurality of integrated device dies, a plurality of TSVs including first channels, a second plurality of TSVs including second channels, and a carrier, according to one embodiment. [Diagram 3] FIG. 1 is a schematic cross-sectional side view of a first plurality of integrated device dies and a second plurality of integrated device dies stacked on top of one another according to one embodiment, showing a state in which the integrated device dies of the first plurality of integrated device dies are interleaved with the integrated device dies of the second plurality of integrated device dies, and further showing a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, and a carrier. [Figure 4]FIG. 1 is a schematic cross-sectional side view of a first plurality of integrated device dies and a second plurality of integrated device dies stacked on top of one another according to one embodiment, where the integrated device dies of the first plurality of integrated device dies are interleaved with the integrated device dies of the second plurality of integrated device dies such that the active sides of the first and second plurality of dies are face-to-face; and further showing a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, and a carrier. [Diagram 5] FIG. 1 is a schematic cross-sectional side view of a first plurality of integrated device dies and a second plurality of integrated device dies directly bonded to each other in a stack according to one embodiment, where the integrated device dies of the first plurality of integrated device dies are interleaved with the integrated device dies of the second plurality of integrated device dies, and further showing a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, and a carrier. [Figure 6] FIG. 1 is a schematic cross-sectional side view of a first plurality of integrated device dies and a second plurality of integrated device dies directly bonded to each other in a stack according to one embodiment, where the integrated device dies of the first plurality of integrated device dies are interleaved with the integrated device dies of the second plurality of integrated device dies, and further showing a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, and a carrier. [Figure 7] 1 is a schematic cross-sectional side view of a plurality of conductive features directly bonded to one another; [Figure 8]FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly attached to the first stacked assembly and including a second plurality of integrated device dies, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a first channel path, a second channel path, a processor or logic die, a dicing lane, TSVs disposed within the dicing lane, a carrier, and a substrate according to one embodiment. [Figure 9] FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly deposited on the first stacked assembly and including a second plurality of integrated device dies, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a processor or logic die, a dicing lane, a signal TSV disposed within the dicing lane on one side of the stack, an additional TSV disposed within the dicing lane on the opposite side of the stack, a carrier, and a substrate, according to one embodiment. [Figure 10] FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly deposited on the first stacked assembly and including a second plurality of integrated device dies, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a processor or logic die, a dicing lane, signal TSVs disposed within the dicing lane on one side of the stack, additional TSVs disposed within the dicing lane on the opposite side of the stack, power and / or ground TSVs passing through the first and second stacked assemblies, a carrier, and a substrate, according to one embodiment. [Figure 11]FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly disposed on the first stacked assembly and including a second plurality of integrated device dies, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a dicing lane, a signal TSV disposed within the dicing lane on one side of the stack, an additional TSV disposed within the dicing lane on the opposite side of the stack, and power and / or ground TSVs passing through the first and second stacked assemblies, according to one embodiment. [Figure 12] FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly disposed on the first stacked assembly and including a second plurality of integrated device dies, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a dicing lane, a signal TSV disposed within the dicing lane on one side of the stack, an additional TSV disposed within the dicing lane on the opposite side of the stack, power and / or ground TSVs passing through the first and second stacked assemblies, a carrier, and an interposer, according to one embodiment. [Figure 13] FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly disposed on the first stacked assembly and including a second plurality of integrated device dies, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a dicing lane, a signal TSV disposed in the dicing lane on one side of the stack, an additional TSV disposed in the dicing lane on the opposite side of the stack, power and / or ground TSVs passing through the first and second stacked assemblies, and an interposer, according to one embodiment. [Figure 14]FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly disposed on the first stacked assembly and including a second plurality of integrated device dies, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a dicing lane, a plurality of dummy dies, a signal TSV disposed through a lower dummy die on one side of the stack, an additional TSV disposed through the lower dummy die on the opposite side of the stack, power and / or ground TSVs disposed through the first and second stacked assemblies, a carrier, and an interposer, according to one embodiment. [Figure 15] FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first plurality of integrated device dies, a second stacked assembly disposed on the first stacked assembly and including a second plurality of integrated device dies, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a dicing lane, a plurality of dummy dies, a signal TSV disposed through a lower dummy die on one side of the stack, an additional TSV disposed through the lower dummy die on the opposite side of the stack, power and / or ground TSVs disposed through the first and second stacked assemblies, and an interposer, according to one embodiment. [Figure 16A] FIG. 1 is a schematic cross-sectional side view showing a first stacked assembly including a first integrated device die, a second stacked assembly attached to the first stacked assembly and including a second integrated device die, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a first channel path, a second channel path, a logic die, and a dicing lane, according to one embodiment. [Figure 16B] FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first integrated device die, a second stacked assembly attached to the first stacked assembly and including a second integrated device die, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a first channel path, a second channel path, a logic die, a dicing lane, and TSVs disposed within the dicing lane, according to one embodiment. [Figure 16C]FIG. 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first integrated device die, a second stacked assembly attached to the first stacked assembly and including a second integrated device die, a first plurality of TSVs including a first channel, a first channel path, a second channel path, a logic die, a dicing lane, a dummy die, a TSV disposed in the dummy die, and a TSV disposed in the dicing lane, according to one embodiment. [Figure 16D] 1 is a schematic cross-sectional side view illustrating a first stacked assembly including a first integrated device die, a second stacked assembly attached to the first stacked assembly and including a second integrated device die, a first plurality of TSVs including a first channel, a second plurality of TSVs including a second channel, a first channel path, a second channel path, a logic die, an interposer, a plurality of dummy dies, and a plurality of TSVs disposed within the dummy die, according to one embodiment. [Figure 17A] 1 is a schematic cross-sectional side view of a first microelectronic element and a second microelectronic element. [Figure 17B] 1 is a schematic cross-sectional side view of a first microelectronic element and a second microelectronic element direct hybrid bonded to one another. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The same reference numbers are used throughout the detailed description and drawings to refer to like features.

[0010] Enabling electrical communication between multiple stacked device dies can be a challenge, especially in transmitting signals through a device die of a certain thickness while maintaining a very fine pitch. Compared to solder bonding, direct hybrid bonding allows for very fine pitch electrical connections between vertically adjacent dies while also allowing for a significant reduction in the thickness of the die stack compared to using thick solder balls between the dies. In a conventional memory die stack, the system includes a single channel configured to provide read / write signals throughout the entire die stack. In particular, in high bandwidth memory (HBM) technology, one channel exists in the die stack and every signal is sent to every die in the die stack. In hybrid memory cube (HMC) technology, the die stack has multiple channels and every signal is sent to every die in the die stack. Various embodiments disclosed herein connect second subsets in the die stack together to form a bandwidth channel. For example, a first channel can send a signal to a plurality of dies in a first stacking assembly, and a second channel can send a signal to a plurality of dies in a second stacking assembly that is deposited on the first stacking assembly, such that the second channel bypasses a plurality of second active circuits in the first stacking assembly. Such techniques can be utilized for any suitable type of integrated device die, including memory dies (e.g., dynamic random access memory (DRAM), flash memory with logic NAND type structures (NAND)), and advantageously allow for the implementation of multiple channels, where each channel can provide a unique signal. For example, interconnects can be provided through dicing lanes within the dies, such that high speed signals can be provided on the leading edge of the front side or face of the die stack, while other signal inputs / outputs can be provided on other edges of the die stack.In various embodiments, some of the dies may have signal paths through vias. In various embodiments, thermocompression or direct hybrid bonding electrically connects vertically adjacent dies to each other. In various embodiments, power and ground (reference potentials) may be shared by all channels in the stacked devices, and in various embodiments, the interconnects may be provided in the dummy silicon blocks under the same conditions as used in the dicing lanes. In various embodiments, a redistribution layer (RDL), sometimes called surface wiring, may be deposited on the active front side or on the die surface for configurations where inter-placed dies are stacked face-to-face.

[0011] FIG. 1 is a schematic cross-sectional side view of a conventional stacked electronic device 4. The stacked electronic device may be used in any suitable type of electronic system, such as high bandwidth memory (HBM), hybrid memory cube (HMC) technology, or any other suitable stacked system. As shown, multiple integrated device dies 1a-1h (memory dies, processor dies, etc.) may be stacked on top of each other. A bonding layer 42 may be deposited on a semiconductor layer 43 for each of the dies 1a-1h. The semiconductor layer 43 may have semiconductor device regions in which active devices (e.g., transistors) may be formed. The bonding layer 42 may include one or more metallization layers deposited on the semiconductor layer 43. The stacked dies may be mounted on a carrier 2. In the illustrated configuration, the carrier 2 may include a logic die or a processor die, and the stacked dies 1a-1h may include memory dies. Multiple signal lines 3 may be provided through the stacked dies 1a-1h. For example, each die may have multiple interconnects (e.g., multiple through substrate vias (TSVs) 46) that carry signals through the die to couple to vertically adjacent dies (e.g., TSVs 46 are physical metal interconnects or vias that run through each die separately). The dies may be attached to one another and stacked, for example, by solder balls or thermocompression bonding (TCB). In FIG. 1, the signal line 3 may have a single channel that couples to every die 1a-1h in the stack. In some configurations, the signal line 3 may have multiple channels, with each channel connected to every die in the stack.

[0012] FIG. 2 is a schematic cross-sectional side view of various embodiments of a stacked electronic device 5. The electronic device 5 may have a first stacked assembly 6 including a first plurality of integrated devices 6a-6d. The electronic device may have a second stacked assembly 7 including a second plurality of device dies 7a-7d. The second stacked assembly 7 may be deposited on the first stacked assembly 6. A first channel 8 may extend at least partially through the first stacked assembly 6. The first integrated device die 6a may include a first circuit (not shown), and the first channel 8 may be connected to the first circuit. A second channel 9 may extend through and bypass the first stacked assembly 6. The second channel 9 may extend at least partially through the second stacked assembly 7. The second integrated device die 7a may include a second circuit (not shown), and the second channels 9 may be connected to the second circuit. In various embodiments, each of the first plurality of integrated device die 6a-6d may include an active circuit device area 44 (between the bonding layer 42 and the semiconductor layer 43), and at least the read and / or write signals of the second channels 9 may bypass or not electrically couple to the active circuit device areas 44 of the first plurality of integrated device die 6a-6d.

[0013] Further, in FIG. 2, each die may have an active front side or face 14 and a back side or face 13 opposite the active front side 14. In FIG. 2, the stacked device 5 is configured such that the active front sides 14 of the first plurality of dies 6a-6d and the second plurality of dies 7a-7d face in the same direction (e.g., downward toward the carrier) in a front-to-back arrangement. The dies may be directly hybrid bonded in a front-to-back arrangement. However, in other embodiments, the dies may be directly bonded in a front-to-front or back-to-back arrangement. In various embodiments, the channels (e.g., first and / or second channels 8, 9) may comprise connection paths between a memory controller (e.g., a logic die, e.g., carrier 2) and a memory module (e.g., a dynamic random access memory (DRAM) module, e.g., any of dies 1a-1h). The channels may comprise electrical paths that carry read / write signals. In a single channel application, one read or write signal can be carried at a time, whereas in a multi-channel application, many read / write signals can be carried independently in parallel.

[0014] The first channel 8 and the second channel 9 may extend through the TSVs 46 that pass through the individual dies 6a-6c, 7a-7c of the die stack 6,7. In various embodiments, the TSVs 46 may not be provided in the topmost die 6d,7d of the stack 6,7, e.g., in a face-down arrangement where signals do not need to be routed through the topmost die 6d,7d. The integrated device dies may be attached and electrically connected to each other in any suitable manner. It should be understood that although the die stack 6,7 is shown diagrammatically with vertical gaps between vertically adjacent dies, one skilled in the art would understand that the dies may be physically and electrically coupled to each other (see, e.g., FIGS. 5 and 6). For example, in some embodiments, the first stacked assembly (die stack) 6 may be directly bonded to the second stacked assembly (die stack) 7 without adhesive. Additionally, the dies 6a-6d, 7a-7d in each stack 6,7 may also be directly bonded to each other without adhesive. As described below, a direct hybrid bonding process can be used to connect vertically adjacent die stacks as well as to connect vertically adjacent integrated circuit dies. For example, opposing TSVs 46 can be directly bonded to each other in various embodiments without adhesive (see, for example, FIG. 7). In some embodiments, wide contact pads can be directly bonded to each other with the TSVs 46 attached. In other embodiments, the TSVs 46 can be directly bonded to each other. In other embodiments, the TSVs 46 of the first channel 8 and second channel 9 can be laterally offset in adjacent dies. While the illustrated embodiment shows a directly bonded stacked assembly, in other embodiments, the first stacked assembly 6 can be bonded to the second stacked assembly 7 using solder. The dies within the assembly can be bonded to each other using solder.

[0015] Thus, as shown in FIG. 2, each of the first channel 8 and the second channel 9 can be electrically coupled to only a second subset of the stacked electronic device 5. For example, the first channel 8 can be electrically coupled to only the dies 6a-6d, and the second channel 9 can be electrically coupled to only the dies 7a-7d. Beneficially, the stacked electronic device 5 of FIG. 2 allows for the use of multiple different channels to connect to different dies (or stacks of dies) within the device. Such a configuration can increase the bandwidth of the stacked device. For example, in the configuration of FIG. 1, only one die in stack 1 can be accessed at a time because all of the dies 1a-1h in stack 1 (e.g., the eight dies in the stack of FIG. 1) are shorted together with one channel. In contrast, in FIG. 2, there are two stacks 6,7 of four dies 6a-6d, 7a-7d each with two independent channels 8,9. Thus, in FIG. 2, at least one die can be accessed simultaneously from each of the two channels, thereby doubling the bandwidth of the stacked device. It should be understood that although two channels 8, 9 are shown connected to two respective die stacks 6, 7, any suitable number of channels and die stacks can be provided. For example, three, four, five or more channels and die stacks (or sets) of dies can be provided. In addition, while each die stack 6, 7 in FIG. 2 includes four dies, in other embodiments, each die stack can include two, three, five, six or more dies. Each die stack can include the same number of dies or a different number of dies.

[0016] FIG. 3 is a schematic cross-sectional side view of another embodiment of a stacked electronic device 10. Unless otherwise noted, the components and concepts described herein in connection with FIG. 3 may be the same as or generally similar to the components and concepts described above in connection with FIG. 2. As in FIG. 2, in FIG. 3, the stacked electronic device 10 may include a first plurality of integrated device dies 11a-11d and a second plurality of integrated device dies 12a-12d. The first and second plurality of integrated device dies are stacked on top of one another. A first channel 8 may extend at least partially through the first plurality of integrated device dies 11a-11d and the second plurality of integrated device dies 12a-12d. The first channels 8 are connected to the circuitry in the active circuitry area 44 in the second plurality of integrated device dies 12a-12d and bypass the circuitry in the active circuitry area 44 in the first plurality of integrated device dies 11a-11d (e.g., at least the read and / or write signals of the first channels 8 bypass the active circuitry area 44 in the first plurality of integrated device dies 11a-11d). The second channels 9 may extend at least partially through the first plurality of integrated device dies 11a-11d and the second plurality of integrated device dies 12a-12d. The second channels 9 are connected to the circuitry in the active circuitry area 44 in the first plurality of integrated device dies 11a-11d. Thus, the stacked electronic device 10 of FIG. 3 may realize the use of multiple different channels to couple to different dies (or stacks of dies) within the device, thereby increasing the bandwidth of the stacked device 10.

[0017] Unlike the embodiment of FIG. 2 (e.g., in which the second plurality of dies 7a, 7d are stacked on top of the first plurality of dies 6a-6d, or vice versa), in FIG. 3 the first plurality of integrated device dies 11a-11d and the second plurality of integrated device dies 12a-12d are stacked on top of one another such that the integrated device dies of the first plurality of integrated device dies 11a-11d are interleaved with the integrated device dies of the second plurality of integrated device dies 12a-12d. Further, in FIG. 3 each die may have an active front side 14 and a back side 13 opposite the front side 14. Active circuitry areas 44 (e.g., transistors) may be located closer to the front side 14 than the back side of each die 13. In FIG. 3, the stacked device 10 is configured such that the active front sides 14 of the first and second die plurality 11a-11d, 12a-12d are facing in the same direction (e.g., downward toward the carrier) in a front-to-back arrangement. The dies may be direct hybrid bonded such that the active front side 14 of each die is directly bonded to the back side 13 of a vertically adjacent die. However, in other embodiments, the active front sides 14 in the first and second die plurality 11a-11d, 12a-12d may face upward, away from the carrier 2. It should be understood that although the die plurality 11a-11d, 12a-12d are shown diagrammatically with vertical gaps between vertically adjacent dies, one skilled in the art would understand that the dies may be physically and electrically coupled to one another (see, e.g., FIGS. 5 and 6).

[0018] FIG. 4 is a schematic cross-sectional side view of a stacked electronic device according to another embodiment. Unless otherwise noted, the components and concepts described herein in connection with FIG. 4 may be the same as or generally similar to those described above in connection with FIG. 3. Similar to the embodiment of FIG. 3, the stacked electronic device 15 of FIG. 4 may realize the use of multiple different channels to couple to different dies (or stacks of dies) 11a-11d, 12a-12d within the device. Such a configuration increases the bandwidth of the stacked device 15. In addition, the dies may be directly hybrid bonded to each other. Unlike the embodiment of FIG. 3, the active front sides 14 of the first plurality of dies 11a-11d and the second plurality of dies 12a-12d may be disposed face-to-face facing each other, as shown in FIG. 4. The active front sides 14 of each of the second vertically adjacent dies may be directly bonded to one another, and the back sides 13 of each of the vertically adjacent dies may be directly bonded to one another. For example, the dies of the second plurality of dies 12a-12d may face downward toward the carrier 2, and the dies of the first plurality of dies 11a-11d may face upward, away from the carrier 2. As in Figure 3, in Figure 4, it should be understood that the dies 11a-11d, 12a-12d are shown generally with vertical gaps between vertically adjacent dies, although one skilled in the art would understand that the dies may be physically and electrically coupled to one another (see, e.g., Figures 5 and 6).

[0019] FIG. 5 illustrates a stacked device 17 similar to that illustrated in FIG. 3, in which the active front sides 14 face in the same direction (e.g., downward toward the carrier 2). FIG. 6 illustrates a stacked device 18 similar to that illustrated in FIG. 4, in which the active front sides 14 of the first and second die plurality 11a-11d, 12a-12d face in opposite directions (e.g., toward each other). As illustrated in FIGS. 5-7, the conductive features 16 (e.g., opposing TSVs and / or contact pads) may be directly bonded to each other without adhesive, thereby enabling the use of fine pitch interconnects compared to conventional structures. In some embodiments, the conductive features 16 may include contact features on opposing die that directly contact each other to form electrical connections without adhesive. In various embodiments, the conductive features 16 may include exposed ends of TSVs, contact pads, or other metallization exposed at a bonding surface.

[0020] FIG. 8 is a schematic cross-sectional side view of another embodiment of a stacked electronic device 19. Unless otherwise noted, the components and concepts described herein in connection with FIG. 8 may be the same as or generally similar to the components and concepts described above in connection with FIGS. 2-7. As shown in FIG. 8, a first stacked structure 6 and a second stacked structure 7 may be disposed one above the other as shown in FIG. 2. The stacked die may be attached to a carrier 2, such as a logic die or an interposer. The carrier 2 may be attached to a substrate 20, such as an interposer or other device die. A processor or logic die 21 may be attached to the substrate 20 with the processor or logic die 21 spaced apart from the carrier 2. As shown, the processor or logic die 21 and carrier 2 may be attached to the substrate 20 by solder balls 22. In other embodiments, the processor or logic die 21 and / or carrier 2 may be direct bonded to the substrate 20.

[0021] Unlike the embodiment of Figures 2-7, in Figure 8, the first channel 8 and the second channel 9 may be electrically coupled to their respective die stacks via TSVs 27 provided in the dicing lanes 23a, 23b at or near the periphery of the die (e.g., outside the active areas of the die). As shown, the first channel vias 24 may extend from the logic die 21 through the substrate 20 and carrier 2 (e.g., via traces provided in the substrate 20 and carrier 2) and through the dicing lanes 23a, 23b of the die, bypassing the lower die stack via the TSVs 27. The first channel and vias 24 may be coupled to the upper stack 7 of dies without being electrically coupled to circuitry in the lower stack 6 of dies. The second channel vias 25 may extend from the logic die 21 through the substrate 20 and carrier 2 (e.g., via traces provided in the substrate 20 and carrier 2) and electrically coupled to a die of the lower die stack 6.

[0022] Figure 9 is a schematic cross-sectional side view of another embodiment of a stacked electronic device 26. Unless otherwise noted, the components and concepts described herein in connection with Figure 9 may be the same as or generally similar to the components and concepts described above in connection with Figure 8. In Figure 9, several TSVs 27 may be provided through the first crane 23a on one side of the stack, and additional TSVs 28 may be provided through the first crane 23b on the opposite side of the stack.

[0023] For example, in various embodiments, each channel 8, 9 of the stacked device 26 may have multiple signal lines, including high speed and low speed signal lines, in addition to power connections, ground connections, test interconnects, and / or other connections. In some embodiments, the higher speed signal lines may be provided along physically shorter paths (e.g., the signal TSV input / output (I / O) paths 27 of FIG. 9), while the lower speed signal lines may be provided along physically longer paths (e.g., the remaining TSV I / O paths 28 of FIG. 9). In some embodiments, power may be provided along the power supply lines on the left side of the stack.

[0024] FIG. 10 is a schematic cross-sectional side view of another embodiment of a stacked electronic device 29. Unless otherwise noted, the components and concepts described herein in connection with FIG. 10 may be the same as or generally similar to the components and concepts described above in connection with FIG. 9. In FIG. 10, additional TSVs 30, 45 for power and ground, or shared TSVs 30, 45 may be provided through both die stacks (e.g., through die stacks 6, 7) to provide power and / or ground connections to the dies of device 29. The stacked device 29 of FIG. 10 may utilize a common power and / or ground path such that the dies of die stacks 6, 7 may each access power through power channel 30 and ground channel 45.

[0025] Figure 11 shows a three dimensional integrated circuit (3DIC) stack 31 of dies similar to the stack shown in Figure 10 stacked together to include two channels 8, 9 as described above. The dies in Figure 11 may be stacked together and direct bonded, and the stacked structure may be attached to a carrier in some embodiments. In some embodiments, the stack 31 may be direct hybrid bonded to the carrier. In other embodiments, the stack 31 may be attached to the carrier with a conductive adhesive, such as solder.

[0026] FIG. 12 is a schematic cross-sectional side view of another embodiment of a stacked electronic device 32. FIG. 13 shows a three-dimensional integrated circuit (3DIC) stack 33 of the dies of the device 32 of FIG. 12 stacked together to include two channels 8, 9. Unless otherwise noted, the components and concepts described herein in conjunction with FIG. 12 and FIG. 13 may be the same as or generally similar to the components and concepts described above in conjunction with FIG. 2-FIG. 11. In FIG. 12 and FIG. 13, an interposer 34 may be provided between the die stacks 6, 7. TSVs 27, 28 extending through the interposer 34 may electrically connect the channel I / O 9 to the upper stack of dies 7. The interposer 34 may include any suitable type of structure, such as a semiconductor interposer with patterned metal vias and traces, a packaging substrate, a ceramic substrate, or the like.

[0027] FIG. 14 is a schematic cross-sectional side view of another embodiment of a stacked electronic device 35. FIG. 15 shows a three-dimensional integrated circuit (3DIC) stack 36 of the dies of the device 35 of FIG. 14 stacked together to include two channels 8, 9. Unless otherwise noted, the components and concepts described herein in conjunction with FIG. 14 and FIG. 15 may be the same as or generally similar to the components and concepts described above in conjunction with FIG. 2-FIG. 13. In FIG. 14 and FIG. 15, instead of providing TSVs 27, 28 through the first cranes 23a, 23b at the periphery of the die, one or more dummy dies 37 (which may be devoid of active circuitry) may be provided outside the periphery of the active dies. The TSVs 27, 28 may be provided through the lower dummy die and the interposer 34 to couple to the upper set 7 of dies connected to the signal channels 9.

[0028] 16A-16D are exemplary architectures that diagrammatically illustrate connections between a logic chip 38 and a pair of first and second stacked dies (e.g., a first die 39 stacked on a second die 40). Although FIGS. 16A-16D show two dies 39, 40 in a stack, in other embodiments multiple dies can be provided in multiple stacks as described above. In FIG. 16A, the logic die 38 can be independently coupled to the first die 39 and the second die 40 via respective arrays of TSVs 46 such that signals are not shared between the first channel path 24 and the second channel path 25. In Figure 16B, the logic die 38 can be independently coupled to the first die 39 and the second die 40 with the first channel path 24 coupled to the top die 39 via the TSVs 41 (e.g., the first channel path 24 passes through the TSVs 41) through the dicing lanes 23, such that signals are not shared between the first channel path 24 and the second channel path 25. In Figure 16C, the logic die 38 can be independently coupled to the first die 39 and the second die 40 with the first channel path 24 coupled to the top die 39 via the TSVs 41 (e.g., the first channel path 24 passes through the TSVs 41) provided through the dummy die 37, such that signals are not shared between the first channel path 24 and the second channel path 25. In FIG. 16D, the logic die 38 can be independently coupled to the first die 39 and the second die 40, with the first channel path 24 coupled to the upper die 39 via a TSV 41 (e.g., the first channel path 24 passes through the TSV 41) that passes through the dummy die 37 and the interposer 34, such that signals are not shared between the first channel path 24 and the second channel path 25.

[0029] Examples of direct bonding methods and directly bonded structures Various embodiments disclosed herein relate to direct bonded structures that can directly bond two or more elements without an intervening adhesive. Figures 17A and 17B are schematic illustrations of a process for forming a direct hybrid bonded structure without an intervening adhesive according to some embodiments. In Figures 17A and 17B, a bonded structure 100 has two elements 102, 104 that can be directly bonded to each other at a bond interface 118 without an intervening adhesive. Two or more microelectronic elements 102, 104 (e.g., semiconductor elements including integrated device dies, wafers, passive devices, and individual active devices such as power switches) can be stacked or bonded to each other to form the bonded structure 100. A conductive feature 106a (e.g., a contact pad, an exposed end of a via (e.g., TSV), or a through-substrate electrode) of a first element 102 can be electrically connected to a corresponding conductive feature 106b of a second element 104. Any suitable number of elements can be stacked in the bonded structure 100. For example, a third element (not shown) can be stacked on the second element 104, a fourth element (not shown) can be stacked on the third element, and so on. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to one another along the first element 102. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the laterally stacked additional elements can be half the size of the second element.

[0030] In some embodiments, the elements 102, 104 are directly bonded to each other without adhesive. In various embodiments, a non-conductive field region comprising a non-conductive or dielectric material may serve as the first bonding layer 108a of the first element 102, and the first bonding layer 108a may be directly bonded to a corresponding non-conductive field region comprising a non-conductive or dielectric material that serves as the second bonding layer 108b of the second element 104 without adhesive. The non-conductive bonding layers 108a, 108b may be provided on the device portions 110a, 110b, e.g., on the front surfaces 114a, 114b of the semiconductor (e.g., silicon) portions of the elements 102, 104, respectively. Active devices and / or circuits may be patterned and / or otherwise provided in or on the device portions 110a, 110b. Active devices and / or circuitry may be provided at or near the front sides 114a, 114b of the device portions 110a, 110b and / or at or near the opposite back sides 116a, 116b of the device portions 110a, 110b. Bonding layers may be provided on the front and / or back sides of the elements. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer 108a of the first element 102. In some embodiments, the non-conductive bonding layer 108a of the first element 102 may be directly bonded to a corresponding non-conductive bonding layer 108b of the second element 104 using dielectric-to-dielectric bonding techniques. For example, the dielectric bond may be formed without adhesive using direct bonding techniques as disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes. It should be understood that in various embodiments, bonding layers 108a and / or 108b may be comprised of a non-conductive material, such as a dielectric, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon.Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, or carbon, such as silicon carbide, silicon oxycarbonitride, low-k dielectrics, S. i The dielectric may include a material containing a COH dielectric, silicon carbonitride, or diamond-like carbon or diamond surface. Such carbon-containing ceramic materials may be considered inorganic, despite the carbon content. In some embodiments, the dielectric does not include a polymeric material, such as an epoxy, resin, or molding compound.

[0031] In some embodiments, the device portions 110a, 110b may have significantly different coefficients of thermal expansion (CTE) that define a heterogeneous structure. The difference in CTE between the device portions 110a, 110b, especially between the bulk semiconductor, typically single crystal portions of the device portions 110a, 110b, may be greater than 5 ppm, or greater than 10 ppm. For example, the difference in CTE between the device portions 110a, 110b may be in the range of 5 ppm to 100 ppm, 5 ppm to 40 ppm, 10 ppm to 100 ppm, or 10 ppm to 40 ppm. In some embodiments, one of the device portions 110a, 110b may be made of an optoelectronic single crystal material (including a perovskite material) useful for opto-piezoelectric or pyroelectric applications, while the other of the device portions 110a, 110b is made of a more conventional substrate material. For example, device portions 110a, 110b may be made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3) and the other of device portions 110a, 110b may be made of silicon (Si), quartz, fused silica, sapphire, or glass. In other embodiments, one of device portions 110a, 110b may be made of a single III-V semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of device portions 110a, 110b may be made of a non-III-V semiconductor material, such as silicon (Si), or another material with a similar CTE, such as quartz, fused silica, sapphire, or glass.

[0032] In various embodiments, the direct hybrid bond can be formed without an intervening adhesive. For example, the non-conductive bonding surfaces 112a, 112b can be polished to a high degree of smoothness. For example, chemical mechanical polishing (CMP) can be used to polish the non-conductive bonding surfaces 112a, 112b. The polished bonding surfaces 112a, 112b can have a roughness of less than 30 Å rms. For example, the roughness of the bonding surfaces 112a, 112b can be in the range of about 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. The bonding surfaces 112a, 112b can be cleaned and exposed to a plasma and / or an etchant to activate the surfaces 112a, 112b. In some embodiments, the surfaces 112a, 112b can be terminated with chemical species after or during activation (e.g., during a plasma and / or etching process). Without being bound by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces, and a termination process can provide one or more additional chemical species at the bonding surfaces 112a, 112b that improves the bonding energy during direct bonding. In some embodiments, activation and termination can be provided in the same step, e.g., the surfaces 112a, 112b can be activated and terminated using a plasma. In other embodiments, the bonding surfaces 112a, 112b can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination species can include nitrogen. For example, in some embodiments, the bonding surfaces 112a, 112b can be exposed to a nitrogen-containing plasma. Additionally, in some embodiments, the bonding surfaces 112a, 112b may be exposed to fluorine, for example to produce one or multiple fluorine peaks at or near the bond interface 118 between the first element 102 and the second element 104.Thus, in the direct bonded structure 100, the bond interface 118 between the two non-conductive materials (e.g., bonding layers 108a, 108b) can comprise a very smooth interface with a high nitrogen content and / or fluorine peak at the bond interface 118. Additional examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes. The roughness of the polished bonding surfaces 112a, 112b may be slightly rough (e.g., about 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or even rougher in some cases) after the activation process.

[0033] In various embodiments, the conductive feature 106a of the first element 102 may also be directly bonded to the corresponding conductive feature 106b of the second element 104. For example, direct hybrid bonding techniques may be used to provide inter-conductor direct bonds along the bond interface 118 that includes a covalently directly bonded non-conductive (e.g., inter-dielectric) surface that has been pretreated as described above. In various embodiments, the inter-conductor (e.g., conductive feature 106a-conductive feature 106b) direct bonds and inter-dielectric hybrid bonds may be formed using direct bonding techniques as disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference in its entirety and for all purposes. In the direct hybrid bonding embodiments described herein, the conductive features are provided within a non-conductive bonding layer, and both the conductive features and the passive conductive features are prepared for direct bonding, for example, by the planarization, activation and / or termination processes described above. Thus, the bonding surface that has been prepared for direct bonding has both conductive and non-conductive features.

[0034] For example, the non-conductive (dielectric) bonding surfaces 112a, 112b (e.g., including inorganic dielectric surfaces) can be pretreated and directly bonded to one another without an intervening adhesive as described above. The conductive contact features (e.g., conductive features 106a, 106b), which may be at least partially surrounded by a non-conductive dielectric field region in the bonding layers 108a, 108b, can also be directly bonded to one another without an intervening adhesive. In various embodiments, the conductive features 106a, 106b may include separate pads or traces at least partially embedded in the non-conductive field region. In some embodiments, the conductive contact features may comprise exposed contact surfaces of through-substrate vias (e.g., through-silicon vias TSVs). In some embodiments, the conductive features 106a, 106b may be recessed below the dielectric field region or the outer surface (e.g., top surface) of the non-conductive bonding layers 108a, 108b, e.g., by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. In various embodiments, prior to direct bonding, the recesses of the opposing elements may be dimensioned such that the total gap between the opposing contact pads is less than 15 nm, or less than 10 nm. The non-conductive bonding layers 108a, 108b may be directly bonded to each other at room temperature without adhesive, and the bonded structure 100 may then be annealed. Upon annealing, the conductive features 106a, 106b may expand and contact each other, thereby forming a metal-to-metal direct bond. Beneficially, Direct Bond Interconnect, or DBI (registered trademark) technology, commercially available from Adeia, Inc. of San Jose, California, can be used to connect high density conductive features 106a, 106b across the direct bond interface 118 (e.g., with a small or fine pitch for a regular array).In some embodiments, the pitch of the conductive features 106a, 106b, e.g., the conductive traces embedded in one of the bonding surfaces of the bonded elements, may be less than 100 microns, less than 10 microns, or even less than 2 microns. For some applications, the ratio of the pitch of the conductive features 106a, 106b to one of the dimensions of the bonding pad (e.g., the diameter) may be less than 20, less than 10, less than 5, less than 3, or even desirably less than 2. In other applications, the width of the conductive traces embedded in one of the bonding surfaces of the bonded elements may be in the range of 0.3 microns to 20 microns (e.g., in the range of 0.3 microns to 3 microns). In various embodiments, the conductive features 106a, 106b may be made of copper or a copper alloy, although other metals may be suitable. For example, the conductive features disclosed herein, e.g., the conductive features 106a, 106b, may be made of a fine-grained metal (e.g., fine-grained copper).

[0035] Thus, in a direct bonding process, the first element 102 may be directly bonded to the second element 104 without an intervening adhesive. In some configurations, the first element 102 may comprise a singulated element, such as a singulated integrated device die. In other configurations, the first element 102 may comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 104 may comprise a singulated element, such as a singulated integrated device die. In other configurations, the second element 104 may comprise a carrier or substrate (e.g., a wafer). Thus, the embodiments disclosed herein may be applicable to wafer-to-wafer (W2W) bonding processes, die-to-die (D2D) bonding processes, or die-to-wafer (D2W) bonding processes. In a wafer-to-wafer (W2W) process, two or more wafers may be directly bonded together (e.g., direct hybrid bonding) and then singulated using a suitable singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially flush with one another and may include indicia indicative of the common singulation process for the bonded structures (e.g., saw marks if a saw singulation process is used).

[0036] As described herein, the first element 102 and the second element 104 can be directly bonded together without adhesive, which is different from a deposition process and results in a structurally different interface compared to deposition. In one application, the width of the first element 102 in the bonded structure is approximately the same as the width of the second element 104. In some other embodiments, the width of the first element 102 in the bonded structure 100 is different from the width of the second element 104. Similarly, the width or area of ​​the larger element in the bonded structure may be at least 10% larger than the width or area of ​​the smaller element. Thus, the first and second elements 102, 104 may be comprised of non-deposited elements. Furthermore, unlike deposited layers, the direct bonded structure 100 may include defect areas along the bond interface 118 where nanoscale voids (nanovoids) exist. The nanovoids may form due to activation (e.g., exposure to plasma) of the bonding surfaces 112a, 112b. As discussed above, the bond interface 118 may include condensation of materials resulting from activation and / or the final chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak may form at the bond interface 118. The nitrogen peak may be detectable using a secondary ion mass spectrometer. In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding layer to a nitrogen-containing plasma) may replace a hydrolyzed (OH-terminated) surface with NH2 molecules, resulting in a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen peak may form at the bond interface 118. In some embodiments, the bond interface 118 may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As discussed herein, the direct bond includes a covalent bond, which is stronger than a van der Waals bond. The bonding layers 108a, 108b may further have a polished surface that is planarized to a high degree of smoothness.

[0037] In various embodiments, the metal-to-metal bond between the conductive features 106a, 106b may be bonded such that the metal grains grow into one another across the bond interface 118. In some embodiments, the metal is or includes copper, which may have grains oriented along (111) crystallographic planes to enhance copper diffusion across the bond interface 118. In some embodiments, the conductive features 106a, 106b may include a nano-twinned copper crystal structure, which may aid in the coalescence of the conductive features during annealing. The bond interface 118 may extend substantially completely to at least a portion of the bonded conductive features 106a, 106b, such that there are substantially no gaps between the non-conductive bonding layers 108a, 108b at or near the bonded conductive features 106a, 106b. In some embodiments, a barrier layer may be provided underneath or laterally surrounding the conductive features 106a, 106b (which may, for example, comprise copper). However, in other embodiments, there may not be a barrier layer underneath the conductive features 106a, 106b, as described, for example, in U.S. Patent No. 11,195,748, which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0038] Beneficially, the use of the hybrid bonding techniques described herein allows for very fine pitches of adjacent conductive features 106a, 106b and / or small pad sizes. For example, in various embodiments, the pitch p between adjacent conductive features 106a (or 106b) (i.e., edge-to-edge or center-to-center distance as shown in FIG. 17A) may be in the range of 0.5 microns to 50 microns, 0.75 microns to 25 microns, 1 micron to 25 microns, 1 micron to 10 microns, or 1 micron to 5 microns. Furthermore, the major lateral dimensions (e.g., pad diameter) may also be small, e.g., in the range of 0.25 microns to 30 microns, 0.25 microns to 5 microns, or 0.5 microns to 5 microns.

[0039] As described above, the non-conductive bonding layers 108a, 108b may be directly bonded to one another without an adhesive, and then the bonded structure 100 may be annealed. Upon annealing, the conductive features 106a, 106b may expand and contact one another, thereby forming a direct metal-to-metal bond. In some embodiments, the materials of the conductive features 106a, 106b may interdiffuse during the annealing process.

[0040] Exemplary embodiments of multi-channel device stacking In one embodiment, the electronic device can have a first stacked assembly including a first plurality of integrated device die, the first plurality of integrated device die including the first integrated device die, the electronic device can have a second stacked assembly including a second plurality of integrated device die, the second stacked assembly is deposited on the first integrated assembly, the second plurality of integrated device die including the first integrated device die, the electronic device can have a first channel extending at least partially through the first stacked assembly, the first integrated device die having a first circuit, the first channel connected to the first circuit, the electronic device can have a second channel extending through and bypassing the first stacked assembly, the second channel extending at least partially through the second stacked assembly, the second integrated device die having a second circuit, the second channel connected to the second circuit.

[0041] In some embodiments, the first stacked assembly is directly bonded to the second stacked assembly. In some embodiments, the first integrated device die has a first non-conductive bonding layer, the first non-conductive bonding layer further having a first plurality of conductive features, and the second integrated device die has a second non-conductive bonding layer, the second non-conductive bonding layer further having a second plurality of conductive features, the first non-conductive bonding layer is directly bonded to the second non-conductive bonding layer, and the first plurality of conductive features are directly bonded to the second plurality of conductive features. In some embodiments, the first stacked assembly is bonded to the second stacked assembly using solder. In some embodiments, each of the first plurality of integrated device dies has an active circuit device area, and at least the read and / or write signals of the second channel bypass the active circuit device area of ​​the first plurality of integrated device dies. In some embodiments, the first stacking assembly includes a dummy die disposed adjacent to the first plurality of integrated device dies, and the second channel extends through the dummy die. In some embodiments, the second channel does not extend through the first plurality of integrated device dies. In some embodiments, the second stacking assembly is directly mounted on the first stacking assembly. In some embodiments, the first stacking assembly is direct hybrid bonded to the second stacking assembly. In some embodiments, the electronic device may include an interposer, and the second stacking assembly is mounted on the interposer, and the interposer is mounted on the first stacking assembly. In some embodiments, the second channel does not extend through the first plurality of integrated device dies. In some embodiments, the second channel extends through the interposer. In some embodiments, the second stacking assembly is direct hybrid bonded to the interposer.In some embodiments, the first channel has one or more first interconnects that at least partially penetrate the first integrated device die, and the second channel has one or more second interconnects that penetrate the second integrated device die. In some embodiments, the one or more second interconnects penetrate an active circuitry area of ​​the first integrated device die, and the one or more second interconnects penetrate a dicing lane of the first integrated device die. In some embodiments, the one or more second interconnects penetrate a dicing lane of the first integrated device die. In some embodiments, the second channel is configured to conduct a first signal along a first path, and the first channel is configured to conduct a second signal along a second path, the second path being longer than the first path, and the first signal having a higher frequency than the second signal. In some embodiments, the first path is provided between the second stacked assembly and the processor die, and the second path is provided between the first stacked assembly and the processor die.

[0042] In another embodiment, an electronic device may have a first integrated device assembly, a second integrated device assembly deposited on the first integrated device assembly, a first channel connected to a first circuit of the first integrated device assembly, and a second channel different from the first channel, where the second channel bypasses the first integrated device assembly and is connected to a second circuit of the second integrated device assembly.

[0043] In some embodiments, the second integrated device assembly is direct hybrid bonded to the first integrated device assembly. In some embodiments, the second channel extends through the first integrated device assembly. In some embodiments, the first integrated device assembly is comprised of a plurality of integrated device dies stacked together. In some embodiments, at least two of the plurality of integrated devices are direct hybrid bonded to one another. In some embodiments, the plurality of integrated device dies are direct hybrid bonded to one another. In some embodiments, the second channel extends through the plurality of integrated device dies. In some embodiments, the second channel extends along a side edge of the plurality of integrated device dies. In some embodiments, the first integrated device assembly includes a dummy die disposed adjacent to the plurality of integrated device dies, the second channel extends through the dummy die, and in some embodiments, the second channel does not extend through the plurality of integrated device dies of the first integrated device assembly. In some embodiments, the electronic device may include an interposer located between the first integrated device assembly and the second integrated device assembly, and the second channel extends through the interposer. In some embodiments, the second channel does not extend through the integrated device dies of the first integrated device assembly. In some embodiments, the second integrated device assembly is direct hybrid bonded to the interposer. In some embodiments, the integrated device dies include a dicing lane, and the second channel is disposed within the dicing lane.

[0044] In another embodiment, an electronic device may have a first plurality of integrated device dies and a second plurality of integrated device dies, the first and second plurality of integrated device dies being stacked on top of one another, the electronic device may further have a first channel extending at least partially through the first and second plurality of integrated device dies, the first channel connecting to circuitry in the second plurality of integrated device dies and bypassing circuitry in the first plurality of integrated device dies, and the electronic device may further have a second channel extending at least partially through the first and second plurality of integrated device dies, the second channel connecting to circuitry in the first plurality of integrated device dies.

[0045] In some embodiments, at least two of the first plurality of integrated device dies are direct hybrid bonded to one another and at least two of the second plurality of integrated device dies are direct hybrid bonded to one another. In some embodiments, each die of the first plurality of integrated device dies is direct hybrid bonded to another die of the first plurality of integrated device dies and each die of the second plurality of integrated device dies is direct hybrid bonded to another die of the second plurality of integrated device dies. In some embodiments, the first and second plurality of integrated device dies are stacked together such that the integrated device dies of the first plurality of integrated device dies are interleaved with the integrated device dies of the second plurality of integrated device dies. In some embodiments, a die of the first plurality of integrated device dies is direct hybrid bonded to a die of the second plurality of integrated device dies. In some embodiments, the first plurality of integrated device dies are stacked together to form a first integrated device assembly, and the second plurality of integrated device dies are stacked together to form a second integrated device assembly, and the second integrated device assembly is deposited onto the first integrated device assembly. In some embodiments, the first integrated device assembly is direct hybrid bonded to the second integrated device assembly. In some embodiments, each of the first plurality of integrated device dies has at least one dicing lane, and the first channel extends through the at least one dicing lane.

[0046] In another embodiment, an integrated device assembly may include a first integrated device die having a first circuit and a second integrated device die having a second circuit, the second integrated device die being attached to the first integrated device die, the integrated device assembly may include a carrier, the first integrated device die is attached to the carrier, the integrated device assembly may include a first channel coupled between the carrier and the first circuit, the first channel extending at least partially through the first integrated device die, the integrated device assembly may include a second channel coupled between the carrier and the second circuit, the second channel extending through the first integrated device die and at least partially through the second integrated device die, the second channel being electrically isolated from the first channel and the first circuit.

[0047] In some embodiments, the integrated device assembly may include a third integrated device die having a third circuit, the third integrated device die being disposed on the first integrated device die, and the first channel being coupled between the carrier and the third circuit, and the integrated device assembly may include a fourth integrated device die having a fourth circuit, the fourth integrated device die being disposed on the first integrated device die, the second integrated device die, and the third integrated device die, and the second channel being coupled between the carrier and the fourth circuit. In some embodiments, the third integrated device die is disposed between the second integrated device die and the fourth integrated device die, and the first channel extends through the second integrated device die. In some embodiments, the third integrated device die is disposed between the first integrated device die and the second integrated device die. In some embodiments, the carrier comprises a logic device.

[0048] Unless the context clearly requires otherwise, throughout the specification and claims, the terms "comprise", "comprising", "include", "including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to", as opposed to an exclusive or exhaustive sense. As used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other through one or more intermediate elements. Similarly, as used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other through one or more intermediate elements. In addition, the terms "herein," "above," "below," and words of similar import as used in the parent application refer to the application as a whole and not to any particular portion of the application. Furthermore, as used herein, when a first element is described as being located "on" or "over" a second element, the first element may be directly located on or over the second element such that the first element and the second element are in direct contact with each other, or the first element may be indirectly located on or over the second element such that one or more elements are interposed between the first element and the second element. Where the context permits, terms in the above detailed description using the singular or plural may include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0049] Furthermore, conditional terms used in the specification, particularly "can," "could," "might," "may," "eg," "for example," "such as," and the like, unless expressly specified otherwise or understood otherwise within the context in which they are used, are generally intended to imply that certain embodiments include certain features, elements, and / or conditions and that other embodiments do not include certain features, elements, and / or conditions. Thus, such conditional terms are not generally intended to imply that features, elements, and / or conditions are present in any required manner for one or more embodiments.

[0050] Although certain embodiments have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, although blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention as set forth in the appended claims and equivalents thereto is intended to include such forms or modifications within the scope and spirit of the invention.

Claims

1. 1. An electronic device comprising: a first stacked assembly including a first plurality of integrated device dies, the first plurality of integrated device dies including a first integrated device die; a second stacked assembly including a second plurality of integrated device dies, the second stacked assembly being attached to the first stacked assembly, the second plurality of integrated device dies including a second integrated device die; a first channel extending at least partially through the first stacked assembly, the first integrated device die having a first circuit, the first channel connected to the first circuit; an integrated device die including a second channel extending through and bypassing the first stacked assembly, the second channel extending at least partially through the second stacked assembly, the second integrated device die including a second circuit, the second channel connected to the second circuit.

2. The electronic device of claim 1 , wherein the first laminated assembly is direct bonded to the second laminated assembly.

3. 3. The electronic device of claim 2, wherein the first integrated device die has a first non-conductive bonding layer, the first non-conductive bonding layer further having a first plurality of conductive features; the second integrated device die has a second non-conductive bonding layer, the second non-conductive bonding layer further having a second plurality of conductive features; the first non-conductive bonding layer is direct-bonded to the second non-conductive bonding layer; and the first plurality of conductive features are direct-bonded to the second plurality of conductive features.

4. The electronic device of claim 1 , wherein the first laminated assembly is bonded to the second laminated assembly with solder.

5. 2. The electronic device of claim 1, wherein each of the first plurality of integrated device dies has an active circuit device area, and wherein at least the read and / or write signals of the second channel bypass the active circuit device areas of the first plurality of integrated device dies.

6. 2. The electronic device of claim 1, wherein the first stacked assembly includes a dummy die disposed adjacent to the first plurality of integrated device dies, and the second channel extends through the dummy die.

7. The electronic device of claim 1 , wherein the second stacked assembly is mounted directly onto the first stacked assembly.

8. The electronic device of claim 1 , wherein the first laminated assembly is direct hybrid bonded to the second laminated assembly.

9. The electronic device of claim 1 , further comprising an interposer, wherein the second stacked assembly is mounted on the interposer, and the interposer is mounted on the first stacked assembly.

10. The electronic device of claim 9 , wherein the second channel extends through the interposer and does not extend through the first plurality of integrated device dies.

11. 2. The electronic device of claim 1, wherein the first channel has one or more first interconnects extending at least partially through the first integrated device die, and the second channel has one or more second interconnects extending through the second integrated device die.

12. 12. The electronic device of claim 11, wherein the one or more second interconnects extend through active circuitry areas of the first integrated device die, and the one or more second interconnects extend through dicing lanes of the first integrated device die.

13. The electronic device of claim 11 , wherein the one or more second interconnects extend through a dicing lane of the first integrated device die.

14. 10. The electronic device of claim 1, wherein the second channel is configured to carry a first signal along a first path and the first channel is configured to carry a second signal along a second path, the second path being longer than the first path and the first signal having a higher frequency than the second signal.

15. 1. An electronic device comprising: a first integrated device assembly; a second integrated device assembly attached to the first integrated device assembly; a first channel connected to a first circuit of the first integrated device assembly; and a second channel different from the first channel, the second channel bypassing the first integrated device assembly and connected to a second circuit of the second integrated device assembly.

16. The electronic device of claim 15 , wherein the second integrated device assembly is direct hybrid bonded to the first integrated device assembly.

17. The electronic device of claim 15 , wherein the second channel extends through the first integrated device assembly.

18. 20. The electronic device of claim 17, wherein the first integrated device assembly comprises a plurality of integrated device dies stacked together.

19. 20. The electronic device of claim 18, wherein the second channel extends along a side edge of the plurality of integrated device dies.

20. 20. The electronic device of claim 18, wherein the first integrated device assembly includes a dummy die disposed adjacent to the plurality of integrated device dies, and the second channel extends through the dummy die but does not extend through the plurality of integrated device dies of the first integrated device assembly.

21. 16. The electronic device of claim 15, further comprising an interposer positioned between the first integrated device assembly and the second integrated device assembly, the second channel extending through the interposer and not through the plurality of integrated device dies of the first integrated device assembly.

22. 20. The electronic device of claim 18, wherein the plurality of integrated device dies have dicing lanes, and the second channel is disposed within the dicing lanes.

23. 1. An electronic device comprising: a first plurality of integrated device dies; a second plurality of integrated device dies, the first and second plurality of integrated device dies being stacked on top of one another; a first channel extending at least partially through the first and second plurality of integrated device dies, the first channel connecting to circuitry in the second plurality of integrated device dies and bypassing circuitry in the first plurality of integrated device dies; an electronic device having a second channel extending at least partially through the first and second pluralities of integrated device dies, the second channel connected to circuitry in the first pluralities of integrated device dies.

24. 24. The electronic device of claim 23, wherein at least two of the first plurality of integrated device dies are direct hybrid bonded to one another and at least two of the second plurality of integrated device dies are direct hybrid bonded to one another.

25. 24. The electronic device of claim 23, wherein the first and second plurality of integrated device dies are stacked on top of one another such that the integrated device dies of the first plurality of integrated device dies are interleaved with the integrated device dies of the second plurality of integrated device dies.

26. 24. The electronic device of claim 23, wherein the first plurality of integrated device dies are stacked together to form a first integrated device assembly, and the second plurality of integrated device dies are stacked together to form a second integrated device assembly, the second integrated device assembly being attached to the first integrated device assembly.

27. 27. The electronic device of claim 26, wherein the first integrated device assembly is direct hybrid bonded to the second integrated device assembly.

28. 1. An integrated device assembly comprising: a first integrated device die having a first circuit; a second integrated device die having second circuitry, the second integrated device die being attached to the first integrated device die; a carrier, the first integrated device die being attached to the carrier; a first channel coupled between the carrier and the first circuit, the first channel extending at least partially through the first integrated device die; a second channel coupled between the carrier and the second circuit, the second channel extending through the first integrated device die and at least partially through the second integrated device die, the second channel being electrically isolated from the first channel and the first circuit.

29. 30. The integrated device assembly of claim 28, wherein the integrated device assembly further includes a third integrated device die having a third circuit, the third integrated device die being attached to the first integrated device die, and the first channel being coupled between the carrier and the third circuit; and the integrated device assembly further includes a fourth integrated device die having a fourth circuit, the fourth integrated device die being attached to the first integrated device die, the second integrated device die, and the third integrated device die, and the second channel being coupled between the carrier and the fourth circuit.

30. 30. The integrated device assembly of claim 28, wherein the carrier comprises a logic device.

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