Reducing parasitic capacitance in coupling structures

Abstract

A bonding structure having a conductive feature and an insulating feature is disclosed. In one example, the bonding structure can include a first element including a first insulating layer and at least two first conductive features disposed in the first insulating layer. The bonding structure can also include a second element including a second insulating layer and at least two second conductive features disposed in the second insulating layer. The first element can be directly bonded to the second element with the at least two first conductive features aligned with the at least two second conductive features. The bonding structure can also include an insulating feature between the at least two second conductive features of the second insulating layer. The insulating feature can have a dielectric constant lower than the dielectric constant of the second insulating layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 257,035, filed October 18, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] The field relates to microelectronics, including directly bonded elements. [Background technology]

[0003] Microelectronic devices such as dies and wafers prior to die separation can be directly bonded to each other. Direct bonding can be between the dielectric materials of the bonded devices and can also include conductive materials at or near the bonding interface for direct hybrid bonding, such as DBI® connections available from Adeia, Inc., San Jose, Calif. The conductive materials at the bonding interface can be bond pads formed in or on a redistribution layer (RDL) covering the die or wafer, and / or passive electronic components such as capacitors, resistors, inductors, etc. that can participate in signal transformation within the microelectronic device. Summary of the Invention [Problem to be solved by the invention]

[0004] Conductive features in integrated devices are closely spaced and separated by dielectrics, which can result in parasitic capacitances that can cause undesirable power dissipation, undesirable coupling and crosstalk, especially in high frequency circuits. Thus, there is a continuing need for improved designs of passive features in microelectronic devices that minimize or eliminate undesirable signal integrity losses. [Means for solving the problem]

[0005] Specific implementations are now described, by way of example and not limitation, with reference to the following drawings in which: [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view of a first element 10 having a plurality of first conductive features 14 embedded in a first insulating layer 12 according to an embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view of a first element 10 having a first insulating feature 16 formed between first conductive features 14 of a first insulating layer 12. [Diagram 3] 2 is a schematic cross-sectional view of a second element 20 having a plurality of second conductive features 24 embedded in a second insulating layer 22. FIG. [Figure 4] 2 is a schematic cross-sectional view of the second element 20 showing a thin third insulating layer 26 grown on the top surface of the second element 20, covering the second conductive feature 24 and the surrounding second insulating layer 22. [Diagram 5] FIG. 2 is a schematic cross-sectional view of a second element 20 having a second insulating feature 28 formed between second conductive features 24 through the third insulating layer and into the second insulating layer 22. [Figure 6] FIG. 1 is a schematic cross-sectional view showing a first element 10 and a second element 20 bonded together to form an electronic device 1 by a direct bonding process. [Figure 7] FIG. 2 is a schematic cross-sectional view showing a bonded electronic device 2 having insulating features in the second element 20 but not in the first element 10. [Figure 8] FIG. 1 is a schematic cross-sectional view showing that a bonded electronic device 3 has insulating features in the first element 10 but not in the second element, such that there is no intervening insulating layer at the bonded interface. [Figure 9A] 1A-1C are schematic top views of four example devices 30, 40, 50 and 90 showing different forms of insulating features disposed around conductive features at or near the bond interface. [Figure 9B]1A-1C are schematic top views of four example devices 30, 40, 50 and 90 showing different forms of insulating features disposed around conductive features at or near the bond interface. [Figure 9C] 1A-1C are schematic top views of four example devices 30, 40, 50 and 90 showing different forms of insulating features disposed around conductive features at or near the bond interface. [Figure 9D] 1A-1C are schematic top views of four example devices 30, 40, 50 and 90 showing different forms of insulating features disposed around conductive features at or near the bond interface. [Figure 10] FIG. 6 is a schematic cross-sectional view of an element 60 showing insulating features of different depths separating or surrounding respective conductive features. [Figure 11] FIG. 1 is a schematic cross-sectional view of a combined electronic device 4 including passive electronic components embedded in back-end (BEOL) layers surrounded by insulating features. [Figure 12A] 1 is a schematic cross-sectional view of a semiconductor device 100 having one or more embedded three-dimensional (3D) capacitors separated therebetween by insulating features. [Figure 12B] FIG. 12B is a schematic cross-sectional view of the semiconductor device 100 of FIG. 12A with the top planarized to expose contact pads and conductive material prepared for direct bonding with another device. [Figure 13A] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13B] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13C] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13D] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13E]12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13F] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13G] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13H] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13I] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13J] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13K] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13L] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13M] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 13N] 12B-12C are schematic cross-sectional views illustrating an example manufacturing process for the 3D capacitor structure shown in FIG. 12A, according to various embodiments. [Figure 14A] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14B] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14C] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14D] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14E]12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14F] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14G] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14H] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14I] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14J] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14K] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14L] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14M] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. [Figure 14N] 12B is a schematic cross-sectional view showing another example manufacturing process of the 3D capacitor structure shown in FIG. 12A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Disclosed herein are microelectronic devices and methods for forming such devices that reduce inductive parasitic capacitance between conductive features at or near a bonding interface. In one example, the disclosed devices and methods use insulating features or spacers to reduce parasitic coupling between conductive features. Non-limiting advantages of such devices with low parasitic capacitance include improved power consumption with comparable performance, reduced antenna problems, reduced crosstalk, and lower leakage currents and improved power efficiency. Additionally, the use of insulating spacers to reduce parasitic capacitance allows the conductive features to be closely packed to achieve narrow pitch features.

[0008] For example, FIG. 1 is a schematic cross-sectional view of a semiconductor element including an integrated device die or wafer at a manufacturing process stage. FIG. 1 shows a first element 10 as part of a microelectronic device. As shown in FIG. 1, at least two first conductive features 14, such as contact pads, can be formed in the direct bonding layer of the first element 10. Although the conductive features 14 shown in FIG. 1 include contact pads (or bond pads), in some embodiments, the conductive contact features can also include TSVs (through substrate vias), portions of capacitors / inductors, etc. The first conductive features 14 can be embedded in a first insulating layer or dielectric material formed on the semiconductor layer 13, or in the BEOL layer 12. In some embodiments, an insulating layer 12 suitable for direct bonding can be formed in or on a redistribution layer (RDL) that can be formed on a reconstituted wafer before dicing the wafer or after dicing to fill the spaces between the dies. The first conductive features 14 can be present at or near the surface of the first element 10. In one example, the two or more first conductive features 14 may include or form part of multiple capacitor structures, such as metal plates formed within damascene cavities in the first insulating layer 12 of the first element 10.

[0009] FIG. 2 is a schematic cross-sectional view of the first element 10 of FIG. 1 (e.g., after the steps of FIG. 1) showing the formation of a first insulating feature or spacer 16 in the first element 10. The insulating feature 16 may be disposed between adjacent first conductive features 14 and may be disposed at or near the surface of the first element 10 to at least partially surround the first conductive feature 14, such as a capacitor structure. The process of forming the first insulating feature 16 may include etching a trench in the insulating layer 12 to form a void. The void may be filled or partially filled with a low dielectric constant material, such as a low-k dielectric material having a lower k value compared to the surrounding (structural) first insulating layer 12 in which the void is formed. For example, if the surrounding first insulating layer 12 includes silicon oxide, which has a dielectric constant of about 3.6, the material of the first insulating feature 16 may have a dielectric constant lower than that of silicon oxide, such as less than 3.5 or less than 3. As is known in the art, such low-k materials include porous silicon oxide, fluorine-doped silicon oxide, organosilicate glass, polymeric materials, and air or inert gas (gas-filled voids). The surrounding first insulating layer 12 is suitable for direct bonding and has sufficient structural integrity to withstand polishing, which may not be achieved when using a low-k dielectric material alone as a bonding layer. Examples of materials for the first insulating layer 12 include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride, ceramic, glass-ceramic, or diamond-like carbon. Forming a first insulating layer 16 between the first conductive features 14 of the first element 10 can reduce parasitic capacitance between the first conductive features 14 of the first element 10. The surface of the bonding layer can be prepared for direct bonding, including one or more of the planarization, activation, and termination processes described herein. In various embodiments, after the step of forming the first insulating layer 16, the tie layer can be prepared for direct bonding.

[0010] FIG. 3 shows a schematic cross-sectional view of a second element 20 at a certain stage of processing. The second element 20 at this stage has at least two second conductive features 24, such as TSVs, bond pads, capacitor plates, inductor lines, similar to the first element 10 shown in FIG. 1. The second conductive features 24 can be embedded in a second insulating or dielectric layer 22 suitable for direct bonding, which can be formed on another dielectric or semiconductor layer 23. The second conductive features 24 can be at or near the surface of the second element 20. In one example, the second conductive features can include or form part of multiple capacitor structures, such as metal plates formed in a damascene cavity in the second insulating layer 22 of the second element 20.

[0011] Proceeding to FIG. 4, a third thin insulating layer 26 (which may include or function as a capacitor dielectric layer) is formed, e.g., deposited, on top of the second element 20 shown in FIG. 3 to cover the second conductive feature 24 and the surrounding second insulating layer 22. The third insulating layer 26 may be formed of a high-k material, e.g., having a dielectric constant greater than that of silicon oxide. The dielectric constant may be greater than 4, such as for silicon nitride or silicon oxynitride, or greater than 10 or 20, such as for metal oxides such as zirconium oxide, hafnium oxide, barium titanate (BT), strontium bismuth tantalate (SBT), etc. The third insulating layer 26 may be relatively thin, e.g., in the range of about 20-100 nm, or may be up to a few microns thick. The third insulating layer 26 may be substantially thinner than the thickness of the first element 10 or the second element 20.

[0012] Similar to the first element 10 shown in FIG. 2, the second element 20 is shown in FIG. 5 having an insulating feature or insulating spacer 28 formed therein. As shown in FIG. 5, the second insulating feature 28 is formed through the third insulating layer 26 and into the second insulating layer 22. The second insulating feature 28 may be located between adjacent second conductive features 24 and may be located at or near the surface of the second element 20 to at least partially surround the second conductive feature 24, such as a capacitor structure. The step of forming the second insulating feature 28 may include etching a trench partially through the third insulating layer 26 and into the second insulating layer 22 to form a void. The void may then be filled or partially filled with a low-k material, i.e., a material having a lower dielectric constant than the dielectric constant of the surrounding structural second insulating layer 22, as described above. By forming second insulating features 28 between the second conductive features 24 of the second element 20, parasitic capacitance between the first conductive features 24 of the second element 20 can be reduced.

[0013] After the first element 10 and the second element 20 are formed as shown in Figures 1-5, the two elements can be bonded, for example, by a direct bonding process, to form a bonded structure or microelectronic device 1 as shown in the schematic cross-sectional view of Figure 6. For example, a surface of the first element 10 at or near the capacitor structure is bonded to a third insulating layer 26 on the second element 20. As shown in this example, at the bond interface 29, the first conductive feature 14 of the first element 10 can be aligned with the second conductive feature 24 of the second element 20. In other words, the first insulating layer 12 of the first element 10 is bonded to the third insulating layer 26 of the second element 20, while direct conductor-conductor bonds can be formed elsewhere (not shown). In the illustrated example, a capacitor can be formed at the bond interface, while direct conductor-conductor bonds can be formed elsewhere on the substrate (not shown). Therefore, as shown in FIG. 6, in both the first element 10 and the second element 20 of the coupling structure of the electronic device 1, insulating features 16 and 28 are disposed between the conductive features 14 and 24, respectively, to reduce parasitic capacitance.

[0014] One of the bonded elements may not utilize an insulating feature depending on which element of the bonded structure provides the larger parasitic capacitance. FIG. 7 is a schematic cross-sectional view of an example directly bonded electronic device 2 in which only the second element 20 has an insulating feature 28. In this view, the first element 10 remains as shown in FIG. 1 without the insulating feature. It is believed that analysis shows that in the device 2 of FIG. 7, in the absence of insulating features, the parasitic capacitance would be primarily on the second element 20 and to a lesser extent on the first element 10. Thus, even if the element 10 does not have insulating features, good results can be achieved by forming insulating features 28 on the element 20 to control the parasitic capacitance.

[0015] Another example embodiment shown in schematic cross-section in FIG. 8 illustrates that in the bonded electronic device 3, the first insulating feature 16 is disposed between the first conductive features 14 of the first element 10, while the second element 20 can be free of insulating features. This implementation can be used when analysis indicates that the absence of insulating features would result in parasitic capacitance occurring primarily at the first element 10. In some embodiments, as shown in FIG. 8, the electronic device 3 can be directly hybrid bonded even in the absence of a third insulating layer at the bonding interface 29, e.g., contact feature 14 is directly bonded to contact feature 24, and insulating layers 12, 22 are directly bonded to each other without adhesive. Thus, the embodiments disclosed herein can be utilized with capacitive electrical connections between opposing pads (e.g., FIGS. 6-7) or direct conductive connections between opposing pads (e.g., FIG. 8).

[0016] In some embodiments, the capacitor formed at the bond interface can include a planar capacitor. In some embodiments, the use of insulating spacers can reduce parasitic capacitance, allowing for a higher density of conductive features, e.g., the spacing between capacitors can be narrower than the width of the capacitors. In some embodiments, the bonding process can be configured for room temperature, atmospheric pressure direct bonding, such as the ZIBOND®, DBI®, and / or DBI® Ultra processes available from Adeia, Inc., San Jose, Calif.

[0017] 9A-9D are schematic plan views of four example devices with different configurations of insulating features at least partially surrounding the conductive features 14 or 24 at the bonding interface 29 of FIGS. 6-8. In these figures, example devices 30, 40 and 50 each have a plurality of generally horizontally arranged conductive features 34, 44 and 54, respectively. In FIG. 9D, the conductive features 9D are arranged in two rows. In other embodiments, the conductive features may have different arrangements. In each of the embodiments shown in FIGS. 9A-9D, one or more effectively annular insulating features 36, 46, 56 or 96 may at least partially surround the respective conductive features 34, 44, 54 and 94. In FIG. 9A, a rounded (e.g., circular) insulating feature 36 may be formed at least partially (e.g., completely) surrounding two of the three conductive features 34, such as the left and right features, but not around the central conductive feature 34. In some embodiments, a ring-shaped or annular insulating feature 36 may insulate the central conductive feature 34 despite being disposed only around the left and right conductive features 34. Additionally or alternatively, in some arrangements, the central conductive feature 34 may not generate a significant amount of parasitic capacitance.

[0018] 9B, the two left conductive features 44 may each be at least partially surrounded by a round (e.g., circular) insulating feature 46. In contrast, the right conductive feature 44 may be at least partially surrounded by multiple (e.g., two) round (e.g., circular) insulating features, including an inner insulating feature 46a and an outer insulating feature 46b. In some embodiments, multiple annular insulating features 46a and 46b are provided around the right conductive feature 44 because the rightmost conductive feature 44 may generate a larger parasitic capacitance than the left feature 44.

[0019] The insulating feature 56 in FIG. 9C can have different shapes, such as polygonal or rounded shapes. The insulating feature 56 at least partially surrounding the left conductive feature 54 can include a quadrilateral conductive feature 54, for example a rectangle or a square. The insulating feature 56 at least partially surrounding the central conductive feature 54 can be a rounded shape (e.g., circular) and can include multiple insulating feature segments including 56a and 56b spaced apart by one or more gaps 57a and 57b on the upper and lower sides. The insulating feature 56 at least partially surrounding the right conductive feature 54 can be polygonal, for example a quadrilateral feature, for example a rectangle or a square, including two narrow openings 58a and 58b at two opposite corners.

[0020] FIG. 9D shows a schematic plan view of a plurality (e.g., six) conductive features 94 surrounded by an insulating feature 96. Similar to the insulating features shown in FIGS. 9A-9C above, in FIG. 9D, each of the six conductive features 94 is individually surrounded or partially surrounded by its insulating feature 96, except for the conductive feature 94 at the top center position. As mentioned above, the different arrangements of these insulating features can be due to the nature of the parasitic capacitance caused by the surrounded conductive features 94. It should therefore be understood that the insulating features disclosed herein can have different shapes (when viewed from above) depending on the structure of the conductive features or other aspects of the parasitic capacitance or inductance to be isolated. Furthermore, the conductive features at or near the bonding interface 29 can be at least partially surrounded by two or more insulating spacers. Furthermore, the width of the insulating features can be any suitable width, such as, for example, in the range of 0.02 to 5 microns, preferably 0.05 to 2 microns.

[0021] Referring to FIG. 10, a schematic cross-sectional view of an element 60 shows that insulating features 63, 65, 67, and 69 separating or surrounding conductive features 66 can have different depths. In FIG. 10, a plurality of conductive features 66 are disposed on a base insulating layer 62 formed on another dielectric layer 68. The top surface of the insulating layer 62 is covered by a top insulating layer 64, which in some embodiments can function as a dielectric layer of a capacitor structure. The insulating features 63, 65, 67, and 69, which at least partially surround each conductive feature 66 at or near the bonding interface, have different depths. In one example, the depth of the insulating features can be deeper than 10% of the depth of the adjacent conductive features, and preferably deeper than 20% of the depth of the capacitor structure, for example. Meanwhile, the insulating feature 65 near the center conductive feature 66 and the outer insulating feature 69 adjacent to the right conductive feature 66 have a depth similar to that of the adjacent conductive features. In one example, two or more insulating features having different depths may be placed at least partially surrounding a given capacitor structure, such as the insulating feature surrounding conductive feature 66 on the right side of Figure 10. Multiple spaced apart insulating features may function better to interpose between adjacent conductive features and reduce parasitic capacitance.

[0022] FIG. 11 is a schematic cross-sectional view of an electronic device 4 including a semiconductor element 70, which may include a die, and another semiconductor element 80, which may include a wafer, an interposer, or another die, bonded at a bonding interface 79. When bonded, conductive features 76, 77, and 78, and passive electronic components 84, 86, and 88 may be disposed in insulating back-end (BEOL) layers 72 and 74 of element 70 and insulating back-end (BEOL) layers 82 and 83 of element 80. Passive electronic components 84, 86, and 88 may include capacitors, inductors, and the like. In FIG. 11, an insulating feature 85 may be embedded near passive electronic component 84, at least partially surrounding passive electronic component 84, across bonding interface 79 in both BEOL layers of semiconductor elements 70 and 80. Similarly, an insulating feature 87 may be embedded near passive electronic component 86 in the BEOL layers, at least partially surrounding passive electronic component 86. In other embodiments, passive electronic components 84, 86 may be formed to span across bonding interface 79 upon bonding. Insulating features 85 and 87 may be similarly formed. Another insulating feature 89 may be formed adjacent passive electronic component 88, at least partially surrounding passive electronic component 88 and positioned away from bonding interface 79, such as in a BEOL layer of bonding element 70.

[0023] In various embodiments, the embedded passive electronic components formed at or near the bonding interface can be planar capacitors or three-dimensional (3D) capacitors. FIG. 12A shows a schematic cross-sectional view of a semiconductor device 100. A first 3D capacitor 104 and a second 3D capacitor 106 are embedded in an insulating or dielectric material 102 suitable for direct bonding, with two insulating features 108 as described above disposed between the two 3D capacitors. The first 3D capacitor 104 includes a first electrode 112 and a second electrode 114, and the second 3D capacitor 106 includes a third electrode 116 and a fourth electrode 118. Meanwhile, the insulating material 102 can function as a capacitor dielectric between the electrodes 112 and 114 of the first 3D capacitor 104 and between the electrodes 116 and 118 of the second 3D capacitor 106. By placing an insulating feature 108 between two adjacent 3D capacitors, the parasitic capacitance between the two 3D capacitors and other adverse effects including crosstalk, antenna effects, digital noise, reduced power efficiency, etc. can be significantly reduced.

[0024] 12B shows that a portion of the top insulating material 102 can be removed by a planarization process, such as, for example, a chemical mechanical polishing or CMP process, to expose the top conductive material of the contact pad 115 and the second electrode 114 of the first electrode 112 of the first 3D capacitor 104, and the top conductive material of the contact pad 117 and the fourth electrode 118 of the third electrode of the second 3D capacitor 106. In this way, the semiconductor device 100 can be prepared for direct bonding with another device, which can include direct hybrid bonding of the contact pads and the conductive material at the substrate surface. Such contact pads can also be connected to internal connections that (indirectly) electrically connect the 3D capacitor with a conductive feature of another device by direct hybrid bonding. Also, the lower capacitor plate can be internally interconnected (not shown), whereas the top plate can be prepared for direct bonding with a conductive feature of another device by direct hybrid bonding.

[0025] 13A-13N and 14A-14N illustrate example processes and methods for fabricating the 3D capacitor and insulating features shown in FIGS. 12A and 12B. FIGS. 13A-13J illustrate an example process for forming a 3D capacitor in or on an element 120 that is to be directly bonded to another element. FIG. 13A is a schematic cross-sectional view of an element 120 at a manufacturing stage, according to various embodiments. FIG. 13A illustrates coating a first dielectric layer 126 over a conductive layer 124 bonded to a base non-conductive layer 122 of the element 120. FIG. 13B illustrates the first dielectric layer 126 being selectively patterned, for example by reactive ion etching (RLE) techniques, to form a first cavity 128 in the first dielectric layer 126.

[0026] The first cavity 128 in FIG. 13B can be filled with a conductive material to form a first electrode 132 electrically connected to the conductive layer 124 of the element 120 as shown in FIG. 13C, which is a schematic cross-sectional view of the element 120. The conductive feature material filling step can include electrochemical deposition using a suitable chemical bath, or atomic layer deposition (ALD), chemical vapor deposition (CVD), or other suitable deposition methods. For some materials, such as some electrode materials such as copper that tend to diffuse through the dielectric, the cavity filling step can include depositing a thin barrier layer (e.g., metal nitride) and / or adhesion layer over the walls of the dielectric layer. In some embodiments, a seed layer can be coated over the barrier layer, for example, before filling the cavity. In some embodiments, a high resistance barrier may not be desired, and instead a nitrogen-containing plasma can be applied to treat the surface of the cavity of the second dielectric layer before filling the cavity with the conductive material. The seed layer can be applied to the surface of the cavity before the cavity filling step.

[0027] Proceeding to FIG. 13D, a planarization process is applied to remove excess conductive portions, such as portions of the conductive features that extend beyond the insulating layer 126, so that the buried first electrode 132 is flush with the top surface of the insulating layer 126. The planarization process can include removing portions of any barrier layers between the conductor and the dielectric material, and portions of the first dielectric layer. The first electrode 132 and the conductive layer 124 can have the same material composition so as to be electrically connected. Next, in FIG. 13E, a second dielectric layer 134 can be coated over the buried first electrode 132 and the first dielectric layer 126. In some embodiments, the second dielectric layer 134 can have the same material as the first dielectric layer 126, while in other embodiments they can be different materials.

[0028] As can be seen with reference to FIG. 13F, selective patterning, for example by RIE, is applied to form a cavity 136 between the buried first electrodes 132 through the second dielectric layer 134 and the first dielectric layer 126 for forming a second electrode. As shown in FIG. 13G, which is a schematic cross-sectional view of the element 120, the cavity 136 can be filled with a conductive feature material to form a second top electrode 138. FIG. 13H shows that a portion of the conductive feature 138 of the second electrode is removed, for example by a planarization process, to form a buried second electrode and a contact area 139 to the second electrode in the element 120. In FIG. 13I, selective patterning is applied to a portion of the second dielectric layer 134 to form a contact pad cavity 142 to reach the first electrode 132. FIG. 13J shows that a planarized conductive contact pad 144 can be formed in the contact cavity 142. The contact pad 144 of the first electrode 132 and the exposed top contact surface 139 of the second electrode 138 may be prepared for direct bonding to another semiconductor device.

[0029] Alternatively, a lower cost method of 3D capacitor fabrication can be used. This low cost method can include the same steps as described with respect to Figures 13A-13E followed by the steps shown in Figures 13K-13M. In Figure 13K, selective patterning, for example by the RIE method described above, is applied to the second dielectric layer 134 and the first dielectric layer 126 between the embedded first electrode 132 to form a second cavity 137 in the dielectric layers 134 and 126 for the second electrode, and at the same time a via cavity 143 for a contact pad feature connected to the first electrode 132. In Figure 13L, a conductive material is deposited in the second cavity 137 and in the via cavity 143 to form the second electrode 138 and the contact pad of the first electrode 132, respectively. As shown in Figure 13M, excess portions of the conductive material 138 can be removed by a planarization process, such as a chemical mechanical polishing or CMP process, to form contact features 139 for the second electrode 138 and contact pad features 144 for the first electrode 132 in the element 120. In some embodiments, the element can include a passive component having a top contact or a bottom contact, or both, connected to the first and / or second electrodes of the 3D capacitor. As an example of such an embodiment, Figure 13N shows a schematic cross-sectional view of the element 120 showing a top contact pad 144 and a bottom contact 146 that connect to the first electrode 132 of the element 120. The second electrode 138 of the 3D capacitor in Figure 13N can have a top contact surface 139 and a bottom contact pad that is not visible in the figure.

[0030] In some embodiments, multiple types of dielectric materials can be applied during the formation of electrical or non-electrical components of interest. For example, a cavity formed in a first dielectric layer can be filled with a second dielectric material having a different composition, such as dielectric constant, hardness, material composition, or different dielectric or optical properties. As an example, the first dielectric layer can include silicon oxide and the second dielectric layer can have a dielectric constant k higher than the dielectric constant k of silicon oxide. Such second dielectric layers can include silicon nitride, titanium dioxide, tantalum oxide, barium titanate, zirconium oxide, hafnium oxide-containing dielectrics, and the like. Passive components can be formed in the patterned cavities of the second dielectric layer. Figures 14A-14N illustrate such a structure and an example method for forming a 3D capacitor in an element including multiple dielectric layers.

[0031] FIG. 14A is a schematic cross-sectional view of the device 210 at a certain manufacturing stage. In FIG. 14A, a first conductive layer 214 can be formed on the base dielectric layer 212. A RIE (reactive ion etching) method can be applied to form a cavity of a predetermined dimension in the base dielectric layer 212, and a desired conductive material can be deposited in the cavity of the base dielectric layer 212 to form the first conductive layer 214. A CMP (chemical mechanical polishing) method can be applied to planarize the coated conductive material to form a flat surface including a portion of the base dielectric layer 212 and the upper surface of the conductive layer 214. The first conductive layer 214 can form a portion of the first electrode. In FIG. 14B, a first dielectric material 216 is deposited on the upper portion of the base dielectric layer 212 and on the upper surface of the first conductive layer 214. After the first dielectric layer 216 is formed, it cooperates with the base dielectric layer 212 to embed the first conductive layer 214 therein. An additional portion of the first dielectric layer or material 216 may be coated over the top surface of the first conductive layer 214 to completely embed the first conductive layer. A CMP process may be applied to planarize the top surface of the first dielectric layer 216 to a predetermined thickness.

[0032] In FIG. 14C, the first dielectric layer 216 is selectively patterned, for example by RLE, to form a cavity 218 and expose the first conductive layer 214. In FIG. 14D, the cavity 218 is filled with a second dielectric material 222. The second dielectric layer 222 can have a different composition or different dielectric or optical properties, such as, for example, dielectric constant, hardness, material composition, from the first dielectric layer 216. The step of forming the second dielectric layer 222 embedded in the cavity 218 of the first dielectric layer 216 in FIG. 14C can include multiple intermediate coatings and polishing of the coated dielectric layers, depending on the depth and width of the cavity 218. For example, if the depth of the cavity 218 in the first dielectric layer 216 is 3 microns, the second dielectric layer 222 can be formed by depositing 1 micron of the second dielectric material at a time inside the cavity and on the top surface of the first dielectric layer 216. A CMP process or other method may be applied to remove the unwanted second dielectric portions over element 210. This process may be repeated a sufficient number of times to substantially fill or overfill cavity 218.

[0033] 14E, the second dielectric layer 222 is planarized such that the second dielectric layer 222 is embedded on the first conductive layer 214 and surrounded by the first dielectric layer 216. For example, the unwanted portion of the coated second dielectric layer 222 may be planarized to form a flat surface including a portion of the first dielectric layer 216 and a portion of the second dielectric layer 222. The planarization process may further include removing a portion of the top surface of the first dielectric material 216.

[0034] Next, as can be seen with reference to FIG. 14F, the second dielectric layer 222 is selectively patterned, for example by RIE, to form a cavity 224 for a first electrode member. The formed cavity 224 can expose the top surface of the buried first conductive layer 214. In FIG. 14G, the cavity 224 is filled with a conductive material to form a first electrode member 225 that connects to the buried first conductive layer 214 of the element 210. For example, the conductive material can fill or overfill the cavity 224 formed in the second dielectric layer 222 to form the first electrode member 225. After this step, the conductive first electrode member 225 connects to the first conductive layer 214 to form a first electrode of the 3D capacitor.

[0035] In FIG. 14H, the excess conductive material connected to the first electrode 225 in FIG. 14G can be removed, for example, by a planarization process. The planarization process can include removing a portion of any barrier layer between the conductor and the dielectric material, as well as a portion of the first and second dielectric layers. In FIG. 14I, a third dielectric layer 226 of suitable thickness can be coated over the planarized surface to embed the first electrode members 225. This third dielectric material 226 can have the same material and properties as the second dielectric layer 222. FIG. 14J illustrates selectively patterning the third dielectric layer 226 and the second dielectric layer 222 to form a second cavity 228 for depositing a second electrode member between the embedded first conductive electrode members 225, as well as a contact cavity 232 for the contact pad of the first conductive electrode 225, similar to the method and structure described in connection with FIG. 13F.

[0036] As can be seen with reference to FIG. 14K, a conductive material fills the second cavity 228 to form the second electrode member 234 and contact pads for the first electrode 225. For example, the cavity 228 of the dielectric layers 226 and 222 between the first electrode member 225 can be filled to form the conductive features of the second electrode. Then, the contact pads of the first electrode 225 can be formed in the cavity 232 that connect to the first electrode 225. FIG. 14L shows the step of removing excess conductive material by, for example, a CMP method to form a smooth surface of the second electrode 234, similar to the method described in connection with FIG. 13J. The smooth top surface of the second electrode 234 serves as a contact surface 235 for bonding to another semiconductor device together with the contact pads 236 formed after planarization. The CMP process can include removing the barrier layer and a portion of the top surfaces of the first and second dielectric layers. 14M shows that a contact 238 is formed on the bottom of element 210 that connects to conductive layer 214 that is part of the first electrode, including first electrode member 225. Element 210 has a top electrical contact 236 that connects to first electrode member 225, and a contact surface 235 that connects to second electrode 234, in addition to a bottom contact 238 that connects to conductive layer 214 of the first electrode. Element 210 can have a contact on the bottom (not shown) that connects to second electrode 234.

[0037] As can be seen with reference to FIG. 14N, the 3D capacitor 240 in the element 210 includes a first electrode 225 and a second electrode 234 embedded in the dielectric layers 212, 216, 222 and 226. The first electrode 225 and the second electrode 234 have conductive contacts 236 and 235, respectively, on their top surfaces, which are prepared for hybrid bonding with another element. An insulating feature 242 extends through the third dielectric layer 226 and the second dielectric layer 222 into the first dielectric layer 216 to reduce or minimize parasitic capacitance that may exist between the 3D capacitor 240 and other passive or conductive features of the element 210. The insulating feature or spacer 242 can be similar to those described above in FIGS. 2, 5, 9 and 12, among others. The insulating spacer 242 can reduce the spacing of electrical components to reduce or minimize crosstalk or parasitic capacitance. The structure of FIG. 14N can be prepared for direct hybrid bonding with another element having exposed conductive contacts.

[0038] Although Figures 14A-14N illustrate a method for forming a parallel plate 3D passive element including an insulating spacer, it should be understood that a similar method can be applied to the fabrication of 2D passive elements such as rod-shaped 3D capacitors or other non-parallel plate 3D capacitors, or 2D capacitors including insulating spacers. The 2D capacitors can be oriented parallel or perpendicular to the bonding plane of the element. In some example embodiments, the 2D capacitors can have a capacitor dielectric between the electrodes that has a different composition or different dielectric or optical properties than that of the surrounding material. For example, the capacitor dielectric of the 2D capacitor can have a higher dielectric constant than the dielectric constant of the surrounding material.

[0039] Electronic Devices Die can refer to any suitable type of integrated device die. For example, an integrated device die can include electronic components such as integrated circuits (such as a processor die, a controller die, or a memory die), a microelectromechanical systems (MEMS) die, an optical device, or any other suitable type of device die. In some embodiments, the electronic components can include passive devices such as capacitors, inductors, or other surface mount devices. In various embodiments, circuitry such as active components such as transistors can be patterned at or near the active surface of the die. The active surface can be on the side of the die opposite the back surface of the die. The back surface can include or not include any active circuitry or passive devices.

[0040] The integrated device die may include a bonding surface and a back surface opposite the bonding surface. The bonding surface may have a plurality of conductive bond pads including conductive bond pads and a non-conductive material adjacent to the conductive bond pads. In some embodiments, the conductive bond pads of the integrated device die may be directly bonded to corresponding conductive pads of the substrate or wafer without the use of an intervening adhesive, and the non-conductive material of the integrated device die may be directly bonded to a portion of the corresponding non-conductive material of the substrate or wafer without the use of an intervening adhesive. Direct bonding without the use of adhesive is described in U.S. Pat. Nos. 7,126,212, 8,153,505, 7,622,324, 7,602,070, 8,163,373, 8,389,378, 7,485,968, 8,735,219, 9,385,024, 9,391,143, 9,485,968 ... Nos. 9,431,368, 9,953,941, 9,716,033, 9,852,988, 10,032,068, 10,204,893, 10,434,749, and 10,446,532, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0041] Examples of direct bonding methods and direct bonding structures Various embodiments disclosed herein relate to direct bonding structures that allow two elements to be directly bonded together without the use of an intervening adhesive. Two or more electronic elements, which may be semiconductor elements (such as integrated device dies, wafers, etc.), may be stacked or bonded together to form a bonded structure. The conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements may be stacked in the bonded structure. The contact pads may include metal pads formed within the non-conductive bonded regions and may be connected to an underlying metallization such as a redistribution layer (RDL).

[0042] In some embodiments, the elements are directly bonded to each other without the use of adhesive. In various embodiments, the non-conductive or dielectric material of the first element can be directly bonded to the corresponding non-conductive or dielectric field area of ​​the second element without the use of adhesive. The non-conductive material can be referred to as the non-conductive bonding area or bonding layer of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-dielectric bonding techniques. For example, the dielectric-dielectric bond can be formed without the use of adhesive using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes. Suitable dielectric materials for direct bonding can include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or carbon such as silicon carbide, silicon oxynitride, silicon carbonitride, or diamond-like carbon. In some embodiments, the dielectric material does not include a polymeric material such as an epoxy, resin, or molding compound.

[0043] In various embodiments, a hybrid direct bond can be formed without the use of an intervening adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to plasma and / or etchants to activate the surfaces. In some embodiments, the surfaces can be terminated with chemical species after or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces, and the termination process can provide additional chemical species at the bonding surfaces that increase the bond energy during direct bonding. In some embodiments, activation and termination are performed in the same process, such as activating and terminating the surfaces with plasma or wet etchants. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the terminating species can include nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there can be one or more fluorine peaks near the layers and / or bonding interface. Thus, in a direct bonding structure, the bond interface between the two dielectric materials can include a very smooth interface with a high nitrogen content and / or fluorine peak at the bond interface. Further examples of activation and / or termination processes are described in U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0044] In various embodiments, the conductive contact pads of a first component can also be directly bonded to corresponding conductive contact pads of a second component. For example, hybrid direct bonding techniques can be used to provide conductor-conductor direct bonds along a bonding interface that includes a covalently directly bonded dielectric-dielectric surface prepared as described above. In various embodiments, conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds can be formed using direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0045] For example, the dielectric bonding surfaces can be prepared as described above and bonded directly to each other without the use of an intervening adhesive. The conductive contact pads (which can be surrounded by a non-conductive dielectric field region) can also be bonded directly to each other without the use of an intervening adhesive. In some embodiments, each contact pad can be recessed downward from the outer surface (e.g., top surface) of the dielectric field region or the non-conductive bonding region by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, within a range of 2 nm to 20 nm, or within a range of 4 nm to 10 nm. In some embodiments, the non-conductive bonding regions can be bonded directly to each other without the use of an adhesive at room temperature in a bonding tool described herein, and the bonded structure can then be annealed. The annealing can be performed in a separate apparatus. Upon annealing, the contact pads can expand and contact each other to form a direct metal-metal bond. The use of hybrid bonding technologies such as Direct Bond Interconnect or DBI®, commercially available from Adeia, San Jose, Calif., can advantageously allow for a high density of connected pads across the direct bond interface (e.g., small or fine pitch for regular arrays). In some embodiments, the pitch of the bond pads, or the pitch of the conductive trace embedded in the bonding surface of one of the bonded elements, can be less than 40 microns, or less than 10 microns, or even less than 2 microns. In some applications, it is desirable for the ratio of the bond pad pitch to one of the bond pad dimensions to be less than 5 or less than 3, and in some cases less than 2. In other applications, the width of the conductive trace embedded in the bonding surface of one of the bonded elements can range from 0.3 to 3 microns. In various embodiments, the contact pads and / or traces can include copper, although other metals may be suitable.

[0046] Thus, in a direct bonding process, the first element can be directly bonded to the second element without the use of an intervening adhesive. In some configurations, the first element can include a singulated element, such as a singulated integrated device die. In other configurations, the first element can include a carrier or substrate (e.g., a wafer) that includes multiple (e.g., tens, hundreds, or more) element regions that, upon singulation, form multiple integrated device dies. In the embodiments described herein, the first element, whether a die or a substrate, can be considered a host substrate and mounted on a support within a bonding tool to receive the second element from a pick-and-place or robotic end effector. The second element in the illustrated embodiment includes a die. In other configurations, the second element can include a carrier or substrate (e.g., a wafer).

[0047] As described herein, the first and second elements can be directly bonded to each other without the use of adhesive, which is distinct from a deposition process. In one application, the width of the first element in the bonded structure can be similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure can be different from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% greater than the width or area of ​​the smaller element. Thus, the first and second elements can include non-deposited elements. Furthermore, the direct bonded structure, unlike a deposition layer, can include defect regions along the bond interface where nanovoids exist. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonded surface. As discussed above, the bond interface can include concentrations of materials from the activation and / or last chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, nitrogen peaks can be formed at the bond interface. In embodiments utilizing oxygen plasma for activation, oxygen peaks can be formed at the bond interface. In some embodiments, the bond interface can include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond can include a covalent bond that is stronger than van der Waals bonds. The bond layer can also include a highly smoothly planarized polished surface. For example, the bond layer can have a surface roughness of less than 2 nm root mean square (RMS) per micron or less than 1 nm RMS per micron.

[0048] In various embodiments, metal-metal bonds between contact pads of a direct hybrid bonding structure can be bonded such that conductive feature grains, such as copper grains on a conductive feature, grow into one another across the bond interface. In some embodiments, the copper can have grains oriented along 111 crystal planes to enhance copper diffusion across the bond interface. The bond interface can extend substantially completely to at least a portion of the bonded contact pads such that there are substantially no gaps between non-conductive bonded regions at or near the bonded contact pads. In some embodiments, a barrier layer (which can include, for example, copper) can be provided beneath the contact pads. However, in other embodiments, there can be no barrier layer beneath the contact pads, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated herein by reference in its entirety for all purposes.

[0049] Unless the context clearly requires otherwise, words such as "comprise, comprising, include, including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to," rather than an exclusive or exhaustive sense. The word "coupled," as generally used herein, means two or more elements that may be connected directly or through one or more intermediate elements. Similarly, the word "connected," as generally used herein, means two or more elements that may be connected directly or through one or more intermediate elements. Additionally, when the application uses words such as "herein," "above," "below," and words of similar import, these words are intended to refer to the application as a whole and not to any particular portion of the application. Furthermore, when a first element is described herein as being "on" or "over" a second element, the first element can be directly on or over the second element such that the first and second elements are in direct contact with each other, or indirectly on or over the second element such that there are one or more intervening elements between the first and second elements. Words using the singular or plural in the above detailed description can also include the plural or singular, respectively, where the context allows. The word "or" when referring to a list of two or more items covers all interpretations of the word, such as any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0050] Additionally, as used herein, inter alia, conditional terms such as "can, could, might, may" and "eg, for example, such as" are generally intended to convey that some embodiments include certain features, elements and / or conditions and other embodiments do not include them, unless expressly stated otherwise or understood otherwise within the context of use. Thus, such conditional terms are generally not intended to imply that features, elements and / or conditions are in any way required for one or more embodiments.

[0051] Although several embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, method and system described herein may be embodied in various other forms, and various omissions, substitutions and modifications of the forms of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, although blocks are shown in a given arrangement, another embodiment may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. A bonding structure comprising: a first element including a first insulating layer and at least two first conductive features disposed within the first insulating layer; a second element including a second insulating layer and at least two second conductive features disposed within the second insulating layer; wherein the first element is directly bonded to the second element with the at least two first conductive features aligned with the at least two second conductive features, and the bonding structure comprises: further comprising an insulating feature present in the second insulating layer between the at least two second conductive features and having a dielectric constant lower than that of the second insulating layer; the insulating feature extends to a direct bonding interface between the first element and the second element; bond structure.

2. the first insulating layer and the second insulating layer are directly bonded without an intervening adhesive, and the at least two first conductive features and the at least two second conductive features are directly bonded without an intervening adhesive. The bonded structure of claim 1 .

3. the second element further includes a third insulating layer on the second insulating layer, and the first element is directly bonded to the third insulating layer. The bonded structure of claim 1 .

4. the insulating feature extends through the third insulating layer to the direct bond interface; The bonded structure according to claim 3 .

5. one of the first conductive features, one of the second conductive features, and the third insulating layer cooperate to form a capacitor; The bonded structure according to claim 3 .

6. the insulating feature between the at least two second conductive features reduces parasitic capacitance between the at least two second conductive features. The bonded structure of claim 1 .

7. a spacing between the at least two second conductive features that is smaller than a width of any one of the at least two second conductive features; The bonded structure of claim 1 .

8. a spacing between the at least two first conductive features that is smaller than a width of any one of the at least two first conductive features; The bonded structure of claim 1 .

9. the insulating feature is filled with a low dielectric constant material; The bonded structure of claim 1 .

10. the dielectric constant of the insulating feature is less than about 3.5; The bonded structure of claim 1 .

11. the insulating feature comprises a gas-filled void; The bonded structure of claim 1 .

12. The at least two second conductive features are disposed at or near the direct bond interface between the first and second elements. The bonded structure of claim 1 .

13. a width of the insulating feature parallel to the direct bonding interface that is smaller than a width of any one of the at least two second conductive features parallel to the direct bonding interface; The bonded structure of claim 12.

14. the width of the insulating feature parallel to the direct bonding interface is between about 1 μm and about 2 μm; The bonded structure of claim 12.

15. a depth of the insulating feature perpendicular to the direct bond interface that is at least 10% of a depth of any one of the at least two second conductive features perpendicular to the direct bond interface; The bonded structure of claim 12.

16. a depth of the insulating feature perpendicular to the direct bonding interface is less than a depth of the second insulating layer perpendicular to the direct bonding interface; The bonded structure of claim 12.

17. the insulating feature surrounds one of the at least two second conductive features in a plane substantially parallel to the direct bond interface; The bonded structure of claim 12.

18. further comprising an additional insulating feature present in the first insulating layer between the at least two first conductive features and having a dielectric constant lower than that of the first insulating layer, the additional insulating feature extending to the direct bond interface. The bonded structure of claim 1 .

19. the additional insulating feature between the at least two first conductive features reduces parasitic capacitance between the at least two first conductive features. The bonded structure of claim 18.

20. the dielectric constant of the further insulating feature is less than about 3.5; The bonded structure of claim 18.

21. the further insulating feature is partially filled with a low dielectric constant material. The bonded structure of claim 18.

22. the further insulating feature comprises a gas-filled void; The bonded structure of claim 18.

23. The method of claim 22, wherein the at least two first conductive features are disposed at or near the direct bond interface between the first and second elements. The bonded structure of claim 18.

24. a width of the further insulating feature parallel to the direct bonding interface that is smaller than a width of any one of the at least two first conductive features parallel to the direct bonding interface; 24. The bonded structure of claim 23.

25. the width of the further insulating feature parallel to the direct bonding interface is between about 1 μm and about 2 μm; 24. The bonded structure of claim 23.

26. a depth of the further insulating feature perpendicular to the direct bond interface that is at least 10% of a depth of any one of the at least two first conductive features perpendicular to the direct bond interface; 24. The bonded structure of claim 23.

27. a depth of the further insulating feature perpendicular to the direct bonding interface is less than a depth of the first insulating layer perpendicular to the direct bonding interface; 24. The bonded structure of claim 23.

28. the further insulating feature surrounds any one of the at least two first conductive features in a plane substantially parallel to the direct bond interface; 24. The bonded structure of claim 23.

29. 1. A method for forming a bonded structure, comprising: Providing a first element including a first insulating layer and at least two first conductive features disposed within the first insulating layer; providing a second element including a second insulating layer and at least two second conductive features disposed within the second insulating layer; forming an insulating feature in the second insulating layer between the at least two second conductive features, the insulating feature having a dielectric constant lower than a dielectric constant of the second insulating layer; directly bonding the first element to the second element along a direct bonding interface with the at least two first conductive features aligned with the at least two second conductive features; wherein the insulating feature extends to the direct bond interface. method.

30. directly bonding the first element to the second element includes directly bonding the first insulating layer to the second insulating layer and directly bonding the at least two first conductive features to the at least two second conductive features.

30. The method of claim 29.

31. forming a third insulating layer on the second insulating layer, the first element being directly bonded to the third insulating layer; 30. The method of claim 29.

32. the insulating feature extends through the third insulating layer to the direct bond interface; 32. The method of claim 31 .

33. a spacing between the at least two second conductive features that is smaller than a width of any one of the at least two second conductive features; 30. The method of claim 29.

34. a spacing between the at least two first conductive features that is smaller than a width of any one of the at least two first conductive features; 30. The method of claim 29.

35. further comprising filling the insulating feature with a low dielectric constant material.

30. The method of claim 29.

36. further comprising partially filling the insulating feature with a low dielectric constant material.

30. The method of claim 29.

37. the insulating feature comprises a gas-filled void; 30. The method of claim 29.

38. the at least two first conductive features are disposed at or near the direct bond interface between the first and second elements.

30. The method of claim 29.

39. The at least two second conductive features are disposed at or near the direct bond interface between the first and second elements.

30. The method of claim 29.

40. a width of the insulating feature parallel to the direct bonding interface that is smaller than a width of any one of the at least two second conductive features parallel to the direct bonding interface; 40. The method of claim 39.

41. the width of the insulating feature parallel to the direct bonding interface is between about 1 μm and about 2 μm; 40. The method of claim 39.

42. a depth of the insulating feature perpendicular to the direct bond interface that is at least 10% of a depth of any one of the at least two second conductive features perpendicular to the direct bond interface; 40. The method of claim 39.

43. a depth of the insulating feature perpendicular to the direct bonding interface is less than a depth of the second insulating layer perpendicular to the direct bonding interface; 40. The method of claim 39.

44. the insulating feature surrounds any one of the at least two second conductive features in a plane substantially parallel to the direct bond interface; 40. The method of claim 39.

45. forming an additional insulating feature having a dielectric constant lower than that of the first insulating layer present between the at least two first conductive features in the first insulating layer, the additional insulating feature extending to the direct bond interface; 30. The method of claim 29.

46. further comprising filling the further insulating feature with a low dielectric constant material.

46. ​​The method of claim 45.

47. further comprising partially filling the further insulating feature with a low dielectric constant material.

46. ​​The method of claim 45.

48. 46. ​​The method of claim 45, wherein the further insulating feature comprises a gas-filled void.

49. the further insulating feature is located at or near the direct bond interface between the first and second elements.

46. ​​The method of claim 45.

50. a width of the further insulating feature parallel to the direct bonding interface that is smaller than a width of any one of the at least two first conductive features parallel to the direct bonding interface; 50. The method of claim 49.

51. the width of the further insulating feature parallel to the direct bonding interface is between about 1 μm and about 2 μm; 50. The method of claim 49.

52. a depth of the further insulating feature perpendicular to the direct bond interface that is at least 10% of a depth of any one of the at least two first conductive features perpendicular to the direct bond interface; 50. The method of claim 49.

53. a depth of the further insulating feature perpendicular to the direct bonding interface is less than a depth of the first insulating layer perpendicular to the direct bonding interface; 50. The method of claim 49.

54. the further insulating feature surrounds one of the at least two first conductive features in a plane substantially parallel to the direct bond interface; 50. The method of claim 49.

55. 1. An electronic device configured for direct bonding, comprising: an insulating layer of the first element; a first conductive feature and a second conductive feature in the insulating layer; a first insulating feature in the insulating layer separating the first and second conductive features and having a dielectric constant lower than a dielectric constant of the insulating layer; wherein the first and second conductive features and the first insulating feature are disposed at a direct bond interface configured for direct hybrid bonding. Electronic devices.

56. the direct bond interface comprises a surface that is planarized to a root mean square roughness of less than 2 nm per micron; 56. The electronic device of claim 55.

57. The direct bond interface includes a fluorine peak.

56. The electronic device of claim 55.

58. the direct bond interface comprises a nitrogen peak; 56. The electronic device of claim 55.

59. the insulating feature is filled with a low dielectric constant material; 56. The electronic device of claim 55.

60. the insulating feature is partially filled with a low dielectric constant material; 56. The electronic device of claim 55.

61. the insulating feature comprises a gas-filled void; 56. The electronic device of claim 55.

62. the first insulating feature surrounds one of the first and second conductive features in a plane substantially parallel to the direct bond interface; 56. The electronic device of claim 55.

63. one or both of the first and second conductive features are part of a passive electronic component; 56. The electronic device of claim 55.

64. the passive electronic component includes a capacitor; 64. The electronic device of claim 63.

65. the passive electronic component includes an inductor; 64. The electronic device of claim 63.

66. a passive electronic component embedded in the insulating layer; a second insulating feature embedded in the insulating layer adjacent the passive electronic component and having a dielectric constant lower than that of the insulating layer; 56. The electronic device of claim 55, further comprising:

67. one of the at least two first conductive features or the at least two second conductive features is an electrode of a three-dimensional capacitor; The bonded structure of claim 1 .

68. one of the at least two first conductive features or the at least two second conductive features is an electrode of a three-dimensional capacitor; 30. The method of claim 29.

69. the passive electronic component includes a three-dimensional capacitor; 64. The electronic device of claim 63.

70. a capacitor dielectric between electrodes of the three-dimensional capacitor is formed of a material different from the material of the insulating layer of the first element; 70. The electronic device of claim 69.

71. a capacitor dielectric between electrodes of the three-dimensional capacitor having a dielectric constant higher than the dielectric constant of the insulating layer of the first element; 70. The electronic device of claim 69.

72. the passive electronic component embedded in the insulating layer includes a three-dimensional capacitor; 67. The electronic device of claim 66.

73. a capacitor dielectric between the electrodes of the capacitor is formed of a material different from the material of the insulating layer of the first element; 65. The electronic device of claim 64.

74. a capacitor dielectric between the electrodes of the capacitor having a dielectric constant higher than the dielectric constant of the insulating layer of the first element; 65. The electronic device of claim 64.

75. the third insulating layer has a dielectric constant higher than the dielectric constants of the first and second insulating layers; The bonded structure according to claim 3 .

76. the third insulating layer has a dielectric constant higher than the dielectric constants of the first and second insulating layers; 32. The method of claim 31 .

77. An electronic device configured for direct bonding, comprising: an insulating layer; at least two conductive features disposed within the insulating layer; an insulating feature disposed in the insulating layer, the insulating feature being disposed between the at least two conductive features, the insulating feature being disposed on both sides of one of the at least two conductive features in a cross-sectional view, the insulating feature having a dielectric constant lower than a dielectric constant of the insulating layer; the at least two conductive features are disposed at or near a bond interface configured for direct hybrid bonding; Electronic devices.

78. The electronic device described in Claim 77, wherein the insulating feature is arranged to at least partially surround one of the at least two conductive features.

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