Fluid Cooling of the Die Stack

Abstract

The disclosed technology relates to a microelectronic device capable of efficiently dissipating heat. In some aspects, the microelectronic device includes a first semiconductor element and a second semiconductor element disposed on the first semiconductor element. The microelectronic device may further include a fluid cooling unit disposed on the first semiconductor element. In some embodiments, the fluid cooling unit may include a cavity structure that contains a fluid. In some embodiments, the fluid cooling unit may include a thermal path for transferring and dissipating heat from the first semiconductor element.

Description

[Technical field]

[0001] The technical field relates to dissipating heat in microelectronic devices, particularly in microelectronic devices made with direct bonded components.

[0002] [Citation to Related Applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 264,261, filed November 18, 2021 (titled FLUID COOLING FOR DIE STACKS), which is incorporated by reference in its entirety and is incorporated herein by reference in its entirety. [Background technology]

[0003] The miniaturization and high density integration of electronic components increases the heat flux density in microelectronics. If the heat generated during the operation of microelectronics is not dissipated, the microelectronics may stop working or burn out. In particular, heat dissipation is a serious problem in high power devices. Summary of the Invention

[0004] According to one aspect of the invention, there is provided a microelectronic device comprising: A first semiconductor element; at least one second semiconductor element disposed on the first semiconductor element; A microelectronic device is provided having a fluid cooling unit provided on a first semiconductor element, the fluid cooling unit having a cavity structure for accommodating a fluid, and the fluid cooling unit having a thermal path for transferring and dissipating heat from the first semiconductor element.

[0005] According to another aspect of the invention, there is provided a method of fabricating a microelectronic device, comprising the steps of: providing a first semiconductor device; bonding the second semiconductor device and the fluid cooling unit to the first semiconductor device such that the second semiconductor device and the fluid cooling unit are disposed on the first semiconductor device; The method includes providing a fluid cooling unit having a cavity structure for containing a fluid, the fluid cooling unit having a thermal path for transferring and dissipating heat from the first semiconductor device.

[0006] According to yet another aspect of the present invention, there is provided a microelectronic device comprising: A first semiconductor element; A microelectronic device is provided, comprising: a fluid cooling unit directly bonded to a first semiconductor element without any intervening adhesive; and the fluid cooling unit has a cavity structure for containing a fluid.

[0007] Specific embodiments will now be described with reference to the following drawings, which are provided by way of illustration and not by way of limitation. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of an exemplary microelectronic system according to some embodiments of the disclosed technology; [Diagram 2] FIG. 2 is a schematic cross-sectional view of another exemplary microelectronic system according to some embodiments of the disclosed technology. [Figure 3A] FIG. 1 is a schematic cross-sectional view of yet another exemplary microelectronic system according to some embodiments of the disclosed technology. [Figure 3B] 3B is a schematic cross-sectional view of an example fluid cooling unit that can be used in the example microelectronic system of FIG. 3A. [Figure 3C] 3B is a schematic cross-sectional view of an example fluid cooling unit that can be used in the example microelectronic system of FIG. 3A. [Figure 3D] 3B is a schematic cross-sectional view of an example fluid cooling unit that can be used in the example microelectronic system of FIG. 3A. [Figure 4] FIG. 2 is a schematic cross-sectional view of another exemplary microelectronic system according to some embodiments of the disclosed technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Microelectronic elements (e.g., dies / chips) can be stacked and bonded together to form a device. Dissipating heat in a device with chip stacking is difficult, especially as the chips become thinner. The use of chip attachment techniques, such as adhesive bonding, can result in less efficient heat dissipation in the device because the adhesive can reduce heat transfer or insulate. In addition, it is difficult to achieve a particularly low temperature in a desired portion of the device. For example, when packaging a stack of dies, heat dissipation is typically aided by a heat sink at the top of the stack, but drawing heat away from the lower die is a challenge. Heat dissipation can be a serious problem, especially for high-power chips. Thus, improved techniques for dissipating heat in microelectronic devices continue to be needed.

[0010] Methods and structures are provided for redirecting the thermal path from a lower die in a stack to an upper heat dissipation structure (e.g., heat sink / heat pipe). In one aspect, a microelectronic device can have a fluid cooling unit that can help redirect the heat flow through the device as well as remove heat from the device, thereby reducing the heat flow rate through, for example, one chip in the device. For example, the fluid cooling unit can include a thermal path that transfers and dissipates heat from a lower / bottom semiconductor element. Such a fluid cooling unit occupies a small footprint in the device.

[0011] In some embodiments, the lower wall of the fluid-cooling unit is directly bonded to another element in the device (e.g., the lower die), thus avoiding the use of adhesives that may reduce heat transfer. The coefficient of thermal expansion (CTE) of the lower wall of the fluid-cooling unit may be selected to substantially match the CTE of the element to avoid breakage or cracking of the bonded structure when temperatures rise during operation of the device. For example, the element to which the fluid-cooling unit can be directly bonded (e.g., the lower die) may be made of silicon, and the lower wall material may have a CTE approximately the same as that of silicon.

[0012] In some embodiments, the fluid cooling unit may include channels containing a fluid coolant that can be transported / circulated using a pump. In some embodiments, the fluid cooling unit may include heat pipes containing a working fluid that can transfer heat through a phase change cycle. Compared to the neighboring chips, the fluid cooling unit may be more efficient at transferring heat from the lower die, thus redirecting the heat flow in the device and reducing the heat flow rate through the neighboring chips.

[0013] FIG. 1 is a schematic cross-sectional view of an example microelectronic system 100 including stacked semiconductor elements (e.g., dies / chips) and a fluid cooling unit 137 connected to a heat sink 131 (e.g., a metal heat sink or a heat pipe with a fluid coolant) located at the top of the stack. For example, the fluid cooling unit 137 may include a thermal path to transfer and dissipate heat from the lower / bottom semiconductor element 1000. The fluid cooling unit 137 may be formed of a semiconductor (e.g., silicon), a metal, a plastic, or any combination thereof, and may include a cavity structure (e.g., a liquid channel 1391 or a heat pipe 1392) and may contain a fluid configured to transfer heat by circulation or phase change cycles. For example, the fluid may include a gas or a liquid (e.g., water or a dielectric liquid). Heat generated by the semiconductor devices 1000, 101 and / or 102 during operation may be transferred to the heat sink 131 to be dissipated from the system 100. For example, a fluid may be pumped into the cavity, e.g., liquid channel 1391 or heat pipe 1392, via an inlet conduit, and the fluid may exit the cavity, e.g., liquid channel 1391 or heat pipe 1392, via an outlet conduit. From the outlet conduit, the fluid may be conveyed to an external heat exchanger (not shown), where the fluid may be cooled, and then the fluid may be returned to the cavity, e.g., liquid channel 1391 or heat pipe 1392, via the inlet conduit. The fluid cooling unit 137 and one or more chips (e.g., the "first die" 101 and the "second die" 102) may be attached to a base element 1000, which may be a die, a wafer, or the like. In some embodiments, the "first die" or the "second die" may be disposed within the fluid cooling unit 137. In other embodiments, the "first die" 101 or the "second die" 102 may be disposed outside the fluid cooling unit 137. The fluid cooling unit 137 may be located adjacent to at least one chip (e.g., at least the "first die 101"), thus reducing the heat flow through the at least one chip.

[0014] In some embodiments, the bottom wall 137-1 of the fluid cooling unit 137 may have a CTE that is very close to the CTE of the base element 1000. For example, the base element 1000 may include a semiconductor material, such as silicon (Si), and the bottom wall 137-1 of the fluid cooling unit 137 may have a CTE that is close to or matches the CTE of the semiconductor material (e.g., Si). In one example, the bottom wall 137-1 of the fluid cooling unit 137 may have a CTE that is lower than the CTE of copper or less than 10 μm / m° C. In some embodiments, the bottom wall 137-1 of the fluid cooling unit 137 may be made of an electrical non-conductor or semiconductor, such as a non-metal. In some embodiments, the bottom wall 137-1 of the fluid cooling unit 137 may be made of a semiconductor material, such as silicon (e.g., Si).

[0015] In some embodiments, the bottom wall 137-1 of the fluid cooling unit 137 may be attached to the base element 1000 by direct bonding without an intervening adhesive, such as by a non-conductive direct bonding technique and / or a hybrid direct bonding technique. For example, the bottom wall 137-1 may be attached using ZIBOND® and / or DBI® processes configured for room temperature atmospheric pressure direct bonding or DBI® Ultra process configured for low temperature hybrid bonding, which are commercially available from Adeia, Inc., San Jose, Calif. In some embodiments, the bottom wall 137-1 of the fluid cooling unit 137 may be attached to the bottom chip 1000 by solder bonding or adhesive bonding. In some embodiments, the bottom wall 137-1 of the fluid cooling unit may be attached to the bottom chip via a thermally conductive material (TIM).

[0016] In some embodiments, the stacked semiconductor devices may be directly bonded to one another without an intervening adhesive. For example, the “first die” 101 and / or the “second die” 102 may be directly bonded to the base device 1000. In some embodiments, the super heat sink may be directly bonded to the semiconductor device (e.g., the “first die” 101 and / or the “second die” 102 and / or the fluid cooling unit 137) or may be attached to the semiconductor device and / or the fluid cooling unit via a thermally conductive material (TIM). For example, direct bonding processes include the ZIBOND® and DBI® processes configured for room temperature atmospheric pressure direct bonding or the DBI® Ultra process configured for low temperature hybrid bonding, which are commercially available from Adair, Inc., San Jose, Calif. The direct bonds may be located between the dielectrics of the bonded devices and may further include a conductive material at or near the bond interface for direct hybrid bonding. The conductive material at the bond interface may be bond pads and / or passive electronic components formed in or on a redistribution layer (RDL) deposited on the die.

[0017] 2 is a cross-sectional view of an example microelectronic device similar to the microelectronic system of FIG. 1, with like reference numerals used to refer to like features. However, the fluid cooling unit is not coupled to a heat sink. Instead, the fluid cooling unit is directly coupled to a fluid system 240 (which may include a pump and / or additional fluid channels) configured to transport / circulate a fluid coolant within the fluid cooling unit, thus transferring / dissipating heat from the microelectronic system. The top heat sink 131 may be attached to the semiconductor device via a thermally conductive material (TIM) 249.

[0018] For example, the microelectronic device may include a first semiconductor element, a fluid cooling unit directly bonded to the first semiconductor element without an adhesive, the fluid cooling unit including a cavity structure that contains a liquid. In one embodiment, the microelectronic device further includes at least one second semiconductor element disposed on the first semiconductor element. In one embodiment, the fluid cooling unit reduces the heat flow through the at least one second semiconductor element (e.g., the heat flow bypasses the at least one second semiconductor element). In one embodiment, the at least one second semiconductor element is directly bonded to the first semiconductor element without an intervening adhesive (e.g., direct hybrid bonded). In one embodiment, the interface between the at least one second semiconductor element and the first semiconductor element includes conductor-conductor (inter-conductor) and dielectric-dielectric (inter-dielectric) direct bonds. In one embodiment, the microelectronic device further includes a heat sink disposed on the at least one second semiconductor element. In one embodiment, the fluid cooling unit is configured to transfer heat from the first semiconductor device to a heat sink. In one embodiment, the heat sink is direct bonded to the at least one second semiconductor device without an intervening adhesive. In one embodiment, the first semiconductor device includes an integrated device die. In one embodiment, the at least one second semiconductor device includes an integrated device die. In one embodiment, the fluid comprises a gas. In one embodiment, the fluid comprises a liquid. In one embodiment, the fluid cooling unit reduces a heat flow rate through the at least one second semiconductor device (e.g., the heat flow bypasses the at least one second semiconductor device). In one embodiment, the at least one second semiconductor device is disposed within the fluid cooling unit. In one embodiment, the at least one second semiconductor device is disposed external to the fluid cooling unit.

[0019] FIG. 3A is a cross-sectional view of an example microelectronic system similar to the microelectronic system of FIG. 2, with like reference numbers used to refer to like features. However, the inner walls of the fluid-cooling unit may include finger features 391, 392, 393 (e.g., fingers / pillars), which may help prevent laminar flow in the fluid. In some embodiments, features 391, 392, and / or 393 may protrude inwardly into cavity 1391. In some examples, these features may help promote turbulence in the fluid, thus facilitating fluid mixing and heat transport. Thus, a non-limiting advantage of the disclosed technology is that features 391, 392, and / or 393 may help increase heat dissipation. In some embodiments, the inner walls of the fluid-cooling unit may be made of a semiconductor material, such as silicon (Si). In some embodiments, the inner bottom wall of the fluid cooling unit includes fingers 391 made of semiconductor material (e.g., Si) or fingers 392 or vias 393 made of metal (e.g., copper). In one embodiment, some metal fingers may extend to the base element 1000. For example, metal fingers extending from the fluid cooling unit to the bottom chip may be formed by direct bonding (e.g., by direct hybrid bonding, e.g., using a DBI® process) metal features of the fluid cooling unit to the bottom chip conductive vias 393. The conductive vias 393 may help conduct heat upward from the base element 1000 to the cavity 1301. The top heat sink 131 may be attached to the semiconductor element 101 and / or 102 via a thermally conductive material (TIM).

[0020] In another embodiment shown in Figures 3B, 3C and 3D, the bottom / base portion 301 of the fluid cooling unit and the top portion 302 of the fluid cooling unit may be made of different materials. In addition, the fluid cooling unit may further include an encapsulation portion 303. For example, the bottom / base portion 301 of the fluid cooling unit may be made of a semiconductor material, such as silicon (Si) 336. However, other portions of the fluid cooling unit, such as the top portion 302 or the encapsulation portion 303, may be made of another semiconductor material 337 or a polymer / plastic material 338.

[0021] For example, a microelectronic device may include a first semiconductor element, at least one second semiconductor element disposed on the first semiconductor element, and a fluid cooling unit disposed on the first semiconductor element, the fluid cooling unit including a cavity structure that contains a fluid, the fluid cooling unit including a thermal path for transferring and dissipating heat from the first semiconductor element. The fluid is transported through the cavity structure by an active mechanism. In one embodiment, the cavity structure is made of one or more electrical non-conductors or semiconductors. In one embodiment, the one or more electrical non-conductors or semiconductors comprise silicon or plastic. In one embodiment, an inner surface of the cavity structure includes features configured to increase turbulence in the fluid. In one embodiment, the features include an array of pillars. In one embodiment, the features include silicon or metal. In one embodiment, the cavity structure includes a bottom wall, the features disposed on the bottom wall. In one embodiment, the features include metal features extending to the first semiconductor element. In one embodiment, the metal features extending to the first semiconductor element are formed by direct bonding features on the bottom wall to conductive vias in the first semiconductor element, hi one embodiment, the features are disposed on the first semiconductor element.

[0022] FIG. 4 is a cross-sectional view of an example microelectronic system similar to that of FIG. 3A, with like reference numbers used to refer to like features. However, instead of attaching a pre-formed cavity structure, e.g., liquid channel 1391, to the base element 1000, the fluid cooling unit is formed by attaching / bonding a cap structure 450 (without a bottom wall) to the bottom chip, thus forming a cavity, e.g., liquid channel 1391, that can contain a fluid. In some embodiments, the cap structure may be directly bonded (e.g., ZIBOND® or DBI®) to the bottom chip. In some embodiments, the portion of the bottom chip that interfaces with the cavity, e.g., liquid channel 1391, may include features (e.g., semiconductor material (e.g., Si or metal fingers) that can help prevent / promote laminar / turbulent flow in the fluid. A top heat sink may be attached to the semiconductor element via a TIM.

[0023] For example, the microelectronic device may include a first semiconductor element, at least one second semiconductor element disposed on the first semiconductor element, and a fluid cooling unit disposed on the first semiconductor element, the fluid cooling unit including a cavity structure for containing a fluid, the fluid cooling unit including a thermal path for transferring and dissipating heat from the first semiconductor element. The fluid is transported through the cavity structure by an active mechanism. In one embodiment, the cavity structure is formed by direct bonding a cap structure without a bottom wall to the first semiconductor element. In one embodiment, the cavity structure has a bottom wall disposed on the first semiconductor element, and a coefficient of thermal expansion (CTE) of the bottom wall is substantially the same as a CTE of the first semiconductor element. In one embodiment, the first semiconductor element is made of silicon, and the cavity structure includes a bottom wall disposed on the first semiconductor element, and a coefficient of thermal expansion (CTE) of the bottom wall is substantially the same as a CTE of silicon. In one embodiment, the cavity structure includes a bottom wall disposed on the first semiconductor element, the bottom wall having a coefficient of thermal expansion (CTE) lower than that of copper. In one embodiment, the cavity structure includes a bottom wall disposed on the first semiconductor element, the bottom wall having a coefficient of thermal expansion (CTE) lower than 10 μm / m° C. In one embodiment, the cavity structure includes a bottom wall disposed on the first semiconductor element, the bottom wall being made of silicon. In one embodiment, the cavity structure includes a bottom wall disposed on the first semiconductor element, the bottom wall being directly bonded to the first semiconductor element without an intervening adhesive. In one embodiment, the interface between the bottom wall and the first semiconductor element includes a dielectric-dielectric direct bond.

[0024] A method of forming the microelectronic device 100 may include providing a first semiconductor element and bonding a second semiconductor element and a fluid cooling unit to the first semiconductor element such that the second semiconductor element and the fluid cooling unit are disposed on the first semiconductor element, the fluid cooling unit including a cavity structure that contains a fluid, and the fluid cooling unit including a thermal path for transferring and dissipating heat from the first semiconductor element. In one embodiment, bonding the second semiconductor element includes direct bonding the second semiconductor element to the first semiconductor element without an intervening adhesive. In one embodiment, the cavity structure includes a bottom wall, and bonding the fluid cooling unit includes direct bonding the bottom wall to the first semiconductor element without an intervening adhesive. In one embodiment, the method further includes forming the cavity structure by direct bonding a cap structure without a bottom wall to the first semiconductor element. In one embodiment, the second semiconductor element is disposed within the fluid cooling unit. In one embodiment, the second semiconductor device is provided external to the fluid cooling unit.

[0025] Electronic Devices A die may refer to any suitable type of integrated device die. For example, an integrated device die may include electronic components, such as integrated circuits (e.g., a processor die, a controller die, or a memory die), a microelectromechanical system (MEMS) die, an optical device, or any other suitable type of device die. In some embodiments, the electronic components include passive devices, such as capacitors, inductors, or other surface mount devices. Circuitry (e.g., active components such as transistors) may be patterned at or near the active side in various embodiments. The active side may be located on the side of the die opposite the back side of the die (the front side). The back side may or may not include any active or passive circuitry.

[0026] The integrated device die may have a bonding surface and a back surface opposite the bonding surface. The bonding surface may have a plurality of conductive bond pads including one conductive bond pad, and a non-conductive material located proximate the conductive bond pads. In some embodiments, the conductive bond pads of the integrated device die may be directly bonded to corresponding conductive pads of the substrate or wafer without an intervening adhesive, and the non-conductive material of the integrated device die may be directly bonded to a portion of the corresponding non-conductive material of the substrate or wafer without an intervening adhesive. Direct bonding without adhesives is described in U.S. Patent Nos. 7,126,212, 8,153,505, 7,622,324, 7,602,070, 8,163,373, 8,389,378, 7,485,968, 8,735,219, 9,385,024, 9,391,143, and 9,4 Nos. 31,368, 9,953,941, 9,716,033, 9,852,988, 10,032,068, 10,204,893, 10,434,749, and 10,446,532, each of which is incorporated by reference in its entirety and incorporated herein for all purposes.

[0027] Direct bonding method and direct bonded structure Various embodiments disclosed herein relate to a direct bonded structure in which two elements can be directly bonded without an intervening adhesive. The two or more electronic elements can be semiconductor elements (e.g., integrated device dies, wafers, etc.), and the two or more electronic elements can be stacked or bonded together to form a bonded structure. The conductive contact pads of one element can be electrically connected to the corresponding conductive contact pads of the other element. Any suitable number of elements can be stacked into a bonded structure. The contact pads can be metal pads formed on non-conductive bonding areas, and can be connected to an underlying metallization, such as a redistribution layer (RDL).

[0028] In some embodiments, the elements are directly bonded to each other without adhesive. In various embodiments, a non-conductive material or dielectric of a first element may be directly bonded to a corresponding non-conductive or dielectric field region of a second element without adhesive. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of the first element may be directly bonded to a corresponding non-conductive material of the second element using a dielectric-dielectric (inter-dielectric) bonding technique. For example, a dielectric-dielectric bond may be formed without adhesive using direct bonding techniques as disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference herein in its entirety for all purposes. Dielectrics suitable for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, or carbon such as silicon carbide, silicon oxycarbonitride, silicon carbonitride, or diamond-like carbon. In some embodiments, the dielectric does not include a polymeric material such as an epoxy, resin, or molding compound.

[0029] In some embodiments, the direct hybrid bond can be formed without an intervening adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or an etchant to activate the surfaces. In some embodiments, the surfaces can be terminated with a chemical species after or during activation (e.g., during a plasma and / or etch process). Without being bound by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surfaces, and the end-grouping process can provide additional chemical species at the bonding surfaces that improve the bonding energy during direct bonding. In some embodiments, activation and end-grouping can be provided in the same step, for example, the surfaces can be activated and end-grouped using a plasma or a wet etchant. In other embodiments, the bonding surfaces can be end-grouped in a separate process to provide additional chemical species that can be used for direct bonding. In various embodiments, the end-grouping chemical species can include nitrogen. For example, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, one or many fluorine peaks may appear near the layers and / or bonding interface. Thus, in a direct bonded structure, the bonding interface between the two dielectrics may comprise a very smooth interface with high nitrogen content and / or fluorine peaks at the bonding interface. Additional examples of activation and / or end group treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0030] In various embodiments, the contact pads of the first component may also be directly bonded to the corresponding conductive contact pads of the second component. For example, hybrid direct bonding techniques may be used to provide conductor-conductor direct bonds along a bond interface that includes a covalently directly bonded inter-dielectric surface that has been pretreated as described above. In various embodiments, conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds may be formed using direct bonding techniques as disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference herein in its entirety for all purposes.

[0031] For example, the dielectric bonding surfaces may be pretreated and directly bonded to each other without an intervening adhesive as described above. The conductive contact pads, which may be surrounded by a non-conductive dielectric field region, may also be directly bonded to each other without an intervening adhesive. In some embodiments, the contact pads may be recessed below the dielectric field region or the outer surface (e.g., top surface) of the non-conductive bonding layer, for example by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm or in the range of 4 nm to 10 nm. The non-conductive bonding layers may in some embodiments be directly bonded to each other without an adhesive at room temperature with a bonding tool described herein, after which the bonded structure may be annealed. The annealing may be performed in a separate apparatus. During annealing, the contact pads may expand and contact each other, thereby forming a metal-metal (intermetal) direct bond. Advantageously, the use of hybrid bonding technology, such as Direct Bond Interconnect, or DBI® technology, commercially available from Xperi, Inc., San Jose, Calif., allows for a high density of pads connected across the direct bond interface (e.g., with a small or fine pitch for a regular array). In some embodiments, the pitch of the bond pads, or the conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 microns, or less than 10 microns, or even less than 2 microns. For some applications, the ratio of the bond pad pitch to one of the bond pad features is less than 5 or less than 3, and in some cases desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range from 0.3 microns to 5 microns. In various embodiments, the contact pads and / or traces may be made of copper, although other metals may be suitable.

[0032] Thus, in a direct bonding process, the first element can be directly bonded to the second element without an intervening adhesive. In some configurations, the first element can be a singulated element, such as a singulated integrated device die. In other configurations, the first element can be a carrier or substrate (e.g., a wafer) that includes multiple (e.g., tens, hundreds, or more) device regions that, when singulated, form multiple integrated device dies. In the embodiments described herein, the first element, whether a die or a substrate, may be considered a host substrate, which is attached to a support of a bonding tool for pick-and-placement of the second element or for receiving a robotic end effector. The second element in the illustrated embodiment is a die. In other configurations, the second element can be a carrier or flat panel, or a substrate (e.g., a wafer).

[0033] As described herein, the first and second elements can be directly bonded together without adhesive, which is different from a deposition process. In one application, the width of the first element in the bonded structure can be approximately the same as the width of the second element. In some other embodiments, the width of the first element in the bonded structure can be different from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Thus, the first and second elements can be comprised of non-deposited elements. Furthermore, unlike deposited layers, the direct bonded structure can include defect areas along the bond interface where nanovoids exist. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonding surface. As discussed above, the bond interface can exhibit a concentration of material resulting from activation and / or final chemical treatment process. For example, in an embodiment utilizing nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface. In embodiments utilizing oxygen plasma for activation, oxygen peaks may form at the bond interface. In some embodiments, the bond interface may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond may include a covalent bond, which is stronger than a van der Waals bond. The bonding layer may further have a polished surface that is planarized to a high degree of smoothness. For example, the bonding layer may have a surface roughness of 2 nm root mean square (RMS) per micron or 1 nm RMS per micron.

[0034] In various embodiments, the metal-metal bonds between the contact pads in the direct hybrid bonded structure may be bonded such that the conductive feature grains on the conductive features, e.g., copper grains, grow into one another across the bond interface. In some embodiments, the copper may have grains oriented along 111 crystal planes to improve diffusion of the copper across the bond interface. The bond interface may extend substantially completely to at least a portion of the bonded contact pad, such that there are substantially no gaps between the non-conductive bond regions at or near the bonded contact pad. In some embodiments, a barrier layer may be provided under the contact pad (e.g., which may include copper). However, in other embodiments, there may be no barrier layer under the contact pad, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated by reference in its entirety and incorporated by reference herein for all purposes.

[0035] In one aspect, the disclosed technology relates to a microelectronic device having a first semiconductor element, at least one second semiconductor element provided on the first semiconductor element, and a fluid cooling unit provided on the first semiconductor element, the fluid cooling unit having a cavity structure for containing a fluid, and the fluid cooling unit having a thermal path for transferring and dissipating heat from the first semiconductor element.

[0036] In one embodiment, the fluid is transported through the cavity structure by an active mechanism.

[0037] In one embodiment, the cavity structure is made of one or more electrical insulators or semiconductors.

[0038] In one embodiment, the one or more electrical non-conductors or semiconductors comprise silicon or plastic.

[0039] In one embodiment, the interior surface of the cavity structure has features configured to increase turbulence in the fluid.

[0040] In one embodiment, the features consist of an array of pillars.

[0041] In one embodiment, the features are made of silicon or metal.

[0042] In one embodiment, the cavity structure has a bottom wall and the feature is disposed on the bottom wall.

[0043] In one embodiment, the feature comprises a metal feature that extends to the first semiconductor element.

[0044] In one embodiment, the metal feature extending to the first semiconductor element is formed by direct bonding a feature provided on the bottom wall to a conductive via provided in the first semiconductor element.

[0045] In one embodiment, the feature is located on the first semiconductor device.

[0046] In one embodiment, the cavity structure is formed by direct bonding a bottom-less cap structure to the first semiconductor element.

[0047] In one embodiment, the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall having a coefficient of thermal expansion (CTE) substantially the same as the CTE of the first semiconductor element.

[0048] In one embodiment, the first semiconductor element is made of silicon, and the cavity structure has a bottom wall disposed on the first semiconductor element, and the coefficient of thermal expansion (CTE) of the bottom wall is substantially the same as the CTE of silicon.

[0049] In one embodiment, the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall having a coefficient of thermal expansion (CTE) lower than the CTE of copper.

[0050] In one embodiment, the cavity structure has a bottom wall disposed on the first semiconductor element, and the bottom wall has a coefficient of thermal expansion (CTE) lower than 10 μm / m° C.

[0051] In one embodiment, the cavity structure has a bottom wall disposed on the first semiconductor device, the bottom wall being made of silicon.

[0052] In one embodiment, the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall being directly bonded to the first semiconductor element without an intervening adhesive.

[0053] In one embodiment, the interface between the bottom wall and the first semiconductor element comprises a dielectric-to-dielectric direct bond.

[0054] In one embodiment, the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall being bonded to the first semiconductor element by solder bonding.

[0055] In one embodiment, the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall being bonded to the first semiconductor element by adhesive bonding.

[0056] In one embodiment, the cavity structure has a bottom wall disposed on the first semiconductor device, the bottom wall being bonded to the first semiconductor device by a thermally conductive material (TIM).

[0057] In one embodiment, the at least one second semiconductor element is direct bonded (eg, direct hybrid bonded) to the first semiconductor element without an intervening adhesive.

[0058] In one embodiment, the interface between the at least one second semiconductor element and the first semiconductor element comprises a conductor-to-conductor direct bond and a dielectric-to-dielectric direct bond.

[0059] In one embodiment, the microelectronic device further comprises a heat sink disposed on the at least one second semiconductor element.

[0060] In one embodiment, the fluid cooling unit is configured to transfer heat from the first semiconductor device to a heat sink.

[0061] In one embodiment, the heat sink is directly bonded to the at least one second semiconductor device without an intervening adhesive.

[0062] In one embodiment, the first semiconductor element comprises an integrated device die.

[0063] In one embodiment, the at least one second semiconductor element comprises an integrated device die.

[0064] In one embodiment, the fluid comprises a gas.

[0065] In one embodiment, the fluid comprises a liquid.

[0066] In one embodiment, the fluid cooling unit reduces the heat flow through the at least one second semiconductor device (eg, the heat flow bypasses the at least one second semiconductor device).

[0067] In one embodiment, the at least one second semiconductor device is disposed within the fluid cooling unit.

[0068] In one embodiment, the at least one second semiconductor device is disposed outside the fluid cooling unit.

[0069] In another aspect, the disclosed technology relates to a method of fabricating a microelectronic device, comprising the steps of providing a first semiconductor element; and bonding a second semiconductor element and a fluid cooling unit to the first semiconductor element such that the second semiconductor element and the fluid cooling unit are disposed on the first semiconductor element, the fluid cooling unit having a cavity structure for containing a fluid, and the fluid cooling unit having a thermal path for transferring and dissipating heat from the first semiconductor element.

[0070] In one embodiment, the step of bonding the second semiconductor element comprises direct bonding the second semiconductor element to the first semiconductor element without an intervening adhesive.

[0071] In one embodiment, the cavity structure has a bottom wall, and bonding the fluid cooling unit comprises directly bonding the bottom wall to the first semiconductor device without an intervening adhesive.

[0072] In one embodiment, the method further includes forming a cavity structure by direct bonding a bottom-wall-less cap structure to the first semiconductor element.

[0073] In one embodiment, the second semiconductor device is disposed within a fluid cooling unit.

[0074] In one embodiment, the second semiconductor device is disposed outside the fluid cooling unit.

[0075] In another aspect, the disclosed technology relates to a microelectronic device having a first semiconductor element and a fluid cooling unit directly bonded to the first semiconductor element without any intervening adhesive, the fluid cooling unit having a cavity structure for containing a fluid.

[0076] In one embodiment, the microelectronic device further comprises at least one second semiconductor element disposed on the first semiconductor element.

[0077] In one embodiment, the fluid cooling unit reduces the heat flow through the at least one second semiconductor device (eg, the heat flow bypasses the at least one second semiconductor device).

[0078] Unless the context clearly requires otherwise, throughout the specification and claims, the terms "comprise", "comprising", "include", "including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to", as opposed to an exclusive or exhaustive sense. As used generally herein, the term "coupled" means two or more elements that are directly connected to each other or that are connected to each other through one or more intermediate elements. Similarly, as used generally herein, the term "coupled" means two or more elements that are directly connected to each other or that are connected to each other through one or more intermediate elements. In addition, the terms "herein," "above," "below," and words of similar import as used in the parent application refer to the application as a whole and not to any particular portion of the application. Furthermore, as used herein, when a first element is described as being located "on" or "over" a second element, the first element may be directly located on or over the second element such that the first element and the second element are in direct contact with each other, or the first element may be indirectly located on or over the second element such that one or more elements are interposed between the first element and the second element. Where the context permits, terms in the above detailed description using the singular or plural may include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0079] Furthermore, conditional terms used in the specification, particularly "can," "could," "might," "may," "eg," "for example," "such as," and the like, unless expressly specified otherwise or understood otherwise within the context in which they are used, are generally intended to imply that certain embodiments include certain features, elements, and / or conditions and that other embodiments do not include certain features, elements, and / or conditions. Thus, such conditional terms are not generally intended to imply that features, elements, and / or conditions are present in any required manner for one or more embodiments.

[0080] Although certain embodiments have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and furthermore, various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, although blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention as set forth in the appended claims and equivalents thereto is intended to include such forms or modifications within the scope and spirit of the invention.

Claims

1. 1. A microelectronic device comprising: a first semiconductor element; at least one second semiconductor element disposed on the first semiconductor element; a fluid cooling unit provided on the first semiconductor element, the fluid cooling unit having a cavity structure for accommodating a fluid, and the fluid cooling unit having a thermal path for transferring and dissipating heat from the first semiconductor element.

2. The microelectronic device of claim 1 , wherein the fluid is conveyed through the cavity structure by an active mechanism.

3. The microelectronic device of claim 1 , wherein the cavity structure is made of one or more electrically non-conductors or semiconductors.

4. The microelectronic device of claim 1 , wherein an interior surface of the cavity structure has features configured to increase turbulence in the fluid.

5. The microelectronic device of claim 4 , wherein the features comprise an array of pillars.

6. The microelectronic device of claim 4 , wherein the feature is made of silicon or metal.

7. The microelectronic device of claim 1 , wherein the cavity structure is formed by directly bonding a bottomless cap structure to the first semiconductor element.

8. 2. The microelectronic device of claim 1, wherein the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first semiconductor element.

9. 2. The microelectronic device of claim 1, wherein the first semiconductor element is made of silicon, and the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall having a coefficient of thermal expansion (CTE) substantially the same as a CTE of silicon.

10. The microelectronic device of claim 1 , wherein the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall having a coefficient of thermal expansion (CTE) lower than the CTE of copper.

11. The microelectronic device of claim 1 , wherein the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall having a coefficient of thermal expansion (CTE) of less than 10 μm / m° C.

12. The microelectronic device of claim 1 , wherein the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall being made of silicon.

13. 2. The microelectronic device of claim 1, wherein the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall being directly bonded to the first semiconductor element without an intervening adhesive.

14. The microelectronic device of claim 1 , wherein the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall being bonded to the first semiconductor element by solder bonding.

15. The microelectronic device of claim 1 , wherein the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall being bonded to the first semiconductor element by adhesive bonding.

16. 2. The microelectronic device of claim 1, wherein the cavity structure has a bottom wall disposed on the first semiconductor element, the bottom wall being bonded to the first semiconductor element by a thermally interface material (TIM).

17. The microelectronic device of claim 1 , wherein the at least one second semiconductor element is direct hybrid bonded to the first semiconductor element without an intervening adhesive.

18. The microelectronic device of claim 1 , further comprising a heat sink disposed on the at least one second semiconductor element.

19. 1. A method of fabricating a microelectronic device, said method comprising: providing a first semiconductor device; bonding a second semiconductor device and a fluid cooling unit to the first semiconductor device such that the second semiconductor device and the fluid cooling unit are disposed on the first semiconductor device; The method, wherein the fluid cooling unit has a cavity structure for containing a fluid, and the fluid cooling unit has a thermal path for transferring and dissipating heat from the first semiconductor device.

20. 20. The method of claim 19, wherein said step of bonding said second semiconductor element comprises direct bonding said second semiconductor element to said first semiconductor element without an intervening adhesive.

21. 20. The method of claim 19, wherein the cavity structure has a bottom wall, and wherein bonding the fluid cooling unit comprises directly bonding the bottom wall to the first semiconductor device without an intervening adhesive.

22. 20. The method of claim 19, further comprising forming the cavity structure by direct bonding a bottom-wallless cap structure to the first semiconductor element.

23. The microelectronic device of claim 1 , wherein the fluid cooling unit reduces the heat flow rate through the at least one second semiconductor element.

24. 1. A microelectronic device comprising: a first semiconductor element; a fluid cooling unit directly bonded to the first semiconductor element without any intervening adhesive, the fluid cooling unit having a cavity structure for containing a fluid.

25. 25. The microelectronic device of claim 24, further comprising at least one second semiconductor element disposed on the first semiconductor element.

26. 26. The microelectronic device of claim 25, wherein the fluid cooling unit reduces the heat flow rate through the at least one second semiconductor element.

27. The microelectronic device of claim 1 , wherein the at least one second semiconductor element is disposed within the fluid cooling unit.

28. The microelectronic device of claim 1 , wherein the at least one second semiconductor element is disposed outside the fluid cooling unit.

29. 20. The microelectronic device of claim 19, wherein the second semiconductor element is disposed within the fluid cooling unit.

30. 20. The microelectronic device of claim 19, wherein the second semiconductor element is disposed outside the fluid cooling unit.

Images