SYSTEM AND METHOD FOR DETERMINING PHASE DIFFERENCE BETWEEN RF SIGNALS PROVIDED TO ELECTRODES - Patent application

Abstract

A method is described for increasing a rate at which a substrate is processed to achieve an etch profile for the substrate. The method includes receiving a parameter signal from a first sensor when a first radio frequency (RF) signal is provided to the substrate support and a second RF signal is provided to the upper electrode. The method further includes determining a first time at which a value of the parameter is maximum based on the parameter signal. The method also includes receiving a variable signal from a second sensor. The method includes determining a second time at which a first amount of flux of secondary electrons from the upper electrode to the substrate support is maximum based on the variable signal. The method includes determining a phase difference is a difference between the first time and the second time and achieving the phase difference.

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The embodiments described in this disclosure relate to systems and methods for determining the phase difference between radio frequency (RF) signals provided to electrodes. [Background technology]

[0002] The background description provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be regarded as prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure.

[0003] One or more radio frequency (RF) generators generate one or more RF signals and supply the RF signals to a plasma reactor. The plasma reactor has a semiconductor wafer that is etched when the one or more RF signals are supplied and an etchant gas is supplied to the plasma reactor. The semiconductor wafer includes a number of features. Sidewalls of the features are etched when the RF signals are supplied.

[0004] It is against this background that the embodiments described in this disclosure arise. Summary of the Invention

[0005] The embodiments of the present disclosure provide a system and method for determining a phase difference between radio frequency (RF) signals provided to electrodes. It should be understood that the embodiments can be implemented in numerous ways, such as, for example, a process, an apparatus, a system, hardware, or a method on a computer readable medium. Several embodiments are described below.

[0006] In one embodiment, a method for increasing a rate at which a substrate is processed is described. The method includes receiving a parameter signal from a first sensor when a first radio frequency (RF) signal is provided to the substrate support and a second RF signal is provided to the upper electrode. The method further includes determining a first time at which a value of the parameter is maximum based on the parameter signal. The first time occurs during a cycle of a clock signal. The method also includes receiving a variable signal from a second sensor. The method includes determining a second time at which a first amount of flux of secondary electrons from the upper electrode to the substrate support is maximum based on the variable signal. The second time occurs during the cycle and after the first time. The method includes determining a phase difference is a difference between the first time and the second time, and creating a phase difference between a phase of a third RF signal and a phase of a fourth RF signal. The third RF signal is provided to the upper electrode and the fourth RF signal is provided to the substrate support. The creating a phase difference is performed to increase a rate at which the substrate is processed.

[0007] In an embodiment, a method for increasing a rate at which a substrate is processed is described. The method includes determining a first time at which a first amount of secondary electron flux from the substrate support to the upper electrode is maximum. The first time occurs within a first clock cycle in which the substrate support receives a first RF signal and the upper electrode receives a second RF signal. The method further includes determining a second time at which a second amount of secondary electron flux from the upper electrode to the substrate support is maximum. The second time occurs within the first clock cycle. The method includes determining a phase difference to be a difference between the second time and the first time, and creating a phase difference between a phase of a third RF signal and a phase of a fourth RF signal. The third RF signal is provided to the upper electrode and the fourth RF signal is provided to the substrate support. The act of creating a phase difference is performed to increase a rate at which the substrate is processed.

[0008] In one embodiment, a controller is described. The controller includes a processor that receives a parameter signal from a first sensor when a first RF signal is provided to the substrate support and a second RF signal is provided to the upper electrode. The processor determines a first time when a value of the parameter is maximum based on the parameter signal. The first time occurs during a cycle of a clock signal. The processor further receives a variable signal from a second sensor. The processor determines a second time when a first amount of flux of secondary electrons from the upper electrode to the substrate support is maximum based on the variable signal. The second time occurs during the cycle and after the first time. The processor determines a phase difference is a difference between the first time and the second time. The processor creates a phase difference between a phase of a third RF signal and a phase of a fourth RF signal. The third RF signal is provided to the upper electrode and the fourth RF signal is provided to the substrate support, and the phase difference is created to increase a speed of processing the substrate. The controller includes a memory device coupled to the processor.

[0009] Some advantages of the systems and methods described herein for determining a phase difference between RF signals provided to the electrodes include increasing the speed at which a substrate is processed and improving the etch profile of the substrate. The etch profile provides a cross-section of an etch feature (such as a contact hole or trench) on the substrate. Achieving the phase difference increases the acceleration of secondary electrons flowing from the top electrode to the bottom electrode. The secondary electrons can penetrate the top plasma sheath, the plasma, the bottom plasma sheath, and are incident on the surface of the substrate being processed. The accelerated secondary electrons penetrate the etch feature on the substrate and discharge the positively charged sidewalls and bottom of the etch feature, thus improving the etch profile and etch rate of the etch feature. The accelerated secondary electrons also reduce the chance of the sidewalls of the etch feature on the substrate being etched. More penetration into the etch feature and reduced chance of the sidewalls being etched increases the depth of the etch feature and improves the etch profile.

[0010] Certain other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0011] The embodiments are understood by reference to the following description taken in conjunction with the accompanying drawings.

[0012] [Figure 1] FIG. 1 is a diagram of one embodiment of a system to illustrate a method for determining phase difference during a lab routine.

[0013] [Figure 2A] FIG. 2A is one embodiment of a graph to illustrate a plot of voltage versus time associated with a lower electrode and voltage versus time associated with an upper electrode of a substrate support.

[0014] [Figure 2B] FIG. 2B is one embodiment of a graph to illustrate a plot of voltage versus time associated with a lower electrode and voltage versus time associated with an upper electrode.

[0015] [Diagram 3] FIG. 3 is a diagram of one embodiment of a system to illustrate the application of determined phase differences during a lab routine.

[0016] [Figure 4] FIG. 4 is a diagram of one embodiment of a graph to illustrate a clock signal.

[0017] [Diagram 5] FIG. 5 is an illustration of one embodiment of a graph to illustrate a pulsed radio frequency (RF) signal.

[0018] [Figure 6] FIG. 6 is a diagram of an embodiment of a graph to illustrate another pulsed RF signal.

[0019] [Figure 7A] FIG. 7A is a top-down view of one embodiment of a stack illustrating that sidewalls of stack features (such as channels) are etched when no phase difference is applied during stack processing.

[0020] [Figure 7B] FIG. 7B is a side view of one embodiment of the stack of FIG. 7A.

[0021] [Figure 8] FIG. 8 is one embodiment of a graph to illustrate the reduction in transient wiggling when a phase difference is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] In the following embodiments, systems and methods for determining a phase difference between radio frequency (RF) signals provided to electrodes are described. It will be understood that the embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail so as not to unnecessarily obscure the embodiments.

[0023] 1 is a diagram of an embodiment of a system 100 to illustrate a phase difference determination method. The system 100 includes a master RF generator system 102, a matcher 104, a plasma chamber 106, a slave RF generator system 108, another matcher 110, and a host computer 112. The host computer 112 includes a processor 114 and a memory device 116. The system 100 further includes another slave RF generator system 118 and a matcher 120.

[0024] As used herein, a matcher is a network of circuit components such as inductors, capacitors, and resistors. For example, a matcher includes one or more shunt circuits and one or more series circuits. Each shunt circuit has one or more circuit components, as does each series circuit. A branch circuit of the matcher includes one or more shunt circuits, or one or more series circuits, or a combination thereof, and is coupled between the input of the matcher and the output of the matcher.

[0025] The system 100 further includes a magnetic field sensor, which is shown as B-sensor in Figure 1. The system 100 further includes a voltage (V1) sensor and another voltage (V2) sensor.

[0026] The plasma chamber 106 includes a substrate support SS, an edge ring ER, and an upper electrode UE. An example of the substrate support SS is a chuck that includes a lower electrode. The edge ring ER is an annular ring that surrounds the periphery of the substrate support SS. The upper electrode UE faces the substrate support SS.

[0027] Examples of the host computer 112 include controllers, laptop computers, desktop computers, tablets, and smartphones. Examples of the processor 114 include application specific integrated circuits (ASICs), programmable logic devices (PLDs), central processing units (CPUs), microprocessors, and microcontrollers. Examples of the memory device 116 used herein include read only memory (RAM), random access memory (ROM), and combinations thereof. Illustratively, the memory device 116 is a flash memory, or a redundant array of independent disks (RAID).

[0028] The processor 114 is coupled to the memory device 116. The processor 114 is also coupled to the master RF generator system 102, the slave RF generator system 108, and the slave RF generator system 118. For example, the processor 114 is coupled to a digital signal processor (DSP) of the master RF generator system 102 via a transfer cable, to the DSP of the slave RF generator system 108 via another transfer cable, and to the DSP of the slave RF generator system 118 via yet another transfer cable. Examples of transfer cables include cables that transfer recipe signals in a serial or parallel manner, or using a Universal Serial Bus (USB) protocol.

[0029] An example of the master RF generator system 102 is a master RF generator having a low, medium, or high operating frequency. An example of the slave RF generator system 108 is a slave RF generator having a low, medium, or high frequency. Also, an example of the slave RF generator system 118 is a slave RF generator having a low, medium, or high frequency. For example, when the master RF generator system 102 has a low frequency, the slave RF generator systems 108 and 118 each have a low frequency. As another example, when the master RF generator system 102 has a medium frequency, the slave RF generator systems 108 and 118 each have a medium frequency. As yet another example, when the master RF generator system 102 has a high frequency, the slave RF generator systems 108 and 118 each have a high frequency.

[0030] Examples of low frequencies include 400 kilohertz (kHz) and 2 megahertz (MHz). Examples of medium frequencies include 13.56 MHz and 27 MHz. An example of a high frequency is 60 MHz.

[0031] The master RF generator system 102 is coupled to the matcher 104 via an RF cable 122, and the matcher 104 is coupled to the lower electrode of the substrate support SS via an RF transmission line 124. The slave RF generator system 108 is coupled to the matcher 110 via an RF cable 126, and the matcher 110 is coupled to the upper electrode UE via an RF transmission line 128. Also, the slave RF generator system 118 is coupled to the matcher 120 via an RF cable 130, and the matcher 120 is coupled to the edge ring ER via an RF transmission line 132. The master RF generator system 102 is coupled to the slave RF generator system 108 and the slave RF generator system 118. For example, the DSP of the master RF generator system 102 is coupled to the DSP of the slave RF generator system 108 via a transmission cable, and the DSP of the master RF generator system 102 is coupled to the DSP of the slave RF generator system 118 via another transmission cable.

[0032] The V1 sensor is coupled to a point P1 on the RF transmission line 124. Additionally, the B sensor is coupled to a point P1 on the RF transmission line 124, and the V2 sensor is coupled to a point P2 on the RF transmission line 128. A substrate S (such as a semiconductor wafer or a dummy substrate) is placed on an upper surface of a substrate support SS in the plasma chamber 106.

[0033] Processor 114 provides recipe signal 103 to master RF generator system 102, recipe signal 105 to slave RF generator system 108, and another recipe signal 107 to slave RF generator system 118. Upon receiving recipe signal 103 from processor 114, master RF generator system 102 provides the frequency indicated in recipe signal 103 to each of slave RF generator system 108 and slave RF generator system 118.

[0034] The recipe signal 103 provided to the master RF generator system 102 includes the power level, phase, pulse frequency, and frequency of the RF signal 134 generated by the master RF generator system 102. As an example, the pulse frequency of the RF signal is the frequency at which the envelope of the RF signal is pulsed from a first power level to a second power level. In this example, the envelope is the peak-to-peak amplitude or the zero-to-peak amplitude of the RF signal. By way of example, the pulse frequency of the RF signal is lower than the frequency of the RF signal. Similarly, the recipe signal 105 provided to the slave RF generator system 108 includes the power level of the RF signal 136 generated by the slave RF generator system 108, and the recipe signal 107 provided to the slave RF generator system 118 includes the power level of the RF signal 138 generated by the slave RF generator system 118.

[0035] Upon receiving the recipe signal 103 from the master RF generator system 102, the slave RF generator system 108 identifies the frequency indicated in the recipe signal 103 and determines the frequency of the RF signal 136 generated by the slave RF generator system 108 based on the frequency indicated in the recipe signal 103. For example, the DSP of the slave RF generator system 108 determines that the frequency of the RF signal 136 is equal to the frequency of the RF signal 134. As another example, the DSP of the slave RF generator system 108 determines that the frequency of the RF signal 136 is within a predetermined range from the frequency of the RF signal 134.

[0036] Also, upon receiving the recipe signal 103 from the master RF generator system 102, the slave RF generator system 108 identifies the pulse frequency indicated in the recipe signal 103 and determines the pulse frequency of the RF signal 136 generated by the slave RF generator system 108. For example, the DSP of the slave RF generator system 108 determines that the pulse frequency of the RF signal 136 is synchronized with the pulse frequency of the RF signal 134. Illustratively, the envelope of the RF signal 136 transitions from a first power level to a second power level at the same time that the envelope of the RF signal 134 transitions from a third power level to a fourth power level. As another example, the DSP of the slave RF generator system 108 determines that the pulse frequency of the RF signal 136 is within a predetermined range from the pulse frequency of the RF signal 134. Illustratively, the envelope of RF signal 136 transitions from the first power level to the second power level within a predetermined period of time from the time the envelope of RF signal 134 transitions from the third power level to the fourth power level.

[0037] Upon receiving the recipe signal 103 from the master RF generator system 102, the slave RF generator system 118 identifies the frequency and phase indicated in the recipe signal 103 and determines the frequency and phase of the RF signal 138 generated by the slave RF generator system 118. For example, the DSP of the slave RF generator system 118 determines that the frequency of the RF signal 138 is equal to the frequency of the RF signal 134. As another example, the DSP of the slave RF generator system 118 determines that the frequency of the RF signal 138 is within a predetermined range from the frequency of the RF signal 134. As yet another example, the DSP of the slave RF generator system 118 determines that the phase of the RF signal 138 is the same as the phase of the RF signal 134. As yet another example, the DSP of the slave RF generator system 118 determines that the phase of the RF signal 138 is within a predetermined range from the phase of the RF signal 134.

[0038] Also, upon receiving the recipe signal 103 from the master RF generator system 102, the slave RF generator system 118 identifies the pulse frequency indicated in the recipe signal 103 and determines the pulse frequency of the RF signal 138 generated by the slave RF generator system 118. For example, the DSP of the slave RF generator system 118 determines that the pulse frequency of the RF signal 138 is synchronized with the pulse frequency of the RF signal 134. Illustratively, the envelope of the RF signal 138 transitions from a first power level to a second power level at the same time that the envelope of the RF signal 134 transitions from a third power level to a fourth power level. As another example, the DSP of the slave RF generator system 118 determines that the pulse frequency of the RF signal 138 is within a predetermined range from the pulse frequency of the RF signal 134. Illustratively, the envelope of RF signal 138 transitions from the first power level to the second power level within a predetermined period of time from the time the envelope of RF signal 134 transitions from the third power level to the fourth power level.

[0039] Additionally, the processor 114 transmits a trigger signal to each of the master RF generator system 102, the slave RF generator system 108, and the slave RF generator system 118. Upon receiving the trigger signal, the master RF generator system 102 generates an RF signal 134 having a frequency, phase, pulse frequency, and power level indicated in the recipe signal 103 received from the processor 114, and transmits the RF signal 134 to an input of the matcher 104 via the RF cable 122. Similarly, upon receiving the trigger signal, the slave RF generator system 108 generates an RF signal 136 having a power level indicated in the recipe signal 105 received from the processor 114 based on the frequency and pulse frequency identified in the recipe signal 103 received from the master RF generator system 102, and transmits the RF signal 136 to an input of the matcher 110 via the RF cable 126. Also, upon receiving the trigger signal, the slave RF generator system 118 generates an RF signal 138 having a power level indicated in the recipe signal 107 received from the processor 114 based on the frequency and phase identified in the recipe signal 103 received from the master RF generator system 102, and transmits the RF signal 138 via the RF cable 130 to the input of the matcher 120.

[0040] When the RF signal 134 is received at the input of the matcher 104, the matcher 104 matches the impedance of a load coupled to the output of the matcher 104 with the impedance of a source coupled to the input of the matcher 104. Examples of sources coupled to the input of the matcher 104 include the master RF generator system 102 and the RF cable 122, and examples of loads coupled to the output of the matcher 104 include the plasma chamber 106 and the RF transmission line 124. The impedance is matched to modify the impedance of the RF signal 134, and a modified RF signal 139 is provided at the output of the matcher 104. The modified RF signal 139 is provided to the lower electrode of the substrate support SS via the RF transmission line 124.

[0041] Similarly, when the RF signal 136 is received at the input of the matcher 110, the matcher 110 matches the impedance of a load coupled to the output of the matcher 110 with the impedance of a source coupled to the input of the matcher 110. Examples of sources coupled to the input of the matcher 110 include the slave RF generator system 108 and the RF cable 126, and examples of loads coupled to the output of the matcher 110 include the plasma chamber 106 and the RF transmission line 128. The impedances are matched to modify the impedance of the RF signal 136, and a modified RF signal 140 is provided at the output of the matcher 110. The modified RF signal 140 is provided to the upper electrode UE via the RF transmission line 128.

[0042] Also, when the RF signal 138 is received at the input of the matcher 120, the matcher 120 matches the impedance of a load coupled to the output of the matcher 120 with the impedance of a source coupled to the input of the matcher 120. Examples of sources coupled to the input of the matcher 120 include the slave RF generator system 118 and the RF cable 130, and examples of loads coupled to the output of the matcher 120 include the plasma chamber 106 and the RF transmission line 132. The impedances are matched to modify the impedance of the RF signal 138, and a modified RF signal 142 is provided at the output of the matcher 120. The modified RF signal 142 is provided to the edge ring ER via the RF transmission line 132.

[0043] A plasma is struck or maintained in the plasma chamber 106 when one or more process gases are supplied to a gap between the substrate support SS and the upper electrode UE in the plasma chamber 106 in addition to the modified RF signals 139, 140, and 142. Examples of the one or more process gases include an oxygen-containing gas, a nitrogen-containing gas, a fluorine-containing gas, and combinations thereof. The plasma generated in the plasma chamber 106 is used to process the substrate S. For example, the plasma may be used to deposit material on an upper surface of the substrate S, or to etch the substrate S, or to clean the substrate S. The plasma is surrounded on its top side by an upper plasma sheath 144 and on its bottom side by a bottom plasma sheath 146. The plasma is a mixture of electrons (e - ) and negative ions (-ve), which are incident on the upper surface of the substrate S to process the substrate S.

[0044] As the substrate S is processed, the V1 sensor measures the voltage at point P1 on the RF transmission line 124 and outputs a parameter signal PS1, and the V2 sensor measures the voltage at point P2 on the RF transmission line 128 and outputs a parameter signal PS2. An example of a parameter as used herein is voltage. Also, the B sensor measures the magnetic field or flux at point P1 on the RF transmission line 124 and outputs a variable signal VS1.

[0045] The parameter signal PS1 is provided from the V1 sensor to the processor 114. The processor 114 controls the set point of the RF signal 134 based on the parameter signal PS1. For example, when the processor 114 determines that the voltage indicated by the parameter signal PS1 is not within a predetermined range from the predetermined voltage set point, the processor 114 modifies the power level provided to the master RF generator system 102 in the recipe signal 103. It should be noted that when the set point of the RF signal 134 is controlled, the set point of the RF signal 138 is also controlled. For example, the modified power level transmitted from the processor to the master RF generator system 102 is further transmitted from the master RF generator system 102 to the slave RF generator system 118. Upon receiving the modified power level, the slave RF generator system 118 modifies the power level of the RF signal 138 to achieve the modified power level.

[0046] Similarly, parameter signal PS2 is provided from the V2 sensor to processor 114. Processor 114 controls the set point of RF signal 136 based on parameter signal PS2. For example, upon determining that the voltage indicated by parameter signal PS2 is not within a predetermined range from a predetermined voltage set point, processor 114 modifies the power level provided to slave RF generator system 108 in recipe signal 105.

[0047] In one embodiment, the B sensor measures the magnetic field or flux at a point different from point P1 on the RF transmission line 124. The different point is located between the output of the matcher 104 and the plasma chamber 106.

[0048] In an embodiment, the V2 sensor is coupled to any other point between the output of the matcher 110 and the plasma chamber 106 instead of point P2.

[0049] In an embodiment, the V1 sensor is coupled to any other point between the output of the matcher 104 and the plasma chamber 106 instead of point P1.

[0050] In one embodiment, the B sensor is replaced with a complex voltage-current (VI) probe that measures the complex voltage-current at point P1.

[0051] In one embodiment, the master RF generator system 102 includes multiple RF generators, such as a first master RF generator and a second master RF generator. Similarly, the slave RF generator system 108 includes multiple RF generators, such as a first slave RF generator and a second slave master RF generator. Also, the slave RF generator system 118 includes multiple RF generators, such as a third slave RF generator and a fourth slave master RF generator. The first master RF generator has a low, medium, or high operating frequency, and the second master RF generator has a low, medium, or high operating frequency. Also, the first slave RF generator has a low, medium, or high operating frequency, and the second slave RF generator has a low, medium, or high operating frequency. Furthermore, the third slave RF generator has a low frequency, a medium frequency, or a high frequency operating frequency, and the fourth slave RF generator has a low frequency, a medium frequency, or a high frequency operating frequency. For example, each of the first slave RF generator and the third slave RF generator has the same operating frequency as the operating frequency of the first master RF generator, and each of the second slave RF generator and the fourth slave RF generator has the same operating frequency as the operating frequency of the second master RF generator. Note that the first master RF generator is coupled to the first slave RF generator and the third slave RF generator, and the second master RF generator is coupled to the second slave RF generator and the fourth slave RF generator.

[0052] Further, in this embodiment, the first and second master RF generators are coupled to the substrate support SS via a first matcher, the first and second slave RF generators are coupled to the edge ring ER via a second matcher, and the third and fourth slave RF generators are coupled to the upper electrode UE via a third matcher. The processor 114 is coupled to each of the first master RF generator, the second master RF generator, the first slave RF generator, the second slave RF generator, the third slave RF generator, and the fourth slave RF generator.

[0053] Continuing with this embodiment, the processor 114 controls the first master RF generator, the first slave RF generator, and the third slave RF generator in the same manner that the master RF generator system 102, the slave RF generator system 118, and the slave RF generator system 108 are controlled. The first master RF generator also controls each of the first and third slave RF generators in the same manner that the master RF generator system 102 controls each of the slave RF generator system 118 and the slave RF generator system 108. Also, in this embodiment, the processor 114 controls the second master RF generator, the second slave RF generator, and the fourth slave RF generator in the same manner that the master RF generator system 102, the slave RF generator system 118, and the slave RF generator system 108 are controlled. The second master RF generator also controls each of the second and fourth slave RF generators in the same manner as the master RF generator system 102 controls the slave RF generator system 118 and the slave RF generator system 108, respectively.

[0054] In one embodiment, the terms causing and achieving are used interchangeably herein. Also, in this embodiment, the terms causing and achieving are used interchangeably herein.

[0055] FIG. 2A is one embodiment of a graph 200 for illustrating a plot of voltage versus time t associated with a lower electrode of a substrate support SS and voltage versus time t associated with an upper electrode UE. The voltage associated with the lower electrode is plotted as parameter signal PSa on a first y-axis and measured in kilovolts (kV) by a V1 sensor (FIG. 1), and the voltage associated with the upper electrode is plotted as parameter signal PSb on a second y-axis and measured in kV by a V2 sensor (FIG. 1). Parameter signal PSa is an example of parameter signal PS1 (FIG. 1), and parameter signal PSb is an example of parameter signal PS2 (FIG. 1). Time t is plotted on the x-axis and is measured in seconds and includes progressively occurring times t0, t1, t2, t3, t4, t5, and t6. Parameter signal PSa is shown as a solid curve, and parameter signal PSb is shown as a dotted curve. Additionally, graph 200 includes a plot of the voltage at a plasma sheath (FIG. 1), such as bottom plasma sheath 146 or top plasma sheath 144 or a combination thereof. The voltage at the plasma sheath is shown as the curve with an "x".

[0056] At location A on the plot of parameter signal PSa, the bottom plasma sheath (WS) 146 has a minimum amount of thickness when parameter signal PSa has a minimum value (WS represents wafer sheath or plasma sheath). As an example, parameter signal PSa has a minimum value when RF signal 134 provided by master RFG system 102 has a minimum value. Parameter signal PSa has a minimum value at time t0 during cycle 1 of the clock signal. Cycle 1 spans from time t0 to time t6, and cycle 2 of the clock signal is repeated after time t6. Cycle 2 spans from time t6 to time t12 at time t. The clock signal is generated by a clock source such as a digital clock signal generator or an electronic oscillator. For example, the clock signal is generated by a clock source of host computer 112 (FIG. 1). As another example, the clock signal is generated by processor 114 (FIG. 1). Location A corresponds to time t0.

[0057] As the voltage of parameter signal PSa increases from a minimum value to an intermediate value at location B on the plot of parameter signal PSa, the bottom plasma sheath 146 expands. As an example, when the RF signal 134 provided by the master RFG system 102 has an intermediate value, the parameter signal PSa has an intermediate value. The parameter signal PSa has an intermediate value during a period from time t0 to time t1, where the period and time t1 occur during cycle 1 of the clock signal. Time t1 occurs after time t0. During the period from time t0 to t1, as the bottom plasma sheath 146 expands, electrons in the bottom plasma sheath 146 gain energy, and as a result of the increased energy, ionization increases, and with the increased ionization, positive ions are generated. With the increased ionization, the energy of the positive ions in the bottom plasma sheath 146 increases, and the energy of the fast neutral atoms in the bottom plasma sheath 146 increases.

[0058] Furthermore, the voltage of the parameter signal PSa further increases from the intermediate value to a maximum value at position I on the plot of the parameter signal PSa. As an example, the parameter signal PSa has a maximum value when the RF signal 134 provided by the master RFG system 102 has a maximum value. The maximum value of the master RF signal 134 is greater than the intermediate value of the master RF signal 134, and the intermediate value is greater than the minimum value of the master RF signal 134. Also, the maximum value of the parameter signal PSa is greater than the intermediate value of the parameter signal PSa, and the intermediate value is greater than the minimum value of the parameter signal PSa. The parameter signal PSa has a maximum value at time t1.21, which occurs during cycle 1 of the clock signal. Time t1.21 occurs after time t1 and before time t2. At time t1.21, the positive ions of the bottom plasma sheath 146 that have gained energy accelerate from the bottom plasma sheath 146 toward the bottom electrode, generating secondary electrons.

[0059] It should be noted that secondary electrons are different from the bulk electrons of the plasma located between the top plasma sheath 144 and the bottom plasma sheath 146. Secondary electrons have a higher energy, measured in kiloelectronvolts (keV), than bulk electrons. For example, secondary electrons have energies in the keV range, while bulk electrons have energies in the 2-5 eV range.

[0060] As secondary electrons accelerate from the bottom plasma sheath 146 toward the lower electrode, there is a kink in the plot of parameter signal PSa at position 1. For example, there is a small amount of distortion in the plot of parameter signal PSa at position 1. Position 1 occurs in the period from time t2 to time t2.4. Time t2.4 occurs between time t2 and time t3.

[0061] As the voltage of parameter signal PSa decreases from its maximum value, the flux of secondary electrons from the lower electrode to the upper electrode UE increases. At location C on the plot of parameter signal PSb, the increased flux of secondary electrons causes a distortion in parameter signal PSb. The distortion in parameter signal PSb indicates a distortion in the voltage at the upper electrode UE. Location C spans the time period from time t1.21 to time t3.

[0062] The voltage of the parameter signal PSb decreases from time t0 to time t1.21 and increases from time t1.21 to time t3. Also, the amplitude of the RF signal 136 (FIG. 1) generated by the slave RFG system 108 (FIG. 1) decreases from time t0 to time t1.21 and increases from time t1.21 to time t3.

[0063] During the period from time t3 to time t5, the voltage of the parameter signal PSa increases. Also, during the period from time t3 to time t5, the amplitude of the RF signal 134 increases. As the amplitude of the RF signal 134 increases during the period from time t3 to time t5, the flux of secondary electrons flowing from the upper electrode UE to the lower electrode increases. The secondary electrons penetrate the upper plasma sheath 144 (FIG. 1), flow through the plasma from the upper plasma sheath 144 to the bottom plasma sheath 146, and penetrate the bottom plasma sheath 146 to process the substrate S (FIG. 1). At time t5, the voltage of the parameter signal PS1 becomes maximum. Also, at time t5, the amplitude of the RF signal 134 becomes maximum. For example, the amplitude of the RF signal 134 and the voltage of the parameter signal PS1 become maximum for the second time at time t5 during cycle 1. In this example, the amplitude of the RF signal 134 and the voltage of the parameter signal PS1 become maximum for the first time at time t1.21 during cycle 1. Furthermore, position II on parameter signal PSa occurs at time t4.7, which occurs between times t4 and t5, during cycle 1 of the clock signal. At position II, the flux of secondary electrons flowing from the upper electrode UE to the lower electrode is at a maximum.

[0064] As shown in the plot of plasma sheath voltage, the plasma sheath voltage tracks or follows parameter signal PSa from time t0 until time t3.58, which occurs between times t3 and t4. The plasma sheath voltage achieves a flat plateau level from time t3.58 until time t5.7, which occurs between times t5 and t6, after which the plasma sheath voltage continues to track the variable signal parameter signal PSa. At the flat plateau level, the plasma sheath voltage is at a minimum. Thus, a peak (e.g., a maximum) in the voltage of parameter signal PSa occurs during the time period in which the plasma sheath voltage achieves the flat plateau level.

[0065] Graph 200 is used to illustrate a phase difference determination method that includes determining a phase difference between parameter signals PSa and PSb. The phase difference determination method occurs during a lab routine that occurs prior to processing another substrate. In the phase difference determination method, processor 114 receives parameter signal PSa from the V1 sensor and variable signal VS1 (FIG. 1) from the B sensor. Processor 114 determines that the voltage of parameter signal PSa is at a maximum value for the first time at time t1.21 during cycle 1 of the clock signal. For example, processor 114 determines that the voltage of parameter signal PSa achieves a maximum value for the first time after time t0, when the voltage of parameter signal PSa is at a minimum. In this example, the voltage of parameter signal PSa achieves another maximum value a second time at time t5, after time t0. To illustrate, processor 114 determines that the value of parameter signal PSa received at time t1.21 is the maximum among all values ​​of parameter signal PSa received from voltage sensor VS1. In this example, values ​​of parameter signal PSa are received during a period from time t0 to t3. The processor 114 stores the time t1.21 in the memory device 116 .

[0066] Further, the processor 114 receives the variable signal VS1 from the B sensor. From the variable signal VS1, the processor 114 determines whether the flux of secondary electrons reaches a maximum value for a second time during cycle 1 of the clock signal, and further identifies the time within the period when the second time occurs. When the flux of secondary electrons reaches a maximum value for a second time during cycle 1, the second maximum flux of secondary electrons occurs during cycle 1. As an example, the processor 114 receives the variable signal VS1 from the B sensor between times t3 and t6, determines that among the values ​​of the variable signal VS1, the value of the variable signal VS1 reaches a maximum value between times t3.58 and t5.7, and further determines that the second maximum flux occurs between times t3.58 and t5.7.

[0067] As another example, the processor 114 determines from the variable signal VS1 whether the amplitude of the variable signal VS1 is substantially the same during a predetermined period. Illustratively, the processor 114 determines from the variable signal VS1 whether the amplitude of the variable signal VS1 is within a predetermined range during a predetermined period during which the variable signal VS1 is received from the B sensor. In this example, an example of a predetermined period is half a period of cycle 1 of the clock signal. Illustratively, the processor 114 determines from the variable signal VS1 whether the amplitude of the variable signal varies within 5% during a period from time t3.58 to t5.7 during which the variable signal VS1 is received from the B sensor. In this further example, the processor 114 determines that the amplitude varies within 5% from the amplitude of the variable signal at time t3.58. In this further example, upon determining that the amplitude varies within 5%, the processor 114 determines that the secondary electron flux is at a maximum value for a second time during cycle 1. In this further example, processor 114 identifies time t4.7, which occurs within the time period from time t3.58 to t5.7.

[0068] As yet another example, processor 114 determines from variable signal VS1 that the amplitude of variable signal VS1 is substantially the same and maximum over a given time period, and determines that the secondary electron flux is maximum for a second time at time t4.7. Note that in any of the three examples above, processor 114 identifies any time within the time period from time 3.58 to t5.7. For example, instead of time t4.7, processor 114 identifies time t4.6 or time t5 (both of which occur within the time period from time 3.58 to t5.7).

[0069] Note that the secondary electron flux is maximum for the first time during cycle 1, and the flux is maximum for the second time after the first maximum flux. For example, the processor 114 receives the variable signal VS1 between times t0 and t3, determines that the value of the variable signal VS1 is maximum at time t2.5 among the values ​​of the variable signal VS1, and further determines that the flux is maximum for the first time at time t2.5. There is a delay between times t1.21 and t2.5. The flow of secondary electrons is maximum from the bottom electrode to the top electrode at time t2.5. Time t2.5 occurs between times t2 and t3.

[0070] Processor 114 determines the time difference between the time when the secondary electron flux reaches a maximum for the second time (e.g., time t4.7) and the time when the voltage of parameter signal PSa reaches a maximum for the first time (e.g., time t1.21). Processor 114 stores the time difference in memory device 116 as phase difference Φ1.

[0071] In one embodiment, during a lab routine, instead of identifying any time within the period when the secondary electron flux is at its second maximum, the processor 114 identifies the time during cycle 1 when the secondary electron flux is at its second maximum as being equal to half the period from time t3.58 to t5.7.

[0072] In one embodiment, during a lab routine, the processor 114 determines the phase difference Φ2 as the difference between time t4.7 and time t2.5. During the time period from time t0 to t4, the processor 114 receives the variable signal VS1 from the B sensor and determines that the amplitude of the variable signal VS1 is maximum for the first time at time t2.5. For example, the processor 114 compares all values ​​of the variable signal VS1 received during the time period from time t0 to t4 and determines that the amplitude of the variable signal VS1 is maximum among all values. In this example, the processor 114 further determines that the maximum amplitude is received from the B sensor at time t2.5 and determines the time t2.5 at which the flux of secondary electrons from the lower electrode to the upper electrode UE is maximum. Similarly, during the time period from time t4 to t6, the processor 114 receives the variable signal VS1 from the B sensor and determines that the amplitude of the variable signal VS1 is maximum for the second time at time t4.7. For example, the processor 114 compares all values ​​of the variable signal VS1 received during the time period from time t4 to t6 and determines that the amplitude of the variable signal VS1 is the largest of all values. In this example, the processor 114 further determines that the largest amplitude is received from the B sensor at time t4.7. Different ways of determining time t4.7 are described above. The processor 114 calculates the difference between times t4.7 and t2.5 to determine the phase difference Φ2.

[0073] FIG. 2B is an embodiment of a graph 250 to illustrate a plot of voltage versus time t associated with the lower electrode of the substrate support SS and voltage versus time t associated with the upper electrode UE. The voltage associated with the lower electrode is plotted as parameter signal PSc on a first y-axis and measured in kV by the V1 sensor (FIG. 1), and the voltage associated with the upper electrode is plotted as parameter signal PSd on a second y-axis and measured in kV by the V2 sensor (FIG. 1). The parameter signal PSc is an example of parameter signal PS1 (FIG. 1), and the parameter signal PSd is an example of parameter signal PS2 (FIG. 1). Time t is plotted on the x-axis and measured in seconds. The time period shown in FIG. 2B spans cycle 1 of the clock signal. The parameter signal PSc is shown as a dark curve, and the parameter signal PSd is shown as a light curve. Additionally, the graph 250 includes a plot of a variable signal VSa measured by the B sensor (FIG. 1). The variable signal VSa is illustrated as a plurality of distortions and is an example of the variable signal VS1 (FIG. 1).

[0074] A kink 252, such as a distortion or disturbance, occurs in the plot of the parameter signal PSc. The kink 252 occurs during a period during cycle 1 of the clock signal when the amount of distortion 254 of the variable signal VSa exceeds a predetermined range PR1 for the first time. An example of the predetermined range PR1 is a range ranging from -15% to 15% from a statistical value (such as an average or median) generated from the value of the variable signal VSa during cycle 1. The processor 114 (FIG. 1) determines the statistical value from the value of the variable signal VSa received from the B sensor during cycle 1. The predetermined range PR1 is also stored in the memory device 116. The processor 114 determines that the value of the variable signal VSa exceeds the predetermined range PR1 for the first time during cycle 1. The amount of distortion 254 of the variable signal VSa occurs for the first time during cycle 1 due to secondary electrons flowing from the lower electrode to the upper electrode UE (FIG. 1). The first time the amount of distortion 254 is generated in the variable signal VSa is the first time the distortion 254 occurs in the variable signal VSa or the first time interval occurs. The location of kink 252 is an example of location 1 of graph 200 (FIG. 2A).

[0075] Additionally, the amount of distortion 256 in the variable signal VSa exceeds the predetermined range PR1 a second time during cycle 1 of the clock signal. The processor 114 determines that the value of the variable signal VSa exceeds the predetermined range PR1 a second time during cycle 1. The amount of distortion 256 in the variable signal VSa is generated a second time during cycle 1 by secondary electrons flowing from the upper electrode UE to the lower electrode. When the amount of distortion 256 is generated a second time in the variable signal VSa, the distortion 256 occurs a second time in the variable signal VSa or a second time interval occurs.

[0076] The processor 114 calculates the time difference between the occurrence of the distortion 256 and the occurrence of the distortion 254 to determine the phase difference Φ2. For example, the processor 114 identifies a first time within the time interval at which the distortion 256 is measured by the B sensor and received by the processor 114, and further identifies a second time within the time interval at which the distortion 254 is measured by the B sensor and received by the processor 114. In this example, the processor 114 calculates the difference between the first time and the second time to determine the phase difference Φ2.

[0077] Note that when the voltage of the upper plasma sheath 144 (FIG. 1) is low, secondary electrons from the upper electrode UE cannot penetrate the bottom plasma sheath 146, and distortion 256 does not occur. Thus, distortion 256 occurs when the voltage of the upper plasma sheath 144 is high, and the phase of the upper plasma sheath 144 is aligned with the phase of the low voltage of the bottom plasma sheath 146 such that secondary electrons generated from the upper electrode UE penetrate the bottom plasma sheath 146.

[0078] 3 is a diagram of an embodiment of a system 300 to illustrate application of a phase difference Φ (such as a phase difference Φ1 or a phase difference Φ2) determined during a lab routine. The phase difference Φ determined during a lab routine is applied during processing of a substrate SU. An example of a substrate SU is a semiconductor wafer. To illustrate, the substrate S is not a dummy wafer.

[0079] System 300 is structurally the same as system 100 (FIG. 1), except that system 300 does not include the V1, V2 and B sensors. In addition, substrate SU is placed on the top surface of substrate support SS instead of substrate S.

[0080] The processor 114 provides a recipe signal 303 to the master RF generator system 102, a recipe signal 305 to the slave RF generator system 108, and another recipe signal 307 to the slave RF generator system 118. The recipe signal 303 is the same as the recipe signal 103 (FIG. 1), except that the recipe signal 303 includes the phase of the RF signal 302 generated by the master RFG system 102. The phase of the RF signal 302 included in the recipe signal 303 differs from the phase of the RF signal 304 generated by the slave RFG system 108 by a phase difference Φ. For example, the phase difference achieved between the phase of the RF signal 302 and the phase of the RF signal 304 is equal to Φ. To illustrate, the phase of the RF signal 302 lags the phase of the RF signal 304 by the phase difference Φ, or the phase of the RF signal 304 leads the phase of the RF signal 302 by the phase difference Φ. Upon receiving the recipe signal 303 from the processor 114 , the master RF generator system 102 provides the frequencies indicated in the recipe signal 303 to each of the slave RF generator systems 108 and 118 .

[0081] The recipe signal 303 provided to the master RF generator system 102 includes the power level, phase, pulse frequency, and frequency of the RF signal 302 generated by the master RF generator system 102. Similarly, the recipe signal 305 provided to the slave RF generator system 108 includes the power level and phase of the RF signal 304 generated by the slave RF generator system 108, and the recipe signal 307 provided to the slave RF generator system 118 includes the power level of the RF signal 306 generated by the slave RF generator system 118.

[0082] Upon receiving the recipe signal 303 from the master RF generator system 102, the slave RF generator system 108 identifies the frequency indicated in the recipe signal 303 and determines the frequency of the RF signal 304 to be generated by the slave RF generator system 108 in the same manner as the frequency of the RF signal 136 (FIG. 1) is determined from the frequency of the RF signal 134 (FIG. 1).

[0083] Additionally, upon receiving the recipe signal 303 from the master RF generator system 102, the slave RF generator system 108 identifies the pulse frequency indicated in the recipe signal 303 and determines the pulse frequency of the RF signal 304 generated by the slave RF generator system 108. The pulse frequency of the RF signal 304 is determined in the same manner that the pulse frequency of the RF signal 136 is determined from the pulse frequency of the RF signal 134.

[0084] Upon receiving the recipe signal 303 from the master RF generator system 102, the slave RF generator system 118 identifies the frequency and phase indicated in the recipe signal and determines the frequency and phase of the RF signal 306 generated by the slave RF generator system 118. The frequency and phase of the RF signal 306 are determined in the same manner that the frequency and phase of the RF signal 138 (FIG. 1) are determined from the frequency and phase of the RF signal 134.

[0085] Additionally, upon receiving the recipe signal 303 from the master RF generator system 102, the slave RF generator system 118 identifies the pulse frequency indicated in the recipe signal 303 and determines the pulse frequency of the RF signal 306 generated by the slave RF generator system 118. The pulse frequency of the RF signal 306 is determined in the same manner that the pulse frequency of the RF signal 138 is determined from the pulse frequency of the RF signal 134.

[0086] Additionally, the processor 114 transmits a trigger signal to each of the master RF generator system 102, the slave RF generator system 108, and the slave RF generator system 118. Upon receiving the trigger signal, the master RF generator system 102 generates an RF signal 302 having a frequency, phase, pulse frequency, and power level indicated in the recipe signal 303 received from the processor 114, and transmits the RF signal 302 to an input of the matcher 104 via the RF cable 122. Similarly, upon receiving the trigger signal, the slave RF generator system 108 generates an RF signal 304 having a power level and phase indicated in the recipe signal 305 received from the processor 114 based on the frequency and pulse frequency identified from the recipe signal 303 received from the master RF generator system 102, and transmits the RF signal 304 to an input of the matcher 110 via the RF cable 126.

[0087] It should be noted that after receiving the trigger signal, the master RF generator system 102 generates the RF signal 302 to achieve a phase difference Φ with respect to the RF signal 304. For example, the master RF generator system 102 generates the RF signal 302 after an amount of time equal to the phase difference Φ has elapsed after the RF signal 304 is generated or after the trigger signal is received. To illustrate, the DSP of the master RF generator system 102 transmits a master control signal to a master RF power supply, such as an RF oscillator, after an amount of time equal to the phase difference Φ. In this example, the master RF power supply is coupled to the DSP of the master RF generator system 102 and located within the master RF generator system 102. In this example, the DSP of the slave RF generator system 108 transmits a slave control signal to a slave RF power supply, such as an RF oscillator, before the DSP of the master RF generator system 102 transmits the master control signal to the master RF power supply. In this example, the slave RF power supply is coupled to the DSP of the slave RF generator system 108 and located within the slave RF generator system 108. Further, in this example, upon receiving the master control signal, the master RF power supply generates an RF signal 302, and upon receiving the slave control signal, the slave RF power supply generates an RF signal 304. Also, upon receiving the trigger signal, the slave RF generator system 118 generates an RF signal 306 having a power level indicated in the recipe signal 307 received from the processor 114 based on the frequency, pulse frequency, and phase identified in the recipe signal 303 received from the master RF generator system 102, and transmits the RF signal 306 via the RF cable 130 to the input of the matcher 120.

[0088] An RF signal 302 is received at the input of the matcher 104, which matches the impedance of a load coupled to the output of the matcher 104 with the impedance of a source coupled to the input of the matcher 104. The impedance is matched to modify the impedance of the RF signal 302, and a modified RF signal 308 is provided at the output of the matcher 104. The modified RF signal 308 is provided to the bottom electrode of the substrate support SS via the RF transmission line 124.

[0089] Similarly, when an RF signal 304 is received at the input of the matcher 110, the matcher 110 matches the impedance of a load coupled to the output of the matcher 110 with the impedance of a source coupled to the input of the matcher 110. The impedance is matched to modify the impedance of the RF signal 304, and a modified RF signal 310 is provided at the output of the matcher 110. The modified RF signal 310 is provided to the upper electrode UE via the RF transmission line 128.

[0090] Also, when an RF signal 306 is received at the input of the matcher 120, the matcher 120 matches the impedance of a load coupled to the output of the matcher 120 with the impedance of a source coupled to the input of the matcher 120. The impedance is matched to modify the impedance of the RF signal 306, and a modified RF signal 312 is provided at the output of the matcher 120. The modified RF signal 312 is provided to the edge ring ER via the RF transmission line 132.

[0091] A plasma is struck or maintained in the plasma chamber 106 when one or more process gases are supplied to the gap between the substrate support SS and the upper electrode UE in the plasma chamber 106 in addition to the modified RF signals 308, 310, and 312. The plasma generated in the plasma chamber 106 is used to process the substrate SU. For example, the plasma is used to deposit material on the top surface of the substrate SU, or to etch the substrate SU, or to clean the substrate SU. When the phase difference between the phases of the RF signals 306 and 304 is Φ, the rate of processing the substrate SU (such as the etching rate, deposition rate, or cleaning rate) increases compared to when the phase difference is not Φ. The rate increases when the flux of secondary electrons flowing from the upper electrode UE to the lower electrode is at a maximum. The increased flux reduces the chance of transition wiggling, which will be described later, and increases the rate of processing.

[0092] In an embodiment, the recipe signal 303 does not include the phase of the RF signal 302, and the recipe signal 305 does not include the phase of the RF signal 304. More precisely, the processor 114 transmits a master trigger signal to the master RF generator system 102 and a slave trigger signal to the slave RF generator system 108 to achieve the phase difference Φ. For example, the processor 114 transmits the master trigger signal to the master RF generator system 102 after a period of time equal to the phase difference Φ after transmitting the slave trigger signal to the slave RF generator system 108. To illustrate, the processor 114 transmits the slave trigger signal to the slave RF generator system 108 at a first time. In this example, after transmitting the slave trigger signal, the processor 114 waits a period of time equal to the phase difference Φ and transmits the master trigger signal to the master RF generator system 102 at a second time. Furthermore, in this example, upon receiving the master trigger signal, the master RF generator system 102 generates the RF signal 302. Also in this example, upon receiving the slave trigger signal, the slave RF generator system 108 generates an RF signal 304 .

[0093] In an embodiment, in a power control mode, the power levels of the RF signals 302, 304, and 306 are controlled. In the power control mode, the power level of the RF signal 302, the power level of the RF signal 304, and the power level of the RF signal 306 are controlled by the processor 114. Based on the phase difference Φ and the power levels of the RF signals 302, 304, and 306, an etch profile and an etch rate of an etch feature of the substrate SU are controlled.

[0094] In one embodiment, instead of the power levels, the voltage levels of the RF signals are controlled in a voltage control mode, in which the voltage levels of the RF signal 302, the voltage level of the RF signal 304, and the voltage level of the RF signal 306 are controlled by the processor 114. Based on the phase difference Φ and the voltage levels of the RF signals 302, 304, and 306, an etching profile and an etching rate of an etching feature of the substrate SU are controlled.

[0095] 4 is an illustration of one embodiment of a graph 400 to illustrate a clock signal 402. In the graph 400, the logic levels of the clock signal 402 are plotted versus time t. As shown, the clock signal 402 pulses from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t3. The clock signal 402 pulses from logic level 1 to logic level 0 at time t3 and remains at logic level 0 from time t3 to time t6. Cycle 1 of the clock signal 402 begins at time t0 and ends at time t6. Cycle 2 of the clock signal 402 begins at time t6 and ends at time t12.

[0096] FIG. 5 is an embodiment of a graph 500 to illustrate a pulsed RF signal 502. In the graph 500, a parameter of the RF signal 502 is plotted versus time t. The RF signal 502 is an example of an RF signal 136 or 304 (FIGS. 1 and 3) generated by the slave RF generator system 108 (FIG. 1). The RF signal 502 has an envelope 504, which is pulsed with a duty cycle. An example of the envelope 504 is a peak-to-peak amplitude or a zero-to-peak amplitude. The envelope 504 transitions from a parameter level P0 to parameter levels P1 and -P1 at time t0 and remains at parameter levels P1 and -P1 from time t0 to time t18. The parameter level P1 is greater than the parameter level P0. An example of the parameter is voltage or power.

[0097] Envelope 504 transitions from parameter levels P1 and -P1 to parameter level P0 at time t18 and remains at parameter level P0 from time t18 to time t36. Parameter levels P1 and -P1, and P0 are repeated again from time t36 to time t72. Envelope 504 forms a pulse between times t0 and t36 and another pulse between times t36 and t72. Thus, envelope 504 has a 50% duty cycle and represents a digital signal or a digital pulse signal.

[0098] The duty cycle of the envelope provides a pulse frequency of the envelope, e.g., the number of pulses of the envelope per second, which is less than the frequency of the RF signal that has the envelope.

[0099] In one embodiment, instead of being pulsed, a continuous wave (CW) RF signal is generated by the slave RF generator system 108 (FIG. 1).

[0100] In one embodiment, the envelope 504 has a duty cycle different from 50%, such as 25% or 60%.

[0101] In one embodiment, the phase difference Φ is applied during a subsequent cycle of the clock signal 402 (FIG. 4). For example, during cycle 2 or cycle 3 or cycle 4 of the clock signal 402, the processor 114 controls the phase of the RF signal 134 or the phase of the RF signal 136 (FIG. 1) or a combination thereof to achieve the phase difference Φ between the phases. In this example, either cycle 2, 3 or 4 follows cycle 1 of the clock signal 402. Also, in this example, cycle 2 is consecutive to cycle 1, cycle 3 is consecutive to cycle 2, and cycle 4 is consecutive to cycle 3. The phases of the RF signals 134 and 136 are controlled in the same manner that the phases of the RF signals 302 and 304 are controlled.

[0102] FIG. 6 is an embodiment of a graph 600 to illustrate a pulsed RF signal 602. In the graph 600, a parameter of the RF signal 602 is plotted versus time t. The RF signal 602 is an example of an RF signal 134 or 302 (FIGS. 1 and 3) generated by the master RF generator system 102. The RF signal 602 has an envelope 604, which is pulsed with a duty cycle. An example of the envelope 604 is a peak-to-peak amplitude or a zero-to-peak amplitude. The envelope 604 transitions from a parameter level P0 to parameter levels Pa and -Pa at time t0 and remains at parameter levels Pa and -Pa from time t0 to time t18. The parameter level Pa is greater than the parameter level P0.

[0103] The envelope 604 transitions from parameter levels Pa and -Pa to parameter level P0 at time t18 and remains at parameter level P0 from time t18 to time t36. The parameter levels Pa and -Pa, and P0 are repeated again from time t36 to time t72. The envelope 604 forms a pulse between times t0 and t36 and another pulse between times t36 and t72. Thus, the envelope 604 has a 50% duty cycle and represents a digital signal or a digital pulse signal.

[0104] In one embodiment, the envelope 604 has a duty cycle different from 50%, such as 30% or 70%.

[0105] In an embodiment, the RF signal 138 or 306 (FIGS. 1 and 3) generated by the slave RF generator system 118 is similar to the RF signal 602. For example, the RF signal 138 or 306 has the same frequency as the RF signal 602 but has a different parameter level (such as a higher or lower parameter level) than the RF signal 602. As another example, the RF signal 138 or 306 has the same frequency and the same parameter level as the RF signal 602.

[0106] 7A is a top-down view of one embodiment of a stack 700 to illustrate that the sidewalls 702 of the stack 700 are etched when the phase difference is not Φ. The stack 700 includes another stack of oxide (O) and nitride (N) layers, with a silicon dioxide (SiO 2 ) layer. As shown, a cavity 704 is formed in the sidewall 702, representing the transition wiggle that occurs due to not using a phase difference Φ. As an example, the transition wiggle represents the depth of the cavity 704 from the flat surface of the sidewall 702.

[0107] Figure 7B is a side view of one embodiment of stack 750, which is an example of stack 700 (Figure 7A). Stack 750 includes a silicon substrate overlaid with an ONON layer, which is overlaid with a silicon dioxide layer. A cavity 752 is shown in Figure 7B. Cavity 752 represents a wiggling transition.

[0108] 8 is one embodiment of a graph 800 to illustrate the reduction of transition wiggling when a phase difference Φ is applied. In the graph 800, the transition wiggling in nanometers (nm) is plotted against the configuration of the upper electrode UE. When the phase difference Φ is not applied, the amount of transition wiggling 802 is large. For example, when the upper electrode UE is coupled to a ground (GND) potential, a transition wiggling of amount 802 occurs. The amount 802 is greater than another amount of transition wiggling 804 when a phase difference Φ is applied to the upper electrode UE.

[0109] The embodiments described herein may be practiced with a variety of computer system configurations including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments described herein may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0110] In some embodiments, the controller is part of a system that may be part of the examples above. The system includes semiconductor processing equipment such as one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). The system is integrated with electronics to control the operation of the system before, during, and after processing of the semiconductor wafer or substrate. This electronics is referred to as a "controller" that may control various parts or sub-parts of the system. The controller is programmed to control any of the processes disclosed herein, such as delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, transfer of wafers into and out of tools and other transfer tools and / or load locks that connect or interface with the system, depending on the processing requirements and / or type of system.

[0111] Broadly speaking, in various embodiments, a controller is defined as electronic equipment having various integrated circuits, logic, memory, and / or software that, for example, receives instructions, issues instructions, controls operations, enables cleaning operations, enables end-point measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, DSPs, chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various personalizations (or program files) that define operational parameters for performing processes on or for semiconductor wafers. The operational parameters, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps in the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer types.

[0112] The controller, in some embodiments, is part of or coupled to a computer that is integrated into, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a host computer system in the "cloud" or at a fab that allows remote access of wafer processing. By allowing remote access to the system, the controller may monitor the current progress of a manufacturing operation, review the history of past manufacturing operations, review trends or performance criteria from multiple manufacturing operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process.

[0113] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system through a computer network, including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of settings for processing the wafer. It should be understood that the settings are specific to the type of process to be performed on the wafer and the type of tool the controller interfaces with or controls. Thus, as described above, the controller is distributed, such as by including one or more separate controllers that are networked together and work toward a common purpose, such as fulfilling the processes described herein. Examples of controllers distributed for such purposes include one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) combined to control the process in the chamber.

[0114] Without being limited thereto, in various embodiments, the plasma systems described herein include plasma etch chambers, deposition chambers, spin rinse chambers, metal plating chambers, clean chambers, bevel edge etch chambers, physical vapor deposition (PVD) chambers, chemical vapor deposition (CVD) chambers, atomic layer deposition (ALD) chambers, atomic layer etch (ALE) chambers, ion implantation chambers, track chambers, or any other semiconductor processing chambers associated with or used in the manufacturing and / or production of semiconductor wafers.

[0115] It is further noted that while the above operations are described with reference to parallel plate plasma chambers (e.g., capacitively coupled plasma chambers), in some embodiments, the above operations apply to other types of plasma chambers (e.g., plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma (TCP) reactors, conductor tools, dielectric tools, electron cyclotron resonance (ECR) reactors, etc.). For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor in an ICP plasma chamber.

[0116] As described above, depending on the process operations being performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool parts, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, other controllers, or tools used in material transport to bring containers of wafers into and out of tool locations and / or load ports within a semiconductor production factory.

[0117] In view of the above embodiments, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations manipulate physical quantities.

[0118] Some embodiments also relate to a hardware unit or apparatus for performing these operations. An apparatus is specially configured for a special purpose computer. When defined as a special purpose computer, the computer performs other processes, program execution, or routines that are not part of the special purpose while remaining operable for the special purpose.

[0119] In some embodiments, the operations described herein are performed by a computer selectively activated or configured by one or more computer programs stored in a computer memory or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, for example, a cloud of computing resources.

[0120] One or more embodiments described herein may also be manufactured as computer readable code on a non-transitory computer readable medium. A non-transitory computer readable medium is any data storage hardware unit (e.g., memory device, etc.) that stores data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROM (CD-ROM), recordable CD (CD-R), rewriteable CD (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer readable medium includes a computer readable tangible medium distributed over network-coupled computer systems such that the computer readable code is stored and executed in a distributed manner.

[0121] Although some of the method operations described above have been presented in a particular order, it should be understood that in various embodiments, other housekeeping operations are performed between method operations, method operations are coordinated to occur at slightly different times, are distributed in a system that allows method operations to occur at various intervals, or are performed in an order different from that described above.

[0122] It should further be noted that in some embodiments, one or more features from any of the above-described embodiments may be combined with one or more features of any of the other embodiments without departing from the scope of the various embodiments described in this disclosure.

[0123] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Thus, the present embodiments are to be considered as illustrative and not restrictive, and the present embodiments are not to be limited to the details given herein, but may be modified within the scope of the appended claims and their equivalents.

Claims

1. 1. A method for increasing a rate at which a substrate is processed, comprising: receiving a parameter signal from a first sensor when a first radio frequency (RF) signal is provided to the substrate support and a second RF signal is provided to the upper electrode; determining a first time during a cycle of a clock signal at which a value of the parameter is greatest based on the parameter signal; receiving a variable signal from a second sensor; determining a second time during the cycle and after the first time when a first amount of secondary electron flux from the upper electrode to the substrate support is maximum based on the variable signal; and determining a phase difference between the first time and the second time; creating a phase difference between a phase of a third RF signal provided to the upper electrode and a phase of a fourth RF signal provided to the substrate support to increase a rate at which the substrate is processed.

2. 2. The method of claim 1, wherein the generating a phase difference comprises: providing a first trigger signal to a bias RF generator at a fourth time to generate the fourth RF signal; generating the third RF signal at a fifth time by providing a second trigger signal to a source RF generator, wherein a difference between the fourth time and the fifth time is equal to the phase difference.

3. 2. The method of claim 1, wherein the parameter is voltage, the first sensor is a voltage sensor coupled between an impedance matcher and the substrate support, and the second sensor is a magnetic field sensor.

4. 10. The method of claim 1, further comprising a third time during which a second amount of secondary electron flux is greatest, the third time occurring during the cycle and between the first time and the second time.

5. 2. The method of claim 1, wherein the inducing of the phase difference is performed during processing of the substrate, and wherein receiving the parameter signal, determining the first time, receiving the variable signal, determining the second time, and determining the phase difference are performed during a lab routine.

6. 2. The method of claim 1, wherein the creating a phase difference occurs during a subsequent cycle of the clock signal.

7. 2. The method of claim 1, wherein determining the first time is based on the clock signal, determining the second time is based on the clock signal, the second RF signal has a frequency generated based on a frequency of the first RF signal, and the third RF signal has a frequency generated based on a frequency of the fourth RF signal.

8. The method of claim 1 , wherein the variable signal is generated based on magnetic flux.

9. 1. A method of increasing a rate at which a substrate is processed to produce an etching profile for said substrate, comprising: determining a first time at which a first amount of secondary electron flux from the substrate support to the upper electrode is maximum, the first time occurring within a first clock cycle during which the substrate support receives a first radio frequency (RF) signal and the upper electrode receives a second RF signal; determining a second time at which a second amount of secondary electron flux from the upper electrode to the substrate support is maximum, the second time occurring within the first clock cycle; determining a phase difference between the second time and the first time; creating a phase difference between a phase of a third RF signal provided to the upper electrode and a phase of a fourth RF signal provided to the substrate support to increase a rate at which the substrate is processed.

10. 10. The method of claim 9, wherein the generating a phase difference comprises: providing a first trigger signal to a bias RF generator at a fourth time to generate the fourth RF signal; generating the third RF signal at a fifth time by providing a second trigger signal to a source RF generator, wherein a difference between the fourth time and the fifth time is equal to the phase difference.

11. 10. The method of claim 9, further comprising receiving measurement signals representative of the first amount and the second amount of flux from a magnetic field sensor.

12. 10. The method of claim 9, wherein the second time occurs after the first time.

13. 10. The method of claim 9, wherein the inducing of the phase difference is performed during processing of the substrate, and wherein determining the first time, determining the second time, and determining the phase difference are performed during a lab routine.

14. 10. The method of claim 9, wherein the effecting of the phase difference is performed during a second clock cycle of a clock signal, the second clock cycle following the first clock cycle.

15. A controller, the controller comprising:

1. A processor, comprising: receiving a parameter signal from the first sensor when a first radio frequency (RF) signal is provided to the substrate support and a second RF signal is provided to the upper electrode; determining a first time during a cycle of a clock signal at which a value of the parameter is greatest based on the parameter signal; receiving a variable signal from a second sensor; determining a second time during the cycle and after the first time at which a first amount of secondary electron flux from the upper electrode to the substrate support is maximum based on the variable signal; determining a phase difference between the first time and the second time; a processor configured to create a phase difference between a phase of a third RF signal provided to the upper electrode and a phase of a fourth RF signal provided to the substrate support to increase a rate at which the substrate is processed; and a memory device coupled to the processor; The controller containing the

16. 16. The controller of claim 15, wherein to generate the phase difference, the processor: providing a first trigger signal to a bias RF generator at a fourth time to generate the fourth RF signal; a controller configured to generate the third RF signal at a fifth time by providing a second trigger signal to a source RF generator, wherein a difference between the fourth time and the fifth time is equal to the phase difference.

17. 16. The controller of claim 15, wherein the parameter is voltage, the first sensor is a voltage sensor coupled between an impedance matcher and the substrate support, and the second sensor is a magnetic field sensor.

18. 16. The controller of claim 15, wherein the processor is configured to determine a third time at which a second amount of secondary electron flux is greatest, the third time occurring during the cycle and between the first time and the second time.

19. 16. The controller of claim 15, wherein the phase difference occurs during processing of the substrate, and wherein the parameter signal is received, the first time is determined, the variable signal is received, the second time is determined, and the phase difference is determined during a lab routine.

20. 16. The controller of claim 15, wherein the phase difference occurs during a subsequent cycle of the clock signal.

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