Thermal Bypass for Stacked Dies

Abstract

The disclosed technology relates to a microelectronic device capable of efficiently dissipating heat. In some aspects, the microelectronic device includes a first semiconductor element and at least one second semiconductor element disposed on the first semiconductor element. The microelectronic device may further include a thermal block disposed on the first semiconductor element adjacent to the at least one second semiconductor element. The thermal block may include a heat transfer path for transferring heat from the first semiconductor element to a heat sink disposed on the thermal block. In some embodiments, the thermal conductivity (CTE) of the thermal block is less than 10 μm / m° C. In some embodiments, the thermal conductivity of the thermal block is less than 150 Wm at room temperature. -1 K -1 Higher than.

Description

[Technical field]

[0001] The technical field relates to dissipating heat in microelectronic devices, particularly in microelectronic devices made with direct bonded components.

[0002] [Citation to Related Applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 264,214, filed on November 17, 2021 (title: THERMAL BYPASS FOR STACKED DIES), which is incorporated by reference in its entirety. [Background technology]

[0003] The miniaturization and high density integration of electronic components increases the heat flux density in microelectronics. If the heat generated during the operation of microelectronics is not dissipated, the microelectronics may stop working or burn out. In particular, heat dissipation is a serious challenge in high power devices and / or stacked devices. Summary of the Invention

[0004] According to one aspect of the invention, there is provided a microelectronic device comprising: A first semiconductor element; at least one second semiconductor element disposed on the first semiconductor element; a thermal block disposed on the first semiconductor device adjacent to at least one second semiconductor device, the thermal block having a heat transfer path for transferring heat from the first semiconductor device to a heat sink disposed on the thermal block; The coefficient of thermal expansion (CTE) of the thermal block is less than 10 μm / m°C. The thermal conductivity of the thermal block is 150Wm at room temperature. -1 K -1 In accordance with the present invention, a microelectronic device characterized by a thickness of 100 nm or more is suitable.

[0005] According to another aspect of the invention, there is provided a method of fabricating a microelectronic device, the method comprising the steps of: Providing a first semiconductor device; bonding a second semiconductor device and a thermal block to the first semiconductor device; attaching a heat sink to the thermal block, the thermal block providing a thermal path between the first semiconductor device and the heat sink; The coefficient of thermal expansion (CTE) of the thermal block is less than 10 μm / m°C. The thermal conductivity of the thermal block is 150Wm at room temperature. -1 K -1 In accordance with the present invention, a method is provided in which the

[0006] According to another aspect of the invention, there is provided a microelectronic device comprising: a first integrated device die; a second integrated device die disposed on the first semiconductor device; a heat block directly bonded to a first integrated device die without adhesive; and a heat sink attached to at least the heat block.

[0007] According to yet another aspect of the present invention, there is provided a microelectronic device comprising: a first integrated device die; a second integrated device die disposed on the first integrated device die; a heat block disposed on the first integrated device die; A heat sink attached to at least the heat block, A microelectronic device is provided in which the heat flux through the heat block is greater than the heat flux through the second integrated device die during operation of the microelectronic device.

[0008] According to yet another aspect of the invention, there is provided a method of operating a microelectronic device having a first integrated device die and a second integrated device die disposed on the first integrated device die, the method comprising the steps of: directing a first heat flux through a heat block disposed on a first integrated device die and a second heat flux through a second integrated device die; The method is characterized in that the first heat flux through the heat block is greater than the second heat flux through the second integrated device die.

[0009] Specific embodiments will now be described with reference to the following drawings, which are provided by way of illustration and not by way of limitation. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional view of an exemplary microelectronic system according to some embodiments of the disclosed technology; [Diagram 2] FIG. 2 is a schematic plan view of the example microelectronic system shown in FIG. [Diagram 3] FIG. 2 is a schematic cross-sectional view of another exemplary microelectronic system according to some embodiments of the disclosed technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Microelectronic elements (e.g., dies / chips) can be stacked and bonded together to form a device. Dissipating heat in a device with chip stacking is difficult, especially as the chips become thinner. The use of chip attachment techniques, such as adhesive bonding, can result in less efficient heat dissipation in the device because the adhesive can reduce heat transfer or insulate. In addition, it is difficult to achieve a particularly low temperature in a desired portion of the device. For example, when packaging a stack of dies, heat dissipation is typically aided by a heat sink at the top of the stack, but drawing heat away from the lower die is a challenge. Heat dissipation can be a serious problem, especially for high-power chips. Thus, improved techniques for dissipating heat in microelectronic devices continue to be needed.

[0012] Methods and structures are provided for redirecting the thermal path from the lower die of the stack to the upper heat dissipation structure, e.g., heat sink. For example, the microelectronic device 100 may have a thermal block / heat block 137 that can redirect the flow of heat within the device, thus reducing the flow of heat through one chip (e.g., 101 and 102) within the device or through a particular region of a chip within the device. In some embodiments, the microelectronic device 100 may have one thermal block. In other embodiments, the microelectronic device 100 may have multiple thermal blocks spaced apart from one another. For example, the thermal block 137 may have a thermal path that transfers heat from the bottom semiconductor element 1000 to the heat sink 131 located on top of the thermal block 137. Such a thermal block 137 (or thermal bypass) occupies a small footprint within the device. In some embodiments, the thermal block 137 may be free of active circuitry (e.g., no transistors), while in other embodiments, the thermal block may be free of passive circuitry.

[0013] In some embodiments, the thermal block 137 is directly bonded to another element in the device 100 (e.g., the bottom die 1000), thus avoiding the use of adhesives that may reduce heat transfer. The coefficient of thermal expansion (CTE) of the thermal block 137 may be selected to substantially match the CTE of the element to avoid breaking or cracking the bonded structure when temperatures increase during operation of the device 100. For example, the element to which the thermal block 137 is directly bonded (e.g., the bottom die 1000) may be made of silicon, and the thermal block material may have a CTE approximately the same as the CTE of silicon.

[0014] In some embodiments, the thermal block 137 is made of a high thermal conductivity material (e.g., a material that has a thermal conductivity higher than that of silicon or copper at least about the device operating temperature, e.g., about 0-40° C.). The thermal conductivity of the thermal block 137 may be higher than that of the adjacent chips (e.g., 101 and 102), thus redirecting and reducing the heat flow through the adjacent chips (e.g., 101 and 102) in the device 100. For example, the thermal block 137 may be a single crystal diamond block, a nanofiber block, or a nanoporous metal (e.g., tungsten (W)) filled block.

[0015] In one embodiment, the stacking system 100 may include a thermal path unit 137 attached directly (e.g., directly bonded without adhesive) to the bottom element 1000 (which may have a high temperature during operation) by direct bonding (e.g., non-conductive direct bonding) or hybrid bonding in which the non-conductive regions are directly bonded to each other and the conductive features are directly bonded to each other. The thermal path unit 137 may be located adjacent to at least one chip, e.g., the first die 101. The thermal path unit 137 may be coupled to the top heat sink 131. The thermal path unit 137 may have a CTE of less than 10 μm / m° C. (or close to the CTE of Si) and a thermal conductivity higher than that of copper (e.g., many times that of copper). Thus, the thermal flux in the stacking system 100 may be redirected, so that the thermal flux through the thermal unit 137 is greater than the thermal flux through the first die 101. Thus, a non-limiting advantage of the disclosed technology is that the majority of the heat bypasses the operating die, e.g., the first die 101 and / or the second die 102, and does not adversely affect their operation.

[0016] 1 and 2 are cross-sectional and plan views, respectively, of an exemplary microelectronic system 100 that includes stacked semiconductor elements (e.g., dies / chips) and a thermal block 137 (or thermal bypass) that connects to a heat sink 131 (e.g., a metal heat sink or a heat pipe with a fluid coolant) at the top of the stack. Heat generated by the semiconductor elements during operation may be transferred to the heat sink as shown by the arrows to dissipate the heat from the system. For example, the thermal block 137 may have a thermal conduction path that transfers heat from a bottom semiconductor element / base element 1000 to the heat sink 131 provided on top of the thermal block 137. The thermal block 137 and one or more chips (e.g., a "first die" 101, a "second die" 102, and a "third die" 103) may be attached to a base element 1000, which may be a die, a wafer, or the like. The thermal block 137 may be located adjacent to at least one chip (e.g., at least the "first die" 101), thus reducing the heat flow through the at least one chip. In other embodiments, the thermal block 137 may also be located adjacent to additional chips provided on the base element 1000. For example, the thermal block 137 may also be located adjacent to the second die 102 and / or the third die 103. In use, a method of operating the microelectronic system 100 may include directing a heat flux through the thermal block 137 provided on the base element 1000 and a heat flux through the first die 101 (or the second die 102) such that the heat flux through the thermal block 137 is greater than the heat flux through the first die 101 (or the second die 102).

[0017] In some embodiments, the thermal block 137 has a CTE that is very close to the CTE of the base element 1000. For example, the thermal block 137 may have a CTE that is close to the CTE of silicon (Si). In one example, the thermal block 137 may have a CTE that is at least about less than the CTE of copper at about the device operating temperature, or a CTE of 10 μm / m° C. or less (e.g., less than), 9 μm / m° C. or less, 8 μm / m° C. or less, or more preferably 7 μm / m° C. or less.

[0018] In some embodiments, the thermal block 137 has a higher thermal conductivity than the adjacent chip (e.g., the "first die"), thus reducing the heat flow through the adjacent chip. For example, the adjacent chip (e.g., the "first die") may include silicon, and the thermal block 137 may have a higher thermal conductivity than that of silicon. In some embodiments, the thermal block 137 has a thermal conductivity approximately the same as or higher than that of copper (e.g., about three times the thermal conductivity of copper, or about five times the thermal conductivity of copper). In some embodiments, the thermal block 137 has a thermal conductivity of approximately 1000-2000 Wm at room temperature. -1 K -1 It has a thermal conductivity of

[0019] In some embodiments, the thermal block 137 may include a diamond block (e.g., single crystal diamond) or similar material, a nanofiber block, a nanoporous metal (e.g., W) filled block, graphite, or GeSe. In some embodiments, the thermal block 137 may be made of an electrically non-conductor or semiconductor (e.g., a non-metal). In various embodiments, the thermal block 137 is made of a material that has both a low CTE at room temperature (e.g., less than 10 μm / m° C., e.g., less than 8 μm / m° C., or less than 7 μm / m° C.) and a thermal conductivity that is at least greater than the thermal conductivity of Si at approximately the device operating temperature (e.g., the thermal block may have a thermal conductivity of less than 100 W / m° C.). -1 K -1 Higher than, for example, 110Wm -1 K -1(It is preferable that the thermal conductivity is higher than that of the

[0020] In some embodiments, the thermal block 137 may be attached to the base element 1000 by direct bonding without an intervening adhesive, such as by a non-conductive direct bonding technique or a hybrid direct bonding technique. For example, the thermal block 137 may be attached using the ZIBOND® and / or DBI® process configured for room temperature atmospheric pressure direct bonding or the DBI® Ultra process configured for low temperature hybrid bonding, which are commercially available from Adeia, Inc., San Jose, Calif. In some embodiments, the thermal block 137 may be attached to the bottom chip by solder bonding or adhesive bonding. In some embodiments, the thermal block may be attached to the bottom chip by a thermally conductive material (TIM).

[0021] In some embodiments, the stacked semiconductor devices may be directly bonded to each other without an intervening adhesive. For example, the "first die" 101, the "second die" 102, and / or the "third die" 103 may be directly bonded (e.g., direct hybrid bonded) to the base device 1000. In some embodiments, the super heat sink may be directly bonded to the semiconductor device (e.g., the "first die" 101, the "second die" 102, and / or the "third die" 103) and / or the thermal block 137, or may be attached to the semiconductor device and / or the thermal block via a TIM. For example, direct bonding processes include the ZIBOND® or DBI® process configured for room temperature atmospheric pressure direct bonding or the DBI® Ultra process configured for low temperature hybrid bonding, which are commercially available from Adair, Inc. of San Jose, Calif. The direct bond may be located between the dielectrics of the bonded elements, and in some embodiments the direct bond may further include a conductive material at or near the bond interface for direct hybrid bonding. The conductive material at the bond interface may be a bond pad and / or passive electronic components formed in or on a redistribution layer (RDL) deposited on the die.

[0022] For example, a microelectronic device may include a first semiconductor element, at least one second semiconductor element disposed on the first semiconductor element, and a thermal block disposed on the first semiconductor element adjacent to the at least one second semiconductor element, the thermal block having a heat transfer path for transferring heat from the first semiconductor element to a heat sink disposed on the thermal block, the thermal block having a coefficient of thermal conductivity (CTE) of less than 10 μm / m° C., and the thermal conductivity of the thermal block being less than 150 Wm at room temperature. -1 K -1The thermal block is configured to reduce a heat flow through the at least one second semiconductor element, which may be comprised of silicon, and the thermal conductivity of the thermal block at about the device operating temperature is higher than the thermal conductivity of silicon, such that the heat flux through the thermal block is greater than the heat flux through the at least one second semiconductor element during operation of the microelectronic device.

[0023] In one embodiment, the thermal conductivity (CTE) of the thermal block is substantially the same as the CTE of the first semiconductor element. In one embodiment, the first semiconductor element is made of silicon and the thermal conductivity (CTE) of the thermal block is substantially the same as the CTE of silicon. In one embodiment, the thermal conductivity (CTE) of the thermal block is lower than the thermal conductivity of copper. In one embodiment, the thermal conductivity (CTE) of the thermal block is lower than 7 μm / m° C. In one embodiment, the thermal conductivity of the thermal block is higher than the thermal conductivity of at least one second semiconductor element. In one embodiment, the thermal conductivity of the thermal block is higher than the thermal conductivity of silicon. In one embodiment, the thermal conductivity of the thermal block is higher than 200 Wm at room temperature. -1 K -1 In one embodiment, the thermal conductivity of the thermal block is within 10% of the thermal conductivity of copper. In one embodiment, the thermal conductivity of the thermal block is at least three times the thermal conductivity of copper. In one embodiment, the thermal block is made of diamond, nanofibers, nanoporous metals, graphite, or GeSe. In one embodiment, the thermal block is made of an electrical non-conductor or semiconductor.

[0024] In one embodiment, the thermal block is direct bonded to the first semiconductor device without an intervening adhesive. In one embodiment, the interface between the thermal block and the first semiconductor device comprises a dielectric-to-dielectric (inter-dielectric) direct bond. In one embodiment, the thermal block is bonded to the first semiconductor device by solder bonding. In one embodiment, the thermal block is bonded to the first semiconductor device by adhesive bonding. In one embodiment, the thermal block is bonded to the first semiconductor device by a thermally conductive material (TIM). In one embodiment, the at least one second semiconductor device is direct bonded to the first semiconductor device without an intervening adhesive. In one embodiment, the interface between the at least one second semiconductor device and the first semiconductor device comprises a conductor-to-conductor (inter-conductor) and a dielectric-to-dielectric direct bond.

[0025] In one embodiment, the heat sink is in contact with the at least one second semiconductor device. In one embodiment, the heat sink is direct bonded to the at least one second semiconductor device without an intervening adhesive. In one embodiment, the heat sink is direct bonded to the thermal block without an intervening adhesive. In one embodiment, the first semiconductor device comprises an integrated device die. In one embodiment, the at least one second semiconductor device comprises an integrated device die. In one embodiment, the thermal block is free of active circuitry. In one embodiment, the thermal block is further free of passive circuitry.

[0026] FIG. 3 is a schematic cross-sectional view of another exemplary microelectronic system 300 that includes stacked semiconductor devices 301 (e.g., dies / chips), several thermal blocks 337, and a heat sink 331 (e.g., a metal heat sink or a heat pipe with a fluid coolant) located at the top of the stack. The thermal blocks 337 can be arranged in a variety of ways. In some embodiments, the thermal blocks 337 can extend from the bottom device 3000 to the top die that is coupled to the heat sink 331. In other embodiments, the thermal blocks 337 can extend directly from the bottom device 3000 to the heat sink 331. In another embodiment, the thermal blocks 337 can extend from the bottom die (which is attached to the bottom device 3000) to the heat sink 331. The thermal blocks 337 can redirect the heat flow through the system as shown by the arrows, thus reducing the heat flow through these neighboring / nearby chips.

[0027] For example, the microelectronic device may include a first integrated device die, a second integrated device die disposed on the first integrated device die, a heat block directly bonded to the first integrated device die without adhesive, and a heat sink attached to at least the heat block. In one embodiment, the heat block has a thermal conduction path for transferring heat from the first integrated device die to the heat sink. In one embodiment, the heat block is configured to reduce the heat flow through the second integrated device die. In one embodiment, the second integrated device die is made of silicon, and the thermal conductivity of the heat block is higher than the thermal conductivity of silicon. In one embodiment, the coefficient of thermal expansion (CTE) of the heat block is lower than 10 μm / m° C. In one embodiment, the heat flux through the heat block is higher than the heat flux through the second integrated device die during operation of the microelectronic device. In one embodiment, the second integrated device die is directly bonded to the first integrated device die without adhesive.

[0028] In another embodiment, the microelectronic device may include a first integrated device die, a second integrated device die disposed on the first integrated device die, a heat block disposed on the first integrated device die, and a heat sink attached to at least the heat block, wherein a heat flux through the heat block is greater than a heat flux through the second integrated device die during operation of the microelectronic device. In one embodiment, the coefficient of thermal expansion (CTE) of the heat block is less than 10 μm / m° C., and the thermal conductivity of the heat block is greater than the thermal conductivity of silicon. In one embodiment, the second integrated device die is directly bonded to the first integrated device die without adhesive. In one embodiment, the heat block is directly bonded to the first integrated device die without adhesive.

[0029] Disclosed herein is a method of fabricating a microelectronic device, comprising the steps of providing a first semiconductor element, bonding a second semiconductor element and a thermal block to the first semiconductor element, and providing a heat sink on the thermal block, the thermal block providing a thermal path between the first semiconductor element and the heat sink, the thermal block having a coefficient of thermal expansion (CTE) of less than 10 μm / m° C. and a thermal conductivity of the thermal block of less than 150 Wm at room temperature. -1 K -1 In one embodiment, the second semiconductor element is direct bonded to the first semiconductor element without an intervening adhesive. In one embodiment, the thermal block is direct bonded to the first semiconductor element without an intervening adhesive.

[0030] A method of operating a microelectronic device having a first integrated device die and a second integrated device die disposed on the first integrated device die includes directing a first heat flux through a heat block disposed on the first integrated device die and a second heat flux through the second integrated device die, the first heat flux through the heat block being greater than the second heat flux through the second integrated device die. In one embodiment, the coefficient of thermal expansion (CTE) of the heat block is less than 10 μm / m° C. and the thermal conductivity of the heat block is greater than the thermal conductivity of silicon. In one embodiment, a heat sink is attached to at least the heat block.

[0031] Electronic Devices A die may refer to any suitable type of integrated device die. For example, an integrated device die may include electronic components, such as integrated circuits (e.g., a processor die, a controller die, or a memory die), a microelectromechanical system (MEMS) die, an optical device, or any other suitable type of device die. In some embodiments, the electronic components include passive devices, such as capacitors, inductors, or other surface mount devices. Circuitry (e.g., active components such as transistors) may be patterned at or near the active side in various embodiments. The active side may be located on the side of the die opposite the back side of the die (the front side). The back side may or may not include any active or passive circuitry.

[0032] The integrated device die may have a bonding surface and a back surface opposite the bonding surface. The bonding surface may have a plurality of conductive bond pads including one conductive bond pad, and a non-conductive material located proximate the conductive bond pads. In some embodiments, the conductive bond pads of the integrated device die may be directly bonded to corresponding conductive pads of the substrate or wafer without an intervening adhesive, and the non-conductive material of the integrated device die may be directly bonded to a portion of the corresponding non-conductive material of the substrate or wafer without an intervening adhesive. Direct bonding without adhesives is described in U.S. Patent Nos. 7,126,212, 8,153,505, 7,622,324, 7,602,070, 8,163,373, 8,389,378, 7,485,968, 8,735,219, 9,385,024, 9,391,143, and 9,4 Nos. 31,368, 9,953,941, 9,716,033, 9,852,988, 10,032,068, 10,204,893, 10,434,749, and 10,446,532, each of which is incorporated by reference in its entirety and incorporated herein for all purposes.

[0033] Direct bonding method and direct bonded structure Various embodiments disclosed herein relate to a direct bonded structure in which two elements can be directly bonded without an intervening adhesive. The two or more electronic elements can be semiconductor elements (e.g., integrated device dies, wafers, etc.), and the two or more electronic elements can be stacked or bonded together to form a bonded structure. The conductive contact pads of one element can be electrically connected to the corresponding conductive contact pads of the other element. Any suitable number of elements can be stacked into a bonded structure. The contact pads can be metal pads formed on non-conductive bonding areas, and can be connected to an underlying metallization, such as a redistribution layer (RDL).

[0034] In some embodiments, the elements are directly bonded to each other without adhesive. In various embodiments, a non-conductive material or dielectric of a first element may be directly bonded to a corresponding non-conductive or dielectric field region of a second element without adhesive. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of the first element may be directly bonded to a corresponding non-conductive material of the second element using a dielectric-dielectric (inter-dielectric) bonding technique. For example, a dielectric-dielectric bond may be formed without adhesive using direct bonding techniques as disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference herein in its entirety for all purposes. Dielectrics suitable for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, or carbon such as silicon carbide, silicon oxycarbonitride, silicon carbonitride, or diamond-like carbon. In some embodiments, the dielectric does not include a polymeric material such as an epoxy, resin, or molding compound.

[0035] In some embodiments, the direct hybrid bond can be formed without an intervening adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or an etchant to activate the surfaces. In some embodiments, the surfaces can be terminated with a chemical species after or during activation (e.g., during a plasma and / or etch process). Without being bound by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surfaces, and the end-grouping process can provide additional chemical species at the bonding surfaces that improve the bonding energy during direct bonding. In some embodiments, activation and end-grouping can be provided in the same step, for example, the surfaces can be activated and end-grouped using a plasma or a wet etchant. In other embodiments, the bonding surfaces can be end-grouped in a separate process to provide additional chemical species that can be used for direct bonding. In various embodiments, the end-grouping chemical species can include nitrogen. For example, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, one or many fluorine peaks may appear near the layers and / or bonding interface. Thus, in a direct bonded structure, the bonding interface between the two dielectrics may comprise a very smooth interface with high nitrogen content and / or fluorine peaks at the bonding interface. Additional examples of activation and / or end group treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0036] In various embodiments, the contact pads of the first component may also be directly bonded to the corresponding conductive contact pads of the second component. For example, hybrid direct bonding techniques may be used to provide conductor-conductor direct bonds along a bond interface that includes a covalently directly bonded inter-dielectric surface that has been pretreated as described above. In various embodiments, conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds may be formed using direct bonding techniques as disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference herein in its entirety for all purposes.

[0037] For example, the dielectric bonding surfaces may be pretreated and directly bonded to each other without an intervening adhesive as described above. The conductive contact pads, which may be surrounded by a non-conductive dielectric field region, may also be directly bonded to each other without an intervening adhesive. In some embodiments, the contact pads may be recessed below the dielectric field region or the outer surface (e.g., top surface) of the non-conductive bonding layer, for example by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm or in the range of 4 nm to 10 nm. The non-conductive bonding layers may in some embodiments be directly bonded to each other without an adhesive at room temperature with a bonding tool described herein, after which the bonded structure may be annealed. The annealing may be performed in a separate apparatus. During annealing, the contact pads may expand and contact each other, thereby forming a metal-metal (intermetal) direct bond. Advantageously, the use of hybrid bonding technology, such as Direct Bond Interconnect, or DBI® technology, commercially available from Xperi, Inc., San Jose, Calif., allows for a high density of pads connected across the direct bond interface (e.g., with a small or fine pitch for a regular array). In some embodiments, the pitch of the bond pads, or the conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 microns, or less than 10 microns, or even less than 2 microns. For some applications, the ratio of the bond pad pitch to one of the bond pad features is less than 5 or less than 3, and in some cases desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range from 0.3 microns to 5 microns. In various embodiments, the contact pads and / or traces may be made of copper, although other metals may be suitable.

[0038] Thus, in a direct bonding process, the first element can be directly bonded to the second element without an intervening adhesive. In some configurations, the first element can be a singulated element, such as a singulated integrated device die. In other configurations, the first element can be a carrier or substrate (e.g., a wafer) that includes multiple (e.g., tens, hundreds, or more) device regions that, when singulated, form multiple integrated device dies. In the embodiments described herein, the first element, whether a die or a substrate, may be considered a host substrate, which is attached to a support of a bonding tool for pick-and-placement of the second element or for receiving a robotic end effector. The second element in the illustrated embodiment is a die. In other configurations, the second element can be a carrier or flat panel, or a substrate (e.g., a wafer).

[0039] As described herein, the first and second elements can be directly bonded together without adhesive, which is different from a deposition process. In one application, the width of the first element in the bonded structure can be approximately the same as the width of the second element. In some other embodiments, the width of the first element in the bonded structure can be different from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Thus, the first and second elements can be comprised of non-deposited elements. Furthermore, unlike deposited layers, the direct bonded structure can include defect areas along the bond interface where nanovoids exist. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonding surface. As discussed above, the bond interface can exhibit a concentration of material resulting from activation and / or final chemical treatment process. For example, in an embodiment utilizing nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface. In embodiments utilizing oxygen plasma for activation, oxygen peaks may form at the bond interface. In some embodiments, the bond interface may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond may include a covalent bond, which is stronger than a van der Waals bond. The bonding layer may further have a polished surface that is planarized to a high degree of smoothness. For example, the bonding layer may have a surface roughness of 2 nm root mean square (RMS) per micron or 1 nm RMS per micron.

[0040] In various embodiments, the metal-metal bonds between the contact pads in the direct hybrid bonded structure may be bonded such that the conductive feature grains on the conductive features, e.g., copper grains, grow into one another across the bond interface. In some embodiments, the copper may have grains oriented along 111 crystal planes to improve diffusion of the copper across the bond interface. The bond interface may extend substantially completely to at least a portion of the bonded contact pad, such that there are substantially no gaps between the non-conductive bond regions at or near the bonded contact pad. In some embodiments, a barrier layer may be provided under the contact pad (e.g., which may include copper). However, in other embodiments, there may be no barrier layer under the contact pad, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated by reference in its entirety and incorporated by reference herein for all purposes.

[0041] In one aspect, the disclosed technology provides a microelectronic device having a first semiconductor element, at least one second semiconductor element disposed on the first semiconductor element, and a thermal block disposed on the first semiconductor element adjacent to the at least one second semiconductor element, the thermal block having a heat transfer path for transferring heat from the first semiconductor element to a heat sink disposed on the thermal block, the coefficient of thermal expansion (CTE) of the thermal block being less than 10 μm / m° C., and the thermal conductivity of the thermal block being less than 150 Wm at room temperature. -1 K -1 The present invention relates to a microelectronic device characterized in that

[0042] In one embodiment, the thermal block is configured to reduce the heat flow through the at least one second semiconductor device.

[0043] In one embodiment, the at least one second semiconductor element is made of silicon, and the thermal conductivity of the thermal block at about the device operating temperature is greater than the thermal conductivity of silicon.

[0044] In one embodiment, the heat flux through the thermal block is greater than the heat flux through the at least one second semiconductor element during operation of the microelectronic device.

[0045] In one embodiment, the coefficient of thermal expansion (CTE) of the thermal block is substantially the same as the CTE of the first semiconductor element.

[0046] In one embodiment, the first semiconductor element is made of silicon and the coefficient of thermal expansion (CTE) of the thermal block is substantially the same as the CTE of silicon.

[0047] In one embodiment, the coefficient of thermal expansion (CTE) of the thermal block is less than the thermal conductivity of copper.

[0048] In one embodiment, the coefficient of thermal expansion (CTE) of the thermal block is less than 7 μm / m° C.

[0049] In one embodiment, the thermal conductivity of the thermal block is greater than the thermal conductivity of the at least one second semiconductor element.

[0050] In one embodiment, the thermal conductivity of the thermal block is greater than the thermal conductivity of silicon.

[0051] In one embodiment, the thermal conductivity of the thermal block is 200 Wm -1 K -1 Higher than.

[0052] In one embodiment, the thermal conductivity of the thermal block is within 10% of the thermal conductivity of copper.

[0053] In one embodiment, the thermal conductivity of the thermal block is at least three times that of copper.

[0054] In one embodiment, the thermal block is made of diamond, nanofiber, nanoporous metal, graphite, or GeSe.

[0055] In one embodiment, the thermal block is made of an electrical non-conductor or semiconductor.

[0056] In one embodiment, the thermal block is direct bonded to the first semiconductor element without an intervening adhesive.

[0057] In one embodiment, the interface between the thermal block and the first semiconductor device comprises a dielectric-to-dielectric direct bond.

[0058] In one embodiment, the thermal block is bonded to the first semiconductor device by solder bonding.

[0059] In one embodiment, the thermal block is bonded to the first semiconductor device by adhesive bonding.

[0060] In one embodiment, the thermal block is bonded to the first semiconductor device by a thermally conductive material (TIM).

[0061] In one embodiment, the at least one second semiconductor element is direct hybrid bonded to the first semiconductor element without an intervening adhesive.

[0062] In one embodiment, the interface between the at least one second semiconductor element and the first semiconductor element comprises a conductor-to-conductor direct bond and a dielectric-to-dielectric direct bond.

[0063] In one embodiment, the heat sink is in contact with the at least one second semiconductor device.

[0064] In one embodiment, the heat sink is directly bonded to the at least one second semiconductor device without an intervening adhesive.

[0065] In one embodiment, the heat sink is directly bonded to the thermal block with no intervening adhesive.

[0066] In one embodiment, the first semiconductor element comprises an integrated device die.

[0067] In one embodiment, the at least one second semiconductor element comprises an integrated device die.

[0068] In another aspect, the disclosed technology provides a method of fabricating a microelectronic device, the method including providing a first semiconductor element, bonding a second semiconductor element and a thermal block to the first semiconductor element, and attaching a heat sink to the thermal block, the thermal block providing a thermal path between the first semiconductor element and the heat sink, the thermal block having a coefficient of thermal expansion (CTE) of less than 10 μm / m° C. and a thermal conductivity of the thermal block of less than 150 Wm at room temperature. -1 K -1 is greater than or equal to

[0069] In one embodiment, the second semiconductor element is direct bonded to the first semiconductor element without an intervening adhesive.

[0070] In one embodiment, the thermal block is direct bonded to the first semiconductor element without an intervening adhesive.

[0071] In another aspect, the disclosed technology relates to a microelectronic device comprising a first integrated device die, a second integrated device die disposed on a first semiconductor device, a heat block directly bonded to the first integrated device die without adhesive, and a heat sink attached to at least the heat block. In one embodiment, the microelectronic device of claim 33, wherein the heat block has a thermal conduction path for transferring heat from the first integrated device die to the heat sink.

[0072] In one embodiment, the heat block is configured to reduce the heat flow through the second integrated device die.

[0073] In one embodiment, the second integrated device die is made of silicon and the thermal conductivity of the heat block is higher than the thermal conductivity of silicon.

[0074] In one embodiment, the coefficient of thermal expansion (CTE) of the heat block is less than 10 μm / m° C.

[0075] In one embodiment, the heat flux through the heat block is greater than the heat flux through the second integrated device die during operation of the microelectronic device.

[0076] In one embodiment, the second integrated device die is directly bonded to the first integrated device die without an adhesive.

[0077] In another aspect, the disclosed technology relates to a microelectronic device having a first integrated device die, a second integrated device die disposed on the first integrated device die, a heat block disposed on the first integrated device die, and a heat sink attached to at least the heat block, wherein a heat flux through the heat block is greater than a heat flux through the second integrated device die during operation of the microelectronic device.

[0078] In one embodiment, the coefficient of thermal expansion (CTE) of the heat block is less than 10 μm / m° C. and the thermal conductivity of the heat block is greater than the thermal conductivity of silicon.

[0079] In one embodiment, the second integrated device die is directly bonded to the first integrated device die without an adhesive.

[0080] In one embodiment, the heat block is directly bonded to the first integrated device die without adhesive.

[0081] In another aspect, the disclosed technology relates to a method of operating a microelectronic device having a first integrated device die and a second integrated device die disposed on the first integrated device die, the method including directing a first heat flux through a heat block disposed on the first integrated device die and a second heat flux through the second integrated device die, wherein the first heat flux through the heat block is greater than the second heat flux through the second integrated device die.

[0082] In one embodiment, the coefficient of thermal expansion (CTE) of the heat block is less than 10 μm / m° C. and the thermal conductivity of the heat block is greater than the thermal conductivity of silicon.

[0083] In one embodiment, a heat sink is attached to at least the heat block.

[0084] Unless the context clearly requires otherwise, throughout the specification and claims, the terms "comprise", "comprising", "include", "including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to", as opposed to an exclusive or exhaustive sense. As used generally herein, the term "coupled" means two or more elements that are directly connected to each other or that are connected to each other through one or more intermediate elements. Similarly, as used generally herein, the term "coupled" means two or more elements that are directly connected to each other or that are connected to each other through one or more intermediate elements. In addition, the terms "herein," "above," "below," and words of similar import as used in the parent application refer to the application as a whole and not to any particular portion of the application. Furthermore, as used herein, when a first element is described as being located "on" or "over" a second element, the first element may be directly located on or over the second element such that the first element and the second element are in direct contact with each other, or the first element may be indirectly located on or over the second element such that one or more elements are interposed between the first element and the second element. Where the context permits, terms in the above detailed description using the singular or plural may include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0085] Furthermore, conditional terms used in the specification, particularly "can," "could," "might," "may," "eg," "for example," "such as," and the like, unless expressly specified otherwise or understood otherwise within the context in which they are used, are generally intended to imply that certain embodiments include certain features, elements, and / or conditions and that other embodiments do not include certain features, elements, and / or conditions. Thus, such conditional terms are not generally intended to imply that features, elements, and / or conditions are present in any required manner for one or more embodiments.

[0086] Although certain embodiments have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and furthermore, various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, although blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention as set forth in the appended claims and equivalents thereto is intended to include such forms or modifications within the scope and spirit of the invention.

Claims

1. 1. A microelectronic device comprising: a first semiconductor element; at least one second semiconductor element disposed on the first semiconductor element; a thermal block disposed on the first semiconductor element adjacent to the at least one second semiconductor element, the thermal block having a heat transfer path for transferring heat from the first semiconductor element to a heat sink disposed on the thermal block; the thermal block has a coefficient of thermal expansion (CTE) of less than 10 μm / m° C.; The thermal conductivity of the thermal block is 150 Wm at room temperature. -1 K -1 Higher than microelectronic devices.

2. The microelectronic device of claim 1 , wherein the thermal block is configured to reduce heat flow through the at least one second semiconductor element.

3. The microelectronic device of claim 2 , wherein the heat flux through the thermal block is greater than the heat flux through the at least one second semiconductor element during operation of the microelectronic device.

4. The microelectronic device of claim 1 , wherein the coefficient of thermal expansion (CTE) of the thermal block is substantially the same as the CTE of the first semiconductor element.

5. The microelectronic device of claim 1 , wherein the first semiconductor element is made of silicon and the coefficient of thermal expansion (CTE) of the thermal block is substantially the same as the CTE of silicon.

6. The microelectronic device of claim 1 , wherein the thermal block has a thermal conductivity greater than the thermal conductivity of the at least one second semiconductor element.

7. The microelectronic device of claim 1 , wherein the thermal block is made of diamond, nanofiber, nanoporous metal, graphite, or GeSe.

8. The microelectronic device of claim 1 , wherein the thermal block is made of an electrically non-conductor or semiconductor.

9. The microelectronic device of claim 1 , wherein the thermal block is directly bonded to the first semiconductor element without an intervening adhesive.

10. The microelectronic device of claim 1 , wherein the thermal block is bonded to the first semiconductor element by a thermally interface material (TIM).

11. The microelectronic device of claim 1 , wherein the interface between the at least one second semiconductor element and the first semiconductor element comprises a conductor-to-conductor direct bond and a dielectric-to-dielectric direct bond.

12. The microelectronic device of claim 1 , wherein the heat sink is in contact with the at least one second semiconductor element.

13. The microelectronic device of claim 1 , wherein the heat sink is directly bonded to the thermal block without an intervening adhesive.

14. The microelectronic device of claim 1 , wherein the first semiconductor element comprises an integrated device die.

15. 1. A method of fabricating a microelectronic device, said method comprising: providing a first semiconductor device; bonding a second semiconductor device and a thermal block to the first semiconductor device; and attaching a heat sink to the thermal block, the thermal block providing a thermal path between the first semiconductor device and the heat sink; the thermal block has a coefficient of thermal expansion (CTE) of less than 10 μm / m° C.; The thermal conductivity of the thermal block is 150 Wm at room temperature. -1 K -1 Way higher than that.

16. 16. The method of claim 15, wherein the second semiconductor element is direct bonded to the first semiconductor element without an intervening adhesive.

17. 16. The method of claim 15, wherein the thermal block is directly bonded to the first semiconductor device without an intervening adhesive.

18. The microelectronic device of claim 1 , wherein the thermal block is free of active circuitry.

19. 20. The microelectronic device of claim 18, wherein the thermal block is further free of passive circuitry.

20. 1. A microelectronic device comprising: a first integrated device die; a second integrated device die disposed on the first integrated device die; a heat block directly bonded to the first integrated device die without adhesive; a heat sink attached to at least the heat block.

21. 21. The microelectronic device of claim 20, wherein the heat block has a thermal path for transferring heat from the first integrated device die to the heat sink.

22. 21. The microelectronic device of claim 20, wherein the heat block is configured to reduce heat flow through the second integrated device die.

23. 21. The microelectronic device of claim 20, wherein the second integrated device die is made of silicon and the heat block has a thermal conductivity greater than that of silicon.

24. 21. The microelectronic device of claim 20, wherein the heat block has a coefficient of thermal expansion (CTE) of less than 10 μm / m°C.

25. 21. The microelectronic device of claim 20, wherein the heat flux through the heat block is greater than the heat flux through the second integrated device die during operation of the microelectronic device.

26. 21. The microelectronic device of claim 20, wherein the second integrated device die is directly bonded to the first integrated device die without adhesive.

27. 1. A microelectronic device comprising: a first integrated device die; a second integrated device die disposed on the first integrated device die; a heat block disposed on the first integrated device die; a heat sink attached to at least the heat block, A microelectronic device, wherein the heat flux through the heat block is greater than the heat flux through the second integrated device die during operation of the microelectronic device.

28. 28. The microelectronic device of claim 27, wherein the heat block has a coefficient of thermal expansion (CTE) less than 10 μm / m° C. and a thermal conductivity greater than that of silicon.

29. 30. The microelectronic device of claim 27, wherein the second integrated device die is directly bonded to the first integrated device die without adhesive.

30. 30. The microelectronic device of claim 27, wherein the heat block is directly bonded to the first integrated device die without adhesive.

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