Integrated circuit (IC) package using a package substrate with a double-sided embedded trace substrate (ETS) and related manufacturing method

JP2024541421A5Pending Publication Date: 2025-10-22QUALCOMM INC
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Patent Information

Application Number
JP2024529645
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2021-11-22
Filing Date
2022-10-28
Publication Date
2025-10-22

AI Technical Summary

Technical Problem

Existing IC packages face challenges in achieving reduced thickness while maintaining higher density input/output connections and minimizing thermal expansion mismatch and signal routing impedance, which can lead to warpage and crosstalk issues.

Method used

Incorporating a double-sided embedded trace substrate (ETS) with two metallization layers embedded within insulating layers, providing vertical interconnect accesses to support higher density connections and reduce thickness, while ensuring similar thermal expansion coefficients and minimizing signal routing distance to decrease impedance and crosstalk.

Benefits of technology

The double-sided ETS design achieves reduced package thickness, supports higher density interconnects, minimizes thermal expansion mismatch, and improves signal routing performance by reducing impedance and crosstalk, thereby enhancing the overall functionality of IC packages.

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Abstract

An integrated circuit (IC) package using a package substrate with a double-sided embedded trace substrate (ETS), and related manufacturing methods. To facilitate providing a substrate of reduced thickness in the IC package to facilitate reducing the overall height of the IC package while supporting a higher density of input / output (I / O) connections, the package substrate in the IC package includes a double-sided ETS. The double-sided ETS includes two adjacent ETS metallization layers, both of which include metal traces embedded in an insulating layer. The buried metal traces in the ETS metallization layers of the double-sided ETS can be electrically coupled to each other through vertical interconnect accesses (vias) (e.g., metal pillars, metal posts) to provide signal routing paths between the buried metal traces in the ETS metallization layers.
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