System and method for on-line gain calibration of digital time converters - Patents.com

Abstract

The system (100) includes a first digital time converter (DTC) (140) adapted to receive a first DTC code and a first clock signal. The first DTC (140) provides an output clock signal. The system (100) includes a calibration DTC (150) adapted to receive a calibration DTC code and a second clock signal. The calibration DTC (150) provides a calibration output signal. The system (100) includes a latching comparator (188) providing an output indicative of whether the output clock signal or the calibration output signal is received first. The system (100) includes an average calculation module (196) providing an average value of the output of the latching comparator. The system (100) includes a digital controller (120) adapted to receive the average value. The digital controller (120) provides the DTC code and the calibration DTC code.

Description

[Technical field]

[0001] This description relates generally to digital time converters (DTCs) and, more particularly, to online gain calibration of DTCs.

[0002] Digital Time Converters (DTCs) are used in Phase Locked Loop (PLL) systems and Fractional Output Dividers (FODs) where the DTC receives input (e.g., a DTC code) from a digital controller and, in response, synthesizes fine time edges by interpolating between the input clock edges to generate the desired phase of the DTC's output signal.

[0003] The accuracy of the DTC output phase depends on the input clock frequency and its gain. Since the DTC can be operated without interruption for several years, analog disturbances (such as gain deviations caused by aging of the DTC) can occur, which can result in gain errors. To compensate for the gain errors, the gain of the DTC must be recalibrated.

[0004] Recalibrating the DTC during operation is difficult. There are several known methods for recalibrating the gain of the DTC during operation when the DTC code is zero. The drawback of these methods is that the probability of the DTC code being zero is very low. For example, if the DTC code has 12 bits, the probability that the code is zero is 0.00024, and therefore such an event occurs only rarely. Other methods for recalibrating the gain of the DTC during operation increase the jitter in the output, thereby degrading the performance of the DTC. Since most FODs have stringent jitter requirements (e.g., jitter in the output less than 125 femtoseconds), increased jitter in the output may make the FOD unsuitable for the desired application. Summary of the Invention

[0005] In one aspect, a system includes a first digital time converter (DTC) having a first input adapted to receive a DTC code and a second input adapted to receive a first clock signal. The first DTC provides an output clock signal at a first DTC output. The system includes a calibration DTC having a first input adapted to receive a calibration DTC code and a second input adapted to receive a second clock signal. The calibration DTC provides a calibration output signal at a calibration DTC output. The system includes a latch comparator having a first input coupled to the first DTC output and a second input coupled to the calibration DTC output. The latch comparator provides a plurality of output values ​​at a latch comparator output indicative of whether the output clock signal or the calibration output signal is received first. The system includes an average calculation module having an input coupled to the latch comparator output. The average calculation module provides an average of the output values ​​received from the latched comparator at an output of the average calculation module. The system includes a digital controller having an input coupled to the output of the average calculation module. The digital controller provides a DTC code, a calibrated DTC code, and a gain error signal.

[0006] The digital controller also includes a sigma-delta modulator having an input adapted to receive the gain error signal, the sigma-delta modulator providing the DTC code.

[0007] The digital controller also includes a code level detector having an input adapted to receive the first DTC code, the code level detector providing a first indication when the first DTC code is less than a lower threshold and providing a second indication when the first DTC code is greater than an upper threshold.

[0008] The digital controller also includes a state machine having a first input adapted to receive the average value and a second input adapted to receive the first indicator or the second indicator, The state machine provides a gain error signal and a calibration DTC code.

[0009] The state machine also aligns the output clock signal with the calibrated output signal by adjusting the calibrated DTC code to bring the average value closer to 0.5.

[0010] Additionally, the output value provided by the latched comparator is a binary number indicating whether the output clock signal or the calibration output signal is received first.

[0011] A system also includes a first digital time converter (DTC) having a first input adapted to receive a first DTC code and a second input adapted to receive a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC having a first input adapted to receive a calibration DTC code and a second input adapted to receive a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latching comparator having a first input adapted to receive the output clock signal and a second input adapted to receive the calibration output clock signal. The latching comparator provides a binary output indicative of whether the output clock signal or the calibration output signal is received first. The system includes an average calculation module having an input adapted to receive the binary output and providing an average value of the binary output. The system includes a state machine having a first input adapted to receive the average value and a second input adapted to receive a first indication when the first DTC code is less than a lower threshold and a second indication when the first DTC code is greater than an upper threshold. The state machine provides a gain error signal and a calibrated DTC code. The system includes a sigma-delta modulator having an input adapted to receive the gain error signal and provides the first DTC code.

[0012] Also, a method of calibrating a first DTC using a calibration DTC includes providing a first digital code and a first clock signal to the first DTC and providing an output clock signal. If the first digital code is less than a lower threshold, the method includes providing a first calibration digital code and a second clock signal to the calibration DTC and providing a calibration output signal, where the first calibration digital code is equal to the first digital code. The method includes adjusting the first calibration digital code to align the calibration output signal with the output clock signal. The method includes delaying a second clock signal applied to the calibration DTC by one clock period and providing a third digital code to the first DTC. If the third digital code is greater than an upper threshold, the method includes providing a second calibration digital code to the calibration DTC and adjusting the second calibration digital code to align the output clock signal with the calibration output signal.

[0013] The method also includes determining a gain error of the first DTC from the adjusted second calibration digital code.

[0014] The method also includes aligning edges of the output clock signal with corresponding edges of the calibration output signal by adjusting a second calibration digital code applied to the calibration DTC.

[0015] The method of adjusting the first calibration digital code also includes providing a binary output in response to the output clock signal and the calibration output signal indicating whether the output clock signal or the calibration output signal is received first, determining an average value of the binary output, and adjusting the calibration digital code until the average value of the binary output approaches 0.5. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a block diagram of an example fractional output divider (FOD) with gain calibration.

[0017] [Diagram 2] FIG. 2 is a block diagram of an example digital controller.

[0018] [Diagram 3] 1 is a flow chart of an example method.

[0019] [Figure 4A] FIG. 4 is a timing diagram of an example method for calibrating a DTC. [Figure 4B] FIG. 4 is a timing diagram of an example method for calibrating a DTC.

[0020] In the drawings, the same reference numbers or other reference identifiers are used to denote the same or similar (structural and / or functional) features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] 1 is a block diagram of an example fractional output divider (FOD) 100. FOD 100 receives an input clock signal CLK_IN and generates an output clock signal CLK_OUT by dividing CLK_IN by a fractional divider. The output clock signal CLK_OUT has a frequency equal to a particular fraction of CLK_IN.

[0022] The FOD 100 includes a signal generator 104 (e.g., an oscillator such as a bulk acoustic wave (BAW) device) that provides an input clock signal CLK_IN of an appropriate frequency (e.g., 100 MHz, 1 GHz, 10 GHz) at an output 106. The FOD 100 includes a frequency divider 110 having a first input 112 coupled to receive CLK_IN and a second input 114 coupled to receive a signal (e.g., a digital signal) representing an integer N (e.g., N=2, 5, 10, 100). The integer N corresponds to the integer portion of a fractional divider. For example, if the fractional divider is 10.5, the corresponding integer portion is 10. The frequency divider 110 divides CLK_IN by the integer N and provides an intermediate clock signal CLK_IMD at an output 116.

[0023] In some examples, frequency divider 110 may be implemented with a counter that counts the number of edges of CLK_IN (equal to the integer portion of the fractional divider) to generate a signal having a period that approximates the approximate period of the desired output signal. For example, if the fractional divider is 10.5, frequency divider 110 may count 10 edges and generate a corresponding signal CLK_IMD that has an approximate period of the desired output clock signal CLK_OUT. Thus, in this example, CLK_IMD has a clock period equal to 10 clock periods of CLK_IN.

[0024] In some examples, digital controller 120 may provide instructions to frequency divider 110 to count N edges of CLK_IN and generate CLK_IMD. Digital controller 120, or portions thereof, may be implemented in hardware (e.g., logic circuitry, state machines, microprocessors, application specific integrated circuits), firmware, and / or software.

[0025] The FOD 100 includes a first latch 130 having a data input 132 coupled to receive the intermediate clock signal CLK_IMD. The first latch 130 has a clock input 134 coupled to receive the input clock signal CLK_IN. The first latch 130 delays the intermediate clock signal CLK_IMD by one clock period of CLK_IN and provides a delayed intermediate signal DEL_CLK_IMD at an output 136.

[0026] The FOD 100 includes a main digital time converter (DTC) 140, also referred to as a first DTC 140. The main DTC 140 has a first input 142 coupled to receive a delayed intermediate signal DEL_CLK_IMD and a second input 144 coupled to receive a main DTC code MAIN_DTC_CODE. In some examples, the digital controller 120 may provide the MAIN_DTC_CODE to the main DTC 140. The main DTC code MAIN_DTC_CODE may instruct the main DTC 140 to interpolate fractional periods of the input clock signal CLK_IN and to add fractional periods between edges of DEL_IMD_CLK to generate an output clock CLK_OUT at an output 146. This has the effect of generating a desired length between edges of CLK_OUT by adding fractional periods between the edges.

[0027] For example, if the fractional divider is 10.5, the integer part is 10 and the fractional part is 0.5. The frequency divider 110 divides CLK_IN by 10 (e.g., the integer part of the fractional divider). The main DTC code MAIN_DTC_CODE may instruct the main DTC 140 to interpolate a fractional period equal to 0.5 periods of CLK_IN. The main DTC 140 may determine 0.5 periods of CLK_IN and add 0.5 of the period of CLK_IN between edges of DEL_IMD_CLK to create the desired length between edges of CLK_OUT. The effect of this is that the output clock signal CLK_OUT at the output 146 has a clock period equal to 10.5 clock periods of CLK_IN.

[0028] In some examples, the process of interpolating fractional periods of CLK_IN is repeated for each period of CLK_OUT. Because the fractional ratio continually changes the edge relationship between CLK_IN and CLK_OUT, each period requires a different amount of interpolation. In some examples, a sigma-delta modulator is implemented (not shown in FIG. 1) to calculate the amount of interpolation.

[0029] In some examples, the main DTC code MAIN_DTC_CODE is a 12-bit binary number, so MAIN_DTC_CODE may have a maximum value of 4096 and a minimum value of 0. In other examples, MAIN_DTC_CODE may have a greater or lesser number of bits.

[0030] Because the FOD 100 may be operated uninterrupted for many years, the gain of the main DTC 140 may change over time due to analog impairments, for example, the capacitance of a capacitor may change over time, resulting in a gain error that requires modification (e.g., recalibration) of the gain of the main DTC 140 to compensate for the gain error.

[0031] In one example, the main DTC 140 is calibrated during operation without degrading its performance. The FOD 100 includes a calibration DTC 150, also referred to as a second DTC 150. The calibration DTC 150 is used to calibrate the main DTC 140 during operation.

[0032] The FOD 100 includes a second latch 160 having a data input 162 coupled to receive the intermediate clock signal CLK_IMD and a clock input 164 coupled to receive the input clock signal CLK_IN. The second latch 160 adds a delay of one clock period of CLK_IN to the intermediate clock signal CLK_IMD and provides a delayed intermediate signal DEL1_CLK_IMD at an output 165. The FOD 100 includes a multiplexer 166 having a first input 168 coupled to receive the CLK_IMD from the frequency divider 110 and a second input 170 coupled to receive the DEL1_CLK_IMD from the second latch 160. The multiplexer 166 has a control input 172 coupled to receive a multiplexer control signal MUX_CNTR, which may be provided by the digital controller 120. In response to a multiplexer control signal MUX_CNTR, the multiplexer 166 selects one of CLK_IMD and DEL1_CLK_IMD and provides the selected signal at an output 174. The FOD 100 includes a third latch 180 having a data input 182 coupled to the output 174 of the multiplexer 166. The third latch 180 has a clock input 184 coupled to receive the input clock signal CLK_IN. The third latch 180 applies a delay of one clock period of CLK_IN to the output of the multiplexer 166 (e.g., CLK_IMD or DEL1_CLK_IMD). The third latch 180 provides a signal DEL2_CLK_IMD at an output 186. Signal DEL2_CLK_IMD may be a delayed intermediate clock signal (if CLK_IMD is output by multiplexer 166) or a delayed clock signal (if DEL1_CLK_IMD is output by multiplexer 166). Depending on whether multiplexer 166 selects the signal at its first input 168 or the signal at its second input 170, the signal path may include a delay equal to one clock period of CLK_IN or two clock periods of CLK_IN.

[0033] The calibration DTC 150 includes a first input 152 coupled to an output 186 of the third latch 180 and a second input 154 coupled to receive a calibration code CALIB_CODE provided by the digital controller 120. In response to the calibration code CALIB_CODE, the calibration DTC 150 interpolates a fraction of a period of CLK_IN, adds a fractional period between two edges of DEL2_CLK_IMD, and provides CALIB_OUT at an output 155.

[0034] In one example, the gain of the main DTC 140 is calibrated in two calibration stages using the calibration DTC 150. In the first calibration stage, the gain of the main DTC 140 is calibrated when the main DTC code MAIN_DTC_CODE is close to zero.

[0035] In the first calibration stage, in response to the multiplexer control signal MUX_CNTR, the multiplexer 166 selects the signal at its first input 168. Thus, in the first calibration stage, the multiplexer 166 selects the CLK_IMD provided by the frequency divider 110. The selected signal CLK_IMD is received by a third latch 180, which applies a delay of one clock period of CLK_IN and outputs DEL2_CLK_IMD.

[0036] When DEL2_CLK_IMD is applied to the calibration DTC 150, the gain of the calibration DTC 150 is aligned with the gain of the main DTC 140 when the main DTC code MAIN_DTC_CODE is close to or approaching zero.

[0037] For example, if MAIN_DTC_CODE is a 12-bit binary number, it has a minimum value of 0 and a maximum value of 4096. Digital controller 120 compares MAIN_DTC_CODE to a lower threshold value, and if MAIN_DTC_CODE is equal to or less than the lower threshold value, MAIN_DTC_CODE is considered to be close or approaching 0 by digital controller 120. The lower threshold value may be set by user input or system requirements.

[0038] As an example, the lower threshold may be set to 15. Thus, the MAIN_DTC_CODE, which may have a value between 0 and 15, may be considered to be close or proximate to 0. In contrast to existing methods that require the DTC code to be 0 for calibration, which rarely occurs because the probability of a DTC code being equal to 0 is low, the described example only requires the MAIN_DTC_CODE to be close or proximate to 0. By requiring the MAIN_DTC_CODE to be close or proximate to 0 instead of being exactly 0, its occurrence probability is significantly increased. If the lower threshold is set to 15, the occurrence probability of a MAIN_DTC_CODE having a value close or proximate to 0 is 15 times higher than the occurrence probability of a code having a value of 0. Increasing the number of lower thresholds may increase the probability of occurrence of a desired code, thereby allowing frequent calibration of the main DTC 140 during operation.

[0039] If MAIN_DTC_CODE is close or approaching 0, the digital controller 120 sets CALIB_CODE equal to MAIN_DTC_CODE. For example, if MAIN_DTC_CODE is 15, then CALIB_CODE is equal to 15. When CALIB_CODE is equal to MAIN_DTC_CODE, CALIB_CODE is adjusted to align the output signal (CALIB_OUT) of the calibration DTC 150 with the corresponding edge of the output signal (CLK_OUT) of the main DTC 140. The calibration DTC code CALIB_CODE is adjusted to minimize any time difference between an edge of CLK_OUT and a corresponding edge of CALIB_OUT. This is done using a strong arm latch (SAL) 188. The SAL 188 is a latch comparator having a first input 190 at which the output CLK_OUT of the main DTC 140 is received and a second input 194 at which the output CALIB_OUT of the calibration DTC 150 is received. SAL 188 determines which of each pair of received input signals arrived first and provides a binary number (0 or 1) at output 189 indicating which input signal arrived first.

[0040] Due to non-ideal operating conditions, there may be noise or jitter on CLK_IN. The effect of this is that the output of the first DTC 140 (CLK_OUT) and the output of the calibration DTC 150 (CALIB_OUT) may not arrive at exactly the same time. Therefore, the edges of CALIB_OUT will not perfectly align with the edges of CLK_OUT, causing the SAL 188 to output a binary 0 or a binary 1.

[0041] For example, if the time difference between the edges of CALIB_OUT and CLK_OUT tend to get closer in response to an increase in CALIB_CODE, the distribution of 0's and 1's at the output of SAL 188 will be approximately equal. Therefore, as CALIB_OUT and CLK_OUT gradually get closer to matching in response to an increase in CALIB_CODE, the number of 0's and 1's at the output of SAL 188 will tend to be approximately equal. Thus, the average of the samples (e.g., 100, 200) at the output of SAL 188 will tend to be closer to 0.5. Conversely, as the calibration codes CALIB_OUT and CLK_OUT tend to move away from matching, the number of 0's and 1's at the output of SAL 188 will become unbalanced. As CALIB_OUT and CLK_OUT move further away from matching, the number of 1's will increase and the number of 0's will decrease, or the number of 0's will increase and the number of 1's will decrease. Thus, the average of the samples (e.g., 100, 200) at the output will tend to move away from 0.5 (closer to 1 or closer to 0). Based on the average of the samples of the output of SAL 188, a determination can be made whether an increase or decrease in CALIB_CODE brings CALIB_OUT and CLK_OUT closer to matching.

[0042] The FOD 100 includes an average calculation unit 196 having an input 197 that receives the output of the SAL 188. The average calculation unit 196 calculates the average of samples (e.g., 100, 200) of the output of the SAL 188 and provides an average value AVG at an output 198. The digital controller 120 receives the average value AVG at an input 122 and, in response, adjusts the CALIB_CODE to adjust the gain of the calibration DTC 150 until the output AVG of the average calculation unit 196 is approximately 0.5, indicating that the output of the calibration DTC 150 (CALIB_OUT) is aligned with the output of the main DTC 140 (CLK_OUT). The average calculation unit 196 is a functional unit that may be implemented in hardware (e.g., logic circuitry, microprocessor, application specific integrated circuit), firmware, and / or software.

[0043] After the main DTC 140 is calibrated in a first stage when the DTC code is close to or near a DTC code of 0 (e.g., MAIN_DTC_CODE is less than the threshold value described above), the main DTC 140 is calibrated in a second stage when the DTC code is close to or near a full code (i.e., maximum value) (e.g., MAIN_DTC_CODE is equal to or greater than an upper threshold value described below). In the second stage, in response to a multiplexer control signal MUX_CNTR, the multiplexer 166 selects a signal at its second input 170 (DEL1_CLK_IMD). The multiplexer 166 provides DEL1_CLK_IMD to a third latch 180, which applies a delay equal to one clock period of CLK_IN and provides DEL2_CLK_IMD to the calibrating DTC 150. In the second stage, main DTC 140 receives a signal delayed by one clock period of CLK_IN, while calibration DTC 150 receives a signal delayed by two clock periods of CLK_IN. Thus, the input signal to calibration DTC 150 is delayed by one clock period of CLK_IN relative to the input signal to main DTC 140.

[0044] When DEL2_CLK_IMD is applied to the calibration DTC 150, CALIB_CODE is adjusted (i.e., increased or decreased) to align the output of the calibration DTC 150 with the output of the main DTC 140 when MAIN_DTC_CODE is close or approaching the full code. For example, if MAIN_DTC_CODE is a 12-bit binary number, it has a maximum value of 4096. The digital controller 120 compares MAIN_DTC_CODE to an upper threshold, and if MAIN_DTC_CODE is equal to or greater than the upper threshold, MAIN_DTC_CODE is considered by the digital controller 120 to be close or approaching the full code. The upper threshold may be set by user input or system requirements.

[0045] As an example, the upper threshold may be set to be equal to the full code minus 15 (e.g., 4096-15). Thus, MAIN_DTC_CODEs between 4081 and 4096 may be considered to be near or proximate to the full code. In contrast to existing methods that require the code to be a full code value for calibration, which occurs infrequently, the present invention only requires that the MAIN_DTC_CODE be near or proximate to the full code. By requiring the MAIN_DTC_CODE to be near or proximate to the full code, rather than the full code, its occurrence probability is significantly increased, thereby allowing frequent calibration of the main DTC 140 during operation.

[0046] If MAIN_DTC_CODE is close or proximate to the full code, then the digital controller 120 sets CALIB_CODE equal to a value close to 0 (e.g., full code minus MAIN_DTC_CODE). For example, if MAIN_DTC_CODE is 4090, then CALIB_CODE is set to 6 (4096-4090=6).

[0047] Components that add delays in the FOD 100, even tens of picoseconds, should be avoided. Because the first latch 130 adds a delay to the input signal to the first DTC 140, the third latch 180 is added to the signal path of the calibration DTC 150. The third latch 180 adds a delay to the signal path to the calibration DTC 150, thereby compensating for the delay added by the first latch 130. However, when the multiplexer 166 selects the signal at its second input 170, an additional delay is added to the signal path by the second latch 160. As a result, the input signal to the calibration DTC 150 is delayed by one clock period of CLK_IN relative to the input signal of the first DTC 140. To compensate for the additional delay, the digital controller 120 sets CALIB_CODE equal to a value close to zero (e.g., full code minus MAIN_DTC_CODE).

[0048] If CALIB_CODE is equal to (or close to) zero, then CALIB_CODE is adjusted (i.e., increased or decreased) to align the edges of the calibration DTC 150 output signal (CALIB_OUT) with the edges of the main DTC 140 output signal (CLK_OUT). The calibration DTC code CALIB_CODE is adjusted to minimize the time difference between an edge of CLK_OUT and the corresponding edge of CALIB_OUT. This is done using the strong-arm latch (SAL) 188, as described above.

[0049] The output of SAL 188 is received by an average calculation unit 196 which calculates the average of the samples of the output of SAL 188. The average calculation unit 196 generates an average value AVG at an output 198. The digital controller 120 receives the average value AVG at an input 122 and in response adjusts CALIB_CODE to adjust the gain of the calibration DTC 150 until the output of the average calculation unit 196 (AVG) is approximately 0.5. An AVG of approximately 0.5 indicates that the output of the calibration DTC 150 (CALIB_OUT) is aligned with the output of the main DTC 140 (CLK_OUT) when the DTC code DTC1_CODE is near or close to the full code. The gain error of the main DTC 140 is determined from the incremental or decremental adjustment applied to CALIB_CODE from an initial value near or close to the full code to the adjusted code when CALIB_OUT is aligned with CLK_OUT (i.e., AVG is approximately 0.5).

[0050] For example, for a 12-bit DTC code, the full code is 4096 and the initial code (initial code for MAIN_DTC_CODE) may be 4090 (i.e., close or near the full code). Therefore, the initial calibration code CALIB_CODE is 6 (full code minus the initial code of 4090). When the adjusted CALIB_CODE is 100, if CALIB_OUT and CLK_OUT are aligned, the gain error of the main DTC 140 = 100 - (-6) = 106. The gain error is used to calculate the gain correction fraction Fc. When F is a fraction, the gain correction fraction Fc may be expressed as follows:

[0051] Fc=F×(full code-gain error) / full code

[0052] For example, if the full code is equal to 4096 and the gain error is 106, then Fc=F×(4096−106) / 4096. In some examples, a sigma-delta modulator calculates the gain correction fraction Fc that is used to generate the main DTC code MAIN_DTC_CODE.

[0053] The FOD 100 described herein may include one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources). The FOD 100 may include only semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted, at the time of manufacture or after manufacture, by an end user and / or a third party, etc., to couple to at least a portion of the passive elements and / or sources to form the described structure.

[0054] 2 is a block diagram of an example digital controller 120. The digital controller 120 includes a state machine 204 having a first input 206 coupled to receive an average value AVG from the average calculation unit 196. The state machine 204 has a second input 250 coupled to receive an indication of whether the code is close to zero or close to full, and a third input 252 coupled to receive a calibration DTC code CALIB_CODE. The state machine 204 provides a gain error signal GAIN_ERROR at a first output 208, a calibration DTC code CALIB_CODE at a second output 210, and a multiplexer control signal MUX_CNTR at a third output 212. In some examples, the state machine 204 does not receive the calibration DTC code CALIB_CODE, but instead calculates the calibration DTC code CALIB_CODE based on the average value AVG and the indication of whether the code is close to zero or close to full. The state machine 204, or portions thereof, may be implemented in hardware (eg, logic circuitry, microprocessors, application specific integrated circuits), firmware, and / or software.

[0055] The digital controller 120 includes a sigma-delta modulator 220 having an input 222 coupled to receive a gain error signal GAIN_ERROR and providing a main DTC code MAIN_DTC_CODE at an output 224. The main DTC 140 receives MAIN_DTC_CODE and interpolates a fraction of a clock period of CLK_IN to add fractional periods between clock edges of DEL_IMD. This has the effect of producing a desired length between edges of CLK_OUT by adding fractional periods between the edges. The sigma-delta modulator 220, or portions thereof, may be implemented in hardware (e.g., logic circuitry, state machines, microprocessors, application specific integrated circuits), firmware, and / or software.

[0056] The digital controller 120 includes a code level detector 230 having an input 232 coupled to receive the main DTC code MAIN_DTC_CODE. The code level detector 230 compares the MAIN_DTC_CODE to a lower threshold and an upper threshold to detect whether a near-zero or near-full code has arrived. If a near-zero or near-full code is detected, the code level detector 230 provides an indication of the near-full or near-zero code at an output 234. The digital controller 120 includes a calibration code calculation unit 240 having an input 242 coupled to receive the indication of the near-zero or near-full code. The calibration code calculation unit 240 calculates a calibration code CALIB_CODE based on the near-zero or near-full code and provides CALIB_CODE at an output 244. The state machine 204 has a second input 250 coupled to receive the indication of the near-zero or near-full code and a third input 252 coupled to receive CALIB_CODE. In response to receiving inputs 250 and 252, state machine 204 provides a multiplexer control signal MUX_CNTR. If a near-zero code is detected, the MUX_CNTR signal instructs multiplexer 166 to select the signal at first input 168, and if a near-full code is detected, the MUX_SELECT signal instructs multiplexer 166 to select the signal at second input 170. Because the two-stage calibration described herein requires near-zero and near-full codes, if these two conditions are not detected, state machine 204 waits until the conditions occur.

[0057] In some examples, the digital controller 120 does not include the calibration code calculation unit 240. Instead, the state machine 204 calculates the calibration DTC code CALIB_CODE based on the first or second indicator received at the input 250. The code level detector 230 and the calibration code calculation unit 240 may be implemented in hardware (e.g., logic circuitry, a state machine, a microprocessor, an application specific integrated circuit), firmware, and / or software.

[0058] 3 is a flow chart of an example method 300. A near-zero code is detected at block 304. In one example, the code level detector 230 compares MAIN_DTC_CODE to a lower threshold, and if MAIN_DTC_CODE is less than the lower threshold, the code level detector 230 determines that a near-zero code has arrived.

[0059] At block 308, the calibration DTC code CALIB_CODE is set equal to MAIN_DTC_CODE. Therefore, CALIB_CODE is set equal to the detected near-zero code. In one example, the state machine 204 receives an indication of the near-zero code and sets CALIB_CODE equal to the near-zero code. At block 312, CALIB_CODE is adjusted to align an edge of CALIB_OUT (the output of the calibration DTC 150) with a corresponding edge of CLK_OUT (the output of the main DTC 140). In one example, the strong arm latch 188 receives the CLK_OUT and CALIB_OUT. The strong arm latch 188 determines which of each pair of received input signals arrived first and provides a binary number (0 or 1) at output 189 indicating which input signal arrived first. An average determination module 196 receives multiple outputs from the strong arm latch 188 in a set period, calculates an average AVG of the outputs, and provides the average AVG to the state machine 204. The state machine 204 receives the average value AVG and, in response, adjusts CALIB_CODE so that CALIB_OUT aligns with CLK_OUT.

[0060] In block 316, the input of the calibration DTC 150 is delayed by one additional clock period of CLK_IN relative to the input to the main DTC 140. In one example, the multiplexer 166 selects the signal from the second input 170 that is delayed by one clock period of CLK_IN by the second latch 160. Thus, the signal path to the input 152 of the calibration DTC 150 includes an additional delay of one clock period of CLK_IN relative to the signal path to the input 142 of the main DTC 140.

[0061] At block 320, a near-full code is detected. In one example, the code level detector 230 compares MAIN_DTC_CODE to an upper threshold, and if MAIN_DTC_CODE is greater than the upper threshold, the code level detector 230 determines that a near-full code has arrived and provides an indication of the near-full code to the state machine 204. At block 324, in response to the near-full code indication, the state machine 204 sets CALIB_CODE equal to 0 (the near-full code minus DTC1_CODE). At block 328, CALIB_CODE is then adjusted (i.e., increased or decreased) so that an edge of CALIB_OUT aligns with a corresponding edge of CLK_OUT.

[0062] In one example, for each pair of CLK_OUT and CALIB_OUT, the strong arm latch 188 determines which arrived first and provides a binary number (0 or 1) indicating which input signal arrived first. The average calculation unit 196 calculates the average of the samples of the output of the strong arm latch 188 and provides the average value AVG to the state machine 204 (which then adjusts the CALIB_CODE to align CALIB_OUT with CLK_OUT).

[0063] In block 332, the gain error of the main DTC 140 is determined from the incremental adjustment (e.g., the incremental increase or decrease provided via SAL 188) applied to CALIB_CODE from an initial code that is near or close to full to the adjusted code when CALIB_OUT is aligned with CLK_OUT. In some examples, in block 336, the gain error is used by the sigma-delta modulator 220 to calculate a gain correction fraction Fc that is used to generate the main DTC code MAIN_DTC_CODE. The method then returns to block 320.

[0064] In some examples, the gain error may be passed through a low pass filter (not shown in FIG. 3) to remove or suppress erroneous changes in the gain error. For example, the gain error calculated by state machine 204 may be passed through a low pass filter (not shown in FIG. 2) to remove high frequency components, and the filtered gain error is used by sigma delta modulator 220 to generate the main DTC code MAIN_DTC_CODE. The effect of this is that erroneous changes in the gain error do not affect the phase of CLK_OUT.

[0065] In some examples, after block 336, if a condition changes (not shown in FIG. 3), the method returns to block 304. For example, if the temperature sensed by the on-chip temperature sensor changes by a predefined threshold, the method returns to block 304. In some examples, the gain error measurement may be repeated multiple times and filtered before being applied to the main DTC 140.

[0066] 4A-4B are timing diagrams of an example calibration method of the DTC 150. In FIG. 4A, the x-axis represents time for the graphs for CLK_OUT and CALIB_OUT. The y-axis represents voltage for the graphs for CLK_OUT and CALIB_OUT. For the graph for CALIB_CODE, the y-axis ranges from 0 to 2 in this example. 124A represents the code values ​​varying from 0 to 100, while the x-axis does not indicate time. When MAIN_DTC_CODE is close to 0, CALIB_CODE is set to CALIB_CODE1, which is close to 0 (i.e., CALIB_CODE is set equal to MAIN_DTC_CODE). In response, the main DTC 140 outputs CLK_OUT and the calibration DTC 150 outputs CALIB_OUT1. Since the rising edge of CALIB_OUT1 lags the rising edge of CLK_OUT, CALIB_CODE is increased to CALIB_CODE2, thereby shifting the rising edge of CALIB_OUT2 closer to the rising edge of CLK_OUT, but CALIB_OUT2 is still not aligned with CLK_OUT. This process is repeated until CALIB_CODE is adjusted to CALIB_CODE4, thereby shifting CALIB_OUT4 to be aligned with CLK_OUT. In the example of FIG. 4A, only the rising edge of CALIB_OUT is shifted by changing CALIB_CODE. In some examples (not shown in FIG. 4A), both the rising and falling edges of CALIB_OUT may not be aligned with the corresponding edges of CLK_OUT, thus requiring adjustment of both the rising and falling edges of CALIB_OUT to align CALIB_OUT with CLK_OUT.

[0067] In FIG. 4B, the x-axis represents time for the graphs for CLK_OUT and CALIB_OUT. The y-axis represents voltage for the graphs for CLK_OUT and CALIB_OUT. For the graph for CALIB_CODE, the y-axis ranges from 0 to 2 in this example. 124B represents the code value varying from 0 to 100, the x-axis does not indicate time. When MAIN_DTC_CODE is a near-full code, CALIB_CODE is set to CALIB_CODE1=near-full code. In response, the main DTC 140 outputs CLK_OUT and the calibration DTC 150 outputs CALIB_OUT1. Because the rising edge of CALIB_OUT1 lags the rising edge of CLK_OUT, CALIB_CODE is reduced to CALIB_CODE2, so that the rising edge of CALIB_OUT2 is closer to the rising edge of CLK_OUT, but CALIB_OUT2 is still not aligned with CLK_OUT. This process is repeated until CALIB_CODE is adjusted to CALIB_CODE4, so that CALIB_OUT4 shifts and aligns with CLK_OUT. In the example of FIG. 4B, only the rising edge of CALIB_OUT is shifted by changing CALIB_CODE. In some instances, both the rising and falling edges of CALIB_OUT may not be aligned with the corresponding edges of CLK_OUT, and therefore adjustments to both the rising and falling edges of CALIB_OUT are required to align CALIB_OUT with CLK_OUT.

[0068] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, (a) in a first example, device A is coupled to device B, or (b) in a second example, device A is coupled to device B via an intervening component C, such that device B is controlled by device A via a control signal provided by device A, if the intervening component C does not substantially change the functional relationship between device A and device B. A device that is "configured" to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform that function by a manufacturer at the time of manufacture and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through the construction and / or layout of the hardware components and the interconnection of the devices, or a combination thereof. Also, a circuit or device including certain components may instead be configured to be coupled to those components to form the described circuit elements or devices. For example, one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be coupled to at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or a third party, to form the described configurations.

[0069] As used herein, the terms "terminal," "node," "interconnect," and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms are used generally to mean an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0070] Some examples suggest that certain elements are included in an integrated circuit while other elements are external to the integrated circuit. In other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and / or some features illustrated as being in the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (i) incorporated in or on a semiconductor substrate, (ii) incorporated in a single semiconductor package, (iii) incorporated in the same module, and / or (iv) incorporated in or on the same printed circuit board.

[0071] Although certain components are described as being of a particular process technology, these components may be interchangeable with other process technologies. The circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to that available prior to the component replacement. Unless otherwise noted, a component illustrated as a resistor generally represents any one or more elements coupled in series or parallel to provide the amount of impedance represented by the illustrated resistor. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors coupled in series or parallel between the same two nodes as a single resistor or capacitor, respectively. Additionally, the use of the term "ground" in this description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or appropriate to the teachings of this description. Unless otherwise noted, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the stated value.

[0072] Modifications in the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. 1. A system comprising: a first digital-to-time converter (DTC) having a first input, a second input, and a first DTC output; a calibration DTC having a first input, a second input, and a calibration DTC output; a latching comparator having a first input coupled to the first DTC output, a second input coupled to the calibration DTC output, and a latching comparator output; an average calculation module having an input coupled to the latched comparator output and an output; a digital controller having an input coupled to an output of the average calculation module, the digital controller operable to provide a DTC code, a calibration DTC code, and a gain error signal; Including, the system.

2. 10. The system of claim 1, The system, wherein the digital controller includes a sigma-delta modulator having an input adapted to receive the gain error signal, the sigma-delta modulator operable to provide the DTC code.

3. 10. The system of claim 1, The system includes a code level detector, wherein the digital controller has an input adapted to receive the DTC code, the code level detector operable to provide a first indication when the DTC code is less than a lower threshold and to provide a second indication when the DTC code is greater than an upper threshold.

4. 4. The system of claim 3, The system further includes a state machine, wherein the digital controller has a first input adapted to receive an average value and a second input adapted to receive the first indicator or the second indicator, the state machine being operable to provide the gain error signal and the calibration DTC code.

5. 5. The system of claim 4, The system, wherein the state machine is further operable to adjust the calibration DTC code to approach the average value of 0.

5.

6. 5. The system of claim 4, The system, wherein the state machine is further operable to adjust the calibration DTC code to bring the average value closer to 0.5, thereby aligning the output clock signal with the calibration output signal.

7. 10. The system of claim 1, The system wherein the output value provided by the latched comparator is a binary number indicating whether the output clock signal or the calibration output signal is received first.

8. 1. A system comprising: a state machine having a first input, a second input, a first output, and a second output; a first digital-to-time converter (DTC) having a first input, a second input, and an output; a calibration DTC having a first input, a second input coupled to the second output of the state machine, and an output; a latching comparator having a first input coupled to the output of the first DTC, a second input coupled to the output of the calibration DTC, and an output; an average calculation module having an input coupled to the output of the latched comparator and an output coupled to a first input of the state machine; a code level detector having an input coupled to a second input of the first DTC and an output, the code level detector operable to provide a first indicator signal at the output when the first DTC code is less than a lower threshold and to provide a second indicator signal at the output when the first DTC code is greater than an upper threshold; a calibration DTC code calculation module having a first input coupled to an output of the code level detector and an output coupled to a second input of the state machine, the calibration DTC code calculation module operable to provide a calibration DTC code at the output; a sigma-delta modulator having an input coupled to an output of the first state machine and an output coupled to a second input of the first DTC, the sigma-delta modulator operable to provide the first DTC code at its output; Including, the system.

9. 9. The system of claim 8, the mean value signal indicates a mean value; The system wherein the state machine is operable to adjust the calibration DTC code to approach the average value of 0.

5.

10. 10. The system of claim 9, The system, wherein the state machine is further operable to adjust the calibration DTC code to bring the average value closer to 0.5, thereby aligning the output clock signal with the calibration output signal.

11. 9. The system of claim 8, The system wherein the latching comparator is operable to provide a binary number indicating whether the output clock signal or the calibration output signal is received first.

12. 12. The system of claim 11, The system, wherein the mean calculation module is operable to provide a mean value of the binary numbers.

13. 1. A method of calibrating a first digital time converter (DTC) using a calibration digital time converter (DTC), comprising: receiving, by the first DTC, a first digital code and a first clock signal; providing, by the first DTC, an output clock signal in response to receiving the first digital code and a first clock signal; providing a first calibration digital code and a second clock signal to the calibration DTC to provide a calibration output signal when the first digital code is less than a lower threshold, wherein the first calibration digital code is equal to the first digital code; adjusting the first calibration digital code to align the calibration output signal with the clock output signal; delaying the second clock signal applied to the calibration DTC by one clock period; providing a third digital code to the first DTC; providing a second calibration digital code to the calibration DTC if the third digital code is greater than an upper threshold; adjusting the second calibration digital code to align the output clock signal and the calibration output signal; A method comprising:

14. 14. The method of claim 13, The method further includes determining a gain error of the first DTC from the adjusted second calibration digital code applied to the calibration DTC.

15. 14. The method of claim 13, The method further includes aligning edges of the output clock signal with corresponding edges of the calibration output signal by adjusting the second calibration digital code applied to the calibration DTC.

16. 14. The method of claim 13, The method, wherein adjusting the first calibration digital code includes measuring a time difference between the output clock signal and the calibration output signal.

17. 14. The method of claim 13, adjusting the first calibration digital code; providing a binary output in response to said output clock signal and said calibration output signal indicating whether said output clock signal or said calibration output signal is received first; determining an average value of the binary output; adjusting the calibration digital code until the average value of the binary output is close to 0.5; A method comprising:

18. 18. The method of claim 17, The method of claim 1, wherein the output clock signal and the calibration output signal are aligned when the average value is close to 0.

5.

19. 14. The method of claim 13, The method further includes determining a gain error of the first DTC from the adjusted second calibration digital code applied to the calibration DTC.

20. 20. The method of claim 19, The method further comprising generating the first digital code using the gain error.

Images