Recess structure for padless stacked vias

Abstract

A stacked via structure is disclosed in which multiple vias are stacked on top of one another. At least one via is a via having a recess formed from a top surface of at least one via. Another via above the via is formed such that the bottom of the other via is within the recess of the via. In this manner, no capture pad is required between the via and the other via. Also, the contact area between the via and the other via is increased.

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor devices and more particularly, but not exclusively, to recess structures for padless stacked vias and stacked layer structures and fabrication techniques thereof. [Background technology]

[0002] Integrated circuit technology has achieved great strides in increasing computing power by miniaturizing active and passive components. Packaged devices can be found in many electronic devices including processors, servers, radio frequency (RF) integrated circuits, etc. Packaging technologies have become cost-effective for high pin count devices and / or high production volume parts.

[0003] Stacked via structure design rules specify large pads for safe landing. For stacked via applications, larger landing pad (also called capture pad) design rules are applied to improve placement accuracy, which is directly related to via bottom stress and reliability issues. Furthermore, stacked via pads affect the via pad dimensions and design flexibility of all layers due to reduced routing space.

[0004] Therefore, there is a need for systems, devices, and methods that overcome the shortcomings of conventional stacked via structures, including the methods, systems, and devices provided herein. Summary of the Invention [Means for solving the problem]

[0005] The following presents a simplified summary of one or more aspects and / or examples related to the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview of all contemplated aspects and / or examples, nor should it be considered to identify key or critical elements of all contemplated aspects and / or examples or to delineate the scope related to any particular aspect and / or example. As such, the following summary is intended only to present certain concepts related to one or more aspects and / or examples related to the apparatus and methods disclosed herein in a simplified form prior to the detailed description presented below.

[0006] An exemplary stacked via structure is disclosed. The stacked via structure may include a capture pad. The stacked via structure may also include a first via stacked on top of and electrically coupled to the capture pad. The stacked via structure may further include a second via stacked on top of and electrically coupled to the first via. The stacked via structure may further include a cover pad stacked on top of and electrically coupled to the second via. A top width of the first via may be wider than a bottom width of the second via. A recess may be formed in the first via to extend partially into a top surface of the first via. A bottom of the second via may be within the recess. A bottom of the second via may extend from a bottom surface of the second via to a height equal to a depth of the recess. The second via may contact the first via within the recess.

[0007] An exemplary stack layer structure is disclosed. The stack layer structure may include a capture pad and an inner via formed in an inner dielectric layer. The inner via may be stacked on and electrically coupled to the capture pad. The stack layer structure may also include one or more intermediate vias formed in corresponding one or more intermediate dielectric layers stacked on the inner dielectric layer. The one or more intermediate vias may be stacked on and electrically coupled to the inner via. The stack layer structure may further include an outer via formed in an outer dielectric layer stacked on the one or more intermediate dielectric layers. The outer via may be stacked on and electrically coupled to the one or more intermediate vias. The stack layer structure may further include a cover pad stacked on and electrically coupled to the outer via. The stack layer structure may include a first via and a second via stacked on the first via. The first via may be an inner via or one of the one or more intermediate vias. The second via may be another one of the one or more intermediate vias or an outer via. A top width of the first via may be wider than a bottom width of the second via. A recess may be formed in the first via to extend partially into a top surface of the first via. A bottom of the second via may be within the recess. A bottom of the second via may extend from a bottom surface of the second via to a height equal to a depth of the recess. The second via may contact the first via within the recess.

[0008] An exemplary method of fabricating a stacked via structure is disclosed. The method may include forming a capture pad. The method may also include a first via stacked on and electrically coupled to the capture pad. The method may further include forming a second via stacked on and electrically coupled to the first via. The method may further include forming a cover pad stacked on and electrically coupled to the second via. A top width of the first via may be wider than a bottom width of the second via. A recess may be formed in the first via to extend partially into a top surface of the first via. A bottom of the second via may be within the recess. A bottom of the second via may extend from a bottom surface of the second via to a height equal to a depth of the recess. The second via may contact the first via within the recess.

[0009] An exemplary method of fabricating a stacked layer structure is disclosed. The method may include forming a capture pad and an inner via in an inner dielectric layer. The inner via may be stacked on and electrically coupled to the capture pad. The method may also include forming one or more intermediate vias in a corresponding one or more intermediate dielectric layers stacked on the inner dielectric layer. The one or more intermediate vias may be stacked on and electrically coupled to the inner via. The method may further include forming an outer via in an outer dielectric layer stacked on the one or more intermediate dielectric layers. The outer via may be stacked on and electrically coupled to the one or more intermediate vias. The method may further include forming a cover pad stacked on and electrically coupled to the outer via. The stacked layer structure may include a first via and a second via stacked on the first via. The first via may be an inner via or one of the one or more intermediate vias. The second via may be another one of the one or more intermediate vias or an outer via. A top width of the first via may be greater than a bottom width of the second via. A recess may be formed in the first via to extend partially into a top surface of the first via. A bottom of the second via may be within the recess. A bottom of the second via may extend from a bottom surface of the second via to a height equal to a depth of the recess. The second via may contact the first via within the recess.

[0010] Other features and advantages associated with the apparatus and methods disclosed herein will become apparent to one with ordinary skill in the art upon review of the following drawings and detailed description.

[0011] A more complete understanding of the aspects of the present disclosure and many of its attendant advantages will be readily obtained as they become better understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, which are presented merely to illustrate and not to limit the disclosure, and in which: [Brief description of the drawings]

[0012] [Figure 1A]1 shows a cross-sectional view of layers of a conventional stacked via structure. [Figure 1B] 1 shows a top view of layers of a conventional stacked via structure. [Figure 2A] 1 illustrates a cross-sectional view of layers of an exemplary stacked via structure according to one or more aspects of the present disclosure. [Figure 2B] 1 illustrates a top view of a layer of an exemplary stacked via structure according to one or more aspects of the present disclosure. [Diagram 3] 1 illustrates a detailed view of an exemplary via structure, according to one or more aspects of the present disclosure. [Figure 4A] 1A-1D show diagrams of example stages in fabricating a stack layer structure according to one or more embodiments of the present disclosure. [Figure 4B] 1A-1D show diagrams of example stages in fabricating a stack layer structure according to one or more embodiments of the present disclosure. [Figure 4C] 1A-1D show diagrams of example stages in fabricating a stack layer structure according to one or more embodiments of the present disclosure. [Figure 4D] 1A-1D show diagrams of example stages in fabricating a stack layer structure according to one or more embodiments of the present disclosure. [Figure 4E] 1A-1D show diagrams of example stages in fabricating a stack layer structure according to one or more embodiments of the present disclosure. [Figure 4F] 1A-1D show diagrams of example stages in fabricating a stack layer structure according to one or more embodiments of the present disclosure. [Figure 4G] 1A-1D show diagrams of example stages in fabricating a stack layer structure according to one or more embodiments of the present disclosure. [Figure 4H] 1A-1D show diagrams of example stages in fabricating a stack layer structure according to one or more embodiments of the present disclosure. [Figure 4I] 1A-1D show diagrams of example stages in fabricating a stack layer structure according to one or more embodiments of the present disclosure. [Figure 5A] 1A-1D show diagrams of example stages in fabricating another stack layer structure, according to one or more embodiments of the present disclosure. [Figure 5B] 1A-1D show diagrams of example stages in fabricating another stack layer structure, according to one or more embodiments of the present disclosure. [Figure 5C] 1A-1D show diagrams of example stages in fabricating another stack layer structure, according to one or more embodiments of the present disclosure. [Figure 5D] 1A-1D show diagrams of example stages in fabricating another stack layer structure, according to one or more embodiments of the present disclosure. [Figure 5E] 1A-1D show diagrams of example stages in fabricating another stack layer structure, according to one or more embodiments of the present disclosure. [Figure 5F] 1A-1D show diagrams of example stages in fabricating another stack layer structure, according to one or more embodiments of the present disclosure. [Figure 5G] 1A-1D show diagrams of example stages in fabricating another stack layer structure, according to one or more embodiments of the present disclosure. [Figure 6] 1 illustrates a flowchart of an example method for fabricating a stacked via structure in accordance with one or more aspects of the present disclosure. [Figure 7] 1 illustrates a flowchart of an exemplary method for fabricating a stack layer structure in accordance with one or more aspects of the present disclosure. [Figure 8] 1 illustrates a flowchart of an exemplary method for fabricating a stack layer structure in accordance with one or more aspects of the present disclosure. [Figure 9] 1 illustrates a flowchart of another exemplary method for fabricating a stack layer structure, according to one or more aspects of the present disclosure. [Figure 10] 13 shows a flowchart of a further exemplary method for fabricating a stack layer structure, according to one or more aspects of the present disclosure. [Figure 11] 1 illustrates various electronic devices that may utilize one or more aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Other objects and advantages associated with the aspects disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. According to common practice, features illustrated by the drawings may not be drawn to scale. Thus, dimensions of illustrated features may be arbitrarily expanded or reduced for clarity. According to common practice, some of the drawings have been simplified for clarity. Thus, the drawings may not show all components of a particular apparatus or method. Moreover, like reference numerals refer to like features throughout the specification and figures.

[0014] Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternative aspects or embodiments may be devised without departing from the scope of the teachings herein. In addition, well-known elements of the exemplary embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

[0015] In some described exemplary implementations, instances are identified where portions of the structure and operation of various components may be derived from known conventional techniques and configured in accordance with one or more exemplary embodiments. In such instances, some internal details of the structure and / or operation of known conventional components may be omitted to help avoid potentially obscuring the concepts illustrated in the exemplary embodiments disclosed herein.

[0016] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. It is further to be understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] 1A shows a cross-sectional view of a conventional stacked via structure 100. As can be seen, the stacked via structure 100 includes vias 130 stacked vertically on top of one another. Each via 130 is on and in contact with a capture pad 110 (also called a landing pad). A cover pad 120 is on and in contact with the top via 130. The stacked via structure 100 uses the capture pads 110 and cover pads 120 for top and bottom connections.

[0018] As mentioned above, stacked via structure design rules specify large pads for safe landing. For stacked via applications, larger pad design rules are applied for improved placement accuracy. In particular, the diameter of the capture pad 110 is larger than the diameter of the via 130. This can be seen in FIG. 1B, which shows a top view of a layer of a conventional stacked via structure 100. To provide a margin for placement accuracy, the diameter of the capture pad 110 is designed to be larger than the diameter of the via 130. A pattern line 150 can electrically couple two vias 130 together within a layer through the capture pad 110. It should be noted that as the diameter of the capture pad 110 increases, the space available for signal routing decreases, which in turn means less design flexibility.

[0019] To address one or more problems of conventional stacked via structures, it is proposed to provide a stacked via structure in which vias may be stacked directly on top of each other. Thus, a capture pad is required between each pair of vias. An example of the proposed stacked via structure 200 is shown in FIG. 2A. From bottom to top, the stacked via structure 200 may comprise a capture pad 210, an inner via 242, a middle via 240, an outer via 244, and a cover pad 220. Before proceeding further, it is noted that terms such as top, bottom, top, bottom, left, right, etc. are used for ease of description. Unless otherwise stated, these terms should not be construed to imply absolute orientation. The stack of vias 240, 242, 244 and / or pads 210, 220 may be formed from a conductive material such as copper (Cu), aluminum (Al), etc.

[0020] The inner via 242 may be on and in contact with the capture pad 210, the intermediate via 240 may be on and in contact with the inner via 242, the outer via 244 may be on and in contact with the intermediate via 240, and the cover pad 210 may be on and in contact with the outer via 244. In this manner, the capture pad 210 may be electrically coupled to the cover pad 220 via the inner via 242, the intermediate via 240, and the outer via 244, in that order.

[0021] Note that between any two directly adjacent vias there is a recess structure (highlighted by a dashed oval) for stacking the adjacent vias. In particular, the bottom of an upper via (e.g., outer via 244 or middle via 240) may be inserted into a recess formed in a lower via (e.g., inner via 242 or middle via 240).

[0022] Also note that there is no landing pad between the upper and lower vias. This means that there may be additional space for routing. This can be seen in FIG. 2B, which shows a top view of a layer of the stacked via structure 200. Here, a pattern line 250 may electrically couple two vias 230 to each other within the layer. However, unlike the situation shown in FIG. 1B, there is no pad within the layer of the stacked via structure 200. Therefore, the pattern line 250 may directly contact the middle via 240. As a result, design flexibility can be increased by increasing the area available for routing signals.

[0023] It should be noted that although only one intermediate via 240 is shown in the stacked via structure 200 of Figure 2A, in practice there may be any number of intermediate vias 240 between the inner via 242 and the outer via 244. The capture pad 210 may then be electrically coupled to the cover pad 220 via the inner via 242, the one or more intermediate vias 240, and the outer via 244, in that order.

[0024] A more detailed view of the recess structure highlighted as an oval in FIG. 2A is shown in FIG. 3, showing a first via 340A and a second via 340B formed on the first via 340A. The first via 340A can be any via of the stacked via structure 200 other than the outer via 244. That is, the first via 340A can be the inner via 242 or one of the one or more intermediate vias 240. The first via 340A can then be stacked on top of the capture pad 210 and electrically coupled thereto. Note that stacked "on" does not necessarily require that the first via 340A be in contact with the inner via 242, although that is one possibility. For example, all of the one or more intermediate vias 240 can be stacked on top of the capture pad 210. However, only the inner via 242 can be in contact with the capture pad 210. More specifically, the top surface of the capture pad 210 may contact the bottom surface of the inner via 242 .

[0025] The second via 340B may be any via of the stacked via structure 200 other than the inner via 242. That is, the second via 340B may be one of the one or more intermediate vias 240 or the outer via 244. The second via 340B may then be stacked on top of and electrically coupled to the first via 340A. In this case, the first via 340A and the second via 340B may contact each other since they are directly adjacent vias.

[0026] In the context of FIG. 2A, the cover pad 220 may be stacked on top of and electrically coupled to the second via 340B. Again, stacked "on" does not necessarily mean in contact, but is a possibility. If the second via 340B is an outer via 244, the cover pad 220 may be on top of and in contact with the second via 340B. More specifically, the bottom surface of the cover pad 220 may be in contact with the top surface of the outer via 244. However, if the second via 340B is any one of the one or more intermediate vias 240, there is no contact between the cover pad 220 and the second via 340B.

[0027] In one aspect, the vias (e.g., inner via 242, one or more intermediate vias 240, outer via 244) may be tapered such that their respective top widths are wider than their bottom widths. In FIG. 3, this means that the first via 340A and / or the second via 340B may be tapered. If the first via 340A is tapered, the top width of the first via 340A may be wider than the bottom width of the first via 340A. For ease of reference, the top and bottom widths of the first via 340A may be referred to as the "first top width" and the "first bottom width", respectively. Similarly, if the second via 340B is tapered, the second top width (top width of the second via 340B) may be wider than the second bottom width (bottom width of the second via 340B). Also, as seen in FIG. 3, the first top width may be wider than the second bottom width.

[0028] The recess 345 may be formed to extend partially into the first via 340A from a top surface of the first via 340A. That is, the first via 340A may include a recess 345 that extends partially into the first via 340A from its top surface. A portion of the second via 340B that extends from a bottom surface of the second via 340B to a height equal to the depth of the recess 345 may be inserted into the recess 345. For ease of reference, this bottom of the second via 340B may be referred to as the "second bottom." The depth of the recess 345 may nominally be in the range of 5% to 15% of the total height of the first via 340A.

[0029] In one embodiment, the second bottom may contact the first via 340A in the recess 345, as highlighted by the dotted oval. Note that the recess 345 may be tapered such that the recess top width (top width of the recess 345) is wider than the recess bottom width (bottom width of the recess 345). The contact between the first via 340A and the second via 340B may be such that the side of the second bottom contacts the side of the recess 345. Similarly, the second bottom, i.e., the bottom surface of the second bottom (which is also the bottom of the second via 340B), may contact the bottom surface of the recess 345. Thus, the contact area may be increased, thereby enhancing structural integrity. That is, the first via 340A and the second via 340B may be better secured to each other.

[0030] In the context of FIG. 2A above, it is shown that there is no landing pad between the upper and lower vias. In FIG. 3, this can be translated to having no capture pad between the first via 340A and the second via 340B. Also, in the context of FIG. 2B, it is shown that the pattern line 250 can contact two vias in the same layer. In FIG. 3, this can be translated to the pattern line 250 contacting the first via 340A and a via (e.g., the via 240) on the same layer as the first via 340A. Alternatively or in addition, another pattern line 250 can contact the second via 340B and the same or different via (e.g., the same or different via 240) on the same layer as the second via 340B. Furthermore, in the context of FIG. 2A, it is shown that the capture pad 210 can be electrically coupled to the cover pad 220, to the inner via 242, to one or more intermediate vias 240, and to the outer via 244, in that order. 3, this translates to the capture pad 210 being electrically coupled to the cover pad 220 through a first via 340A and a second via 340B, in that order. Of course, it should be noted that there may be other vias (e.g., inner via 242, other intermediate vias 240, outer via 244) that may be in the electrical path between the capture pad 210 and the cover pad 220.

[0031] The stacked via structure 200 of Figures 2A, 2B, and 3 may be used in a stacked layer structure. Figures 4A-4I show example stages of fabricating a stacked layer structure according to one or more aspects of the present disclosure. Before describing the stages, attention is directed to Figure 4I, which shows an example stacked layer structure 400 in which the stacked via structure 200 may be incorporated. The stacked layer structure 400 may be an example of a stacked layer structure based on an embedded trace substrate (ETS).

[0032] 4I, the stacked layer structure 400 may include an initial layer 460, also referred to as a base layer 460. The capture pad 210 and the inner via 242 are formed in an inner dielectric layer 415, which may be stacked on top of the initial layer 460. The inner via 242 may be stacked on top of the capture pad 210 and electrically coupled thereto.

[0033] The stacked layer structure 400 may also include intermediate vias 240 formed in the intermediate dielectric layer 425, which itself may be stacked on the inner dielectric layer 415. Recall from above that the stacked via structure may include any number of intermediate vias 240. Thus, although one intermediate dielectric layer 425 is shown in FIG. 4I, there may be any number of intermediate dielectric layers 425. That is, the stacked layer structure 400 may include one or more intermediate vias 240 formed in a corresponding one or more intermediate dielectric layers 425, which may be stacked on the inner dielectric layer 415. The one or more intermediate vias 240 may be stacked on top of and electrically coupled to the inner vias 242.

[0034] The stacked layer structure 400 may further include an outer via 244 formed in an outer dielectric layer 435 that may be stacked on top of the one or more intermediate dielectric layers 425. The outer via 244 may be stacked on top of and electrically coupled to one or more intermediate vias 240.

[0035] The stacked layer structure 400 may further include a cover pad 220 stacked on and electrically coupled to the outer via 244. It should be noted that the cover pad 220 may be formed in a cover layer 445, which may be the outermost layer of the stacked layer structure 400. It should also be noted that the cover pad 220 may be exposed. That is, the cover pad 220 may be configured to enable a signal connection between the stacked layer structure 400 and a device external to the stacked layer structure 400. For example, the multiple cover pads 220 may function as a ball grid array (BGA).

[0036] In an aspect, the stack layer structure 400 can be said to comprise a first via 340A and a second via 340B as described with respect to Figure 3. The second via 340B can be stacked directly on the first via 340. The first via 340A can be the inner via 242 or one of the one or more intermediate vias 240. The second via 340B can be one of the one or more intermediate vias 240 or the outer via 244. Details of the first via 340A and the second via 340B are provided above and therefore will not be repeated here for the sake of brevity.

[0037] We will now describe the various stages of fabricating the stacked layer structure 400. Figure 4A shows a stage at which the capture pad 210 may be formed on a carrier 405.

[0038] 4B shows a stage where an inner dielectric layer 415 may be formed on the carrier 405 to cover the capture pad 210. For example, the inner dielectric layer 415 may be laminated onto the carrier 405.

[0039] 4C shows a stage where the inner dielectric layer 415 may be processed to form an inner via hole 417 to expose the capture pad 210. For example, the inner via hole 417 may be formed by laser drilling.

[0040] 4D shows a stage where the inner dielectric layer 415 and the inner via hole 417 can be plated with a conductive material (e.g., Cu, Al, etc.) to fill the inner via hole 417 and form the inner via 242. At this stage, no recess has yet been formed in the inner via 242.

[0041] 4E shows a stage where an intermediate via hole 427 may be formed in the intermediate dielectric layer 425. In one embodiment, the intermediate dielectric layer 425 may be laminated onto the inner dielectric layer 415. The intermediate dielectric layer 425 may then be drilled, for example by laser drilling, to expose the inner via 242. The drilling may also drill a recess in the inner via 242.

[0042] 4F shows a stage where the intermediate dielectric layer 425 and the intermediate via hole 427 may be plated with a conductive material (e.g., Cu, Al, etc.) to fill the intermediate via hole 427 and form the intermediate via 240. The intermediate via 240 may also fill the recess of the inner via 242. At this stage, the recess has not yet been formed in the intermediate via 240.

[0043] 4G shows a stage where an outer via hole 437 may be formed in the outer dielectric layer 435. In one embodiment, the outer dielectric layer 435 may be laminated onto the intermediate dielectric layer 425. The outer dielectric layer 435 may then be drilled, for example by laser drilling, to expose the intermediate via 240. The drilling may also drill a recess in the intermediate via 240.

[0044] 4H shows a stage where the outer dielectric layer 435 and the outer via hole 437 may be plated with a conductive material (e.g., Cu, Al, etc.) to form an outer via 244 to fill the intermediate via hole 427. The outer via 244 may also fill the recess of the intermediate via 240.

[0045] 4I shows a stage where the carrier 405 may be removed and an initial layer 460 may be formed under the inner dielectric layer 415. Also, a cover pad 220 may be formed on the outer dielectric layer 435, and then a cover layer 445 may be formed (e.g., laminated) on the outer dielectric layer 435 and the cover pad 220, and then processed to expose the cover pad 220.

[0046] Although not shown, it should be noted that multiple intermediate dielectric layers 425 and corresponding multiple intermediate vias 240 may be fabricated by repeating the steps shown in Figures 4E and 4F.

[0047] 5A-5G show example stages of fabricating another stacked layer structure according to one or more embodiments of the present disclosure. Before describing the stages, attention is directed to FIG. 5G, which shows an example stacked layer structure 500 into which the stacked via structure 200 may be incorporated. The stacked layer structure 500 may be an example of a stacked layer structure based on a semi-additive process (SAP) or modified SAP (mSAP) substrate.

[0048] As seen in FIG. 5G, the stacked layer structure 500 may include an initial layer 560, also referred to as a core layer 560. Note that there are two stacked via structures, one above the core layer and one below the core layer. For ease of reference, the portions of the stacked layer structure 500 above the core layer 560 are referenced with elements ending with an "A" and the portions below the core layer 560 are referenced with elements ending with a "B."

[0049] The upper portion of the core layer 560 may be similar to the stacked layer structure 400 on the base layer 460 of Figure 4I. That is, the stacked layer structure 500 on the initial layer 560 may include a capture pad 210A and an inner via 242A formed in an inner dielectric layer 515A stacked on the initial layer 560. The inner via 242A may be stacked on top of and electrically coupled to the capture pad 210A.

[0050] The stacked layer structure 500 above the initial layer 560 may also include an intermediate via 240A formed in an intermediate dielectric layer 525A stacked on the inner dielectric layer 515A. Again, although one intermediate via 240A formed in one intermediate dielectric layer 515A is shown, the stacked layer structure 500 may include one or more intermediate vias 240A formed in a corresponding one or more intermediate dielectric layers 525A stacked on the inner dielectric layer 515A. The one or more intermediate vias 240A may be stacked on top of and electrically coupled to the inner via 242A.

[0051] The stacked layer structure 500 above the initial layer 560 may further include an outer via 244A formed in an outer dielectric layer 535A stacked on top of one or more intermediate dielectric layers 525A. The outer via 244A may be stacked on top of and electrically coupled to one or more intermediate vias 240A.

[0052] The stacked layer structure 500 above the initial layer 560 may further include a cover pad 220A stacked on and electrically coupled to the outer via 244A. The cover pad 220A may be formed in a cover layer 445A, which may be the outermost layer of the stacked layer structure 500 above the initial layer 560. The cover pad 220A may be exposed. For example, the cover pad 220A may be configured to allow a signal connection with a device external to the stacked layer structure 500.

[0053] In an aspect, the stacked layer structure 500 above the initial layer 560 can be said to comprise a first via 340A and a second via 340B as described with respect to FIG. 3. The second via 340B can be stacked directly on the first via 340A. The first via 340A can be an inner via 242 or one of the one or more intermediate vias 240. The second via 340B can be one of the one or more intermediate vias 240 or an outer via 244. Details of the first via 340A and the second via 340B are provided above and therefore will not be repeated here for the sake of brevity.

[0054] The lower portion of the core layer 560 may be similar to the upper portion of the core layer 560, but in the opposite direction (e.g., downward). The term "lower" is used to distinguish the components below the core layer 560 from the components above. The stack layer structure 500 below the initial layer 560 may include a lower capture pad 210B and a lower inner via 242B formed in a lower inner dielectric layer 515B stacked below the initial layer 560. The lower inner via 242B may be stacked below the lower capture pad 210B and electrically coupled to the lower capture pad 210B.

[0055] The stacked layer structure 500 below the initial layer 560 may also include a lower intermediate via 240B formed in a lower intermediate dielectric layer 525B stacked below the lower inner dielectric layer 515B. Although one lower intermediate via 240B formed in one lower intermediate dielectric layer 525B is shown, the stacked layer structure 500 may include one or more lower intermediate vias 240B formed in a corresponding one or more lower intermediate dielectric layers 525B stacked below the lower inner dielectric layer 515B. One or more lower intermediate vias 240B may be stacked below and electrically coupled to the lower inner vias 242B. It should be noted that the number of intermediate dielectric layers 525A above the core layer 560 may be independent of the number of lower intermediate layers 525B below the core layer 560.

[0056] The stacked layer structure 500 below the initial layer 560 may further include a lower outer via 244B formed in a lower outer dielectric layer 535B stacked below the one or more lower intermediate dielectric layers 525B. The lower outer via 244B may be stacked below and electrically coupled to one or more intermediate vias 210B.

[0057] The stacked layer structure 500 below the initial layer 560 may further include a bottom cover pad 220B stacked below and electrically coupled to the bottom outer via 244B. The bottom cover pad 220B may be formed in a bottom cover layer 445B, which may be the outermost layer of the stacked layer structure 500 below the initial layer 560. The bottom cover pad 220B may be exposed. For example, the bottom cover pad 220B may be configured to enable a signal connection with a device external to the stacked layer structure 500.

[0058] In an aspect, it can be said that the stacked layer structure 500 below the initial layer 560 comprises first and second lower vias, which can be similar to the first via 340A and the second via 340B as described with respect to FIG. 3, except that the orientation can be reversed (not shown). It can then be said that the second lower via can be stacked directly below the first lower via. The first lower via can be the lower inner via 242B or one of the one or more lower intermediate vias 240B. The lower second via can be one of the one or more lower intermediate vias 240B or the lower outer via 244B.

[0059] Although stacked via structures on both sides of the initial layer 560 are shown, this is by way of example only. It is contemplated that the proposed stacked via structures of Figures 2A, 2B, and 3 could be on one or both sides of the initial layer 560.

[0060] We will now describe the various stages of fabricating the stacked layer structure 500. For purposes of explanation, we will assume that the proposed stacked via structure is formed both above and below the initial layer 560. Figure 5A shows the stages where the capture pad 210A may be formed above the initial (or core) layer 560 and the lower capture pad 210B may be formed below the initial layer 560. One or both of the capture pad 210A and the lower capture pad 210B may contact the initial layer 560.

[0061] 5B shows a stage where an inner dielectric layer 515A may be formed on the initial layer 560 to cover the capture pad 210A. Also, a lower inner dielectric layer 515B may be formed below the initial layer 560 to cover the lower capture pad 210B. For example, the inner dielectric layer 515A may be laminated on the initial layer 560. Alternatively or additionally, the lower inner dielectric layer 515B may be laminated below the initial layer 560.

[0062] 5C shows a stage where the inner dielectric layer 515A can be processed to form an inner via hole 517A to expose the capture pad 210A. Similarly, the lower inner dielectric layer 515B can be processed to form a lower inner via hole 517B to expose the lower capture pad 210B. The inner via hole 517A and / or the lower inner via hole 517B can be formed by laser drilling.

[0063] 5D shows a stage where the inner dielectric layer 515A and the inner via hole 517A can be plated with a conductive material (e.g., Cu, Al, etc.) to form the inner via 242A so as to fill the inner via hole 517A. At this stage, the recess has not yet been formed in the inner via 242A. Alternatively or additionally, the lower inner dielectric layer 515B and the lower inner via hole 517B can be plated with a conductive material (e.g., Cu, Al, etc.) to form the lower inner via 242B so as to fill the lower inner via hole 517B. At this stage, the lower recess has not yet been formed in the lower inner via 242B.

[0064] 5E shows a stage where an intermediate via hole 527A can be formed in the intermediate dielectric layer 525A. The intermediate dielectric layer 525A can be laminated onto the inner dielectric layer 515A and then drilled, for example by laser drilling. The drilling can also drill a recess in the inner via 242A.

[0065] Alternatively or additionally, a lower intermediate via hole 527B may be formed in the lower intermediate dielectric layer 525B. The lower intermediate dielectric layer 525B may be laminated below the lower inner dielectric layer 515B and then drilled, for example, by laser drilling. The drilling may also drill a lower recess in the lower inner via 242B.

[0066] 5F shows a stage where the intermediate dielectric layer 525A and the intermediate via hole 527A may be plated with a conductive material (e.g., Cu, Al, etc.) to fill the intermediate via hole 527A and form an intermediate via 240A. The intermediate via 240A may also fill the recess of the inner via 242A. At this stage, the recess has not yet been formed in the intermediate via 240A.

[0067] Alternatively or additionally, the lower intermediate dielectric layer 525B and the lower intermediate via hole 527B may be plated with a conductive material (e.g., Cu, Al, etc.) to fill the lower intermediate via hole 527B and form the lower intermediate via 240B. The lower intermediate via 240B may also fill the recess of the lower inner via 242B. At this stage, the lower recess has not yet been formed in the lower intermediate via 240B.

[0068] 5G shows a stage where an outer dielectric layer 535A may be laminated on the intermediate dielectric layer 525A and drilled (e.g., by a laser) to form a recess in the intermediate via 240A. The outer dielectric layer 535A and the intermediate via 240A may be plated with a conductive material (e.g., Cu, Al, etc.) to form an outer via 244A, which may also fill the recess in the intermediate via 240A. A cover pad 220A may be formed on the outer dielectric layer 535A, and a cover layer 545A may then be formed (e.g., laminated) on the outer dielectric layer 535A and the cover pad 220A, which may then be further processed to enable, for example, connection to an external device.

[0069] Alternatively or additionally, the lower outer dielectric layer 535B may be laminated and drilled (e.g., by a laser) under the lower intermediate dielectric layer 525B, which may also form a lower recess in the lower intermediate via 240B. The lower outer dielectric layer 535B and the lower intermediate via 240B may be plated with a conductive material (e.g., Cu, Al, etc.) to form the lower outer via 244B, which may also fill the lower recess of the lower intermediate via 240B. The lower cover pad 220B may be formed under the lower outer dielectric layer 535B, and then the lower cover layer 545B may be formed (e.g., laminated) under the lower outer dielectric layer 535B and the lower cover pad 220B. The lower cover layer 545B may then be further processed, for example, to enable connection to an external device.

[0070] 5E and 5F, multiple intermediate dielectric layers 525A and corresponding multiple intermediate vias 240A may be fabricated. Alternatively or additionally, multiple lower intermediate dielectric layers 525B and corresponding multiple lower intermediate vias 240B may be fabricated. Again, the number of intermediate dielectric layers 525A may be independent of the number of lower intermediate dielectric layers 525B.

[0071] 6 illustrates a flowchart of an example method 600 of fabricating a stacked via structure, such as stacked via structure 200, in accordance with one or more aspects of the present disclosure. At block 610, a capture pad 210 may be formed.

[0072] At block 620, a first via 340A may be formed. The first via 340A may be stacked on top of and electrically coupled to the capture pad 210. A recess 345 may be formed to extend partially into the first via 340A from a top surface of the first via 340A. In one embodiment, the recess 345 may be formed by a drilling process, such as laser drilling.

[0073] In block 630, a second via 340B may be formed. The second via 340B may be stacked on top of and electrically coupled to the first via 340A. A second bottom (a portion of the second via 340B extending from the bottom surface of the second via 340B to a height equal to the depth of the recess 345) may be in the recess 345. Thus, the second via 340B may contact the first via 340A in the recess 345. Details of the first via 340A and the second via 340B are described above with respect to Figures 2A, 2B, and 3 and therefore will not be repeated here for brevity.

[0074] At block 640, the cover pad 220 may be formed. The cover pad 220 may be stacked over and electrically coupled to the second via 340B.

[0075] 7 illustrates a flowchart of an exemplary method 700 for fabricating a stacked layer structure, such as stacked layer structure 400 or 500, in accordance with one or more aspects of the present disclosure. In block 710, the capture pads 210, 210A and the inner vias 242, 242A may be formed in the inner dielectric layers 415, 515A. The inner vias 242, 242A may be stacked on top of and electrically coupled to the capture pads 210, 210A.

[0076] At block 720, one or more intermediate vias 240, 240A may be formed in corresponding one or more intermediate dielectric layers 425, 525A, which may be stacked on top of the inner dielectric layers 415, 515A. The one or more intermediate vias 240, 240A may be stacked on top of and electrically coupled to the inner vias 242, 242A.

[0077] In block 730, the outer vias 244, 244A may be formed in the outer dielectric layers 435, 535A, which may be stacked on top of the one or more intermediate dielectric layers 425, 525A. The outer vias 244, 244A may be stacked on top of and electrically coupled to the one or more intermediate vias 240, 240A.

[0078] In one aspect, the inner via 242, 242A or one of the one or more intermediate vias 240, 240A may function as the first via 340A, and one of the one or more intermediate vias 240, 240A or the outer via 244A may function as the second via 340B. Details of the first via 340A and the second via 340B are described above with respect to Figures 2A, 2B, and 3 and therefore will not be repeated here for the sake of brevity.

[0079] At block 740, the cover pads 220, 220A may be formed. The cover pads 220, 220A may be stacked on top of and electrically coupled to the outer vias 244, 244A.

[0080] Blocks 710-740 may be performed to fabricate stacked layer structure 400, or to fabricate a portion of stacked layer structure 500 above initial layer 560. Optionally (as indicated by dashed rectangle), block 750 may be performed to fabricate a portion of stacked layer structure 500 below initial layer 560.

[0081] 8 shows a flow chart of an exemplary process for implementing block 750. In block 810, the lower capture pad 210B and the lower inner via 242B may be formed in the lower inner dielectric layer 515B. The lower inner via 242B may be stacked below and electrically coupled to the lower capture pad 210B.

[0082] In block 820, one or more lower intermediate vias 240B may be formed in corresponding one or more lower intermediate dielectric layers 525B, which may be stacked on top of the lower inner dielectric layer 515B. One or more lower intermediate vias 240B may be stacked on top of and electrically coupled to the lower inner vias 242B.

[0083] In block 830, a lower outer via 244B may be formed in a lower outer dielectric layer 535B, which may be stacked on top of the one or more lower intermediate dielectric layers 525B. The lower outer via 244B may be stacked on top of and electrically coupled to the one or more lower intermediate vias 240B.

[0084] In one aspect, the lower inner via 242B or one of the one or more lower intermediate vias 240B may function as a first lower via, and one of the one or more lower intermediate vias 240B or the lower outer via 244B may function as a second lower via. Details of the first and second lower vias are provided above and therefore will not be repeated here for the sake of brevity.

[0085] At block 840, the lower cover pad 220B may be formed. The lower cover pad 220B may be stacked on top of and electrically coupled to the lower outer via 244B.

[0086] 9 illustrates a flowchart of another exemplary method 900 of fabricating a stack layer structure, such as stack layer structure 400, in accordance with one or more aspects of the present disclosure. In block 910, a pattern layer may be formed on a carrier (e.g., carrier 405). A capture pad (e.g., capture pad 210) may be formed as part of the pattern layer.

[0087] In block 920, a carrier (eg, carrier 405) may be laminated with a dielectric layer (eg, inner dielectric layer 415).

[0088] In block 930, a dielectric layer (eg, inner dielectric layer 415) may be drilled to expose a capture pad (eg, capture pad 210).

[0089] In block 940, a pattern layer may be formed on the dielectric layer (e.g., inner dielectric layer 415, middle dielectric layer 425). The pattern layer may include vias (e.g., inner vias 242, middle vias 240).

[0090] In block 950, a dielectric layer (eg, inner dielectric layer 415, middle dielectric layer 425) may be laminated with another dielectric layer (eg, middle dielectric layer 425, outer dielectric layer 435).

[0091] In block 960, another dielectric layer (eg, middle dielectric layer 425, outer dielectric layer 435) may be drilled to expose a via (eg, inner via 242, middle via 240).

[0092] Blocks 940, 950, 960 may be repeated multiple times to form one or more intermediate dielectric layers (e.g., one or more intermediate dielectric layers 425) and corresponding one or more intermediate vias (e.g., one or more intermediate vias 240). During the final repetition of blocks 940, 950, 960, an outer dielectric layer (e.g., outer dielectric layer 435) and outer vias (e.g., outer via 244) may be formed.

[0093] In block 970, the carrier (eg, carrier 405) may be removed.

[0094] At block 980, a base layer (e.g., base layer 460) may be formed. The base layer may underlie and contact an inner dielectric layer (e.g., inner dielectric layer 415).

[0095] In block 990, a cover layer (eg, cover layer 445) including a cover pad (eg, cover pad 220) may be formed on the outer dielectric layer (eg, outer dielectric layer 435).

[0096] 10 shows a flowchart of a further exemplary method 1000 of fabricating a stack layer structure, such as stack layer structure 500, in accordance with one or more aspects of the present disclosure. In block 1010, an upper pattern layer may be formed on a core layer (e.g., core layer 560). An upper capture pad (e.g., capture pad 210A) may be formed as part of the upper pattern layer. Alternatively or in addition, a lower pattern layer may be formed below the core layer. A lower capture pad (e.g., lower capture pad 210B) may be formed as part of the lower pattern layer.

[0097] In block 1020, an upper dielectric layer (e.g., inner dielectric layer 515A) may be laminated onto a core layer (e.g., core layer 560). Alternatively or additionally, a lower dielectric layer (e.g., lower inner dielectric layer 515B) may be laminated onto the core layer.

[0098] In block 1030, an upper dielectric layer (e.g., inner dielectric layer 515A) may be perforated to expose an upper capture pad (e.g., capture pad 210A). Alternatively or additionally, a lower dielectric layer (e.g., lower inner dielectric layer 515B) may be perforated to expose a lower capture pad (e.g., lower capture pad 210B).

[0099] At block 1040, an upper pattern layer may be formed on the upper dielectric layer (e.g., inner dielectric layer 515A, middle dielectric layer 525A). The upper pattern layer may include upper vias (e.g., inner vias 242A, middle vias 240A). Alternatively or in addition, a lower pattern layer may be formed on the lower dielectric layer (e.g., lower inner dielectric layer 515B, lower middle dielectric layer 525B). The lower pattern layer may include lower vias (e.g., lower inner vias 242B, lower middle vias 240B).

[0100] In block 1050, an upper dielectric layer (e.g., inner dielectric layer 515A, middle dielectric layer 525A) may be laminated with another upper dielectric layer (e.g., middle dielectric layer 525A, outer dielectric layer 535A). Alternatively or in addition, a lower dielectric layer (e.g., lower inner dielectric layer 515B, lower middle dielectric layer 525B) may be laminated with another lower dielectric layer (e.g., lower middle dielectric layer 525B, lower outer dielectric layer 535B).

[0101] In block 1060, another upper dielectric layer (e.g., intermediate dielectric layer 525A, outer dielectric layer 535A) may be drilled to expose the upper vias (e.g., inner vias 242A, intermediate vias 240A). Alternatively or additionally, another lower dielectric layer (e.g., lower intermediate dielectric layer 525B, lower outer dielectric layer 535B) may be drilled to expose the lower vias (e.g., lower inner vias 242B, intermediate vias 240B).

[0102] Blocks 1040, 1050, 1060 may be repeated multiple times to form one or more upper intermediate dielectric layers (e.g., one or more intermediate dielectric layers 525A) and corresponding one or more upper intermediate vias (e.g., one or more intermediate vias 240A). Alternatively or additionally, blocks 1040, 1050, 1060 may be repeated multiple times to form one or more lower intermediate dielectric layers (e.g., one or more lower intermediate dielectric layers 525B) and corresponding one or more lower intermediate vias (e.g., one or more lower intermediate vias 240B).

[0103] During the final iteration of blocks 1040, 1050, 1060, an upper outer dielectric layer (e.g., outer dielectric layer 535A) and an upper outer via (e.g., outer via 244A) may be formed. Alternatively or additionally, a lower outer dielectric layer (e.g., lower outer dielectric layer 535B) and a lower outer via (e.g., lower outer via 244B) may be formed.

[0104] At block 1090, an upper cover layer (e.g., cover layer 545A) including an upper cover pad (e.g., cover pad 220A) may be formed on the upper outer dielectric layer (e.g., outer dielectric layer 535A). Alternatively or in addition, a lower cover layer (e.g., lower cover layer 545B) including a lower cover pad (e.g., lower cover pad 220B) may be formed below the lower outer dielectric layer (e.g., lower outer dielectric layer 535B).

[0105] It will be understood that the foregoing fabrication process and related description are provided merely as general illustrations of some of the aspects of the present disclosure, and are not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details in the fabrication process known to those skilled in the art may be omitted or combined in a summary process section to facilitate understanding of the various aspects disclosed without detailed description of each detail and / or all possible process variations. Furthermore, it will be understood that the illustrated configurations and descriptions are provided merely to aid in the explanation of the various aspects disclosed herein. For example, the number and location of inductors, the metallization structure may have more or fewer conductive and insulating layers, the orientation, size, and other aspects of the cavities, whether formed of multiple cavities, closed or open, and other aspects may have variations driven by specific application design features, such as the number of antennas, antenna type, frequency range, power, etc. Thus, the foregoing illustrative examples and related figures should not be construed as limiting the various aspects disclosed and claimed herein.

[0106] 11 illustrates various electronic devices that may utilize one or more aspects of the present disclosure. For example, a mobile phone device 1102, a laptop computer device 1104, and a stationary terminal device 1106 may each generally be considered user equipment (UE) and may include any of the structures 1100 described herein (e.g., stacked via structure 200, stacked layer structure 400, or stacked layer structure 500). The devices 1102, 1104, 1106 illustrated in FIG. 11 are merely illustrative. Other electronic devices may also include stacked via structures and / or stacked layer structures including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented within automotive vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0107] The devices and functions disclosed above may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer readable medium. Some or all of such files may be provided to a fabricator who fabricates devices based on such files. The resulting product may include semiconductor wafers that are then cut into semiconductor dies and packaged with antennas on glass devices. The antennas on glass devices may then be used in devices described herein.

[0108] The following numbered clauses describe example implementations.

[0109] Clause 1: A stacked via structure comprising a capture pad, a first via stacked on top of the capture pad and electrically coupled to the capture pad, a second via stacked on top of the first via and electrically coupled to the first via, and a cover pad stacked on top of the second via and electrically coupled to the second via, wherein a top width of the first via is wider than a bottom width of the second via, a recess is formed in the first via to extend partially into a top surface of the first via, a bottom of the second via is within the recess, and a bottom of the second via extends from the bottom surface of the second via to a height equal to a depth of the recess, and the second via contacts the first via within the recess.

[0110] Clause 2: A stacked via structure as described in clause 1, wherein the first via is tapered such that the top width of the first via is wider than the bottom width of the first via, the second via is tapered such that the top width of the second via is wider than the bottom width of the second via, and the recess is tapered such that the top width of the recess is wider than the bottom width of the recess.

[0111] Clause 3: A stacked via structure described in clause 1 or 2, wherein a side surface of the bottom of the second via is in contact with a side surface of the recess, and a bottom surface of the bottom of the second via is in contact with a bottom surface of the recess.

[0112] Clause 4: The stacked via structure according to any one of clauses 1 to 3, wherein there is no capture pad between the first via and the second via.

[0113] Clause 5: A stacked via structure described in any one of clauses 1 to 4, wherein the second via is electrically coupled to another via in the same layer via a pattern line, and the second via is in contact with the pattern line.

[0114] Clause 6: A stacked via structure described in any of clauses 1 to 5, wherein the cover pad is a pad in a cover layer of a stacked layer structure comprising the stacked via structure, the cover layer being the outermost layer of the stacked layer structure, and the cover pad is configured for signal connection to an external device.

[0115] Clause 7: A stacked via structure described in any one of clauses 1 to 6, wherein between the first via and the second via, a capture pad is electrically connected to the cover pad via the first via and the second via, in that order.

[0116] Clause 8: The stacked via structure of any one of clauses 1 to 7, wherein the first via is formed from copper (Cu), the second via is formed from copper (Cu), or both.

[0117] Clause 9: The stacked via structure according to any one of clauses 1 to 8, wherein the depth of the recess is in the range of 5% to 15% of the height of the first via.

[0118] Clause 10: A stack via structure as described in any of clauses 1 to 9, wherein the stack via structure is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device within an automotive vehicle.

[0119] Clause 11: A method of fabricating a stacked via structure, comprising: forming a capture pad; forming a first via stacked on top of the capture pad and electrically coupled to the capture pad; forming a second via stacked on top of the first via and electrically coupled to the first via; and forming a cover pad stacked on top of the second via and electrically coupled to the second via, wherein a top width of the first via is wider than a bottom width of the second via, a recess is formed in the first via extending partially into a top surface of the first via, a bottom of the second via is within the recess, and the bottom of the second via extends from the bottom surface of the second via to a height equal to a depth of the recess, and the second via contacts the first via within the recess.

[0120] Clause 12: The method of clause 11, wherein the first via is tapered such that the top width of the first via is wider than the bottom width of the first via, the second via is tapered such that the top width of the second via is wider than the bottom width of the second via, and the recess is tapered such that the top width of the recess is wider than the bottom width of the recess.

[0121] Clause 13: The method of clause 11 or 12, wherein a side surface of a bottom of the second via is in contact with a side surface of the recess, and a bottom surface of the bottom of the second via is in contact with a bottom surface of the recess.

[0122] Clause 14: The method of any of clauses 11 to 13, wherein there is no capture pad between the first via and the second via.

[0123] Clause 15: The method of any of clauses 11-14, wherein the second via is electrically coupled to another via in the same layer through a pattern line, the second via being in contact with the pattern line.

[0124] Clause 16: A method according to any of clauses 11 to 15, wherein the cover pad is a pad in a cover layer of a stacked layer structure comprising a stack via structure, the cover layer being the outermost layer of the stacked layer structure, and the cover pad is configured for signal connection with an external device.

[0125] Clause 17: A method according to any of clauses 11 to 16, wherein between the first via and the second via, the capture pad is electrically connected to the cover pad via the first via and the second via, in that order.

[0126] Clause 18: The method of any of clauses 11-17, wherein the first via is formed from copper (Cu), the second via is formed from copper (Cu), or both.

[0127] Clause 19: The method of any one of clauses 11 to 18, wherein the depth of the recess is in the range of 5% to 15% of the height of the first via.

[0128] Clause 20: The method of any of clauses 11-19, wherein the top surface of the first via is drilled to form a recess, and when the second via is formed, the bottom of the second via fills the recess.

[0129] Clause 21: The method of clause 20, wherein the recess is formed by laser drilling a top surface of the first via.

[0130] Clause 22: A capture pad and an inner via formed in an inner dielectric layer, the inner via being stacked on and electrically coupled to the capture pad; one or more intermediate vias formed in a corresponding one or more intermediate dielectric layers stacked on the inner dielectric layer, the intermediate vias being stacked on and electrically coupled to the inner vias; one or more intermediate vias; an outer via formed in an outer dielectric layer stacked on the one or more intermediate dielectric layers, the outer vias being stacked on and electrically coupled to the one or more intermediate vias; and an outer via on the outer via. and a cover pad stacked and electrically coupled to the outer via, the stack layer structure including a first via and a second via stacked on top of the first via, the first via being an inner via or one of one or more intermediate vias, the second via being one of the one or more intermediate vias or an outer via, a top width of the first via being wider than a bottom width of the second via, a recess being formed in the first via to extend partially into a top surface of the first via, a bottom of the second via being within the recess, the bottom of the second via extending from the bottom surface of the second via to a height equal to a depth of the recess, and the second via contacting the first via within the recess.

[0131] Clause 23: A stack layer structure as described in clause 22, wherein the first via is tapered such that the top width of the first via is wider than the bottom width of the first via, the second via is tapered such that the top width of the second via is wider than the bottom width of the second via, and the recess is tapered such that the top width of the recess is wider than the bottom width of the recess.

[0132] Clause 24: A stack layer structure described in clause 22 or 23, wherein a side surface of a bottom of the second via is in contact with a side surface of the recess and a bottom surface of the bottom of the second via is in contact with a bottom surface of the recess.

[0133] Clause 25: A stack layer structure according to any of clauses 22 to 24, wherein there is no capture pad between the first via and the second via.

[0134] Clause 26: A stack layer structure described in any of clauses 22 to 25, wherein the second via is electrically coupled to another via in the same layer via a pattern line, the second via being in contact with the pattern line.

[0135] Clause 27: A stack layer structure described in any of clauses 22 to 26, further comprising a cover layer stacked on the outer dielectric layer, the cover layer being the outermost layer of the stack layer structure, and a cover pad being formed in the cover layer and configured to enable signal connection with an external device.

[0136] Clause 28: A stack layer structure described in any of clauses 22 to 27, wherein between the first via and the second via, the capture pad is electrically connected to the cover pad via the first via and the second via, in that order.

[0137] Clause 29: A stack layer structure according to any of clauses 22 to 28, wherein the first via is formed from copper (Cu), the second via is formed from copper (Cu), or both.

[0138] Clause 30: A stack layer structure according to any of clauses 22 to 29, wherein the depth of the recess is in the range of 5% to 15% of the height of the first via.

[0139] Clause 31: A stack layer structure described in any of clauses 22 to 30, further comprising an initial layer stacked below the inner dielectric layer, the capture pad being on and in contact with the initial layer.

[0140] Clause 32: A capture pad, an inner via, an inner dielectric layer, one or more intermediate vias, one or more intermediate dielectric layers, an outer via, an outer dielectric layer, and a cover pad are formed on the initial layer, and the stack layer structure further includes a lower capture pad and a lower inner via formed in a lower inner dielectric layer stacked under the initial layer, the lower inner via being stacked under and electrically coupled to the lower capture pad, a lower capture pad and a lower inner via, one or more lower intermediate vias formed in a corresponding one or more lower intermediate dielectric layers stacked under the lower inner dielectric layer, the lower intermediate vias being stacked under and electrically coupled to the lower inner vias, one or more lower intermediate vias, and a lower outer via formed in a lower outer dielectric layer stacked under the one or more lower intermediate dielectric layers, the lower outer vias being stacked under the one or more lower intermediate vias. 32. The stack layer structure of claim 31, comprising: a lower outer via stacked and electrically coupled to the one or more lower intermediate vias; and a lower cover pad stacked below the lower outer via and electrically coupled to the lower outer via; wherein the stack layer structure includes a first lower via and a second lower via stacked below the first lower via, the first lower via being a lower inner via or one of the one or more lower intermediate vias, the second lower via being one of the one or more lower intermediate vias or the lower outer via, a bottom width of the first lower via being wider than a top width of the second lower via, a bottom recess being formed in the first lower via to extend partially into a bottom surface of the first lower via, an top of the second lower via being within the bottom recess, and an top of the second lower via extending from a top surface of the second via to a height equal to a depth of the bottom recess, and the second lower via contacting the first lower via in the bottom recess.

[0141] Clause 33: The stack layer structure according to any one of clauses 22 to 32, wherein the stack layer structure is an embedded trace substrate (ETS), a semi-additive process (SAP) substrate, or a modified semi-additive process (mSAP) substrate structure.

[0142] Clause 34: A stack layer structure described in any of clauses 22 to 33, wherein the stack layer structure is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

[0143] Clause 35: A method of fabricating a stacked layer structure, comprising: forming a capture pad and an inner via in an inner dielectric layer, the inner via being stacked on and electrically coupled to the capture pad; forming one or more intermediate vias in corresponding one or more intermediate dielectric layers stacked on the inner dielectric layer, the one or more intermediate vias being stacked on and electrically coupled to the inner vias; and forming an outer via in an outer dielectric layer stacked on the one or more intermediate dielectric layers, the outer via being stacked on and electrically coupled to the one or more intermediate vias. and forming a cover pad stacked on top of the outer via and electrically coupled to the outer via, wherein the stack layer structure includes a first via and a second via stacked on top of the first via, the first via being an inner via or one of one or more intermediate vias, and the second via being one of the one or more intermediate vias or the outer via, a top width of the first via is wider than a bottom width of the second via, a recess is formed in the first via to extend partially into a top surface of the first via, a bottom of the second via is within the recess, and the bottom of the second via extends from the bottom surface of the second via to a height equal to a depth of the recess, and the second via contacts the first via within the recess.

[0144] Clause 36: The method of clause 35, wherein the first via is tapered such that the top width of the first via is wider than the bottom width of the first via, the second via is tapered such that the top width of the second via is wider than the bottom width of the second via, and the recess is tapered such that the top width of the recess is wider than the bottom width of the recess.

[0145] Clause 37: The method of clause 35 or 36, wherein a side surface of a bottom of the second via is in contact with a side surface of the recess, and a bottom surface of the bottom of the second via is in contact with a bottom surface of the recess.

[0146] Clause 38: The method of any of clauses 35 to 37, wherein no capture pad is present between the first via and the second via.

[0147] Clause 39: The method of any of clauses 35-38, wherein the second via is electrically coupled to another via in the same layer through a pattern line, the second via being in contact with the pattern line.

[0148] Clause 40: The method of any of clauses 35 to 39, further comprising a cover layer stacked on the outer dielectric layer, the cover layer being the outermost layer of the stack layer structure, and a cover pad formed in the cover layer and configured to enable signal connection to an external device.

[0149] Clause 41: A method according to any of clauses 35 to 40, wherein between the first via and the second via, the capture pad is electrically connected to the cover pad via the first via and the second via, in that order.

[0150] Clause 42: The method of any of clauses 35-41, wherein the first via is formed from copper (Cu), the second via is formed from copper (Cu), or both.

[0151] Clause 43: The method of any of clauses 35 to 42, wherein the depth of the recess is in the range of 5% to 15% of the height of the first via.

[0152] Clause 44: The method of any of clauses 35 to 43, further comprising an initial layer stacked below the inner dielectric layer, the capture pad being on and in contact with the initial layer.

[0153] Clause 45: A capture pad, an inner via, an inner dielectric layer, one or more intermediate vias, one or more intermediate dielectric layers, an outer via, an outer dielectric layer, and a cover pad are formed on the initial layer, the method further comprising forming a lower capture pad and a lower inner via in a lower inner dielectric layer stacked below the initial layer, the lower inner via being stacked below the lower capture pad and electrically coupled to the lower capture pad; forming one or more lower intermediate vias in corresponding one or more lower intermediate dielectric layers stacked below the lower inner dielectric layer, the one or more lower intermediate vias being stacked below the lower inner vias and electrically coupled to the lower inner vias; and forming a lower outer via in a lower outer dielectric layer stacked below the one or more lower intermediate dielectric layers, the lower outer vias being stacked below the one or more lower intermediate vias. 45. The method of claim 44, comprising: stacking a first lower via and a second lower via stacked below the first lower via to electrically couple to the one or more lower intermediate vias; and stacking a lower cover pad below the lower outer via to electrically couple to the lower outer vias, wherein the stack layer structure includes a first lower via and a second lower via stacked below the first lower via, the first lower via being a lower inner via or one of the one or more lower intermediate vias, and the second lower via being one of the one or more lower intermediate vias or the lower outer via, a bottom width of the first lower via being wider than a top width of the second lower via, a bottom recess being formed in the first lower via to extend partially into a bottom surface of the first lower via, an top of the second lower via being within the bottom recess, an top of the second lower via extending from a top surface of the second lower via to a height equal to a depth of the bottom recess, and the second lower via contacting the first lower via in the bottom recess.

[0154] Clause 46: The method of any of clauses 35 to 45, wherein the stack layer structure is an embedded trace substrate (ETS), a semi-additive process (SAP) substrate, or a modified semi-additive process (mSAP) substrate structure.

[0155] Clause 47: The method of any of clauses 35-46, wherein the top surface of the first via is drilled to form a recess, and when the second via is formed, the bottom of the second via fills the recess.

[0156] Clause 48: The method of clause 47, wherein the recess is formed by laser drilling a top surface of the first via.

[0157] As used herein, terms such as "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal", and variations thereof may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in automobiles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short range radio, etc.). These terms are also intended to include a device that communicates with another device capable of receiving wireless communication and / or navigation signals, such as by a short-range wireless connection, an infrared connection, a wired connection, or other connection, regardless of whether the satellite signal reception, assistance data reception, and / or location-related processing is performed on that device or on another device. Furthermore, these terms are intended to include all devices, including wireless and wired communication devices, that can communicate with a core network via a Radio Access Network (RAN), through which the UE can connect to external networks, such as the Internet, and to other UEs. Of course, other mechanisms for connecting to a core network and / or the Internet are also possible for a UE, such as via a wired access network, a Wireless Local Area Network (WLAN) (e.g., based on IEEE 802.11, etc.), etc.A UE may be embodied by any of several types of devices, including, but not limited to, a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smart phone, a tablet, a tracking device, an asset tag, etc. A communication link through which a UE can transmit signals to a RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). A communication link through which a RAN can send signals to a UE is called a downlink channel or a forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term traffic channel (TCH) may refer to either an uplink / reverse traffic channel or a downlink / forward traffic channel.

[0158] Wireless communication between electronic devices can be based on various technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP® Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread) or other protocols that may be used in wireless or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group that aims to significantly reduce power consumption and cost while maintaining a similar communication range. BLE was integrated into the main Bluetooth standard in 2010 by adopting the Bluetooth Core Specification Version 4.0 and was updated in Bluetooth 5.

[0159] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as advantageous over other examples. Likewise, the term "example" does not imply that all examples include the described features, advantages or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0160] It should be noted that the terms "connected" and "coupled," or any variation thereof, mean any direct or indirect connection or coupling between elements, unless the connection is expressly disclosed as being directly connected, and may encompass the presence of intermediate elements between two elements that are "connected" or "coupled" together through intermediary elements.

[0161] Any reference herein to an element using a designation such as "first," "second," etc. is not intended to limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Also, unless otherwise stated, a set of elements can comprise one or more elements.

[0162] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0163] Nothing described, illustrated, or shown in this application is intended to disclose to the public any element, act, feature, benefit, advantage, or equivalent, whether or not that element, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0164] In the above detailed description, it can be seen that various features are grouped together in each example. This method of disclosure should not be understood as the claimed examples having more features than are expressly recited in each claim. Rather, the disclosure may include fewer features than all of the individual examples disclosed. Thus, the following claims are hereby considered incorporated into this description, with each claim standing alone as a separate example. Although each claim standing alone as a separate example, it should be noted that a dependent claim may refer to a specific combination with one or more claims within the scope of the claim, while other examples may include or include a combination of the dependent claim with the subject matter of any other dependent claim, or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein unless it is expressly stated that a specific combination is not intended. It is further intended that a feature of a claim may be included in any other independent claim, even if the claim is not directly dependent on the independent claim.

[0165] It is further noted that the methods, systems and apparatus disclosed in the present description or claims may be implemented by a device comprising means for performing the respective acts and / or functions of the disclosed methods.

[0166] Further, in some instances, an individual act may be subdivided into or include one or more sub-acts, and such sub-acts may be included in and become part of the disclosure of the individual act.

[0167] Although the above disclosure illustrates exemplary examples of the present disclosure, it should be noted that various modifications and changes can be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or acts of the method claims according to the examples of the present disclosure described herein need not be performed in any particular order. In addition, well-known elements may not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Furthermore, although elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated. [Explanation of symbols]

[0168] 200 Stacked Via Structure 210, 210A Capture Pad 210B Lower Capture Pad 220, 220A Cover Pad 220B Lower Cover Pad 240, 240A Intermediate via 240B Bottom Center Via 242, 242A Inner Via 242B Bottom Inner Via 244, 244A Outer Via 244B Bottom Outer Via 250 Pattern Lines 340A 1st Via 340B 2nd via 345 Recess 400 stack layer structure 405 Career 415 Inner Dielectric Layer 417 Inner via hole 425 Intermediate Dielectric Layer 427 Intermediate via hole 435 Outer dielectric layer 437 Outer via hole 445 Cover Layer 460 Base layer, initial layer 515A Inner Dielectric Layer 515B Lower inner dielectric layer 517A Inner via hole 517B Bottom inner via hole 525A Intermediate Dielectric Layer 525B Lower Intermediate Dielectric Layer 527A Intermediate via hole 527B Bottom middle via hole 535A outer dielectric layer 535B Bottom Outer Dielectric Layer 545A Cover Layer 545B Lower Cover Layer 560 Core and early stage

Claims

1. Capture pad and a first via stacked on the capture pad and electrically coupled to the capture pad; a second via stacked on top of and electrically coupled to the first via; a cover pad stacked on top of and electrically coupled to the second via; Equipped with a top width of the first via is wider than a bottom width of the second via; a recess formed in the first via that extends partially into a top surface of the first via; a bottom of the second via is within the recess, the bottom of the second via extends from a bottom surface of the second via to a height equal to a depth of the recess, the second via contacts the first via within the recess, and no capture pad exists between the first via and the second via; Stacked via structure.

2. the first via is tapered such that the top width of the first via is wider than the bottom width of the first via; the second via is tapered such that the top width of the second via is wider than the bottom width of the second via; The recess is tapered such that the width at the top of the recess is wider than the width at the bottom of the recess. The stacked via structure of claim 1 .

3. a side surface of the bottom of the second via contacts a side surface of the recess; a bottom surface of the bottom of the second via contacts a bottom surface of the recess; The stacked via structure of claim 1 .

4. 2. The stacked via structure of claim 1, wherein the second via is electrically coupled to another via in the same layer through a pattern line, the second via being in contact with the pattern line.

5. 2. The stacked via structure of claim 1, wherein the cover pad is a pad in a cover layer of a stacked layer structure comprising the stacked via structure, the cover layer being an outermost layer of the stacked layer structure, and the cover pad is configured to make a signal connection with an external device.

6. 2. The stacked via structure of claim 1, wherein between the first via and the second via, the capture pad is electrically connected to the cover pad through the first via and the second via in this order.

7. 2. The stacked via structure of claim 1, wherein the first via is formed from copper (Cu), the second via is formed from copper (Cu), or both.

8. The stacked via structure of claim 1 , wherein the depth of the recess is in the range of 5% to 15% of the height of the first via.

9. 10. The stacked via structure of claim 1, wherein the stacked via structure is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

10. 1. A method of fabricating a stacked via structure, comprising: forming a capture pad; forming a first via stacked on and electrically coupled to the capture pad; forming a second via stacked on top of and electrically coupled to the first via; forming a cover pad stacked over and electrically coupled to the second via; Including, a top width of the first via is wider than a bottom width of the second via; a recess formed in the first via that extends partially into a top surface of the first via; a bottom of the second via is within the recess, the bottom of the second via extends from a bottom surface of the second via to a height equal to a depth of the recess, the second via contacts the first via within the recess, and no capture pad is formed between the first via and the second via; method.

11. drilling the top surface of the first via to form the recess; When the second via is formed, the bottom of the second via fills the recess. The method of claim 10.

12. The method of claim 11 , wherein the recess is formed by laser drilling the top surface of the first via.

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