Vertical HEMT, Electrical Circuit, and Method for Making a Vertical HEMT

Abstract

A vertical high electron mobility transistor (HEMT) (100) comprising a substrate (310), a drain contact (410) that is a metal contact via through the substrate, a pillar layer (500) disposed on the drain contact (410) and including at least one vertical pillar (510) and a support material (520) that laterally confines the at least one vertical pillar (510), and an AlGaN layer (610) and a GaGaN layer (620) disposed on the pillar layer (500) that together form a heterojunction (630). A HEMT (100) comprising a heterostructure mesa (600) including an N layer (620), at least one source contact (420a, 420b) electrically connected to the heterostructure mesa (600), and a gate contact (430) disposed on the heterostructure mesa (600) and on at least one vertical pillar (510), the at least one vertical pillar (510) forming an electron transport channel between the drain contact (410) and the heterojunction (630).

Description

[Technical field]

[0001] The present concepts relate generally to vertical high electron mobility transistors (vertical HEMTs), electrical circuits comprising vertical HEMTs, and methods of making vertical HEMTs. [Background technology]

[0002] HEMT is a type of field effect transistor that contains heterojunction materials with different band gaps, such as GaN and AlGaN. The orientation of the transistor can be horizontal or vertical, meaning that the current flow between the source and drain contacts of the transistor can be either perpendicular or parallel to the surface of the transistor or the substrate on which the transistor is located. In a vertical HEMT, the drain contact may be located at the bottom of the device and the source contact may be located at the top. The operation of the transistor, i.e. whether current is conducted between the source and drain contacts, is controlled by the application of a voltage to the gate contact. In the more conventional lateral HEMT, the current flows mainly horizontally through the transistor interposed in a so-called two-dimensional electron gas (2DEG) formed at the interface between the heterojunction of different band gap materials. In a vertical HEMT, as the name suggests, the current flow also includes a significant vertical component. The main vertically conducting part of a vertical HEMT is often referred to as the aperture of the vertical HEMT. Vertical HEMTs generally allow for improved area reduction of the transistor.

[0003] US / 2020381538 discloses a method for manufacturing a semiconductor device. The method includes the following steps: A substrate is provided. A first III-V compound layer is formed on a first side of the substrate. A drain trench and a contact trench are formed on a second side of the substrate. The drain trench extends from the second side of the substrate towards the first side of the substrate and through the substrate. The contact trench extends from the second side of the substrate towards the first side of the substrate and through the substrate. The drain trench and the contact trench are both formed by the same process. A drain electrode is formed in the drain trench. A back contact structure is formed in the contact trench. Summary of the Invention [Problem to be solved by the invention]

[0004] It is an object of the inventive concept to provide a vertical HEMT for high frequency and / or high power and / or high temperature and / or high voltage operation. A further object is to provide a vertical HEMT with a small footprint. These and other objects of the inventive concept are at least partly met by the invention as defined in the independent claims. Preferred embodiments are set out in the dependent claims. [Means for solving the problem]

[0005] Abbreviations of natural elements are used herein according to the periodic table, e.g., Al means aluminum, Ga means gallium, N means nitrogen, As means arsenic, Mg means magnesium, O means oxygen, Si means silicon, and C means carbon.

[0006] According to a first aspect, there is provided a vertical high electron mobility transistor (HEMT), comprising: A substrate; a drain contact which is a metal contact via through the substrate; a pillar layer disposed over the drain contact and including at least one vertical pillar and a support material laterally enclosing the at least one vertical pillar; a heterostructure mesa disposed on the pillar layer, the heterostructure mesa including an AlGaN layer and a GaN layer that together form a heterojunction; at least one source contact electrically connected to the heterostructure mesa; a gate contact disposed on the heterostructure mesa and on at least one vertical pillar; A vertical HEMT is provided, in which at least one vertical pillar forms an electron transport channel between the drain contact and the heterojunction.

[0007] It is understood that the vertical HEMT can include nitride semiconductor materials. In this specification, the term nitride semiconductor materials should be interpreted as any semiconductor material that includes nitrogen, particularly alloys of groups III and V of the periodic table, where the group V portion is nitrogen. The nitride semiconductor material can be a GaN-based material. In this specification, the term "GaN-based material" should be interpreted as any semiconductor material that includes gallium and nitrogen, such as GaN, AlGaN, InGaN, AlInGaN.

[0008] GaN-based materials can facilitate high frequency and / or high power and / or high temperature and / or high voltage operation. Thus, vertical HEMTs including GaN-based materials can operate at high frequency and / or high power and / or high temperature and / or high voltage. Alternatively or additionally, vertical HEMTs including GaN-based materials can be embedded in electronic devices made from GaN-based materials, for example embedded in the same chip or on the same substrate.

[0009] GaN-based HEMTs can offer faster switching speeds, increased electron mobility, lower resistance, higher breakdown voltage, etc. Compared to silicon-based transistors, GaN-based devices can offer lower on-resistance and lower switching losses when used as power switching transistors for voltage converters.

[0010] The inventors have realized that vertical HEMTs can be advantageous because they address the tradeoff between low drain current and high breakdown voltage of HEMT devices at high power. Current collapse of GaN HEMT devices is the main limitation to the output power and even switching frequency that can be used. Current collapse is generally caused by trapped charges in the off-state at the AlGaN barrier plane, i.e., AlGaN / GaN.

[0011] Furthermore, the inventors have realized that vertical HEMTs can provide greater power densities than conventional HEMTs by more efficiently utilizing surface area to reduce device size, and can further improve breakdown voltage by allowing gate widths greater than 1 micron.

[0012] A vertical HEMT according to the present invention includes a heterojunction formed by an AlGaN layer and a GaN layer. Such a heterojunction may form a two-dimensional electron gas (2DEG) at the interface between the AlGaN layer and the GaN layer during operation. The 2DEG may be formed by applying a voltage to a gate contact. Thus, the gate contact may switch electrical conduction on and off at the interface between the AlGaN layer and the GaN layer.

[0013] Various compositions may be used for the AlGaN layer of the heterojunction. For example, the AlGaN layer of the heterojunction may be Al (1-x) Ga (x) N layer, where 0≦x≦0.9 or 0≦x≦0.75. Thus, the AlGaN layer of the heterojunction may be a pure AlN layer.

[0014] Heterozygosity is Al having a thickness of 20 to 22 nm, where 0.72≦x≦0.75 (1-x) Ga (x) N layer and and a GaN layer, Al (1-x) Ga (x) Advantageously, the N layer is located directly on the GaN layer.

[0015] It should be understood that the AlGaN layer of the heterojunction may include two or more sublayers.

[0016] Heterozygosity is Al having a thickness of 20 to 22 nm, where 0.72≦x≦0.75 (1-x) Ga (x)a first AlGaN sublayer which is an N layer; a second AlGaN sublayer, which is an AlN layer having a thickness less than 5 nm; and a GaN layer, Advantageously, the second AlGaN sublayer is disposed directly on the GaN layer, and the first AlGaN sublayer is disposed directly on the second AlGaN sublayer.

[0017] Such thickness and composition of the layers of the heterostructure provide a vertical HEMT with surprisingly high breakdown voltage and switching speed. The carrier concentration in the 2DEG is approximately 100%. (1-x) Ga (x) It is understood that this may depend on the thickness and / or Al concentration of the N layer. (1-x) Ga (x) Increasing the N thickness and / or Al concentration can improve the carrier concentration in the 2DEG, but there may be diminishing returns near a thickness of 20 nm and an Al concentration of 27%. Similarly, the breakdown voltage of a vertical HEMT increases with increasing Al concentration. (1-x) Ga (x) It may depend on the thickness of the N layer and / or the Al concentration. Taking into account the trade-off effect, Al (1-x) Ga (x) It is understood that there is a sweet spot where the N layer has a thickness of 20 to 22 nm and 0.72≦x≦0.75. (1-x) Ga (x) The breakdown voltage can be improved by using a thin AlN layer between the N layer and the GaN layer. (1-x) Ga (x) It is further understood that the positive effects realized by the N-layer are not yet destroyed. It should be understood that other parts of the vertical HEMT other than the heterojunction can also include GaN-based materials. For example, at least one vertical pillar can include a GaN-based material, such as GaN. A support material that laterally encapsulates at least one vertical pillar can include a GaN-based material.

[0018] According to the invention, the vertical HEMT comprises a substrate. The substrate may be any substrate suitable for epitaxial growth. The substrate may comprise silicon, sapphire, silicon carbide or GaN. In particular, the substrate may be silicon. <111> As used herein, the vertical direction refers to the direction normal to the plane of the substrate. Similarly, the lateral direction refers to the direction parallel to the plane of the substrate.

[0019] The substrate may be part of a base layer on which further layers, such as a pillar layer, are disposed. The base layer may be an Al layer disposed directly on the substrate, for example. (1-y) Ga (y) N layers, where 0≦y≦1, for example 0≦y≦0.9 or 0≦y≦0.75. (1-y) Ga (y) The N layer is made of Al deposited on the substrate by physical vapor deposition (e.g., sputtering). (1-y) Ga (y) It may be an N-layer. (1-y) Ga (y) The N layer may be an AlN layer, for example a sputtered AlN layer, which may allow for low defect density on subsequent layers. (1-y) Ga (y) The N layer 320 may be a GaN layer.

[0020] As an example, a vertical HEMT can advantageously comprise a base layer, the base layer including a substrate, an AlN layer on the substrate, and a GaN layer on the AlN layer, the substrate being silicon. <111> substrate, and the AlN and GaN layers are deposited by physical vapor deposition (e.g., sputtering). Hereinafter, these layers are exemplified as sputtered layers.

[0021] The sputtered AlN layer can act as a transition layer from silicon to GaN-based materials. The sputtered GaN layer can act as a transition layer to epitaxial GaN-based materials. It is understood that such sputtered layers on silicon are currently adequate and in fact highly functional. The crystallinity of such layers may be in fact good, and epitaxial growth of the AlN and / or GaN layers may not be necessary. Furthermore, the sputtered AlN and / or GaN may have fewer charge traps than epitaxially grown layers, for example at the interface between the AlN layer and the silicon substrate. An InGaN layer may be placed on top of the GaN layer deposited by physical vapor deposition. Such an InGaN layer may provide a spectroscopic wavelength signal during etching so that the etching is stopped at the correct location. Such an InGaN layer may be sputtered or epitaxially grown. Alternatively, the addition of Sc to the AlN as sputtered Sc(x)Al(1-x)N may be used as an etch stop layer.

[0022] As described, the vertical HEMT further comprises a drain contact, which is a metal contact via through said substrate. A metal contact via may be considered as a metal wire in a hole through the substrate. The metal contact via may extend vertically through the substrate. There may be one metal contact via for each vertical HEMT of a device or electrical circuit. Alternatively, two or more vertical HEMTs of a device or electrical circuit may share one metal contact via. The metal contact via allows one or more vertical HEMTs on the same substrate to have separate drain connections. Thus, it may not be necessary for all vertical HEMTs to share a common drain. Thus, greater design freedom is realized for the design of the electrical circuit.

[0023] As described, the vertical HEMT further comprises a pillar layer. The pillar layer is disposed over the drain contact. The pillar layer may be disposed directly over the drain contact. Alternatively, the pillar layer may be separated from the drain contact by an intermediate layer.

[0024] The pillar layer includes at least one vertical pillar. The at least one vertical pillar may have a diameter smaller than 1 μm, for example, between 5 nm and 500 nm. Advantageously, the pillar may be a nanowire. The nanowire may have a diameter smaller than 100 nm, for example, between 5 and 100 nm or between 10 and 50 nm. The small diameter of the vertical pillar may facilitate a small footprint. Furthermore, a small diameter, such as a diameter below 100 nm, may provide high charge carrier mobility due to quantum confinement effects. This may provide high frequency operation.

[0025] The length of the at least one vertical pillar may be in the range of 50 nm to 500 nm. The length may preferably be in the range of 150 nm to 250 nm.

[0026] The at least one vertical pillar may include a GaN-based material, such as GaN. The at least one vertical pillar may be doped, such as n-doped.

[0027] At least one vertical pillar is configured to form an electron transport channel between the drain contact and the heterojunction.

[0028] At least one vertical pillar may be electrically connected to the drain contact, for example by being placed directly on the drain contact or by a doped region between the pillar and the drain contact. The doped region between the pillar and the drain contact may be a region where metal from the drain contact interdiffuses from the drain contact into an intermediate layer between the drain contact and the pillar layer. Preferably, the n-doped region abuts the drain contact on which the pillar layer is formed. Such a layer is advantageous for etching a trench in the immediate vicinity of the vertical pillar. It is understood that the pillars extend along the length of the gate contact and its width. In a non-limiting example, the pillars may be 15 along a 3 micrometer gate width and 100 along a 20 micrometer gate length, where the pillar diameter is 100 nm and the pitch is 100 nm.

[0029] The drain contact can extend into the nitride semiconductor layers of the vertical HEMT, for example into the sputtered AlN layer and / or the sputtered GaN layer. The drain contact can extend into the MOVPE epitaxially grown layers of the vertical HEMT. The drain contact can have a substantially large surface area abutting the MOVPE epitaxially grown layers of the vertical HEMT. Thus, the drain contact can be laterally confined by the AlN layer and / or the AlGaN layer and / or the GaN layer. The drain contact can be configured to reach within 1 micrometer of the pillar layer, such as within 500 nm of the at least one vertical pillar. Thus, the drain contact can be close enough to the at least one vertical pillar to be electrically connected to said at least one vertical pillar.

[0030] The support material may be configured to be a current blocking layer. The term current blocking layer is to be understood as a layer that prevents current from leaving the electron transport channel. The support material acting as a current blocking layer can reduce current leakage between the at least one vertical pillar and the electron transport channel. This can result in reduced transistor losses and more efficient operation. The support material may be, for example, a nitride semiconductor having a doping opposite to that of the at least one vertical pillar. For example, if the at least one vertical pillar is n-doped, the support material may be p-doped and vice versa. Thus, the pillar layer may be configured to pass current through the at least one vertical pillar and not through the support material. Alternatively, the support material may be an electrically insulating material. However, a support material of a nitride semiconductor material, preferably an epitaxially grown nitride semiconductor material, is advantageous. This facilitates the epitaxial growth of layers above the pillar layer. In accordance with the above, the pillar layer may be configured such that at least one vertical pillar comprises n-doped GaN and the support material comprises a p-doped nitride semiconductor.

[0031] As an example of the above, the support material may include a superlattice of GaN layers and AlN spacer layers. The AlN spacer layer of the support material may have a thickness less than 5 nm, and the GaN layer of the support material may have a thickness greater than 5 nm. Alternatively, both the AlN spacer layer and the GaN layer of the support material may have a thickness less than 5 nm. All or some of the GaN layers may be carbon-doped or iron-doped. Additionally or alternatively, all or some of the AlN layers may be carbon-doped or iron-doped. Such a support material may provide an efficient current blocking layer.

[0032] Alternatively, the support material may include gallium oxide, such as epitaxial Ga2O3. The support material may include epitaxial gallium oxide, such as epitaxial Ga2O3. The epitaxial gallium oxide may be epitaxially deposited gallium oxide. The epitaxial gallium oxide may be crystalline or may have a crystalline relationship with the underlying semiconductor material. The gallium oxide may be an insulator or a semi-insulator.

[0033] As described, the vertical HEMT further comprises a heterostructure mesa disposed on the pillar layer, the heterostructure mesa including an AlGaN layer and a GaN layer that together form a heterojunction. The heterostructure mesa can include a heterostructure layer, the heterostructure layer including an AlGaN layer and a GaN layer that together form a heterojunction.

[0034] The mesa may be an etched mesa. Thus, the heterostructure layer may be disposed on the pillar layer, and then the mesa is formed from the heterostructure layer, e.g., etched. The mesa may be configured to include the heterostructure layer as well as the pillar layer. Alternatively, the mesa may be configured to include the heterostructure layer but not the pillar layer.

[0035] The formation of the mesa electrically isolates the heterojunction of the vertical HEMT from its surroundings, e.g., from the heterojunction of an adjacent vertical HEMT. The formation of the mesa thereby enables high frequency and / or high power and / or high voltage operation. The formation of the mesa prevents crosstalk between adjacent vertical HEMTs.

[0036] The formation of the mesa reduces parasitic capacitance to the neighboring vertical HEMTs, etc., thereby enabling high frequency operation.

[0037] As described, the vertical HEMT further comprises at least one source contact electrically connected to the heterostructure mesa. The at least one source contact may include a metal. The at least one source contact may be electrically connected to a top surface of the heterostructure mesa. The at least one source contact may be electrically connected to the heterojunction by an electrical connection to the heterostructure mesa. The heterostructure mesa may be doped, for example, in a region between the at least one source contact and the heterojunction. Alternatively or additionally, the vertical HEMT may be configured such that the at least one source contact is electrically connected to the heterojunction at least partially by electrical tunneling.

[0038] As described, the vertical HEMT further comprises a gate contact disposed on the heterostructure mesa and disposed on the at least one vertical pillar. The gate contact may be configured to control a 2DEG at the heterojunction on the at least one vertical pillar. Thus, the vertical HEMT may be configured to provide an electrical path from the at least one source contact through the heterojunction and the at least one pillar to the drain contact, and the gate contact may be configured to open and close the electrical path by controlling the 2DEG at the heterojunction on the at least one vertical pillar. The gate contact may include multiple layers, for example, a TiN layer on the heterostructure mesa, followed by an Al layer, followed by a TiN layer.

[0039] The heterojunction may be configured to form a 2DEG with a substantially large charge density. The layers near the heterojunction may be doped, for example n-doped. For example, one of the AlGaN layer and the GaN layer forming the heterojunction may be doped. Modulation doping may be used, where the dopant is spatially separated from the heterojunction interface. Modulation doping may provide a higher crystalline quality of the heterojunction, thus increasing the 2DEG charge density.

[0040] The heterostructure mesa may include further layers in addition to the AlGaN and GaN layers that form the heterojunction. For example, a vertical HEMT may include a p-doped GaN layer disposed above the AlGaN layer that forms part of the heterojunction and below the gate contact. The p-doped GaN layer between the gate contact and the AlGaN layer of the heterojunction may enable a normally-off vertical HEMT. The p-dopant concentration may be 1*10 to deplete the 2DEG from electrons. 18 and may further have a width similar to 50-100 nm thickness and gate length 0.3-5 microns, which allows the 2DEG charge density to be 1*10 for a normally-off device, i.e. in the off state. 13 cm -2 From 0.48*10 13 cm -2 The device may be further configured to have a large 2DEG charge density in the on-state. Thus, the vertical HEMT may operate in enhancement mode with a low on-resistance. A normally-off vertical HEMT may be advantageous for high power operation since it may provide higher reliability of the electrical circuitry of which it is a part.

[0041] The p-doped GaN can include a superlattice including a GaN layer and an Al(1-x)Ga(x)N layer, where 0.2≦x≦0.4. The superlattice can include multiple heterostructure layers, each heterostructure layer including one GaN layer and one Al(z)Ga(1-z)N layer. The superlattice can provide a p-type two-dimensional hole gas (2DHG) that provides a channel for conduction along the interface between the two layers. The periodicity of the superlattice can be 2-6 nm. The p-doping of the superlattice can provide an improved depletion of the 2DEG at room temperature, where 1*10 18 Higher p-dopant concentrations can be provided.

[0042] Alternatively, vertical HEMTs can be used The semiconductor device may comprise a plurality of semiconductor layers, layers of the plurality of semiconductor layers made from AlGaN having an aluminum content greater than or equal to 0%, the plurality of semiconductor layers configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than its adjacent mutually opposing layer, some of the plurality of semiconductor layers being p-doped, and the plurality of semiconductor layers disposed above an AlGaN layer forming part of a heterojunction and below a gate contact.

[0043] It is understood that p-doping can be difficult to achieve in GaN-based materials. Doping atoms such as Mg used for p-doping are often passivated by hydrogen impurities or nitrogen vacancies. To remove the passivation (or activate the doping atoms), a post-growth anneal, for example a post-growth anneal in an atmosphere with low hydrogen concentration, may be used. It is understood that multiple semiconductor layers can eliminate or reduce the need for post-growth annealing of p-doped GaN-based materials. The use of such multiple semiconductor layers under the gate contact facilitates p-doping under the gate (i.e., normally-off vertical HEMT). In particular, it facilitates p-doping without much material diffusion that may accompany post-growth annealing.

[0044] The semiconductor layers can enhance p-doping by variation of the valence-band edge, as described by Kozodoy et al. [Appl. Phys. Lett. 75, 2444 (1999)]. The variation of the valence-band edge herein is caused by variation of the Al content in the semiconductor layers. Where the band edge is far below the Fermi energy, acceptors can be ionized, and where the band edge is close to the Fermi level, the resulting holes can accumulate. The valence-band edge herein can vary in a direction perpendicular to the layers of the semiconductor layers. As a result of the variation of the valence-band edge, the hole concentration can also vary. However, the average hole concentration can be higher than in a bulk film where the valence-band edge does not vary. It is understood that the variation of the valence-band edge can be caused by the variation of the band gap in the semiconductor layers as well as polarization effects due to band bending.

[0045] The AlGaN layer of the heterojunction may be intrinsically doped, and the vertical HEMT may be The semiconductor device further comprises an intrinsically doped GaN layer disposed over the intrinsically doped AlGaN layer of the heterojunction and laterally aligned over the at least one vertical pillar, the GaN layer having a thickness of at least 14 nm, the combined thickness of the GaN layer and the AlGaN layer of the heterojunction being in the range of 20-50 nm, and the AlGaN having a thickness of 20-25 nm.

[0046] Such a layer can provide a sufficiently depleted 2DEG of the heterojunction to enable high frequency and / or high power and / or high temperature and / or high voltage operation. In particular, when such an intrinsically doped layer is combined with a p-doped GaN layer between the gate contact and the intrinsically doped GaN layer, the normally-off vertical HEMT can have high reliability.

[0047] The vertical HEMT may be configured to be in a normally off state and to be turned on with a threshold voltage of 1 V. The threshold voltage may depend on a distance between the gate contact and the heterojunction. The distance between the gate contact and the heterojunction may be configured such that a voltage difference of at least 1 V between the gate contact and the at least one source contact opens a conduction channel in the heterojunction, whereby the vertical HEMT has a threshold voltage of at least 1 V. The threshold voltage may alternatively or additionally depend on a doping profile between the gate contact and the heterojunction. Thus, additionally or alternatively, the doping profile between the gate contact and the heterojunction may be configured such that a voltage difference of at least 1 V between the gate contact and the at least one source contact opens a conduction channel in the heterojunction, whereby the vertical HEMT has a threshold voltage of at least 1 V. A threshold voltage of at least 1 V is advantageous in reducing triggering of the device on-state that may cause malfunctions in, for example, electric motor circuits in electric vehicles, and in improving the reliability of high power electronics, typically designed for reliable use at 1 kW or more.

[0048] The distance between the drain and source contacts may be greater than 4 micrometers. Such separation between the drain and source contacts allows for a large breakdown voltage of the vertical HEMT, thereby enabling high power and / or high voltage operation.

[0049] The at least one vertical pillar may be laterally aligned with the gate contact, such that the gate contact laterally overlaps the at least one vertical pillar, such that the gate contact can efficiently control charge transport through the heterojunction to the at least one vertical pillar.

[0050] The lateral size of the gate contact may be 75%-150% of the lateral size of the drain contact. The lateral size of the gate contact may be 75%-150% of the lateral size of the portion of the drain contact that extends into the nitride semiconductor layer of the vertical HEMT. Thus, the same lithography mask may be used to fabricate the gate contact and a portion of the drain contact. Preferably, the gate contact and the portion of the drain contact that extends into the nitride semiconductor layer of the vertical HEMT have the same lateral size and are laterally aligned. However, due to differences in exposure during lithography or other manufacturing practicalities, the lateral size of the gate contact may be 75%-150% of the lateral size of the drain contact even when the same lithography mask is used.

[0051] The at least one source contact may be laterally separated from the at least one vertical pillar. The lateral separation between the at least one source contact and the at least one vertical pillar may be at least 200 nm. The lateral separation can facilitate low leakage current when the vertical HEMT is turned off. The lateral separation can facilitate high power and / or high voltage operation.

[0052] According to a second aspect, there is provided an electrical circuit comprising first and second vertical HEMTs, the first and second vertical HEMTs being vertical HEMTs according to the first aspect, the electrical circuit comprising an electrical isolator configured to block current flow between the first and second vertical HEMTs, the electrical isolator comprising: a first insulator disposed on a side of a heterostructure mesa of at least one of the first and second vertical HEMTs; and / or a second insulator disposed on a side of at least one source contact of at least one of the first and second vertical HEMTs; and / or and a current blocking layer disposed on a side of a GaN vertical connection, the current blocking layer being an electrical connection between at least one source contact of at least one of the first and second vertical HEMTs and a heterostructure mesa, the current blocking layer comprising carbon-doped or iron-doped GaN.

[0053] Thus, the two vertical HEMTs can form members of an electrical circuit. The electrical circuit can be any kind of electrical circuit, for example a step-down converter or a step-up converter. The first and second vertical HEMTs can share a common substrate. The electrical separator allows for a small isolation between the first and second vertical HEMTs. Thus, the electrical circuit can have a small footprint. Furthermore, the electrical separator reduces the parasitic capacitance between the first and second vertical HEMTs. The electrical separator thereby enables high frequency operation of the electrical circuit.

[0054] The first insulator may be an oxide. The first insulator may be a high frequency deposited plasma enhanced chemical vapor deposition oxide (HDPOX), or a low frequency deposited plasma enhanced chemical vapor deposition oxide (LDPOX), or a phosphorus silicate glass (PSG), or any combination thereof.

[0055] The second insulator may be an oxide. The second insulator may be HDPOX, or LDPOX, or PSG, or any combination thereof.

[0056] The current blocking layer disposed on the side of the GaN vertical connection may include a superlattice of GaN layers and AlN spacer layers. The AlN spacer layer of the current blocking layer may have a thickness less than 5 nm, and the GaN layer of the current blocking layer may have a thickness greater than 5 nm. Alternatively, both the AlN spacer layer and the GaN layer of the current blocking layer may have a thickness less than 5 nm. All or some of the GaN layers may be carbon-doped or iron-doped. Additionally or alternatively, all or some of the AlN layers may be carbon-doped or iron-doped. The GaN vertical connection may be n-doped.

[0057] The use of current blocking layers flanking the GaN vertical junction facilitates improved vertical HEMTs.

[0058] Such GaN vertical contacts can separate the source contact from the heterojunction of the heterostructure mesa. Thus, defect formation (e.g., related to metal diffusion) at the heterojunction can be avoided. This can improve the speed of vertical HEMTs. For example, metal impurities in the heterojunction can reduce the electron mobility at the heterojunction.

[0059] Such a current blocking layer can eliminate or reduce the need for other types of electrical separators between the two vertical HEMTs or between the vertical HEMTs and another component. For example, if the two vertical HEMTs are electrically separated by an oxide (e.g., on the side of at least one heterostructure mesa of the first and second vertical HEMTs) plus a current blocking layer disposed on the side of the GaN vertical junction, the oxide can be made thinner than if the current blocking layer was not used. If the oxide is thinner, the vertical HEMTs can be placed closer together. Thus, more transistors can be accommodated per unit area. As a result, the above-described current blocking layer on the side of the GaN vertical junction allows for a vertical HEMT with a small footprint and / or a vertical HEMT that can be densely integrated with other vertical HEMTs or that can be densely integrated with other components.

[0060] Moreover, such a current blocking layer can eliminate or reduce leakage currents that may be associated with other types of electrical separators. Current may be blocked by said current blocking layer in addition to or as an alternative to being blocked by an etched trench, or an oxidized or oxide-covered surface. It is understood that etched and / or oxidized and / or oxide-covered surfaces may provide trap states that may degrade device performance. For example, such trap states may provide a path for leakage current. Thus, the current blocking layer can reduce current leakage between two separate vertical HEMTs, or reduce current leakage between the source and gate of one individual vertical HEMT, or reduce current leakage between the source of one individual vertical HEMT and another device on the same chip. This can result in reduced transistor losses and more efficient operation.

[0061] It is further understood that carbon or iron may be particularly good dopants to achieve a sufficiently high doping concentration without leakage current. However, it should also be understood that other dopants may alternatively be used, for example other p-type dopants. For example, herein, the GaN vertical junction may be n-type GaN surrounded by a p-type GaN current blocking layer.

[0062] It should be understood that the electrical isolators described above may not only be used to block current flow between the first and second vertical HEMTs, but may alternatively or additionally be used to block current flow between the vertical HEMTs and any component of an electrical circuit.

[0063] According to a third aspect, there is provided a method for fabricating a vertical HEMT, comprising the steps of: Providing a base layer comprising a substrate; forming a pillar layer on the base layer, the pillar layer including at least one vertical pillar and a support material laterally enclosing the at least one vertical pillar; forming a heterostructure mesa on the pillar layer, the heterostructure mesa including an AlGaN layer and a GaN layer that together form a heterojunction; forming at least one source contact electrically connected to the heterostructure mesa; forming a gate contact on both the heterostructure mesa and the at least one vertical pillar; forming a drain contact, the drain contact being a metal contact via through the substrate, electrically connected to the at least one vertical pillar; A method is provided, wherein the at least one vertical pillar forms an electron transport channel between the drain contact and the heterojunction.

[0064] The base layer is Al on the substrate. (1-y) Ga (y) N layer, (1-y) Ga (y) The N-layer is sputtered epitaxially aligned with the crystal orientation of the substrate, preferably the substrate is silicon. <111> and the composition y is 0 or 1 or a value between 0 and 1.

[0065] The method may further include forming a current blocking layer by epitaxial regrowth of iron-doped or carbon-doped GaN.

[0066] The method may further include providing a field plate to the gate contact. The field plate is a metal extension of the gate contact, e.g., on top of the gate contact, and the field plate is vertically separated from the underlying semiconductor. The field plate may be vertically separated from the underlying semiconductor by a dielectric material, e.g., Al2O3. The field plate opposes the electric field on the gate and increases the breakdown voltage of the device.

[0067] The method may further include providing a field plate for the at least one source contact, the field plate extending over the gate contact. Thus, the field plate of the source contact may extend as a metal extension over the gate contact. The field plate of the source contact may be separated from the gate contact by a dielectric material.

[0068] For example, the method can include disposing a first source contact on one side of the gate contact and a second source contact on the other side of the gate contact, and providing a common field plate between the first and second source contacts, the common field plate extending over the gate contact.

[0069] Herein, the source contacts may include bond pins disposed at the same electrical potential.

[0070] This method is depositing a first insulating material on the side of the heterostructure; and / or depositing a second insulator on a side of at least one source contact; and / or The method can further include fabricating a current blocking layer on a side of the GaN connection between the at least one source contact and the heterostructure.

[0071] Forming the drain contact can include etching through at least a portion of the silicon substrate by deep reactive ion etching.

[0072] The above, as well as additional objects, features, and advantages of the inventive concept will be better understood from the following illustrative, non-limiting detailed description which refers to the accompanying drawings, in which like reference numerals are used for similar elements unless otherwise noted, and in which: [Brief description of the drawings]

[0073] [Figure 1] FIG. 1 is a diagram showing a vertical HEMT. [Diagram 2] FIG. 1 is a diagram showing a vertical HEMT. [Diagram 3] FIG. 1 is a diagram showing a vertical HEMT. [Figure 4] FIG. 1 is a diagram showing a vertical HEMT. [Diagram 5] FIG. 1 shows an electrical circuit comprising two vertical HEMTs. [Figure 6] FIG. 1 is a diagram showing a vertical HEMT. [Figure 7] 1 is a flow diagram of a method. [Figure 8] FIG. 1 is a diagram showing a vertical HEMT. [Figure 9] FIG. 1 is a diagram showing a vertical HEMT. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0074] The technical contents and detailed description of the present invention, together with the accompanying drawings, are described below according to the preferred embodiments, and the preferred embodiments are not used to limit the scope of the claims. The present invention may be implemented in many different forms and should not be construed as being limited to the embodiments described herein, but rather these embodiments are provided for thoroughness and completeness, so as to fully convey the scope of the present invention to those skilled in the art.

[0075] 1 to 4 show cross-sectional views of a vertical HEMT 100. Each vertical HEMT 100 shown comprises a base layer 300. The base layer 300 comprises a substrate 310 and a further nitride semiconductor layer. The substrate 310 is made of silicon. <111> In these figures, the base layer includes a substrate, an AlN layer 320 on the substrate 310, and a GaN layer 330 on the AlN layer 320. The AlN layer 320 and / or the GaN layer 330 may be sputtered layers. The AlN layer 320 may include a corrugated surface. For example, the AlN layer 320 may include AlN pillars, as shown. Hereinafter, the AlN pillars of the AlN layer 320 are referred to as base layer pillars. Such base layer pillars facilitate low defect density in subsequent layers.

[0076] It should be understood that these figures are schematic, for example, in reality, substrate 310 will generally be substantially thicker than the layers it supports.

[0077] Each vertical HEMT 100 shown further includes a drain contact 410, which is a metal contact via through the substrate 310. As shown, the drain contact 410 may extend into the nitride semiconductor layers of the vertical HEMT 100. In these figures, the drain contact 410 extends into the AlN layer 320 and the GaN layer 330. Thus, the drain contact may be laterally confined by the AlN layer and / or the AlGaN layer and / or the GaN layer.

[0078] Each illustrated vertical HEMT 100 further comprises a pillar layer 500 disposed on the drain contact 410. Each illustrated pillar layer 500 includes three vertical pillars 510, although it should be understood that the pillar layer 500 may include any number of vertical pillars 510, such as, for example, one, two, or ten vertical pillars 510. In these figures, the vertical pillars 510 are separated from the drain contact 410 by a GaN layer 330. Alternatively or additionally, the vertical pillars 510 may be separated from the drain contact 410 by another layer, such as an epitaxially grown layer, such as an epitaxially grown GaN layer. The region between the vertical pillars 510 and the drain contact 410 may be doped, for example n-doped, to provide electrical contact therebetween. Alternatively, the vertical pillars 510 may be in direct contact with the drain contact 410. Each pillar layer 500 shown includes a support material 520 that laterally encapsulates the vertical pillar 510. In these figures, the support material 520 is configured to be the first current blocking layer 11. The first current blocking layer 11 in these figures includes a superlattice of a GaN layer and an AlN intermediate layer, the AlN intermediate layer having a thickness of less than 5 nm. The GaN layer of the superlattice is carbon doped or iron doped. Herein, the vertical pillar 510 may include n-doped GaN. It should be understood that although the superlattice effectively blocks current, in some cases it may be sufficient to use a semiconductor with the opposite doping of the vertical pillar 510. For example, if an n-doped GaN vertical pillar 510 is used, the current blocking layer may be p-doped GaN or AlGaN.

[0079] Each vertical HEMT 100 shown further comprises a heterojunction 630 formed from an AlGaN layer 610 and a GaN layer 620. The AlGaN layer 610 is (1-x) Ga (x) N layers, where 0≦x≦0.9 or 0≦x≦0.75.

[0080] Heterojunction 630 is Al having a thickness of 20 to 22 nm, where 0.72≦x≦0.75 (1-x) Ga (x) N layer 610, and a GaN layer 620, Al (1-x) Ga (x) Advantageously, the N layer 610 is disposed directly on the GaN layer 620 .

[0081] It should be understood that the AlGaN layer of heterojunction 630 may include two or more sublayers.

[0082] Heterojunction 630 is Al having a thickness of 20 to 22 nm, where 0.72≦x≦0.75 (1-x) Ga (x) a first AlGaN sublayer 610′ which is an N layer; a second AlGaN sublayer 610″, which is an AlN layer having a thickness of less than 5 nm; and a GaN layer 620, Advantageously, a second AlGaN sublayer 610'' is disposed directly on the GaN layer, and a first AlGaN sublayer 610' is disposed directly on the second AlGaN sublayer 610''.

[0083] For example, as shown in FIGS. 2-4, the AlGaN layer 610 can include a first AlGaN sublayer 610′ and a second AlGaN sublayer 610″. The second AlGaN sublayer 610″ can have a higher Al content than the first AlGaN sublayer 610′ and can be located between the first AlGaN sublayer 610′ and the GaN layer 620. Furthermore, the second AlGaN sublayer 610″ can have a thickness less than 5 nm. In particular, the second AlGaN sublayer 610″ can be a 1 nm thin AlN spacer at the heterojunction 630, and the first AlGaN sublayer 610′ can be a 1 nm thin AlN spacer at the heterojunction 630. (0.27) Ga (0.73) There may be N layers.

[0084] For each vertical HEMT 100 shown, a mesa is etched from the nitride semiconductor structure. The mesa extends at least through the heterojunction 630. The AlGaN layer 610 and the GaN layer 620 are thus members of a heterostructure mesa 600 disposed on the pillar layer 500. In FIG. 1, the etched mesa is stepped down slightly below the heterojunction 630, i.e., the bottom of the etched mesa is slightly below the heterojunction 630. In this case, the etched mesa is the heterostructure mesa 600 disposed on the pillar layer 500. In FIGS. 2-4, the etched mesa is stepped down to the substrate 310, i.e., the bottom of the etched mesa is at the substrate 310. In this case, the portion of the etched mesa that is above the pillar layer 500 is the heterostructure mesa 600 disposed on the pillar layer 500.

[0085] Each vertical HEMT 100 shown further comprises two source contacts 420a, 420b electrically connected to the heterostructure mesa 600. The source contacts 420a, 420b may be electrically connected to the heterojunction 630 by electrical connections to the heterostructure mesa 600. The heterostructure mesa 600 may be doped, for example, in the region between the source contacts 420a, 420b and the heterojunction 630. The doped region may be a doped region in the AlGaN layer 610, for example an n-doped region. For example, in FIG. 1, the region of the AlGaN layer 610 between the source contacts 420a, 420b and the heterojunction 630 may be n-doped. Alternatively, there may be a vertical connection 20 leading from the source contacts 420a, 420b to a point close to the heterojunction 630, for example within 100 nm of the heterojunction 630. The vertical connects herein may be doped GaN, e.g., n-doped GaN. Such a vertical connect 20 is shown in Figures 2-4, where the vertical connect 20 is n-doped GaN leading from each source contact 420a, 420b to an AlN spacer 610''. The source contacts 420a, 420b may include a metal, e.g., Ni and / or Al, such as a Ni / Al bilayer.

[0086] As shown in Figures 2-4, a current blocking layer 12 may be disposed on the side of a GaN vertical connection 20, which is an electrical connection between at least one source contact 420a, 420b of a vertical HEMT 100 and a heterostructure mesa 600, said current blocking layer comprising carbon-doped or iron-doped GaN. Such a current blocking layer 12 and such a GaN vertical connection 20 may be disposed on a single vertical HEMT 100, as shown in Figures 2-4, or may be disposed with two separate vertical HEMTs 100', 100'', as shown in Figure 5.

[0087] Each vertical HEMT 100 shown further comprises a gate contact 430 disposed on the heterostructure mesa 600 and disposed above the vertical pillar 510. As shown, the vertical pillar 510 may be laterally aligned with the gate contact 430 such that the gate contact 430 laterally overlaps the vertical pillar 510. Thus, every vertical pillar 510 may be located below the gate contact 430. The gate contact 430 may comprise a metal, for example, Ti and / or Al and / or NiV, such as a triple layer of Ti / Al / NiV or TiN / Al / TiN.

[0088] As shown in Figures 1-3, the gate contact 430 and the portion of the drain contact 410 that extends into the nitride semiconductor layers of the vertical HEMT, in this case into the AlN layer 320 and the GaN layer 330, have the same lateral size and are laterally aligned. Thus, the gate contact 430 and the portion of the drain contact 410 that extends into the nitride semiconductor layers of the vertical HEMT may be fabricated using the same lithography mask. Figure 4 shows a gate contact 430 having a field plate 432 in the form of a metal extension of the gate contact 430 on top of the gate contact 430. The field plate 432 shown is vertically separated from the underlying semiconductor by a dielectric material 434. The dielectric material 434 may be Al2O3. The source contacts 420a, 420b may include a corresponding field plate 432 that extends over the gate contact 430. The two source contacts 420 a , 420 b may have a common field plate 432 that extends over the gate contact 430 .

[0089] One or more field plates 432 may alternatively or additionally be disposed on one or more of the source contacts 420a, 420b. Figure 9 shows a common field plate 432 between the first source contact 420a and the second source contact 420b, where the common field plate 432 extends over the gate contact 430.

[0090] It should be understood that Figures 1-4 are schematic cross-sectional views. There may be more than two source contacts 420a, 420b. Furthermore, the source contacts 420a, 420b may be of various shapes. As an example, Figure 6 shows the configuration of the source contacts 420a, 420b as two interdigitated contacts with a gate contact 430 snaking between them. The contacts are shown on a heterostructure mesa 600 on the substrate 310.

[0091] The nitride semiconductor structure between the gate contact 430 and the heterojunction 630 may be implemented in a variety of ways, as illustrated in FIGS.

[0092] 1, the gate contact 430 is disposed directly on the AlGaN layer 610 that forms part of the heterojunction 630. Herein, the AlGaN layer 610 that forms part of the heterojunction 630 may be intrinsically doped or n-doped, or may include an n-doped layer close to the heterojunction 630, for example within 100 nm of the heterojunction 630.

[0093] In a second example, as shown in Figures 2-4, the gate contact 430 is disposed on a p-doped GaN layer 820, which is disposed on an AlGaN layer 610 forming part of the heterojunction 630. Herein, the p-doped GaN layer 820 may be disposed directly on the AlGaN layer 610 forming part of the heterojunction 630, e.g., directly on the first AlGaN sublayer 610', as shown in Figure 2. Alternatively, as shown in Figures 3-4, the p-doped GaN layer 820 may be disposed on an intrinsically doped GaN layer 810, which is disposed on an intrinsically doped AlGaN layer 610' forming part of the heterojunction 630. Additionally, as shown in Figures 3-4, the intrinsically doped GaN layer 810 may be partially embedded within the intrinsically doped AlGaN layer 610 (embedded within the first AlGaN sublayer 610' in these figures). The intrinsically doped GaN layer 810 may have a thickness of at least 14 nm. The combined thickness of the intrinsically doped GaN layer 810 and the intrinsically doped AlGaN layer 610 may be in the range of 20-50 nm. Thus, in Figures 3-4, the distance from the heterojunction 630 to the top of the intrinsically doped GaN layer 810 may be in the range of 20-50 nm.

[0094] In a third example, as shown in FIG. 8, the gate contact 430 is disposed directly on the first AlGaN sublayer 610'.

[0095] The heterojunction 630 can guide electrons laterally from the source contacts 420a, 420b to the vertical pillar 510. In addition, the vertical HEMT can include one or more quantum wells 30 that are also configured to guide electrons laterally from the source contacts 420a, 420b to the vertical pillar 510. Such quantum wells are shown in Figures 3-4. The quantum wells can be disposed within the GaN layer 620 that forms part of the heterojunction 630. The one or more quantum wells can be InGaN quantum wells 30.

[0096] The materials or features of the vertical HEMT 100 discussed above may be combined in various ways. Non-limiting examples of material options for the vertical HEMT 100 of FIG.

[0097] Silicon <111> The substrate has a sputtered AlN layer 320 on the substrate 310, and a sputtered GaN layer 330 on the AlN layer 320. The pillar layer 500 includes a support material 520 in the form of an n-doped GaN vertical pillar 510 and a first current blocking layer 11. The first current blocking layer 11 includes a superlattice of GaN layers and AlN spacer layers, the AlN spacer layers of the superlattice having a thickness of less than 5 nm, and the GaN layers being carbon doped or iron doped. On top of the pillar layer 500 is an n-doped GaN layer, followed by two InGaN quantum wells separated by GaN, followed by a heterostructure forming a heterojunction 630. The heterostructure includes an AlN vertical pillar 510 having a thickness in the range of 10-25 nm. (0.27) Ga (0.73)The first AlGaN sublayer 610' in the form of an n-layer, a second AlGaN sublayer 610'' in the form of an AlN spacer having a thickness of 1 nm, and a GaN layer 620, with a heterojunction 630 formed at the interface between the AlN spacer 610'' and the GaN layer 620. The first AlGaN sublayer 610' is intrinsically doped, and on top of the first AlGaN sublayer 610' is an intrinsically doped GaN layer 810, followed by a p-doped GaN layer 820 and a gate contact 430, the gate contact 430 comprising Ni / Al. Furthermore, ohmic source contacts 420a, 420b comprising Ti / Al / NiV and a gate contact comprising TiN / Al / TiN are located. A vertical connection 20 of n-doped GaN leads from each source contact 420a, 420b to the AlN spacer 610''.

[0098] Two or more vertical HEMTs 100 may form an electrical circuit 200, such as a half bridge. An electrical circuit 200 comprising a first vertical HEMT 100' and a second vertical HEMT 100'' is shown in FIG. 5. The first vertical HEMT 100' and the second vertical HEMT 100'' of FIG. 5 share a common substrate 310. The first vertical HEMT 100' and the second vertical HEMT 100'' of FIG. 5 may be considered to correspond to the vertical HEMT described in connection with FIG. 4. As will be appreciated by those skilled in the art, in the electrical circuit 200, the source contacts 420 / gate contacts 430 / drain contacts 410 of the first vertical HEMT 100' may be connected in various ways to the source contacts 420 / gate contacts 430 / drain contacts 410 of the second vertical HEMT 100''. Thus, such connections are not explicitly shown in FIG. 5.

[0099] 5, a first insulator 710 is disposed on the side of the heterostructure mesa 600 of the first vertical HEMT 100' and the second vertical HEMT 100". In particular, the first insulator 710 is disposed between the heterostructure mesas 600 of the first vertical HEMT 100' and the second vertical HEMT 100".

[0100] Furthermore, a second insulator 720 is disposed on the side surfaces of the source contacts 420a, 420b of the first vertical HEMT 100' and the second vertical HEMT (100''). In FIG. 5, the first insulator 710 and the second insulator 720 are the same insulator.

[0101] Additionally, a second current blocking layer 12 is disposed on the side of the GaN vertical junction 20. The second current blocking layer 12 includes carbon-doped or iron-doped GaN. In this figure, the second current blocking layer 12 includes a superlattice of GaN layers and AlN spacer layers, where the AlN spacer layers of the superlattice have a thickness of less than 5 nm, and the GaN layers are carbon-doped or iron-doped.

[0102] 7 shows a method 2000 for fabricating a vertical HEMT 100. According to the method 2000, a base layer 300 is provided (S2020), the base layer 300 including a substrate 310. Providing the base layer 300 (S2020) includes forming a silicon <111> A substrate 310 is provided, and Al is deposited on the substrate, where 0≦y≦1. (1-y) Ga (y) sputtering an N layer 320; and (1-y) Ga (y) The method may include sputtering a GaN layer 330 onto the N layer 320. (1-y) Ga (y) The N layer 320 may be an AlN layer 320 and will be described as such below. The sputtered AlN layer 320 may be patterned prior to sputtering the GaN layer 330. The sputtered AlN layer 320 may be patterned to form a corrugated surface, for example to form base layer pillars.

[0103] A pillar layer 500 is formed (S2030) on the base layer 300, the pillar layer 500 including at least one vertical pillar 510 and a support material 520 that laterally encapsulates the at least one vertical pillar 510. Forming the pillar layer may include epitaxially growing a pillar material, for example n-doped GaN, and then etching the vertical pillar 510. The support material 520 may then be deposited around the vertical pillar 510, for example by epitaxial regrowth. A first current blocking layer 11 that encapsulates the vertical pillar 510 may be formed, for example by epitaxial regrowth of iron-doped or carbon-doped GaN.

[0104] Further nitride semiconductor layers may then be epitaxially grown, said layers including a heterostructure including an AlGaN layer 610 and a GaN layer 620 that together form a heterojunction 630. A mesa is then etched from the epitaxially grown layers, thus forming the heterostructure mesa 600 (S2040).

[0105] At least one source contact 420a, 420b is formed (S2050), for example by depositing metal in lithographically defined areas on the heterostructure mesa 600.

[0106] A gate contact 430 is formed (S2060) on both the heterostructure mesa 600 and the at least one vertical pillar 510, such as on a top surface of the heterostructure mesa 600 and on the at least one vertical pillar 510. The gate contact may be formed, for example, by depositing a metal in a lithographically defined area on the heterostructure mesa 600 (S2060).

[0107] The method 2000 may further include separating the substrate 310 from the AlN layer 320 (S3020) using a substrate removal or separation technique.

[0108] The method 2000 may further include forming (S3030) a trench in the AlN layer 320. The trench may also extend into the GaN layer 330, and possibly all the way to the at least one vertical pillar 510. The trench may be formed by etching a lithographically defined area of ​​a bottom surface of the AlN layer 320. The area may be lithographically defined by the same mask used to lithographically define the gate contact 430.

[0109] The method 2000 may further include etching through at least a portion of the substrate 310 by deep reactive ion etching to form a hole through the substrate 310. The substrate may then be bonded (S4020) to the AlN layer 320, such that the hole through the substrate 310 is connected to the trench. The hole may be larger than the trench. If precise alignment is desired during bonding, automated stepper equipment may be used to assist with alignment.

[0110] According to the method 2000, a drain contact 410 is formed (S2070) electrically connected to at least one vertical pillar 510. The drain contact 410 is formed as a metal contact via through the substrate 310 (S2070).

[0111] The drain contact 410 may be formed by depositing metal into holes through the substrate 310 and into trenches in the AlN layer 320 (S2070).

[0112] As an alternative to separating the substrate 310 from the AlN layer 320 (S3020) and bonding the substrate 310 to the AlN layer 320 (S4020), the substrate 310 may remain attached to the AlN layer 320. A hole through the substrate 310 may be etched, for example, at least partially by deep reactive ion etching, possibly into the AlN layer 320, and then filled with metal to form the drain contact 410. Spectroscopic detection may be used to stop the etch at the correct depth. For example, when the base layer 300 is formed, an InGaN layer may be deposited, for example, on top of the AlN layer 320 or on top of the GaN layer 330. When the hole is etched through the substrate 310, a spectroscopic wavelength signal for In may indicate that the InGaN layer has been reached. The etch may then be stopped.

[0113] During etching of the sputtered AlN layer 320 with the base layer pillars, the etch rate of the AlN in the base layer, which is the GaN overgrowth between the AlN pillars, may be faster than the etch rate of the GaN in the GaN layer 330 that encapsulates the base layer pillars. Thus, a pattern corresponding to the base layer pillars can be transferred to the drain contact 410, which thus also includes pillars, which extend into the nitride semiconductor layer, as shown in Figure 9. Such pillars of the drain contact 410 can advantageously increase the contact area between the drain contact 410 and the overlying nitride semiconductor layer.

[0114] Alternatively, during etching of the substantially thin AlN layer with base layer pillars and the substantially thick sputtered GaN layer 320, the etch rate of the MOCVD GaN in the base layer, which is the GaN overgrowth between the sputtered GaN pillars, can be etched at the same magnitude, i.e., 1:1. Thus, a trench may be formed in the sputtered AlN and sputtered GaN stack for the drain contact 410, which thus does not include a vertical pillar. The drain contact is formed by a substantially thin sputtered AlN layer together with the sputtered GaN layer to improve the crystal quality by the lattice-matched overgrowth of the MOCVD GaN, and the sputtered AlN prevents the GaN from alloying with silicon at high temperatures.

[0115] In one embodiment of the present invention, the substrate used to etch the vias may be silicon carbide. Preferred Embodiments In one preferred embodiment of the present invention, a vertical high electron mobility transistor (HEMT) (100) is provided, comprising a substrate (310), a drain contact (410) that is a metal contact via through the substrate (310), a pillar layer (500) disposed on the drain contact (410) and including at least one vertical pillar (510) and a support material (520) that laterally confines the at least one vertical pillar (510), and an AlGaN layer (630) disposed on the pillar layer (500) that together form a heterojunction (630). A vertical HEMT (100) is provided, comprising a heterostructure mesa (600) including an AlGaN layer (620) and a drain contact (410) and at least one source contact (420a, 420b) electrically connected to the heterostructure mesa (600), and a gate contact (430) disposed on the heterostructure mesa (600) and on at least one vertical pillar (510), the at least one vertical pillar (510) forming an electron transport channel between the drain contact (410) and the heterojunction (630). The AlGaN layer (610) of the heterojunction (630) is preferably intrinsically doped. The vertical HEMT (100) may comprise an intrinsically doped GaN layer (810) disposed over an intrinsically doped AlGaN layer (610) of a heterojunction (630) and laterally aligned over at least one vertical pillar (510), the GaN layer (810) having a thickness of at least 14 nm, and a combined thickness of the GaN layer (810) and AlGaN layer (610) of the heterojunction (630) in the range of 20-50 nm. The vertical HEMT (100) may comprise a p-doped GaN layer disposed over the AlGaN layer (610) of the heterojunction (630) and below a gate contact (430). The p-doped GaN may comprise a superlattice comprising a GaN layer and an Al(1-x)Ga(x)N layer, where 0.2≦x≦0.4. The superlattice may comprise a plurality of heterostructure layers, each heterostructure layer comprising one GaN layer and one Al(1-x)Ga(x)N layer. The superlattice may provide a p-type two-dimensional hole gas (2DHG) that provides a channel for conduction along the interface between the two layers. The periodicity of the superlattice may be 2-6 nm.Alternatively, the p-GaN may be annealed at high temperatures to remove the hydrogen in the lattice vacancies, which may degrade the doping profile of the device.

[0116] The distance between the gate contact (430) and the heterojunction (630) may be configured such that a voltage difference of at least 1V between the gate contact (430) and the at least one source contact (420a, 420b) opens a conduction channel in the heterojunction (630), such that the vertical HEMT (100) has a threshold voltage of at least 1V. The drain contact (410) may be laterally enclosed by an AlN layer and / or an AlGaN layer and / or a GaN layer. The vertical HEMT (100) may be laterally aligned with the gate contact (430). The vertical HEMT (100) may be laterally separated from at least one vertical pillar (510). The vertical HEMT (100) may have a lateral separation of at least 200 nm between the at least one source contact (420a, 420b) and the at least one vertical pillar (510). The vertical HEMT (100) may include a support material (520) configured to be the current blocking layer (11). At least one vertical pillar (510) may include n-doped GaN and the support material (520) may include a p-doped nitride semiconductor. The material (520) of the vertical HEMT (100) may include a superlattice of carbon-doped or iron-doped GaN layers and AlN spacer layers having a thickness of less than 5 nm.

[0117] In another preferred embodiment of the present invention, an electrical circuit is provided comprising a first vertical HEMT (100') and a second vertical HEMT (100''), the first vertical HEMT (100') and the second vertical HEMT (100'') being vertical HEMTs according to any one of the preceding claims, the electrical circuit comprising an electrical separator configured to block a current between the first vertical HEMT (100') and the second vertical HEMT (100''), the electrical separator comprising a first insulator (710) arranged on a side of a heterostructure mesa of at least one of the first vertical HEMT (100') and the second vertical HEMT (100''), and / or or a second insulator (720) disposed on a side of at least one source contact (420a, 420b) of at least one of the first vertical HEMT (100') and the second vertical HEMT (100''), and / or a current blocking layer (12) disposed on a side of a GaN vertical connection (20) that is an electrical connection between the at least one source contact (420a, 420b) of at least one of the first vertical HEMT (100') and the second vertical HEMT (100'') and a heterostructure mesa (600), wherein the current blocking layer comprises carbon-doped or iron-doped GaN.

[0118] A method (2000) for fabricating a vertical HEMT (100) includes providing (S2020) a base layer (300) including a substrate (310); forming (S2030) a pillar layer (500) on the base layer (300) including at least one vertical pillar (510) and a support material (520) laterally encapsulating the at least one vertical pillar (510); forming (S2040) a heterostructure mesa (600) on the pillar layer (500) including an AlGaN layer (610) and a GaN layer (620) that together form a heterojunction (630); and forming (S2040) a heterostructure mesa (600) electrically connected to the heterostructure mesa (600). The method (2000) includes forming (S2050) at least one source contact (420a, 420b) on both the heterostructure mesa and the at least one vertical pillar (510), forming (S2060) a gate contact (430) on both the heterostructure mesa and the at least one vertical pillar (510), and forming (S2070) a drain contact (410) that is a metal contact via through the substrate (310) electrically connected to the at least one vertical pillar (510), the at least one vertical pillar (510) forming an electron transport channel between the drain contact (410) and the heterojunction (630). (1-y) Ga (y) N layer (320), (1-y) Ga (y) The N-layer (320) is sputtered epitaxially aligned with the crystal orientation of the substrate (310), which is preferably silicon. <111> and the composition y is 0 or 1, or a value between 0 and 1. Forming (S2070) the drain contact (410) can include etching through at least a portion of the substrate (310) by deep reactive ion etching.

[0119] In one preferred embodiment of the present invention, a high electron mobility transistor (HEMT) (100) is provided, comprising a substrate (310), a drain contact (410), a heterostructure mesa (600) including an AlGaN layer (610) and a GaN layer (620) that together form a heterojunction (630), a source contact (420a) and a drain contact (420b) electrically connected to the heterostructure mesa (600), and a gate contact (430) disposed on the heterostructure mesa (600). The gate contact may comprise TiN / Al / TiN. The AlGaN layer (610) of the heterojunction (630) is preferably intrinsically doped. The Al(x)Ga(1-x)N layer (610) may further comprise a thickness of 20-22 nm, with composition x being 25-28% Al, and forming a heterojunction (630) with the GaN layer (620). The HEMT (100) may comprise an intrinsically doped GaN layer (810) disposed on the intrinsically doped AlGaN layer (610) of the heterojunction (630). The HEMT (100) may comprise a p-doped GaN layer disposed on the AlGaN layer (610) of the heterojunction (630) and below a gate contact (430). The distance between the gate contact (430) and the heterojunction (630) may be configured such that a voltage difference of at least 1V between the gate contact (430) and the at least one source contact (420a, 420b) opens a conduction channel in the heterojunction (630), such that the HEMT (100) has a threshold voltage of at least 1V. The drain contact (410) may be laterally confined by an AlN layer and / or an AlGaN layer and / or a GaN layer. The vertical HEMT (100) may be laterally aligned with the gate contact (430). The vertical HEMT (100) may be laterally separated from the at least one vertical pillar (510). The HEMT (100) may have a lateral separation of at least 200 nm between the at least one source contact (420a, 420b) and the at least one vertical pillar (510).The vertical HEMT (100) can include a support material (520) configured to be the current blocking layer (11). The material (520) of the HEMT (100) can include a superlattice of carbon-doped or iron-doped GaN layers and AlN spacer layers having a thickness of less than 5 nm.

[0120] In another preferred embodiment of the present invention, an electrical circuit is provided comprising a first HEMT (100') and a second HEMT (100''), the first (100') and the second (100'') comprising an electrical separator configured to prevent a current flow between the first HEMT (100') and the second HEMT (100''), the electrical separator being a first insulator (710) disposed on a side of a heterostructure mesa of at least one of the first HEMT (100') and the second HEMT (100'') and / or a first insulator (710) disposed on a side of a heterostructure mesa of at least one of the first HEMT (100') and the second HEMT (100''). An electrical circuit is provided comprising a second insulator (720) disposed on a side of at least one source contact (420a, 420b) of at least one of the HEMTs (100'') and / or a current blocking layer (12) disposed on a side of a GaN vertical connection that is an electrical connection between at least one source contact (420a, 420b) of at least one of the first HEMT (100') and the second HEMT (100'') and a heterostructure mesa (600), the current blocking layer comprising carbon-doped or iron-doped GaN. The HEMT (100) may comprise a p-doped GaN layer disposed above the AlGaN layer (610) of the heterojunction (630) and below the gate contact (430). The p-doped GaN may comprise a superlattice comprising a GaN layer and an Al(y)Ga(1-y)N layer, where 0.2≦x≦0.4. The superlattice may include multiple heterostructure layers, each of which includes one GaN layer and one Al(z)Ga(1-)N layer. The superlattice may provide a p-type two-dimensional hole gas (2DHG) that provides a channel for conduction along the interface between the two layers. The periodicity of the superlattice may be 2-6 nm. Alternatively, the p-GaN may be annealed at high temperatures to remove hydrogen in the lattice vacancies, which may degrade the doping profile of the device.

[0121] Although the inventive concept has been described primarily with reference to a limited number of examples, those skilled in the art will readily appreciate that examples other than those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

Claims

1. A vertical high electron mobility transistor (HEMT) (100), comprising: a substrate (310); a drain contact (410) which is a metal contact via passing through the substrate (310); a pillar layer (500) disposed on the drain contact (410) and including at least one vertical pillar (510) and a support material (520) that laterally encloses the at least one vertical pillar (510); a hetero - structure mesa (600) disposed on the pillar layer (500) and including an AlGaN layer (610) and a GaN layer (620) that together form a hetero - junction (630); at least one source contact (420a, 420b) electrically connected to the hetero - structure mesa (600); a gate contact (430) disposed on the hetero - structure mesa (600) and disposed on the at least one vertical pillar (510); a current blocking layer (12) disposed on a side surface of a GaN vertical connection (20), which is an electrical connection between the at least one source contact (420a, 420b) and the hetero - structure mesa (600) of the vertical HEMT (100), and includes carbon - doped or iron - doped GaN; a vertical HEMT (100), wherein the at least one vertical pillar (510) forms an electron transport channel between the drain contact (410) and the hetero - junction (630).

2. The AlGaN layer (610) of the hetero - junction (630) is intrinsically doped, and the vertical HEMT (100) further comprises: an intrinsically doped GaN layer (810) disposed on the intrinsically doped AlGaN layer (610) of the hetero - junction (630) and laterally aligned on the at least one vertical pillar (510), the GaN layer (810) having a thickness of at least 14 nm, and a combined thickness of the GaN layer (810) and the AlGaN layer (610) of the hetero - junction (630) being in the range of 20 - 50 nm. The vertical HEMT (100) according to Claim 1.

3. The vertical HEMT (100) according to claim 1, further comprising a p-doped GaN layer disposed on the AlGaN layer (610) of the heterojunction (630) and under the gate contact (430).

4. The vertical HEMT (100) according to claim 1, wherein the distance between the gate contact (430) and the heterojunction (630) is configured such that a voltage difference of at least 1 V between the gate contact (430) and the at least one source contact (420a, 420b) opens a conduction channel in the heterojunction (630), whereby the vertical HEMT (100) has a threshold voltage of at least 1 V.

5. The vertical HEMT (100) according to claim 1, wherein the drain contact (410) is laterally sealed by an AlN layer and / or an AlGaN layer and / or a GaN layer.

6. The vertical HEMT (100) according to claim 1, wherein the at least one vertical pillar (510) is laterally aligned with the gate contact (430).

7. The vertical HEMT (100) according to claim 1, wherein the at least one source contact (420a, 420b) is laterally separated from the at least one vertical pillar (510).

8. The vertical HEMT (100) according to claim 7, wherein the lateral separation between the at least one source contact (420a, 420b) and the at least one vertical pillar (510) is at least 200 nm.

9. The vertical HEMT (100) according to claim 1, wherein the support material (520) is a current blocking layer (11).

10. The vertical HEMT (100) according to claim 9, wherein the support material (520) includes a superlattice of a carbon-doped or iron-doped GaN layer and an AlN spacer layer having a thickness of less than 5 nm.

11. The vertical HEMT (100) according to claim 1, wherein the at least one vertical pillar (510) includes n-doped GaN and the support material (520) includes a p-doped nitride semiconductor.

12. The vertical HEMT (100) according to claim 10, wherein the support material (520) includes a superlattice of a carbon-doped or iron-doped GaN layer and an AlN spacer layer having a thickness of less than 5 nm.

13. An electric circuit comprising a first vertical HEMT (100') and a second vertical HEMT (100''), wherein the first vertical HEMT (100') and the second vertical HEMT (100'') are vertical HEMTs according to any one of claims 1 to 12, and the electric circuit comprises an electrical separator configured to block current between the first vertical HEMT (100') and the second vertical HEMT (100''), and the electrical separator is a first insulator (710) disposed on a side surface of at least one of the heterostructure mesas of the first vertical HEMT (100') and the second vertical HEMT (100''), and / or a second insulator (720) disposed on a side surface of at least one of the at least one source contact (420a, 420b) of the first vertical HEMT (100') and the second vertical HEMT (100''), and / or the electric circuit including the current blocking layer (12) disposed on a side surface of the GaN vertical connection of at least one of the first vertical HEMT (100') and the second vertical HEMT (100'').

14. A method (2000) for fabricating a vertical HEMT (100), comprising: providing (S2020) a base layer (300) including a substrate (310); forming (S2030) on the base layer (300) a pillar layer (500) including at least one vertical pillar (510) and a support material (520) that laterally seals the at least one vertical pillar (510); forming (S2040) on the pillar layer (500) a heterostructure mesa (600) including an AlGaN layer (610) and a GaN layer (620) that together form a heterojunction (630); forming (S2050) at least one source contact (420a, 420b) electrically connected to the heterostructure mesa (600); forming (S2060) a gate contact (430) on both the heterostructure mesa and the at least one vertical pillar (510); forming (S2070) a drain contact (410), which is a metal contact via passing through the substrate (310), electrically connected to the at least one vertical pillar (510). It is disposed on a side surface of a GaN vertical connection (20), which is an electrical connection between the at least one source contact (420a, 420b) of the vertical HEMT (100) and the hetero-structure mesa (600), and includes forming a current blocking layer (12) containing carbon-doped or iron-doped GaN. The method (2000) wherein the at least one vertical pillar (510) forms an electron transport channel between the drain contact (410) and the hetero-junction (630).

15. The base layer (300) is Al on the substrate (310). （１－ｙ） Ga （ｙ） The N layer (320) is included, and the Al （１－ｙ） Ga （ｙ） The N layer (320) is sputtered with epitaxial alignment to the crystal orientation of the substrate (310). Preferably, the substrate (310) is silicon <111>, and the value of the composition y is 0 or 1 or a value between 0 and 1. The method (2000) according to claim 14.

16. The method (2000) according to claim 14 or 15, wherein forming the drain contact (410) (S2070) includes etching through at least a part of the substrate (310) by deep reactive ion etching.

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