Wide-Voltage Gate Driver Using Low-Gate-Oxide Transistors

Abstract

The gate driver circuit includes first to third transistors (M1, M3, M4), a first voltage clamp (206), and control logic (210). The first transistor (M1) has a first control input and first and second current terminals. The first current terminal is coupled to a first voltage terminal. The first voltage clamp is coupled between the first voltage terminal and the first control input. The second transistor (M3) is coupled between the first control input and the second voltage terminal. The third transistor (M4) is coupled between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors, thereby turning on the first transistor, and the first control logic (210) is configured to turn off the second transistor after the first transistor is turned on, while keeping the third transistor on to keep the first transistor on.

Description

[Technical field]

[0001] A transistor has a control input and a pair of current terminals. In the example of a metal oxide semiconductor field effect transistor (MOSFET), the control input is the gate and the current terminals are the source and drain. A gate driver is a circuit that receives a digital control signal and produces an output voltage of the appropriate magnitude to turn the transistor on and off. Summary of the Invention

[0002] In one example, a gate driver circuit includes first, second, and third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors, thereby turning on the first transistor. The first control logic is configured to turn off the second transistor after the first transistor is turned on, while maintaining the third transistor in an on state to maintain the first transistor in an on state. [Brief description of the drawings]

[0003] [Figure 1] A pair of transistors are shown, each having a control input that in one example is coupled to the output of a respective driver.

[0004] [Diagram 2] 1 is an example of a gate driver circuit.

[0005] [Diagram 3]3 is a logic circuit of a portion of the gate driver circuit of FIG. 2.

[0006] [Figure 4] 3 is a circuit implementation of a dual knee clamp that can be used in the gate driver of FIG. 2 in one example.

[0007] [Diagram 5] 1 is a graph illustrating dual knee operation of a dual knee clamp in one example.

[0008] [Figure 6] 3 is another circuit implementation of a dual knee clamp that can be used in the gate driver of FIG. 2 in one example.

[0009] [Figure 7] 1 is an example of a gate driver circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In some applications, the transistors should be turned on with a gate-source voltage (Vgs) of, for example, 7V or more. Such applications include buck converters and motor controllers, both of which include a high-side (HS) transistor coupled to a low-side (LS) transistor at a switch node. Thus, the gate driver for each HS and LS transistor must be capable of generating an appropriately sized output voltage (for example, 7V or more). However, many semiconductor processes produce transistors for use in gate drivers that have a maximum rating for their Vg that is less than the voltage that needs to be generated on the output of the gate driver. Such transistors have a limited Vgs voltage rating due to the thin gate oxide layer formed on the gate of the transistor. In one example, a 5V (Vgs) rated transistor is used in a gate driver whose output voltage needs to be higher than 5V. In one gate driver circuit, a sub-rail is generated to generate a supply voltage between the main supply voltage of the gate driver and ground to ensure that the 5V Vgs of the transistor is not exceeded. Such gate drivers may unfortunately include a pass transistor that generates a large sub-rail to provide a sufficiently large current when the main supply voltage to the gate driver is rather low. Also, such gate drivers may not produce adequate output voltages and currents at lower supply voltage levels. However, the gate drivers described herein address these issues.

[0011] FIG. 1 shows an example of an HS transistor coupled to an LS transistor at a switch node (SW). Gate driver 100a is coupled to and drives a voltage on the gate of the HS transistor relative to the SW node, and therefore also connects to the SW node. Gate driver 100b is coupled to and drives a voltage on the gate of the LS transistor relative to ground, and therefore also connects to ground. HS_ON is an input control signal to gate driver 100a, indicating whether the HS transistor should be on or off. LS_ON is an input control signal to gate driver 100b, indicating whether the LS transistor should be on or off. Each gate driver 100a, 100b generally has the same circuit architecture, an example of which is shown in the schematic diagram of FIG. 2.

[0012] 2 is a circuit diagram of a gate driver 200 in one example. The gate driver 200 can be used to implement either or both of the gate drivers 100a and 100b in FIG. 1. The gate driver 200 includes voltage terminals 201 and 203 and a gate terminal 202. The gate 202 couples to the gate of the respective HS or LS transistor. The voltage terminal 203 couples to the SW node in the case of an HS transistor and to ground in the case of an LS transistor. The voltage terminal 201 is a supply voltage rail for the gate driver 200.

[0013] The gate driver 200 includes transistors M10-M18, resistors R1-R5, dual knee clamps 206, 208, 230, control logic circuit A 210, control logic circuit B, and an inverter 228. M1 and M2 are coupled in series between a voltage terminal 201 and a voltage terminal 203. In this example, M1 is a p-type MOSFET (PMOS transistor) and M2 is an n-type MOSFET (NMOS transistor). The source of M1 is coupled to the voltage terminal 201 and the source of M2 is coupled to the voltage terminal 203. The drains of M1 and M2 are coupled together to form a gate terminal 202. The gate driver 200 receives an input control signal 205, labeled "DRV" in FIG. 2. The control signal DRV represents HS_ON or LS_ON in FIG. 1. In response to DRV being a logic high ("1"), the gate driver 200 turns M1 on and turns M2 off. When M1 is on, the voltage on gate terminal 202 is forced high towards VCC. When M2 is on, the voltage on gate terminal 202 is forced low towards ground / SW.

[0014] Dual knee clamp 206 is coupled between voltage terminal 201 and the gate of M1. Dual knee clamp 208 is coupled between the gate of M2 and voltage terminal 203. Thus, dual knee clamp 206 is coupled across the gate and source of M1, and dual knee clamp is coupled across the gate and source of M2. Dual knee clamp 206 ensures that the Vgs of M1 does not exceed a safe operating voltage. In one example, M1 and M2 are 5V (Vgs) transistors, so dual knee clamp 206 ensures that the Vgs of M1 does not exceed 5V, and dual knee clamp 208 ensures that the Vgs of M2 also does not exceed 5V. However, the drain source voltages (Vds) of M1 and M2 are rated for much higher voltages (e.g., 20V).

[0015] M3 and M4 are NMOS transistors. The drains of M3 and M4 are coupled to the gate of M1. In response to M3 and M4 being turned on, M1 is turned on. M3 is of a larger size (the size being the ratio of channel width (W) to channel length (L)) than M1. Thus, the current through M3 is larger than the current through M4. In one example, the current through M3 is 30 milliamps (mA), while the current through M4 is 15 microamps. Thus, M3 represents a larger current path between the gate of M1 and the voltage terminal 203 than the current path through M4. Control logic A210 controls the on and off states of transistors M3 and M4, and therefore the on and off states of the larger and smaller current paths between the gate of M1 and the voltage terminal 203. Control logic A210 includes an edge-triggered flip-flop 212, an AND gate 214, and a delay 216. When M1 should be turned on (DRV is asserted logic high), control logic circuit A210 turns on both M3 and M4 to discharge the gate of M1 very quickly, thus turning M1 on very quickly. Once M1 is on, control logic circuit A210 turns off M3 (the larger current path) while keeping M4 on to keep M1 on. In this example, each dual knee clamp 206 / 208 generates an output control signal labeled CLAMP1_ON / CLAMP2_ON that indicates whether the respective dual knee clamp detects that the Vgs of the respective M1 and M2 transistors has exceeded a clamping voltage (e.g., 5V). This control signal indicates that the respective M1 and M2 transistors are on. Control logic circuit A210 receives CLAMP1_ON from dual knee clamp 206, and control logic circuit B220 receives CLAMP2_ON from dual knee clamp 208. Control logic A210 responds to the assertion of CLAMP1_ON (eg, a logic high) by turning off M3.

[0016] With M2 on and M1 off, the gate driver 200 operates as follows to turn M1 on: The DRV signal 205 transitions from low to high to command the gate driver 200 to turn M1 on. In response to a logic high assertion of the DRV signal 205, M7 turns on, pulling the gate of M2 towards ground, thereby turning M2 off (or otherwise ensuring that M2 remains off). A positive assertion of the DRV signal 205 also turns on M6, which also turns on M5 via the set (S) input of flip-flop 212. When both M5 and M6 are on, current flows from the voltage terminal 201 through M8, through M5 and M6 to the ground / SW terminal 203. M8, M9, and M10 are configured as a current mirror. Thus, the current through M8 is mirrored through M9, thereby turning off M17. M17, which was previously on, turned on M2. Therefore, when M17 is off (and M7 is on), it ensures that M2 is off.

[0017] The control logic A 210 includes a delay 216 and an AND gate 214. An input of the delay 216 receives the DRV signal 205. An output of the delay is coupled to an input of the AND gate and to the gate of M4. An output of the AND gate 214 is coupled to the gate of M3. A positive assertion of the DRV signal 204 sets a flip-flop, thereby driving its Q output high, turning on M5 (as described above) and providing a logic high to one input of the AND gate 214. Following expiration of the delay time period implemented by the delay 216, the other input of the AND gate 214 is driven high, resulting in M3 being turned on. Expiration of the delay time also results in M4 being turned on. The time delay from the positive assertion of the DRV signal 205 provides sufficient time to ensure that M2 is turned off before the control logic A 210 attempts to turn on M1.

[0018] When both M3 and M4 are on, the combined current through the larger current path (M3) and the smaller current path (M4) flows from the gate of M1, discharging the gate of M1 and turning M1 on quickly. With M1 on, the voltage on the gate terminal 202 rises quickly toward the voltage on the voltage terminal 201. Also, the Vgs of M1 increases as M1 turns on. When the Vgs of M1 reaches a clamping voltage implemented in the dual knee clamp 206, the dual knee clamp 206 activates to prevent the Vgs of M1 from exceeding the clamping voltage (e.g., 5V). At the point when the dual knee clamp is activated to clamp the Vg of M1, the dual knee clamp 206 asserts CLAMP1_ON to a logic high level. CLAMP1_ON is coupled to the reset (R) input of flip-flop 212. Flip-flop 212 responds to the positive assertion of CLAMP1_ON by causing its Q output to be a logic low. The logic low on the Q output of flip-flop 212 causes the output of AND gate 214 to be a logic low, thereby turning off the larger current path (M3). The smaller current path (M4) remains on, thereby keeping M1 on. By turning off M3, the average quiescent current of gate driver 200 is reduced compared to if M3 was kept on.

[0019] The operation of the gate driver 200 to turn M1 off and M2 on is similar to that described above. The control logic B 220 also includes a flip-flop 222, an AND gate 224, and a delay 226. The gate driver 200 responds to a logic low assertion of the DRV signal by turning M1 off and turning M2 on. Through an inverter 228, the DRV signal 205 sets the flip-flop, thereby forcing its Q output high. At this point, both M13 and M14 are on, which causes current to flow through resistor R5, thereby forcing the gate of M16 low enough to turn M16 on, thus turning M1 off. While M1 is on and M2 is off, M7 is turned on, preventing M2 from turning on, as described above. When the DRV signal 205 goes logic low to turn M2 on, the DRV signal 205 forces M7 off.

[0020] Following a delay (implemented by delay 226) from the negative edge of the DRV signal 205, both M11 and M12 are turned on, thereby turning on the larger current path (M11) and the smaller current path (M12). The combined current flows through M15 and is mirrored through M17, thereby forcing the gate of M2 to increase and turn on.

[0021] The dual knee clamp 208 ensures that the Vgs of M2 does not exceed a clamping voltage (e.g., 5V). When the Vg of M2 reaches the clamping voltage of the dual knee clamp 208, the dual knee clamp 208 asserts to a logic high state CLAMP2_ON which resets the flip-flop 222. In response to the Q output of the flip-flop 222 going logic low, the larger current path implemented by M11 is turned off, thereby reducing the average quiescent current of the gate driver 200.

[0022] The voltage on voltage terminal 201 can be substantially higher than the maximum Vgs allowed for M1 and M2 (as well as other transistors in gate driver 200). Dual knee clamps 206 and 208 protect M1 and M2 from experiencing voltage differences between their gates and sources that could damage the transistors. In one example, M1 and M2 can be drain-extended transistors that safely operate with Vg up to 5V and Vd up to 20V. Also, the only sub-rail voltage in driver 200 is generated on sub-rail 245 by sub-rail reference 240 and M18. Sub-rail 245 is used to power the digital electronics including flip-flops 212 and 222, inverter 228, delays 216 and 226, and AND gates 214 and 224, and does not use transistors that carry the full output current of the gate driver.

[0023] Although AND gates 214 and 224 are shown in the example of FIG. 2, in other examples, different types of logic gates or combinations of logic gates can be used.

[0024] The additional dual knee clamp 230 is included for much the same reasons as the dual knee clamps 206 and 208. M16 in FIG. 2 is turned on by pulling its gate to ground with a relatively high current, and then a small current is used to keep M16 on. The dual knee clamp 230 is used to protect the gate of M16. In an alternative example, a Zener diode can be used as a clamp to protect the gate of M16, since the high current for M16 is not as high as that of M1 and M2.

[0025] The voltage on the voltage terminal 201 can be low enough with respect to the ground / SW node terminal 203 that either or both of the dual knee clamps 206 and 208 do not operate to clamp the Vg of the respective M1 and M2. Thus, Vgs can remain below the clamping voltage of the dual knee clamps. This condition can occur for lower levels of the supply voltage (VCC). When this condition occurs, the dual knee clamps do not assert their output control signals CLAMP1_ON and CLAMP2_ON. Also, if neither CLAMP1_ON nor CLAMP2_ON assert high, the respective flip-flops 212 and 214 do not receive a logic high on their reset inputs, and therefore the larger current paths (M3 and M11) remain on even after M1 / M2 turn on.

[0026] 3 is an example latch 300 that can be used to implement either or both of flip-flops 212 and 222 of FIG. 2. Latch 300 includes an RS flip-flop 302, a delay 304, and an OR gate 306. The Q output of flip-flop 302 is coupled to an input of delay 304, the output of which is coupled to an input of OR gate 306. The other input of OR gate 306 is coupled to a respective dual knee clamp and therefore receives the CLAMP1_ON or CLAMP2_ON (CLAMPx_ON) output control signal of that clamp. Therefore, flip-flop 302 is reset (positive assertion on its R input) either when the CLAMPx_ON signal is asserted high by the clamp or a fixed time delay after the Q output of the flip-flop becomes a logic high. Thus, the larger current path controlled by the flip-flop is turned off in response to the clamp detecting the Vgs of the respective M1 or M2 equal to the clamping voltage of the clamp, but is turned off regardless after being turned on for a fixed period of time that ensures that the corresponding M1 or M2 is fully on.

[0027] Figure 4 is an example circuit for implementing the dual knee clamp 208. Figure 5 is a graph illustrating the dual knee relationship between the current through the clamp (Iclamp) and the voltage difference (Vclamp) between the gate of M2 and the voltage terminal 203. The first knee is illustrated at 501 and the second knee is illustrated at 502.

[0028] The dual knee clamp 208 includes a current source I1 ("I1" refers to both the current source and the magnitude of the current it generates), resistors RC1, RC2, and R41, transistors MC1 and MC2, a current mirror 402, and an inverter 410. Resistor RC1 is coupled in series with current source I1 to generate a reference voltage (VREF, e.g., 3V) on the gate of MC1. That voltage clamps the gate voltage of MC1. As a PMOS device, MC1 does not turn on until its source voltage exceeds the transistor's threshold voltage above its gate voltage. When M17 turns on, the gate voltage on M2 increases. When the gate voltage of M2 is greater than MC1's threshold voltage above MC1's gate voltage (VREF), MC1 turns on and the source of MC1 and the gate of MC2 are at a threshold voltage above VREF. This is the first "knee" 501. In one example, the first knee is at a Vclamp voltage Vth1 of 4V.

[0029] When the voltage on the gate of M1 increases to a point that is one threshold voltage above its gate voltage (e.g., 5V for a Vth1 of 4V, assuming a Vt of MC2 of 1V), MC2 also turns on. At that point (second knee 502), both MC1 and MC2 are on. MC2 is a larger transistor than MC1, so more Iclamp current flows through MC2 than MC1. The Vgs of M17 is fixed by the gate voltage used to turn M17 on and the drain voltage of M17, which is the voltage of the voltage terminal 201. Therefore, M17 acts as a current source to generate a fixed current as Iclamp through the dual knee clamp 208. The majority of Iclamp (e.g., 90%) flows through MC2. The voltage on the gate of MC2 is fixed, and the voltage on the source of MC2 is set to a level that generates an Iclamp current through MC2, so that the current is balanced against the current source of M17. Therefore, the source voltage of MC2 remains fixed despite further attempts to increase the gate voltage of M2.

[0030] When MC2 turns on, current mirror 402 sinks current through resistor R41. Before MC2 turns on, the input of inverter 410 is pulled high through resistor R41 so the output of the inverter (CLAMP2_ON) is a logic low. When MC2 turns on (which occurs when the voltage between the gate of M2 and terminal 203 reaches second knee 502), the input to inverter 410 becomes a logic low and CLAMP2_ON becomes a logic high.

[0031] FIG. 6 is an example circuit for implementing the dual knee clamp 206. The architecture of this circuit is almost the same as that of the dual-knee clamp 208 of FIG. 4. The PMOS devices MC1 and MC2 of FIG. 4 are the NMOS devices MC1A and MC2A in FIG. 6. As the gate of M1 decreases, MC1A turns on first at the first knee, then MC2A turns on at the second knee. In this example, no inverter is included. This is because the voltage across R6 (CLAMP1_ON) goes low first before the clamp reaches the second knee. At that point, current flows through resistor R6 and CLAMP1_ON goes to logic high.

[0032] FIG. 7 is a circuit diagram of a gate driver 700 in one example. The gate driver 700 can be used to implement either or both of the gate drivers 100a and 100b in FIG. 1. The gate driver 700 is generally similar to the gate driver 200 in FIG. 2. The differences are as follows. As mentioned above, the gate driver 200 includes feedback control signals CLAMP1_ON and CLAMP2_ON from the dual knee clamps 206 and 208 indicating that the respective M1 and M2 are turned on, and the control logic circuits 210 and 220 respond to the assertion of CLAMP1_ON and CLAMP2_ON by turning off the respective larger current paths (M3 and M11). However, the gate driver 700 has dual knee clamps 706 and 708 similar to the corresponding dual knee clamps 206 and 208, but does not have output circuitry to generate the feedback control signals CLAMP1_ON and CLAMP2_ON. For example, compared to clamp 206 of FIG. 6, clamp 706 of FIG. 7 does not have current mirror 602 or resistor R6 to generate CLAMP1. Similarly, compared to clamp 208 of FIG. 4, clamp 708 of FIG. 7 does not have current mirror 402, resistor R41, or inverter 410 to generate CLAMP2. Clamp 706 is a dual knee clamp for M1 and a dual knee clamp for M16. Whereas in FIG. 2, two separate dual knee clamps 206 and 230 were included to protect M1 and M16, respectively, in FIG. 7, a single dual knee clamp provides the same functionality to protect M1 and M16. MC4A is a voltage protection device for the current source (I1) below it. MC4A may be omitted in other examples if current source I1 can handle the applicable voltage, e.g., 20V. MC3A and resistor RC3 are coupled together to provide a clamp for M16.

[0033] In Figure 7, the control logic is identified as control logic circuits 710 and 720. Another difference between the gate drive 700 of Figure 7 and the gate driver 200 of Figure 2 is that the control logic circuits 710 and 720 of Figure 7 include one shots 712 and 722 instead of flip-flops. These timed one shots activate the respective larger current paths (M3) and (M11) for a defined period of time (the pulse width of the one shot's output pulse), so the control logic circuits 710 and 720 do not rely on feedback control signals to identify when M1 and M2 are turned on. The width of the pulse from the one shot is long enough to ensure that M1 and M2 have enough time to turn on.

[0034] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C, where intervening component C does not change the functional relationship between device A and device B, such that device B becomes controlled by device A via the control signal generated by device A.

[0035] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components, through the interconnection of the device, or a combination thereof.

[0036] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to mean an interconnection between, or the termination of, a device element, a circuit element, an integrated circuit, a device, or other electronic or semiconductor component.

[0037] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources, e.g., by an end user and / or a third party, during or after manufacture, to form the described structure.

[0038] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be substituted. For example, a p-type metal oxide silicon field effect transistor ("MOSFET") may be substituted for an n-type MOS FET with little or no modification to the circuit. Also, other types of transistors may be used, such as a bipolar junction transistor (BJT). The "control input" of a transistor is the gate of a MOSFET or the base of a BJT. The "current terminal" of a transistor is the drain or source of a MOSFET, or the collector or emitter of a BJT.

[0039] The circuits described herein are reconfigurable to include additional or different components to provide at least partially similar functionality to that available prior to component replacement. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0040] Use of the term "ground" in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable for the teachings of the present description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the present claims.

[0041] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. A gate driver circuit, a first transistor having a first control input, a first current terminal coupled to the first voltage terminal, and a second current terminal; a second transistor having a second control input, a third current terminal coupled to the second current terminal and to an output terminal of the gate driver circuit, and a fourth current terminal; a first voltage clamp coupled between the first voltage terminal and the first control input; a second voltage clamp coupled between the second control input and the second voltage terminal; a first current path coupled between the first control input and the second voltage terminal; a second current path coupled between the first control input and the second voltage terminal, the second current path configured to provide a smaller current than the first current path; First control logic, turning on the first transistor by turning on both the first and second current paths; turning on the second current path to maintain the first transistor in an on state, while turning off the first current path after the first transistor is turned on; the first control logic configured to a gate driver circuit including:

2. 2. The gate driver circuit of claim 1, the first voltage clamp includes a first voltage clamp control output, the first voltage clamp configured to assert a signal on the first voltage clamp control output in response to a voltage difference between the first voltage terminal and the first control input exceeding a threshold; The gate driver circuit, wherein the first control logic includes a flip-flop having a first input coupled to the first voltage clamp control output, a second input, and an output.

3. 3. The gate driver circuit of claim 2, the first control logic further comprises a logic gate having a first input coupled to the output of the flip-flop, a second input, and a logic gate output coupled to the first current path.

4. 3. The gate driver circuit of claim 2, A gate driver circuit, wherein the flip-flop is a set-reset flip-flop.

5. 2. The gate driver circuit of claim 1, The gate driver circuit, wherein the first voltage clamp is a dual knee voltage clamp and the second voltage clamp is also a dual knee voltage clamp.

6. 2. The gate driver circuit of claim 1, the first voltage clamp: a current source coupled to the third voltage terminal; a first resistor coupled to the third voltage terminal; a third transistor having a control input coupled to the third voltage terminal and a pair of current terminals; a fourth transistor having a control input coupled to one of the pair of current terminals; a gate driver circuit including:

7. 7. The gate driver circuit of claim 6, a current mirror, the first voltage clamp coupled to the other of the pair of current terminals; a second resistor coupled to the current mirror; A gate driver circuit configured such that a voltage across the second resistor generates the first voltage clamp control output.

8. 2. The gate driver circuit of claim 1, The first control logic: a one-shot having an input and an output; a delay having an input coupled to the input of the one-shot and an output; a logic gate having a first input coupled to the output of the one-shot, a second input coupled to the output of the delay, and an output coupled to the first current path; a gate driver circuit including:

9. 2. The gate driver circuit of claim 1, a third current path configured to turn on the second transistor; and a fourth current path configured to turn on the second transistor, the fourth current path configured to provide a smaller current than the third current path; Second control logic, turning on both the third and fourth current paths, thereby turning on the second transistor; maintaining the fourth current path in an on state to maintain the second transistor in an on state, while turning off the third current path after the second transistor is turned on; the second control logic configured to a gate driver circuit further comprising:

10. A gate driver circuit, a first transistor having a first control input, a first current terminal coupled to the first voltage terminal, and a second current terminal; a first voltage clamp coupled between the first voltage terminal and the first control input; a second transistor coupled between the first control input and the second voltage terminal; a third transistor coupled between the first control input and the second voltage terminal, the third transistor being smaller than the second transistor; First control logic, turning on both the second and third transistors, thereby turning on the first transistor; maintaining the third transistor in an on state to maintain the first transistor in an on state, while turning off the second transistor after the first transistor is turned on; the first control logic configured to a gate driver circuit including:

11. 11. The gate driver circuit of claim 10, a fourth transistor having a second control input, a third current terminal coupled to the second current terminal and to an output terminal of the gate driver circuit, and a fourth current terminal coupled to a second voltage terminal; a second voltage clamp coupled between the second control input and the second voltage terminal; a fifth transistor configured to turn on the fourth transistor when on; a sixth transistor configured to turn on the fourth transistor when on, the sixth transistor being smaller than the fifth transistor; Second control logic, turning on both the fifth and sixth transistors, thereby turning on the fourth transistor; maintaining the sixth transistor in an on state to maintain the fourth transistor in an on state, while turning off the fifth transistor after turning on the fourth transistor; the second control logic configured to a gate driver circuit further comprising:

12. 11. The gate driver circuit of claim 10, the first voltage clamp has a first voltage clamp control output, the first voltage clamp configured to assert a signal on the first voltage clamp control output in response to a voltage difference between the first voltage terminal and the first control input exceeding a threshold; The gate driver circuit, wherein the first control logic includes a flip-flop having a first input coupled to the first voltage clamp control output, a second input, and an output.

13. 13. The gate driver circuit of claim 12, the first control logic further comprises a logic gate having a first input coupled to the output of the flip-flop, a second input, and a logic gate output coupled to the first current path.

14. 11. The gate driver circuit of claim 10, The gate driver circuit, wherein the first voltage clamp is a dual knee voltage clamp.

15. 11. The gate driver circuit of claim 10, the first voltage clamp: a current source coupled to the third voltage terminal; a first resistor coupled to the third voltage terminal; a fourth transistor having a control input coupled to the third voltage terminal and a pair of current terminals; a fifth transistor having a control input coupled to one of the pair of current terminals; a gate driver circuit including:

16. 16. The gate driver circuit of claim 15, 1. A gate driver circuit comprising: a first voltage clamp having a voltage clamp output control terminal; and a first voltage clamp configured to generate a signal on the voltage clamp output control terminal indicating that a voltage difference between the first voltage terminal and the first control input has reached a clamping voltage threshold.

17. A gate driver circuit, a first transistor having a first control input, a first current terminal coupled to the first voltage terminal, and a second current terminal; a second transistor having a second control input, a third current terminal coupled to the second current terminal and to an output terminal of the gate driver circuit, and a fourth current terminal coupled to a second voltage terminal; a first current path coupled between the first control input and the second voltage terminal, the first current path having a first current value; a second current path coupled between the first control input and the second voltage terminal, the second current path having a second current value greater than the first current value; a first dual knee voltage clamp coupled between the first voltage terminal and the first control input, the first dual knee voltage clamp configured to clamp a voltage difference between the first voltage terminal and the first control input at a first voltage clamping threshold; a second dual knee voltage clamp coupled between the second control input and the second voltage terminal, the second dual knee voltage clamp configured to clamp a voltage difference between the second control input and the second voltage terminal at a second voltage clamping threshold; a gate driver circuit including:

18. 20. The gate driver circuit of claim 17, At least one of the first or second dual knee voltage clamps: a current source coupled to the third voltage terminal; a first resistor coupled to the third voltage terminal; a third transistor having a control input coupled to the third voltage terminal and a pair of current terminals; a fourth transistor having a control input coupled to one of the pair of current terminals; a gate driver circuit including:

19. 20. The gate driver circuit of claim 18, The gate driver circuit, wherein the fourth transistor is larger than the second transistor.

20. 20. The gate driver circuit of claim 17, At least one of the first or second dual knee voltage clamps: a current mirror; a second resistor coupled to the current mirror; Further comprising: A gate driver circuit configured such that a voltage across the second resistor generates the first voltage clamp control output.

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