Joint structure with interconnect assembly

Abstract

A bonding structure comprising a first semiconductor element, a second semiconductor element spaced apart from the first semiconductor element by a gap, and an interconnect assembly including an insulating substrate having conductive traces, the insulating substrate including a first section directly bonded to the first semiconductor element, a second section directly bonded to the second semiconductor element, and a flexible section disposed between the first section and the second section, the flexible section at least partially bridging the gap.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Application No. 63 / 293,299, filed December 23, 2021, entitled “BONDED STRUCTURES WITH INTERCONNECT ASSEMBLY,” the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0002] (Technical field) The present invention relates to joint structures, and more particularly to joint structures with interconnect assemblies. [Background technology]

[0003] Semiconductor elements can be stacked and bonded together to form a bonded structure. In some devices, the semiconductor elements can be directly bonded together without adhesives, for example, using hybrid direct bonding techniques. It can be difficult to integrate semiconductor elements of different types or material sets in a package, for example, due to mismatches in coefficients of thermal expansion (CTE). Additionally, it can be difficult to provide communication between stacks of semiconductor elements and maintain a low profile of the package or device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 9,564,414 [Patent Document 2] U.S. Pat. No. 9,391,143 [Patent Document 3] U.S. Pat. No. 10,434,749 [Patent Document 4] U.S. Pat. No. 9,716,033 [Patent Document 5] U.S. Pat. No. 9,852,988 [Patent Document 6] US Patent Publication No. 2019 / 0096741

[0005] The detailed description will now be described with reference to the accompanying drawings, in which the use of the same numbers in different drawings indicates similar or identical items.

[0006] For purposes of this discussion, the devices and systems illustrated in the figures are shown as having multiple components. Various implementations of the devices and / or systems as described herein may include fewer components and remain within the scope of the present disclosure. Alternatively, other implementations of the devices and / or systems may include additional components or various combinations of the described components and remain within the scope of the present disclosure. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional side view of a conventional package in which a logic die is mounted to a package substrate and a memory die is mounted to the logic die; [Figure 2A-2B] FIG. 1 is a schematic cross-sectional side view of a stacked and bonded structure in which laterally spaced dies are not in direct communication with each other. [Figure 2C] 1 is a schematic cross-sectional side view of a single layer hybrid interconnect assembly according to various embodiments. [Figure 2D] 1 is a schematic cross-sectional side view of a bonding structure further including a single layer hybrid interconnect assembly connecting laterally adjacent dies. [Figure 3A-3B] 1 is a schematic cross-sectional side view of an exemplary interconnect assembly, according to various embodiments. [Figure 4A-4C] 1 is a schematic cross-sectional side view illustrating an exemplary joint structure utilizing an interconnect assembly, according to various embodiments. [Fig. 4D-4E] 1 is a schematic cross-sectional side view illustrating an exemplary joint structure utilizing an interconnect assembly, according to various embodiments. [Fig. 4F-4H]1 is a schematic cross-sectional side view illustrating an exemplary joint structure utilizing an interconnect assembly, according to various embodiments. [Figure 5A-5B] 1 is a schematic diagram of an exemplary application or device incorporating a joining structure or interconnection assembly disclosed herein. [Fig. 5C-5D] 1 is a schematic diagram of an exemplary application or device incorporating a joining structure or interconnection assembly disclosed herein. [Figures 6A-6C] 1A-1D are schematic cross-sectional side views of a method of forming an interconnect assembly. [Fig. 6D-6F] 1A-1D are schematic cross-sectional side views of a method of forming an interconnect assembly. [Figure 6G-6I] 1A-1D are schematic cross-sectional side views of a method of forming an interconnect assembly. [Fig. 6J-6L] 1A-1D are schematic cross-sectional side views of a method of forming an interconnect assembly. [Figures 6M-6O] 1A-1D are schematic cross-sectional side views of a method of forming an interconnect assembly. [Fig. 6P-6R] 1A-1D are schematic cross-sectional side views of a method of forming an interconnect assembly. [Fig. 6S-6U] 1A-1D are schematic cross-sectional side views of a method of forming an interconnect assembly. [Figure 6V] 1A-1D are schematic cross-sectional side views of a method of forming an interconnect assembly. [Figure 7A-7B] 1A-1C are schematic cross-sectional side views illustrating an example of a dual damascene process. [Figure 7C-7E] 1A-1C are schematic cross-sectional side views illustrating an example of a dual damascene process. [Fig. 7F-7I] 1A-1C are schematic cross-sectional side views illustrating an example of a dual damascene process. [Figure 8A-8B] 1 is a schematic cross-sectional side view of an example interconnect assembly for use in a joining structure; [Fig. 8C-8F] 1 is a schematic cross-sectional side view of an example interconnect assembly for use in a joining structure; [Figure 9A-9C] 11 is a schematic cross-sectional side view of an additional embodiment utilizing test pads connectable to test circuitry disposed on an interconnect assembly. [Fig. 9D-9E]11 is a schematic cross-sectional side view of an additional embodiment utilizing test pads connectable to test circuitry disposed on an interconnect assembly. [Figure 10A-10C] 11A-11C are schematic cross-sectional side views illustrating additional examples of direct bond structures with interconnect assemblies. [Fig. 10D-10E] 11A-11C are schematic cross-sectional side views illustrating additional examples of direct bond structures with interconnect assemblies. [Fig. 10F-10H] 11A-11C are schematic cross-sectional side views illustrating additional examples of direct bond structures with interconnect assemblies. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] FIG. 1 illustrates a conventional package 1 in which a logic die 2 is mounted to a package substrate 3 in a flip-chip configuration, where solder bumps 4 connect the logic die 2 to the package substrate 3. The package substrate 3 may be mounted to a system circuit board 5 (such as a printed circuit board or PCB) via solder balls 6. Multiple memory dies 7 may be mounted to the logic die 2 and spaced laterally apart from one another. Solder bumps 4 or copper pillars may connect the memory die 7 to the logic die 2. The use of solder balls 6 and solder bumps 4 in the conventional package 1 illustrated in FIG. 1 may increase the height of the conventional package 1, which may be undesirable for incorporation into a larger electronic device. Furthermore, in a conventional package 1 in which the memory dies 7 are spaced apart from one another, it may be difficult to provide electrical communication between the memory dies 7, especially when the memory dies 7 are stacked on a common support assembly such as the logic die 2 in FIG. 1.

[0009] Heterogeneous integration of different types of devices or devices with different material sets can be challenging due to thermal mismatch (e.g., mismatch in coefficient of thermal expansion (CTE)) between different substrates or devices. In various applications, it can be important to provide fine pitch features in the organic package substrate 3. In some applications, bridges made of semiconductor materials (e.g., silicon) can be used, but the interconnect bridges still utilize solder reflow, which can create reliability issues and increase package height. Flexible package substrates are commonly used for high performance applications (e.g., high frequency, low loss signals), but conventional packages 1 do not utilize direct hybrid bonding to mount devices (e.g., dies) to the flexible package substrate.

[0010] 2A and 2B show a stacking and bonding structure 8 in which laterally spaced apart dies or semiconductor elements 9 do not directly communicate with each other. The semiconductor elements 9 include a bulk portion 58 and a bonding layer 23. The bulk portion 58 can comprise a semiconductor portion patterned with devices such as transistors. For example, in FIGS. 2A-2B, a first semiconductor element 9a and a second semiconductor element 9b (e.g., an integrated device die having active circuitry such as transistors) can be mounted on a carrier 10 and directly bonded to the carrier 10. Within the scope of the prior art, the carrier 10 can function as a support assembly. The carrier 10 can comprise any suitable type of support structure, such as an integrated device die, a wafer, a reconstituted wafer or die, an interposer, etc. A third semiconductor element 9c and a fourth semiconductor element 9d can be mounted on and directly bonded to the first semiconductor element 9a and the second semiconductor element 9b, respectively. Each semiconductor element 9 can include a bonding layer 23 directly bonded to a bonding layer 23 of the other element 9 at a hybrid bonding surface 18 that enables bonding without the use of adhesive along the bonding interface. As shown in FIG. 2B, any suitable number of semiconductor elements 9 can be stacked on top of each other in either a left stack 14 or a right stack 15 on the carrier 10. In FIGS. 2A-2B, the top elements (e.g., the third 9c, fourth 9d, fifth 9e, sixth 9f, seventh 9g, and eighth 9h semiconductor elements) communicate with the carrier 10 through conductive vias 11 (e.g., through-substrate vias, or TSVs (e.g., through-silicon vias)). In some embodiments, the carrier 10 can provide electrical communication between the first semiconductor element 9a and the second semiconductor element 9b by a suitable wiring layer 12, an example of which is depicted in FIG. 2B. The bonding layer 23 of the carrier 10 includes additional carrier conductive pads 13 for connection to circuitry within the carrier 10 in some embodiments. It should be understood that the wiring layer 12 and vias 11 in the carrier 10 may cooperate to provide electrical communication between the third semiconductor element 9c and the fourth semiconductor element 9d, between the third semiconductor element 9c and the second semiconductor element 9b, and / or between the first semiconductor element 9a and the fourth semiconductor element 9d.

[0011] The lack of direct communication between the laterally spaced apart semiconductor elements 9 of FIGS. 2A-2B may degrade the electrical performance of the bonding structure 8. For example, signals transmitted at least between the first and second semiconductor elements 9a and 9b (or between other laterally spaced apart elements) may pass through the intervening carrier 10, resulting in a long signal path. As another example, as shown in FIG. 2B, the electrical routing path between the seventh semiconductor element 9g, which may be configured as a die, on the left stack 14 to the eighth semiconductor element 9h, which may be configured as a die, on the right stack 15 may be relatively long, e.g., the signal traverses (by TSV 11) a routing path through the bonding layer 23 and the fifth semiconductor element 9e, the third semiconductor element 9c, and the first semiconductor element 9a to the carrier 10. From the carrier 10, the signal traverses (by TSV 11) a routing path through the wiring layer 12 to the eighth semiconductor element 9h via the second semiconductor element 9b, the fourth semiconductor element 9d, and the sixth semiconductor element 9f. Due to the long path between the seventh semiconductor element 9g and the eighth semiconductor element 9h, the signal may experience loss and / or signal delay, potentially reducing performance and / or bandwidth.

[0012] Turning now to Figures 2C-2D, accordingly, various embodiments disclosed herein enable direct communication between laterally spaced apart semiconductor elements 9. Figure 2C shows a schematic cross-sectional side view of a hybrid interconnect assembly 16. As described below in connection with Figures 3A-3B, the interconnect assembly 16 can comprise a flexible unit 17, a direct hybrid bonding surface 18, a conductive trace 19, an insulating substrate 20, a non-conductive bonding layer 23, and an insulating base layer 25. Figure 2D shows a schematic cross-sectional side view of a bonding structure 8 further including the hybrid interconnect assembly 16 of Figure 2C. In various embodiments, the interconnect assembly 16 can include a flexible unit 17 and a direct hybrid bonding surface 18 and can be directly bonded to the laterally spaced apart semiconductor elements 9 to provide a direct electrical connection therebetween. This interconnect assembly 16 can be made with a shorter routing path compared to the paths of Figures 2A-2B, and can therefore provide improved electrical performance (Figures 2C and 2D). In some cases, stack routing signals may not pass through electrically intervening semiconductor elements 9 (e.g., semiconductor elements 9a-f, carrier 10). Unlike wiring layer 12 of Figures 2A-2B, in Figures 2C-2D signals are routed from semiconductor element 9a to semiconductor element 9b through flexible unit 17 of interconnect assembly 16.

[0013] 3A-3B illustrate an exemplary interconnect assembly 16 according to various embodiments. The interconnect assembly 16 can include an insulating substrate 20 having conductive traces 19 embedded therein. The insulating substrate 20 can have a first side 21 and a second side 22 opposite the first side 21. The interconnect assembly 16 can include a first inorganic non-conductive bonding layer 23a on a first section 24a of the first side 21 of the insulating substrate 20. The first inorganic non-conductive bonding layer 23a can be prepared for direct bonding (e.g., direct hybrid bonding). The interconnect assembly 16 can include a second inorganic non-conductive bonding layer 23b on a second section 24b of the first side 21 of the insulating substrate 20. The second section 24b can be spaced apart from the first section 24a. The second inorganic non-conductive bonding layer 23b can be prepared for direct bonding (e.g., direct hybrid bonding). The first inorganic non-conductive bonding layer 23a and the second inorganic non-conductive bonding layer 23b can be disposed on the first side 21 of the insulating substrate 20. In some embodiments, the interconnect assembly 16 can also include third 23c and fourth 23d inorganic non-conductive bonding layers disposed on the first section 24a and the second section 24b, respectively, and disposed on the second side 22 of the insulating substrate 20, as shown in Figures 3A-3B. In various embodiments, the inorganic non-conductive bonding layer 23 can include silicon oxide, silicon nitride, silicon oxynitrocarbide, or any other suitable inorganic non-conductive material. The insulating substrate 20 can include a third section 24c including a flexible unit 17 (e.g., a flexible section) disposed between the first section 24a and the second section 24b. The thickness of the interconnect assembly 16 can be in the range of 1 micron to 50 microns, in the range of 1 micron to 20 microns, or in the range of 1 micron to 3 microns. The thickness of the inorganic bonding layer 23 can be, for example, in the range of 300 angstroms to 50,000 angstroms, in the range of 300 angstroms to 10,000 angstroms, in the range of 300 angstroms to 5,000 angstroms, or in the range of 300 angstroms to 1,000 angstroms.

[0014] As shown in FIGS. 3A-3B, the insulating substrate 20 can include an insulating base layer 25, and the conductive traces 19 are at least partially embedded in the insulating base layer 25. As described herein, the insulating base layer 25 can comprise one insulating layer or multiple insulating layers. As shown, an inorganic non-conductive bonding layer 23 can be disposed on the insulating base layer 25. The semiconductor element 9 includes a bonding interface at the bonding surface 18 for bonding without the use of adhesive. The insulating base layer 25 can extend at least partially through the first section 24a, the second section 24b, and the third section 24c including the flexible unit 17. Additionally, as shown, at least one conductive trace 19 can extend at least partially through the first section 24a, the second section 24b, and the third section 24c including the flexible unit 17. In the illustrated embodiment, the insulating base layer 25 includes a flexible thickness of organic material. In various embodiments, the organic material may include at least one of a polymer or a compliant material, such as a liquid crystal polymer (LCP) and / or a polyimide. In some embodiments, the coefficient of thermal expansion (CTE) of the organic layer of the insulating base layer 25 may be less than 15 ppm / °C, such as less than 12 ppm / °C, or less than 10 ppm / °C. The third section 24c including the flexible unit 17 may have a Young's modulus in the range of 2 GPa to 15 GPa, such as in the range of 2 GPa to 12 GPa. In some embodiments, the third section 24c including the flexible unit 17 may include a composite material including an organic material with particles or chopped fibers to create a reinforced material. In the illustrated embodiment, the third section 24c including the flexible unit 17 may be flexible without breaking the insulating base layer 25 and without disrupting the electrical connectivity of the conductive traces 19. As used herein, it should be understood that the third section 24c including the flexible unit 17 may remain flexible within the joining structure 8, such as the joining structure 8 of FIG. 2D, or may be fixed so as to be non-flexible within the joining structure 8 (e.g., when the joining structure 8 is overmolded).Thus, the third section 24c including the flexible unit 17 can be considered a flexible material in the final structure even though it may lose flexibility in the surrounding materials such as molding compound.

[0015] In the illustrated embodiment, the inorganic non-conductive bonding layer 23 can be prepared for direct bonding. For example, the inorganic non-conductive bonding layer 23 can have a planarized bonding surface 18. Also, the inorganic non-conductive bonding layer 23 can have an activated bonding surface 18.

[0016] 4A-4H show an exemplary bonding structure 8 that can utilize the interconnect assembly 16 of FIGS. 3A-3B. For example, the bonding structure 8 can include a first semiconductor element 9a and a second semiconductor element 9b separated from the first semiconductor element 9a by a gap 26 and electrically connected via the interconnect assembly 16a. In some embodiments, the gap 26 comprises a gap 26 filled with a gas (e.g., air). In other embodiments, a molding compound can be disposed in the gap 26. As shown, the first semiconductor element 9a and the second semiconductor element 9b can be mounted (e.g., directly bonded) on the carrier 10. As described above, the bonding structure 8 can include an interconnect assembly 16 including an insulating substrate 20 with conductive traces 19. The insulating substrate 20 may include a first section 24a directly bonded to the first semiconductor element 9a, a second section 24b directly bonded to the second semiconductor element 9b, and a third section 24c including a flexible unit 17 disposed between the first section 24a and the second section 24b, the third section 24c including the flexible unit 17 at least partially bridging the gap 26.

[0017] As explained above, the insulating substrate 20 may comprise an insulating base layer 25 as shown in Figures 3A and 3B, and the conductive traces 19 are at least partially embedded in the insulating base layer 25. The insulating base layer 25 may at least partially extend through the first section 24a, the second section 24b, and the third section 24c that includes the flexible unit 17. The at least one conductive trace 19 may at least partially extend through the first section 24a, the second section 24b, and the third section 24c that includes the flexible unit 17 that includes a gap 60 between the first section 24a and the second section 24c. Furthermore, the at least one conductive trace 19 may provide electrical communication between the first semiconductor element 9a and the second semiconductor element 9b. In the illustrated embodiment, the insulating base layer 25 comprises a flexible thickness of organic material. For example, the organic material may comprise a polymer, such as a liquid crystal polymer (LCP) and / or a polyimide. The coefficient of thermal expansion (CTE) of the organic layers may be less than 10 ppm / ° C. In other embodiments, the insulating base layer 25 may comprise a flexible thickness of inorganic material.

[0018] As explained above, the first section 24a can include a first inorganic non-conductive bonding layer 23a disposed on the insulating base layer 25. The second section 24b can include a second inorganic non-conductive bonding layer 23b disposed on the insulating base layer 25, and the third section 24c includes a flexible unit 17 disposed between the first inorganic non-conductive bonding layer 23a and the second inorganic non-conductive bonding layer 23b. As above, the first non-conductive bonding layer 23a and the second non-conductive bonding layer 23b include planarized and / or activated bonding surfaces. The first surface 21 of the insulating substrate 20 can be directly bonded to the first semiconductor element 9a and the second semiconductor element 9b. The insulating substrate 20 can have a second surface 22 opposite the first surface 21. The first inorganic non-conductive bonding layer 23a and the second inorganic non-conductive bonding layer 23b can be disposed on the first surface 21 of the insulating substrate 20. The first section 24a can include a third inorganic non-conductive bonding layer 23c disposed on the insulating base layer 25 at the second side 22 of the insulating substrate 20. The second section 24b can include a fourth inorganic non-conductive bonding layer 23d disposed on the insulating base layer 25 at the second side 22 of the insulating substrate 20. As shown, the insulating substrate 20 can include a plurality of conductive contact features 27 of FIGS. 3A and 3B at least partially embedded in the first inorganic non-conductive bonding layer 23a. The first inorganic non-conductive bonding layer 23a can be directly bonded to the non-conductive regions of the first semiconductor element 9a without an intervening adhesive. The plurality of conductive contact features 27 can be directly bonded to the plurality of conductive contact features 27 of the first semiconductor element 9a without an intervening adhesive.

[0019] As shown in FIGS. 4D-4F, multiple semiconductor elements 9 can be stacked on top of each other. Thus, in some embodiments, the second surface 22a of the insulating substrate 20a can be directly bonded to the first semiconductor element 9a and the second semiconductor element 9b. The first insulating substrate 20a of the first interconnect assembly 16a can include a first surface 21a opposite the second surface 22a. The bonding structure 8 can include a third semiconductor element 9c directly bonded to the first surface 21a of the insulating substrate 20a and a fourth semiconductor element 9d directly bonded to the first surface 21a of the insulating substrate 20a. The second interconnect assembly 16b can include a second insulating substrate 20b having conductive traces 19. The second insulating substrate 20b may include a second section 24b directly bonded to the third semiconductor element 9c, a first section 24a directly bonded to the fourth semiconductor element 9d, and a third section 24c including a flexible unit 17 disposed between the first section 24a and the second section 24b.

[0020] As shown in Figure 4G, in some embodiments, the interconnect assembly 16 can advantageously connect laterally spaced semiconductor elements 9 of different heights. For example, in Figure 4G, the first section 24a can be directly bonded to the first semiconductor element 9a at a first vertical position relative to the upper surface of the support solid 10, and the second section 24b can be directly bonded to the second semiconductor element 9b at a second vertical position relative to the upper surface of the support solid 10. The second vertical position can differ by a vertical offset 53 between the bonding surfaces. In Figure 4G, the upper surface of the support assembly includes the upper surface of the first semiconductor element 9a.

[0021] In Fig. 4H, the interconnect assembly 16 may include a test circuit 28 connected to at least one of the first semiconductor element 9a and the second semiconductor element 9b. The test circuit 28 may be configured to test the functionality of the circuitry in at least one of the first semiconductor element 9a and the second semiconductor element 9b. The test circuit 28 may be connected to an external device in any suitable manner. For example, the test circuit 28 may be wire-bonded to the carrier 10 on which at least one of the first 9a and the second 9b semiconductor elements is mounted, as shown, for example, in Figs. 9D-9E.

[0022] 5A-5D show exemplary applications or devices that may incorporate the bonding structure 8 or interconnection assembly 16 disclosed herein. For example, as shown in FIG. 5A, the bonding structure 8 may be incorporated in a wearable consumer device in some embodiments. The interconnection assembly 16 connects two semiconductor devices 9. The semiconductor devices 9 and the interconnection assembly 16 are mounted (e.g., directly hybrid bonded) on a substrate 54. The bonding structure 8 allows for a connection between a first semiconductor element 9a and a second semiconductor element 9b while the interconnection assembly is bent or molded into a new shape, such as a round shape of a bracelet wristband, necklace, or headband. The semiconductor device 9 may include a processor, memory, or a sensor that interacts with the wearer. In FIGS. 5B-5C, the bonding structure 8 may include a semiconductor element 9 attached to the interconnection assembly 16 mounted (e.g., directly bonded) on a substrate 54, and may be used in combination with an optical element 29 (such as a light emitting diode, or LED) that may be connected to a thermoelectric cooler 55 (TEC) in some applications. FIG. 5B shows an optical element 29 connected to a TEC 55. Such connected optical element 29 can be configured as a light-up jewelry such as a light-up necklace or bracelet. In FIG. 5D, multiple bonding structures 8 can be laterally connected to each other to form a flexible band structure 30. Thus, in FIG. 5D, the insulating substrate 20 depicted in, for example, FIGS. 3A-3B can include a third section bonded directly to a third semiconductor element and a second flexible section disposed between the second and third sections. Additional semiconductor elements and flexible sections can be daisy-chained together to form a band structure of any suitable length. Such a daisy-chain bonding structure 8 can be a sensor on a wristband configured for heart rate monitoring or other health-related monitoring. The daisy-chain bonding structure 8 can be configured as a ring-shaped sensor for heart rate monitoring or other health-related monitoring.Similarly, the daisy chain bonding structure 8 can be a signal emitter located on the wearable structure to send out a signal position to track the wearer's movements. Direct bonding, such as the example of Figures 5A-D, can have higher tolerance of non-planarized die and / or height variations in single and multiple die stacks. Further advantages include the ability to add local redistribution layers to all or part of the chip or flex, ease of integrating substrates with different CTEs, enhanced direct testing between dies, reduced signal loss, and shorter paths and lower impedance to connections. In some embodiments, the substrate 54 can act as a support assembly.

[0023] 6A-6V illustrate a method of forming an interconnect assembly 16 according to various embodiments. In FIG. 6A, a backside inorganic insulating bonding layer 23c can be provided (e.g., deposited) on a temporary support structure 37a (also referred to herein as a carrier, handle, or sacrificial substrate). The temporary support structure 37a can comprise any suitable type of substrate, such as a semiconductor substrate (e.g., a silicon substrate), a glass substrate, a panel, a substrate that is permanent or temporary, or generally speaking, a carrier. The backside inorganic insulating bonding layer 23c can comprise any suitable type of inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, and the like. The backside inorganic insulating bonding layer 23c can include a hybrid bonding surface 18 having an embedded conductive layer or pad for subsequent use (not shown in FIG. 6A). A first insulating base layer 25a can be provided (e.g., deposited on the backside inorganic insulating bonding layer 23c). The first insulating base layer 25a can comprise a sub-layer of the insulating base layer 25 described herein. As explained above, in various embodiments, the first insulating layer 25a can include an organic material such as a polymer. For example, the first insulating layer 25a can comprise a polyimide, a liquid crystal polymer (LCP), or any other suitable polymer with a low CTE. This step can include coating a low CTE polymethyl layer of less than 10 ppm / C on the substrate. In FIG. 6B, the temporary support structure 37a, the bonding layer 23c, and the first insulating layer 25a can be cured, for example, using a microwave oven and / or a vacuum cure, or a conventional oven. Curing can extract solvents, reduce the thermal budget, and lower stress in the fabricated structure.

[0024] Turning to FIG. 6C, a first interlevel dielectric layer 31a (ILD) can be provided (e.g., deposited) on the first insulating layer 25a. The first ILD 31a can comprise a thin dielectric layer, such as a thin layer of silicon nitride or silicon oxide. In various embodiments, the first ILD 31a can comprise one or more layers. In various embodiments, the first ILD 31a can function as an etch stop. In some embodiments, the first ILD 31a can serve to improve adhesion between the first insulating layer 25a and the second insulating layer 25b (see FIG. 6I). In FIG. 6D, a photoresist layer 32 can be applied over the first ILD 31a and patterned using lithographic patterning. In FIG. 6E, the first ILD 31a and the first insulating layer 25a can be etched with one or more etching processes, such as a reactive ion etching (RIE) process, to form a single or dual damascene cavity 36. The surface of the first insulating layer 25a, including the cavity 36, may be cleaned to remove residual organic material. In FIG. 6F, a barrier layer 33a may be provided in the cavity 36, and a seed layer (not shown) may be provided on the barrier layer 33a. The barrier layer 33a may comprise any suitable type of barrier that prevents migration of the conductive material 34 (such as copper) into the insulating layer 25. For example, the barrier layer 33a may include a conductive barrier material, such as tantalum nitride, titanium nitride, nickel vanadium, or the like.

[0025] Turning to Figure 6G, a conductive material 34a (such as copper) can be provided (e.g., electroplated) in the cavity 36 over the barrier layer 33a. In Figure 6H, a polishing process (e.g., a chemical mechanical polishing, or CMP process) can be performed to planarize the conductive material 34 and remove the portion of the barrier layer 33a covering the insulating layer 25 leaving a planarized surface 35 of the conductive material 34a.

[0026] In some embodiments, a photodefinable polymer (such as polyimide) can be provided to create a metal cavity 36 (e.g., a cavity for a metal pad) or conductive pad 42. For cavities 36 having lateral dimensions greater than, for example, 2-3 microns, the first ILD layer 31a can be omitted and the coated and soft-baked first insulating layer 25a can be patterned via lithographic exposure and the unwanted areas dissolved with a suitable developer. The patterned first insulating layer 25a can be heat treated at higher temperatures, for example, in a vacuum oven or microwave oven, to improve the thermal, mechanical and / or electrical properties of the patterned first insulating layer 25a. A barrier layer 33a can be provided in the cavity 36 and a seed layer can be provided on the barrier layer 33a. A conductive material layer 34a (such as copper) can be provided (e.g., electroplated) in the cavity 36 on the barrier layer 33a. 6H, a polishing process (e.g., a chemical mechanical polishing, or CMP process) can be performed to planarize the conductive material 34a and remove the portion of the barrier layer 33a that covers the insulating layer 25a. The remaining portions of the barrier layer 33a can be selectively removed by a wet etching process or a reactive ion etching (RIE) method.

[0027] In FIG. 6I, a second insulating layer 25b can be provided on the exposed upper surface of the first ILD 31a and the first conductive material 34a. The second insulating layer 25b can include the same material as the first insulating layer 25a or a different material. A second ILD 31b (which can be the same material as the first ILD 31a or a different material) can be provided on the second insulating layer 25b. In FIG. 6J, a cavity 36 can be formed (e.g., etched) in the second ILD 31b and the second insulating layer 25b. In FIG. 6K, a second conductive material 34b (e.g., copper) can be provided (e.g., electroplated) in the cavity 36 on the second barrier layer 33b. In FIG. 6L, the second conductive material 34b can be polished. Also, as described above, in some embodiments, the multiple interconnects can be formed of a photocurable polymeric material.

[0028] Turning to FIG. 6M, a third insulating layer 25c (which may be the same or different from the first insulating layer 25a and the second insulating layer 25b) can be provided on the second ILD 31b, and a third ILD 31c can be provided on the third insulating layer 25c. A front inorganic insulating bonding layer 23a can be provided on the third ILD 31c. The front inorganic insulating bonding layer 23a can include the same material as the back bonding layer 23c, or can include a different material. In FIG. 6N, a third conductive material 34c can be provided in the cavity 36 of the third insulating layer 25c and the front bonding layer 23a. The third conductive material 34c can function as a conductive contact 27 on the front side of the interconnect assembly 16. In FIG. 6O, a portion of the front bonding layer 23a can be selectively removed to expose the third ILD 31c. In FIG. 6P, the interconnect assembly 16 can be inverted and mounted to a temporary support structure 37. The temporary support 37b structure can function as a carrier, but is removed during this process. In some embodiments, the interconnect assembly 16 can be attached to the temporary support structure 37 with an adhesive. In other embodiments, the interconnect assembly 16 can be directly bonded to the temporary support structure 37b without an adhesive. Also, in FIG. 6P, the temporary support structure 37b can be removed (e.g., by polishing or grinding) to expose the backside bonding layer 23c. In FIG. 6Q, portions of the backside bonding layer 23c can be selectively removed to expose the first insulating layer 25a. In FIG. 6R, the temporary support structure 37b can be removed and the interconnect assembly 16 can be attached to a dicing sheet 38 (e.g., a dicing tape in some arrangements). In some embodiments, the interconnect assembly 16 can be adhesively attached to a processing sheet, and the temporary support structure 37b can be removed. In some applications, the processing sheet can comprise a dicing sheet 38, and in other applications, the interconnect assembly 16 can be transferred to a framed dicing sheet 38.

[0029] In FIG. 6S, a protective layer 39 (such as an organic protective layer) may be provided on the back bonding layer 23c. The protective layer 39 may serve to protect the bonding surface 18 of the bonding layer 25a during singulation. In some embodiments, the protective layer 39 may comprise a photoresist layer. The singulation process may include, for example, wet etching, reactive ion etching (RIE), saw dicing, laser dicing, and any combination thereof. In FIG. 6T, the interconnection assembly 16 may be singulated along a source street 40 to form a plurality of singulated interconnection assemblies 16, as shown in FIG. 6U. In FIG. 6U, the protective layer 39 may be removed by a suitable cleaning solution, such as a resist developer, to prepare the bonding layer 23 for direct bonding. The preparation process may include stripping the residue of the protective layer 39, cleaning unwanted particulates, ashing and activating the cleaned bonding surface 41, rinsing the bonding surface 41 with deionized water or other suitable solvent, and drying the cleaned bonding surface 41. Drying the cleaned bonding surface 41 may include spin drying the rinsed interconnect assembly 16, for example, spin drying the rinsed interconnect assembly 16 at a speed between 500-3000 rpm for a time between 15 seconds-240 seconds. The higher the rotation speed, the shorter the drying time. After the drying step, in some embodiments, the backside of the dicing frame (not shown) may be exposed to UV radiation to reduce adhesion between the interconnect assembly 16 and the dicing sheet 38 for the pick-and-place bonding operation. FIG. 6V shows a singulation interconnect assembly 16 having conductive contact features 27 at least partially embedded in the front and backside dielectric bonding layers 23.

[0030] 7A-7I show an example of a dual damascene process. FIGS. 7A-7C can be the same or generally similar to the steps shown in FIGS. 6G-6I. The backside bonding dielectric layer 23c can include conductive pads embedded in the backside bonding surface (not shown) for direct hybrid bonding. However, in FIG. 7D, a dual damascene cavity 43 can be formed in the second insulating layer 25b, and the dual damascene cavity 43 can be provided with a barrier layer 33b. In FIG. 7E, a second conductive material 34b can be provided in the dual damascene cavity 43, and in FIG. 7F, the second conductive material 34b can be planarized, and the portion of the second barrier layer 33b covering the second ILD 31b is removed. The planarization process of FIG. 7F can also planarize the second ILD 31b, which can function as the bonding surface 18 in the illustrated embodiment. Thus, in FIG. 7F, the second ILD 31b can include an inorganic insulating bonding layer 23, such as silicon oxide, silicon nitride, etc. In FIG. 7G, the temporary substrate 59 can be thinned on the back side (if appropriate for a particular process or structure). In FIG. 7H, the temporary substrate 59 (e.g., temporary substrate) can be removed to expose the back side inorganic bonding layer 23c. In FIG. 7I, a cavity 36 formed in the back side bonding layer 23c can be provided with a conductive contact feature 27 and prepared for direct bonding of the back side bonding layer 23c and the contact feature 27. In some embodiments, an aluminum (Al) metal layer can be used in the back side dielectric layer to compensate for stress from the front side metallization (Cu) as well as overall bowing in the resulting structure. Al is more tensile than Cu and can be used to balance the compressive stress of the dielectric. The aluminum can be added in a build-up layer and / or CMP aluminum process. In a build-up aluminum process, the aluminum is patterned, a dielectric layer is deposited on the build-up aluminum layer, and the aluminum is allowed to shrink to compensate for the dielectric stress. The aluminum can be exposed by etching or a dielectric CMP polishing process. A Cu bonding layer can be formed on the aluminum interconnects.

[0031] 8A-8F show additional examples of interconnect assemblies 16 for use in bonded structures 8. FIG. 8A shows multiple semiconductor elements 9a and 9c (e.g., device dies) mounted on a first surface 21 of an insulating substrate 20 and multiple semiconductor elements 9b and 9d mounted on a second surface 22, the second surface 22 being opposite the first surface 21 of the insulating substrate 20. One or more semiconductor elements 9a may be mounted on the first surface 21 of the first section 24a, and one or more semiconductor elements 9b may be mounted on the second surface 22 of the first section 24a. One or more semiconductor elements 9c may be mounted on the first surface 21 of the second section 24b. One or more semiconductor elements 9d may be mounted on the second surface 22 of the second section 24b.

[0032] 8B, in some embodiments, the conductive traces 19 may be encapsulated with a barrier layer 33. The barrier layer 33 may prevent moisture from contacting the conductive traces 27. The barrier layer 33 may include any suitable type of barrier material, such as CoP, NiP, CoP / NiP, nickel vanadium, tantalum nitride, tantalum, and combinations thereof.

[0033] 8C, the interconnect assembly 16 can be mounted to a support structure 44 that includes a carrier 10 with a recess 45. A third section 24c that includes a flexible unit 17 can at least partially bridge the recess 45. As shown, a semiconductor device 9 can be mounted (e.g., directly bonded) to the opposite side of the interconnect assembly 16, as described above.

[0034] FIG. 8D shows an insulating substrate 20 with a semiconductor device 9 bonded thereto and attached to a dicing sheet 38. FIG. 8E shows a single crystal interconnect assembly 16 with a semiconductor device 9 bonded thereto. FIG. 8F shows a top view of the interconnect assembly 16. As shown in the top view of the interconnect assembly 16 in FIG. 8F, at least one conductive trace 19 can be curved or zigzag. The curves or zigzags can be used to relieve stress in the metal layer of the substrate 20. In some embodiments, the semiconductor device 9 can function as a support assembly.

[0035] 9A-9E illustrate additional embodiments utilizing test pads 46 that can be connected to test circuitry 28 disposed on the interconnect assembly 16. Unless otherwise noted, components in FIGS. 9A-9E may be the same as or generally similar to like-numbered components in FIGS. 2C-8F. As explained above, the test circuitry 28 can be configured to test the functionality of the circuitry in at least one of the first semiconductor element 9a and the second semiconductor element 9b. FIG. 9A illustrates test pads 46 disposed on the interconnect assembly 16. In FIG. 9B, semiconductor elements 9c and 9d are mounted on the interconnect assembly 16 and can be connected to the test circuitry 28 within the interconnect assembly 16. Suitably configured test pads 46 can test the connectivity and functionality of the various semiconductor elements 9 of FIG. 9B, such as the semiconductor elements 9 below and above the interconnect assembly 16. FIG. 9C illustrates a test fixture 47 or socket for testing one or more semiconductor elements 9 bonded to the interconnect assembly 16. For functionality testing, multiple semiconductor devices 9 can be bonded to the interconnect assembly 16. At a later point in time, if the tested devices function correctly, a known good assembled semiconductor device 9 can be bonded to another substrate via the back bonding surface 23c of the interconnect assembly 16 to complete a module or assembly.

[0036] 9D shows test pads 46 bonded to carrier 10 by bond wires 48. In some embodiments, bond wires 48 can serve as power and ground conduits to carrier 10 to provide power and ground to semiconductor device 9 via pads 46. In FIG. 9E, a chiplet 49 (e.g., another integrated device die) can be provided in gap 26 below third section 24c including flexible unit 17 of interconnect assembly 16 (e.g., bonded directly to the carrier). In some embodiments, one or more chiplets 49 can be bonded to interconnect assembly 16 (not shown).

[0037] 10A-10H show additional examples of direct bond structures 8 with interconnect assemblies 16. The features of FIGS. 10A-10E may be formed using methods described above and may include components that are the same or generally similar to those of FIGS. 3A-9E unless otherwise noted. In the embodiments of FIGS. 3A-9E, the insulating base layer 25 (which may include one or more layers) of the interconnect assembly 16 includes an organic material as described above. However, in the embodiments of FIGS. 10A-10E, the insulating base layer 25 may comprise an inorganic base layer. In various embodiments, the inorganic insulating base layer 25 may include a suitable carbide, nitride, and / or oxide material, such as glass, silicon carbide, sapphire, aluminosilicate glass, glass ceramic, Gorilla Glass, Lotus Glass, Diamond-Like Carbon (DLC), or any other suitable inorganic material. The thickness of the inorganic insulating base layer may be at least 1 micron, for example, in the range of 3 microns to 50 microns, or in the range of 5 microns to 20 microns. The carrier 10 can be connected to the semiconductor device 9 by a semiconductor device 57 mounted (e.g., directly bonded) to the carrier 10. In various embodiments, as shown in FIGS. 10B-10C, a molding compound 50 can be overmolded onto the semiconductor device 9, the carrier 10, and within the gap 26. In FIG. 10B, the upper surface of the interconnect assembly 16 can be exposed through the molding compound 50. In FIG. 10C, the molding compound 50 can be provided on top of the interconnect assembly 16. In FIG. 10D, a different configuration of the bonded structure 8 of FIG. 10A is shown, in which the interconnect assembly 16 is bonded with four semiconductor devices 9. FIG. 10E includes a flexible unit 17 directly bonded to semiconductor devices 9 having different heights.

[0038] 10F-10H show inorganic insulating base layers 25 with polymer stress buffer layers 51 (e.g., polyimide layers) disposed between vertically adjacent inorganic insulating base layers 25. The buffer layers 51 can include pass-through conductive vias 52 and conductive traces 19 for bridging the interconnect layers 25 above and below the buffer layers 51. The polymer buffer layers 51 can beneficially function as stress buffers against stresses induced due to CTE mismatch of materials on either side of the layers, particularly when the CTE of the matrix of the dielectric layer above the polymer is different from that below the polymer layer. In some embodiments, the polymer buffer 51 can include particulates of fiber-reinforced polymer. In FIG. 10G, the underside of the interconnect assembly 16 can be formed on a suitable substrate 54. The polymer layer 51 can include traces 19, pass-through vias 52, and an inorganic bonding surface formed on the underside. The top of the interconnect assembly 16 can be formed separately in some embodiments. The lower bonding surface of the top surface portion of the interconnect assembly 16 can be directly bonded to a bonding surface disposed on the polymer layer 51. The temporary substrate 54 can be removed prior to further processing. Figure 10G shows an interconnect assembly similar to Figure 10F with a semiconductor device 9 bonded to the interconnect assembly 16. Figure 10H shows test pads 46 bonded to the carrier 20 by bond wires 48.

[0039] Examples of direct bonding method and direct bonded structure Various embodiments disclosed herein relate to direct bond structures that allow two elements to be directly bonded together without an intervening adhesive. Two or more electronic elements, which may be semiconductor elements (integrated device dies, wafers, etc.) or non-semiconductor elements such as package substrates (including flexible substrates) with inorganic insulating bonding layers as described herein, may be stacked or bonded together to form a bond structure. In embodiments disclosed herein, the electronic component (e.g., wiring layer) may comprise a first element and the package carrier may comprise a second element. The semiconductor device may comprise a third element. The conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements may be stacked on the bond structure. The contact pads may comprise metal pads formed on non-conductive bonding areas and may be connected to an underlying metallization such as a redistribution layer (RDL).

[0040] In some embodiments, the elements are directly bonded to each other without adhesive. In various embodiments, the non-conductive or dielectric material of the first element can be directly bonded to the corresponding non-conductive or dielectric field area of ​​the second element without adhesive. The non-conductive material can be referred to as the non-conductive bonding area or bonding layer of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-to-dielectric bonding techniques. For example, the dielectric-dielectric bond can be formed without adhesive using direct bonding techniques disclosed in at least U.S. Pat. No. 9,564,414, U.S. Pat. No. 9,391,143, and U.S. Pat. No. 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes. Suitable dielectric materials for the direct bonding layer described herein include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon such as silicon carbide, silicon oxynitride, silicon carbonitride, or diamond-like carbon. In some embodiments, the dielectric material of the bonding layer does not comprise a polymeric material such as an epoxy, resin, or molding compound, but the underlying layer may include an organic material, such as the organic insulating layers described herein.

[0041] In various embodiments, the hybrid direct bond can be formed without an intervening adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or an etchant to activate the surfaces. In some embodiments, the surfaces can be terminated with chemical species after activation or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, the activation process can be activated to break chemical bonds at the bonding surfaces, and the termination process can provide additional chemical species to the bonding surfaces that improve the bonding energy during direct bonding. In some embodiments, activation and termination are provided in the same step, e.g., plasma or wet etchant, to activate and terminate the surfaces. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination species can include nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there can be one or more fluorine peaks near the layers and / or bonding interface. Thus, in a direct bond structure, the bond interface between the two dielectric materials can have a very smooth interface with a higher nitrogen content and / or fluorine peak at the bond interface. Additional examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes.

[0042] In various embodiments, the conductive contact pads of the first element can also be directly bonded to the corresponding conductive contact pads of the second element. For example, hybrid direct bonding techniques can be used to provide conductor-to-conductor direct bonding along a bonding interface that includes the covalently directly bonded dielectric-to-dielectric surfaces prepared as described above. In various embodiments, conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds can be formed using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0043] For example, the dielectric bonding surfaces of the bonding layers described herein can be prepared and bonded directly to one another without an intervening adhesive, as described above. The conductive contact pads (which may be surrounded by non-conductive dielectric field regions) can also be bonded directly to one another without an intervening adhesive. In some embodiments, each contact pad can be recessed, e.g., less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm, below the outer (e.g., upper) surface of the dielectric field region or non-conductive bonding region. The non-conductive bonding regions can be directly bonded to one another without adhesive bonding at room temperature in a bonding tool described herein, in some embodiments, and the bonded structure can then be annealed. The annealing can be performed in a separate apparatus. Upon annealing, the contact pads can expand and contact one another, resulting in a direct metal-to-metal bond. Advantageously, the use of hybrid bonding technologies such as DBI® (Direct Bond Interconnect) commercially available from Adeia, Inc., San Jose, Calif., allows for a high density of connected pads across the direct bond interface (e.g., small or fine pitch for regular arrays). In some embodiments, the pitch of the bond pads, or the conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 microns, or less than 10 microns, or less than 2 microns. In some applications, the ratio of the bond pad pitch to the bond pad dimension is less than 5, or less than 3, and in some cases desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range from 0.3 microns to 5 microns. In various embodiments, the contact pads and / or traces may include copper, although other metals may be suitable.

[0044] As described herein, the first and second elements (e.g., electronic components and packaging carriers exemplified herein as wiring layers) can be directly bonded to each other without adhesive, which is different from a deposition process. Accordingly, the first and second elements can include non-deposited elements. Furthermore, the direct bond structure, unlike a deposition layer, can include defect areas along the bond interface where nanovoids exist. The nanovoids can be formed by activation (e.g., exposure to plasma) of the bond surfaces. As described above, the bond interface can include concentrations of materials from the activation and / or last chemical treatment process. For example, in an embodiment utilizing nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface. In an embodiment utilizing oxygen plasma for activation, an oxygen peak can be formed at the bond interface. In some embodiments, the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond can comprise covalent bonds that are stronger than van der Waals bonds. The bond layer can also comprise a polished surface that is planarized to a high degree of smoothness. For example, the bonding layer may have a surface roughness of less than 2 nm root mean square (RMS) per micron, or less than 1 nm RMS per micron.

[0045] In various embodiments, the metal-to-metal bond between conductive features (e.g., contact pads) in a direct hybrid bond structure can be bonded such that the grains of the conductive features, e.g., copper grains on the conductive features, grow together across the bond interface. In some embodiments, the copper can have grains oriented along 111 crystal planes to improve diffusion of copper across the bond interface. The bond interface can extend substantially completely to at least a portion of the bonded contact pad, such that there is substantially no gap between the non-conductive bond regions at or near the bonded contact pad. In some embodiments, a barrier layer can be provided (e.g., can include copper) under the contact pad. However, in other embodiments, there may be no barrier layer under the contact pad, as described, for example, in U.S. Patent Publication No. 2019 / 0096741, which is incorporated herein by reference in its entirety and for all purposes.

[0046] In one embodiment, the bonding structure comprises: a first semiconductor element; a second semiconductor element spaced apart from the first semiconductor element by a gap; and an interconnect assembly including an insulating substrate with conductive traces, wherein the insulating substrate may include a first section directly bonded to the first semiconductor element, a second section directly bonded to the second semiconductor element, and a flexible section disposed between the first and second sections, wherein the flexible section at least partially bridges the gap.

[0047] In some embodiments, the insulating substrate comprises an insulating base layer, and the conductive traces are at least partially embedded in the insulating base layer. In some embodiments, the insulating base layer extends at least partially through the first section, the second section, and the flexible section. In some embodiments, the insulating base layer comprises a plurality of insulating layers. In some embodiments, the bonding structure can include an interlayer dielectric (ILD) layer disposed between the first insulating layer and the second insulating layer. In some embodiments, the ILD layer comprises at least one of silicon nitride and silicon oxide. In some embodiments, at least one conductive trace extends at least partially through the first section, the second section, and the flexible section. In some embodiments, the at least one conductive trace provides electrical communication between the first semiconductor device and the second semiconductor device. In some embodiments, the insulating base layer comprises a flexible thickness of an organic material. In some embodiments, the organic material comprises a polymer. In some embodiments, the organic material comprises at least one of a liquid crystal polymer (LCP) and a polyimide. In some embodiments, the organic layer has a coefficient of thermal expansion (CTE) of less than 12 ppm / °C. In some embodiments, the insulating base layer comprises a flexible thickness of inorganic material. In some embodiments, the first section comprises a first inorganic non-conductive bonding layer disposed on the insulating base layer. In some embodiments, the second section comprises a second inorganic non-conductive bonding layer disposed on the insulating base layer, the flexible section being disposed between the first inorganic non-conductive bonding layer and the second inorganic non-conductive bonding layer. In some embodiments, the first inorganic non-conductive bonding layer and the second inorganic non-conductive bonding layer comprise planarized bonding surfaces. In some embodiments, the first side of the insulating substrate is directly bonded to the first and second semiconductor devices, the insulating substrate comprises a second side opposite the first side, and the first and second inorganic non-conductive bonding layers are disposed on the first side of the insulating substrate. In some embodiments, the first section comprises a third inorganic non-conductive bonding layer disposed on the insulating base layer at the second side of the insulating substrate.In some embodiments, the second section comprises a fourth inorganic non-conductive bonding layer disposed on the insulating base layer at the second side of the insulating substrate. In some embodiments, the insulating substrate comprises a plurality of conductive contact features at least partially embedded in the first inorganic non-conductive bonding layer. In some embodiments, the first inorganic non-conductive bonding layer is bonded directly to the non-conductive regions of the first semiconductor element without an intervening adhesive, and the plurality of conductive contact features are bonded directly to the plurality of conductive contact features of the first semiconductor element without an intervening adhesive. In some embodiments, the first side of the insulating substrate is bonded directly to the first and second semiconductor elements, the insulating substrate includes a second side opposite the first side, and the bonding structure comprises a third semiconductor element bonded directly to the second side of the insulating substrate and a fourth semiconductor element bonded directly to the second side of the insulating substrate. In some embodiments, the bonding structure may include a second interconnect assembly comprising a second insulating substrate having conductive traces, the second insulating substrate comprising a first section bonded directly to a third semiconductor device, a second section bonded directly to a fourth semiconductor device, and a flexible section disposed between the first and second sections. In some embodiments, the first and second semiconductor devices are mounted on a support assembly. In some embodiments, the support assembly comprises a carrier, and the first and second semiconductor devices are mounted to the carrier. In some embodiments, the first and second semiconductor devices are bonded directly to the carrier without an adhesive. In some embodiments, the first section is bonded directly to the first semiconductor device at a first vertical position relative to an upper surface of the support assembly, and the second section is bonded directly to the second semiconductor device at a second vertical position relative to an upper surface of the support assembly, the second vertical position being different from the first vertical position. In some embodiments, a first side of the insulating substrate is directly bonded to the first and second semiconductor devices, the insulating substrate includes a second side opposite the first side, the second side being mounted to the third and fourth devices in spaced apart relation to one another, and the support assembly includes the third and fourth devices. In some embodiments, the insulating substrate includes a third section directly bonded to the third semiconductor device and a second flexible section disposed between the second section and the third section.In some embodiments, the interconnect assembly includes a test circuit connected to at least one of the first and second semiconductor devices, the test circuit configured to test functionality of the circuit in at least one of the first and second semiconductor devices. In some embodiments, the test circuit is wire bonded to a carrier on which at least one of the first and second semiconductor devices is mounted. In some embodiments, the at least one conductive trace is curved or zigzag when viewed from a top view of the interconnect assembly. In some embodiments, the gap includes a gas. In some embodiments, the first and second semiconductor devices are at least partially embedded in a molding compound. In some embodiments, the molding compound is disposed within the gap. In some embodiments, the flexible section has a Young's modulus in the range of 2 GPa to 15 GPa. In some embodiments, the flexible section is bendable without breaking the insulating base layer and without breaking the electrical connections of the conductive traces.

[0048] In another embodiment, the bonding structure can include an interconnect assembly including a carrier and an insulating substrate having conductive traces, the insulating substrate including a first section and a flexible section extending from the first section, the first section including a first inorganic non-conductive bonding layer, the first inorganic non-conductive bonding layer bonded directly to the carrier without an adhesive.

[0049] In some embodiments, the carrier comprises a first semiconductor device. In some embodiments, the bonding structure can include a second semiconductor device, and the insulating substrate comprises a second section comprising a second inorganic non-conductive bonding layer, and the second inorganic non-conductive bonding layer is directly bonded to the second semiconductor device without an adhesive. In some embodiments, the carrier comprises a recess, and the insulating substrate comprises a second section comprising a second inorganic non-conductive bonding layer bonded directly to the carrier, and the flexible section at least partially bridges the recess in the carrier.

[0050] In another embodiment, a bonding structure includes a support assembly having a first bonding surface and a second bonding surface; and an interconnect assembly on the support assembly, the interconnect assembly including an insulating substrate having conductive traces, the insulating substrate including a first section bonded directly to the first bonding surface without an adhesive, a second section bonded directly to the second bonding surface without an adhesive, and a third section extending between the first and second sections, the third section bridging a gap between the first and second bonding surfaces, the gap being filled with a gas.

[0051] In some embodiments, the third section of the insulating substrate is flexible. In some embodiments, the support assembly comprises a first semiconductor device and a second semiconductor device spaced apart from the first semiconductor device by a gap, the first semiconductor device comprising a first bonding surface and the second semiconductor device comprising a second bonding surface. In some embodiments, the first and second semiconductor devices are mounted to a carrier. In some embodiments, the support assembly comprises a carrier having a recess, and the third section at least partially bridges the recess of the carrier. In some embodiments, the insulating substrate comprises an insulating base layer, the first section comprises a first inorganic non-conductive bonding layer disposed on the insulating base layer, and the second section comprises a second inorganic non-conductive bonding layer disposed on the insulating base layer. In some embodiments, the first bonding surface is at a first vertical position relative to the upper surface of the support assembly, and the second bonding surface is at a second vertical position relative to the upper surface of the support assembly, the second vertical position being different from the first vertical position.

[0052] In another embodiment, the joining structure can include a support assembly having a first joining surface at a first vertical position relative to an upper surface of the support assembly and a second joining surface disposed at a second vertical position relative to the upper surface of the support assembly, the second vertical position being different from the first vertical position; and an interconnect assembly including an insulating substrate having a conductive trace, the insulating substrate having a first section bonded directly to the first joining surface without an adhesive, a second section bonded directly to the second joining surface without an adhesive, and a third section extending between the first and second sections.

[0053] In some embodiments, the third section of the insulating substrate is flexible. In some embodiments, the support assembly comprises a first semiconductor element and a second semiconductor element spaced apart from the first semiconductor element by a gap, the first semiconductor element comprising a first bonding surface, the second semiconductor element comprising a second bonding surface, and the upper surface of the support assembly comprises a top surface of the first semiconductor element. In some embodiments, the first and second semiconductor elements are mounted on a carrier. In some embodiments, the support assembly comprises a carrier having a recess, and the third section at least partially bridges the recess of the carrier. In some embodiments, the insulating substrate comprises an insulating base layer, the first section comprises a first inorganic non-conductive bonding layer disposed on the insulating base layer, and the second section comprises a second inorganic non-conductive bonding layer disposed on the insulating base layer.

[0054] In another embodiment, an interconnect assembly comprises an insulating substrate having conductive traces, the insulating substrate having a first side and a second side opposite the first side; a first inorganic non-conductive bonding layer disposed on a first section of the first side of the insulating substrate, the first inorganic non-conductive bonding layer prepared for direct bonding; and a second inorganic non-conductive bonding layer disposed on a second section of the first side of the insulating substrate, the second section disposed spaced apart from the first section, the second inorganic non-conductive bonding layer prepared for direct bonding, wherein the insulating substrate comprises a flexible section disposed between the first section and the second section.

[0055] In some embodiments, the insulating substrate comprises an insulating base layer, and the conductive traces are at least partially embedded in the insulating base layer. In some embodiments, the insulating base layer extends at least partially through the first section, the second section, and the flexible section. In some embodiments, at least one conductive trace extends at least partially through the first section, the second section, and the flexible section. In some embodiments, the insulating base layer comprises a flexible thickness of an organic material. In some embodiments, the organic material comprises a polymer. In some embodiments, the organic material comprises at least one of a liquid crystal polymer (LCP) and a polyimide. In some embodiments, the organic layer has a coefficient of thermal expansion (CTE) of less than 12 ppm / °C. In some embodiments, the insulating base layer comprises a flexible thickness of an inorganic material. In some embodiments, a first inorganic non-conductive bonding layer is disposed on the insulating base layer. In some embodiments, a second inorganic non-conductive bonding layer is disposed on the insulating base layer. In some embodiments, the first inorganic non-conductive bonding layer and the second inorganic non-conductive bonding layer comprise planarized bonding surfaces. In some embodiments, the first inorganic non-conductive bonding layer and the second inorganic non-conductive bonding layer comprise activated bonding surfaces.

[0056] In another embodiment, an interconnect assembly can include an insulating substrate having at least one conductive trace, the insulating substrate having a first section, a second section, and a third section bridging the first and second sections; an inorganic first bonding layer on the first section of the insulating substrate, where the first bonding layer is prepared for direct bonding; and an inorganic second bonding layer on the second section of the insulating substrate, laterally spaced from the first bonding layer by a gap, the inorganic second bonding layer being prepared for direct bonding and overlying the third section.

[0057] In some embodiments, the insulating substrate includes an insulating base layer comprising a flexible thickness of an organic material. In some embodiments, the insulating base layer comprises a flexible thickness of an inorganic material. In some embodiments, the third section of the insulating substrate is flexible.

[0058] In another embodiment, a method can include providing an insulating layer having at least one conductive trace, the insulating layer having a first section, a second section, and a third section bridging the first and second sections; providing an inorganic first bonding layer on the first section of the insulating layer; providing an inorganic second bonding layer on the second section of the insulating layer; and preparing the inorganic second bonding layer for direct bonding.

[0059] In some embodiments, the third section of the insulating layer is flexible. In some embodiments, the method can include providing a blanket inorganic bonding layer on the carrier substrate and providing an insulating layer on the blanket inorganic bonding layer. In some embodiments, the method can include patterning the blanket inorganic bonding layer, the patterned inorganic bonding layer comprising an inorganic first bonding layer and a second bonding layer. In some embodiments, the method can include providing a first interlayer dielectric (ILD) layer on the insulating layer. In some embodiments, the method can include patterning a cavity in the insulating layer and providing a conductive material in the cavity. In some embodiments, the method can include polishing the conductive material. In some embodiments, the method can include providing a second insulating layer on the first insulating layer and the conductive material. In some embodiments, the method can include providing a second interlayer dielectric (ILD) layer on the second insulating layer. In some embodiments, the method can include forming a second cavity in the second insulating layer and providing a second conductive material in the second cavity. In some embodiments, the method can include polishing the second conductive material. In some embodiments, the method can include polishing the second conductive material to prepare the second ILD layer for direct bonding. In some embodiments, the second ILD layer comprises an inorganic first bonding layer and a second bonding layer. In some embodiments, the method can include patterning a conductive contact layer on the first bonding layer and the second bonding layer. In some embodiments, the method can include directly bonding the first bonding layer to the first semiconductor element without an intervening adhesive and directly bonding the second bonding layer to the second semiconductor element without an intervening adhesive.In some embodiments, the method can include preparing the inorganic first and second bonding layers includes planarizing the inorganic first and second bonding surfaces, and the inorganic first and second bonding surfaces can include an embedded conductive layer.

[0060] Unless the context clearly requires otherwise, the terms "comprises," "comprising," "including," "including," and the like, throughout this specification and claims, are to be construed in an inclusive sense, i.e., meaning "including, but not limited to," as opposed to an exclusive or exhaustive sense. The term "coupled," as generally used herein, refers to two or more elements that are either directly coupled or coupled through one or more intermediate elements. Similarly, the term "connected," as generally used herein, refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Additionally, the terms "herein," "up," "down," and similar terms, when used in this application, refer to this application as a whole and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as being "on" or "on" a second element, the first element may be directly on or on the second element such that the first and second elements are in direct contact, or the first element may be indirectly on or on the second element such that one or more elements are interposed between the first and second elements. Wherever the context permits, words using singular or plural numbers in the above Detailed Description may include plural or singular numbers, respectively. The term "or" in reference to a list of two or more items covers the following interpretations of this term: any of the items in the list, all of the items in the list, and all of any combination of the items in the list.

[0061] Additionally, conditional language used herein, such as, among others, "can," "may," "might," "for example," "such as," and the like, are generally intended to convey that certain embodiments include certain features, elements and / or conditions, and that other embodiments do not include certain features, elements and / or conditions, unless otherwise specified or understood within the context in which they are used. Thus, such conditional language is generally not intended to imply that a feature, element and / or condition is in any way required for one or more embodiments.

[0062] Although specific embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, although blocks are shown in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the disclosure. [Explanation of symbols]

[0063] 16 Hybrid Interconnect Assembly 17 Flexible Unit 18 Direct Hybrid Bonding Surface 19 Conductive Traces 20 Insulating substrate 23 Non-conductive bonding layer 25 Insulating base layer

Claims

1. a first semiconductor element; a second semiconductor element disposed at a gap from the first semiconductor element; an interconnect assembly including an insulating substrate with conductive traces; Equipped with the insulating substrate includes a first section directly bonded to the first semiconductor element, a second section directly bonded to the second semiconductor element without an adhesive, and a flexible section disposed between the first section and the second section, the flexible section at least partially bridging the gap; bonded structure.

2. The bonded structure of claim 1 , wherein the insulating substrate comprises an insulating base layer, and the conductive traces are at least partially embedded in the insulating base layer.

3. The bonded structure of claim 2 , wherein the insulating base layer extends at least partially through the first section, the second section, and the flexible section.

4. The joint structure of claim 2 or 3, wherein the insulating base layer comprises a plurality of insulating layers.

5. The bonded structure of claim 4 , further comprising an interlevel dielectric (ILD) layer disposed between the first insulating layer and the second insulating layer.

6. 6. The bonded structure of claim 2, wherein at least one of the conductive traces extends at least partially through the first section, the second section, and the flexible section.

7. The bonded structure of claim 2 , 3 , or 5 , wherein the first section comprises a first inorganic non-conductive bonding layer disposed on the insulating base layer.

8. 8. The bonded structure of claim 7, wherein the second section comprises a second inorganic non-conductive bonding layer disposed on the insulating base layer, and the flexible section is disposed between the first inorganic non-conductive bonding layer and the second inorganic non-conductive bonding layer.

9. 9. The bonded structure of claim 8, wherein a first surface of the insulating substrate is directly bonded to the first and second semiconductor elements, the insulating substrate includes a second surface opposite the first surface, and the first and second inorganic non-conductive bonding layers are disposed on the first surface of the insulating substrate.

10. 10. The bonding structure of claim 2, 3, 5, 8, or 9, wherein the interconnection assembly includes a test circuit connected to at least one of the first and second semiconductor elements, the test circuit configured to test the functionality of a circuit in at least one of the first and second semiconductor elements.

11. A bonded structure, Career and an interconnect assembly including an insulating substrate with conductive traces, the insulating substrate including a first section and a flexible section extending from the first section, the first section including a first inorganic non-conductive bonding layer, the first inorganic non-conductive bonding layer bonded directly to the carrier without an adhesive; A bonded structure comprising:

12. The bonded structure of claim 11 , wherein the carrier comprises a first semiconductor element.

13. 13. The bonded structure of claim 12, further comprising a second semiconductor element, wherein the insulating substrate includes a second section including a second inorganic non-conductive bonding layer, the second inorganic non-conductive bonding layer being bonded directly to the second semiconductor element without an adhesive.

14. 12. The bonded structure of claim 11, wherein the carrier includes a recess, the insulating substrate includes a second section including a second inorganic non-conductive bonding layer bonded directly to the carrier, and the flexible section at least partially bridges the recess in the carrier.

15. A bonded structure, a support assembly having a first mating surface and a second mating surface; an interconnect assembly covering the support assembly, the interconnect assembly including an insulating substrate having conductive traces, the insulating substrate having a first section bonded directly to the first mating surface without an adhesive, a second section bonded directly to the second mating surface without an adhesive, and a third section extending between the first and second sections, the third section bridging a gap between the first and second mating surfaces, the gap being filled with a gas; and A bonded structure comprising:

16. The bonded structure of claim 15 , wherein the third section of the insulating substrate is flexible.

17. the support assembly includes a first semiconductor element and a second semiconductor element spaced apart from the first semiconductor element by a gap, the first semiconductor element having a first bonding surface, and the second semiconductor element having a second bonding surface; The bonded structure according to claim 15 or 16.

18. The bonded structure of claim 17 , wherein the first and second semiconductor devices are mounted on a carrier.

19. The bonded structure of claim 15 , wherein the support assembly comprises a carrier having a recess, and the third section at least partially bridges the recess in the carrier.

20. 20. The bonded structure of claim 15, 16, 18, or 19, wherein the insulating substrate comprises an insulating base layer, the first section comprises a first inorganic non-conductive bonding layer disposed on the insulating base layer, and the second section comprises a second inorganic non-conductive bonding layer disposed on the insulating base layer.

21. 20. The bonded structure of claim 15, 16, 18, or 19, wherein the first bonding surface is at a first vertical position relative to an upper surface of the support assembly, and the second bonding surface is disposed at a second vertical position relative to the upper surface of the support assembly, the second vertical position being different from the first vertical position.

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