System and PWM controller for controlling skip mode in switching power supplies

Abstract

A system and a PWM controller for controlling a skip mode of a switching power supply related to the technical field of power supplies are provided. The system includes a feedback signal detection circuit (10), a primary winding sampling circuit (20), a skip mode soft control circuit (30), and a comparison circuit (40). The feedback signal detection circuit (10) is configured to detect an output voltage of the switching power supply and generate a feedback signal related to the output voltage. The primary winding sampling circuit (20) is configured to couple to a primary winding of the switching power supply and sample a sampling voltage of the primary winding. The skip mode soft control circuit (30) is configured to receive the feedback signal and output an electrical signal. The comparison circuit (40) is configured to determine a sampling voltage threshold based on the electrical signal and the sampling voltage, such that the skip mode is activated when the feedback signal is greater than a soft start voltage threshold, and the skip mode is terminated when the feedback signal is less than a predetermined voltage threshold and greater than a soft end voltage threshold. The system can effectively eliminate audio noise generated when the skip mode is activated or terminated.

Description

[Technical field]

[0001]

[0001] This application claims priority to Chinese Patent Application No. 202210599641.8, entitled "SYSTEM FOR CONTROLLING SKIP MODE OF SWITCHING POWER SUPPLY, AND PWM CONTROLLER", and Chinese Patent Application No. 202221320062.7, entitled "SYSTEM FOR CONTROLLING SKIP MODE OF SWITCHING POWER SUPPLY, AND PWM CONTROLLER", filed with the State Intellectual Property Office of China on May 30, 2022, both of which are incorporated by reference in their entireties into this specification.

[0002] The present disclosure relates to the technical field of power supplies, and more particularly to a system for controlling a skip mode of a switching power supply, and a PWM controller. [Background technology]

[0003]

[0003] A system with a Flayback architecture operates in a uniform mode under light load conditions, and the operating frequency is greater than 20 kHz, so no audio noise is generated and large power loss occurs. The power loss is caused by switching loss. In order to reduce the power loss and achieve good efficiency, the switching frequency must be less than 20 kHz. However, when the switching frequency is less than 20 kHz, audio noise occurs. Therefore, the system usually operates in a skip mode to eliminate the audio noise. However, when the system enters or exits the skip mode, the peak current of the primary winding jumps significantly, resulting in audio noise. Therefore, how to eliminate the audio noise generated when the system enters or exits the skip mode is a technical problem that must be urgently solved by those skilled in the art. Summary of the Invention

[0004]

[0004] According to the present disclosure, there is provided a system for controlling a skip mode of a switching power supply, the system eliminating audio noise when entering or exiting the skip mode. Additionally, according to the present disclosure, there is further provided a PWM controller that also has the above-mentioned technical effects.

[0005]

[0005] According to the present disclosure, in order to solve the above technical solution, a system for controlling a skip mode of a switching power supply is provided. The system includes a feedback signal detection circuit, a primary winding sampling circuit, a skip mode soft control circuit, and a comparison circuit. The feedback signal detection circuit is configured to detect an output voltage of the switching power supply and generate a feedback signal related to the output voltage. The primary winding sampling circuit is configured to couple to a primary winding of the switching power supply and obtain a sampling voltage of the primary winding. The skip mode soft control circuit is configured to receive the feedback signal and output an electrical signal. The comparison circuit is configured to determine a sampling voltage threshold based on the electrical signal and the sampling voltage. The skip mode is activated when the feedback signal is greater than a soft start voltage threshold, and the skip mode is terminated when the feedback signal is less than a predetermined voltage threshold and greater than a soft end voltage threshold.

[0006] In one embodiment, the skip mode soft control circuit includes a first comparator, a second comparator, a third comparator, a controller, and a multiplexer. The first comparator is configured to compare the feedback signal with a soft start voltage threshold. The second comparator is configured to compare the feedback signal with a predetermined voltage threshold. The third comparator is configured to compare the feedback signal with a soft end voltage threshold. The controller is configured to control the multiplexer to output a first predetermined number of electrical signals when the feedback signal is greater than the soft start voltage threshold, the comparison circuit outputs the first predetermined number of thresholds, the first predetermined number of thresholds increasing continuously, and the controller is configured to control the multiplexer to output a second predetermined number of electrical signals when the feedback signal is less than the predetermined voltage threshold and greater than the soft end voltage threshold, the comparison circuit outputs the second predetermined number of thresholds, the second predetermined number of thresholds decreasing continuously.

[0007] In one embodiment, when the feedback signal is less than the soft-activation voltage threshold and greater than a predetermined voltage threshold, the sampling voltage threshold varies with the feedback signal.

[0008] In one embodiment, when the feedback signal is less than the soft-termination voltage threshold, the sampling voltage threshold varies with the feedback signal.

[0009] In one embodiment, the voltage signal output by the skip mode soft control circuit is input to a first terminal of the comparison circuit, and the sampling voltage is input to a second terminal of the comparison circuit.

[0010] In one embodiment, the feedback signal is input to a first terminal of the comparison circuit, and a superposition of the voltage signal output by the skip mode soft control circuit and the sampling voltage is input to a second terminal of the comparison circuit.

[0011]

[0011] In one embodiment, a superposition of the voltage signal output by the skip mode soft control circuit and the feedback signal is input to a first terminal of the comparison circuit, and a sampling voltage is input to a second terminal of the comparison circuit.

[0012]

[0012] In one embodiment, a voltage signal converted from a current signal output by the skip mode soft control circuit is input to a first terminal of a comparison circuit, and a sampling voltage is input to a second terminal of the comparison circuit.

[0013]

[0013] In one embodiment, a feedback signal is input to a first terminal of a comparison circuit, and a superposition of a voltage signal converted from a current signal output by the skip mode soft control circuit and a sampling voltage is input to a second terminal of the comparison circuit.

[0014]

[0014] In one embodiment, a superposition of a voltage signal converted from a current signal output by a skip mode soft control circuit and a feedback signal is input to a first terminal of a comparison circuit, and a sampling voltage is input to a second terminal of the comparison circuit.

[0015] In one embodiment, the comparison circuit includes a fourth comparator, the positive input terminal of the fourth comparator functions as a first terminal of the comparison circuit, the negative input terminal of the fourth comparator functions as a second terminal of the comparison circuit, and the output terminal of the fourth comparator functions as an output terminal of the comparison circuit.

[0016] In one embodiment, a signal terminal of a multiplexer is connected to an output terminal of a feedback signal detection circuit, and the multiplexer outputs the feedback signal when the feedback signal is less than a soft-start voltage threshold and greater than a predetermined voltage threshold.

[0017]

[0017] In one embodiment, the signal terminal of the multiplexer is not connected to the output terminal of the feedback signal detection circuit, and the multiplexer continuously outputs a voltage equal to 0 when the feedback signal is less than the soft-start voltage threshold and greater than a predetermined voltage threshold.

[0018] In one embodiment, the system further includes a first low-frequency signal generator configured to output a low-frequency signal that is superimposed with the signal output by the feedback signal detection circuit.

[0019] In one embodiment, the system further includes a second low frequency signal generator configured to output a low frequency signal that is superimposed with the signal input to the feedback signal detection circuit.

[0020] In one embodiment, the system further includes a third low-frequency signal generator configured to output a low-frequency signal that is superimposed with the signal output by the primary winding sampling circuit.

[0021]

[0021] According to the present disclosure, in order to solve the above technical solution, a PWM controller is further provided, which includes the above system for controlling the skip mode of a switching power supply.

[0022]

[0022] A system according to the present disclosure for controlling a skip mode of a switching power supply includes a feedback signal detection circuit, a primary winding sampling circuit, a skip mode soft control circuit, and a comparison circuit. The feedback signal detection circuit is configured to detect an output voltage of the switching power supply and generate a feedback signal related to the output voltage. The primary winding sampling circuit is configured to couple to a primary winding of the switching mode power supply and obtain a sampled voltage of the primary winding. The skip mode soft control circuit is configured to receive the feedback signal and output an electrical signal. The comparison circuit is configured to determine a sampling voltage threshold based on the electrical signal and the sampling voltage. The skip mode is activated when the feedback signal is greater than a soft start voltage threshold, and the skip mode is terminated when the feedback signal is less than a predetermined voltage threshold and greater than a soft end voltage threshold.

[0023]

[0023] In the system according to the present disclosure for controlling the skip mode of a switching power supply, by using a skip mode soft control circuit and a comparison circuit, it can be seen that, based on a feedback signal related to the output voltage of the switching power supply and a sampling voltage of the primary winding, the skip mode is activated when the feedback signal is greater than a soft start voltage threshold, and the skip mode is terminated when the feedback signal is less than a predetermined voltage threshold and greater than a soft termination voltage threshold. After the skip mode is activated, the peak current of the primary winding gradually increases, and audio noise caused by a large jump in the peak current of the primary winding is avoided. After the skip mode is terminated, the peak current of the primary winding gradually decreases until the end of the skip mode, and audio noise caused by a large jump in the peak current of the primary winding when the skip mode is terminated is avoided.

[0024]

[0024] The PWM controller according to the present disclosure also has the above-mentioned technical effects.

[0025]

[0025] In order to more clearly describe the technical solutions in the embodiments of the present disclosure, the drawings used in the description of the embodiments of the present disclosure or in the prior art are briefly described below. The drawings described below are only used to describe the embodiments of the present disclosure, and it is obvious that a person skilled in the art can obtain other drawings based on the drawings without creative efforts. [Brief description of the drawings]

[0026] [Figure 1] FIG. 1 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to a first embodiment of the present disclosure. [Diagram 2] FIG. 1 is a schematic diagram of a system having a Flayback architecture according to one embodiment of the present disclosure. [Diagram 3] FIG. 4 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to a second embodiment of the present disclosure. [Figure 4] FIG. 2 is a schematic diagram illustrating peak current in a primary winding according to a first embodiment of the present disclosure. [Diagram 5] FIG. 13 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to a third embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic diagram illustrating voltage superposition performed by the system shown in FIG. 5 according to one embodiment of the present disclosure. [Figure 7] FIG. 13 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to a fourth embodiment of the present disclosure. [Figure 8] FIG. 13 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to a fifth embodiment of the present disclosure. [Figure 9] FIG. 13 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to a sixth embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic diagram illustrating voltage superposition performed by the system shown in FIG. 9 according to one embodiment of the present disclosure. [Figure 11]FIG. 13 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to a seventh embodiment of the present disclosure. [Figure 12] FIG. 13 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to an eighth embodiment of the present disclosure. [Figure 13] FIG. 11 is a schematic diagram illustrating peak current in a primary winding according to a second embodiment of the present disclosure. [Figure 14] FIG. 13 is a schematic diagram illustrating peak current in a primary winding according to a third embodiment of the present disclosure. [Figure 15] FIG. 13 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to a ninth embodiment of the present disclosure. [Figure 16] FIG. 23 is a schematic diagram of a system for controlling a skip mode of a switching power supply according to a tenth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027]

[0042] According to the present disclosure, a system for controlling a skip mode of a switching power supply is provided to eliminate audio noise generated when entering or exiting the skip mode. According to the present disclosure, a PWM controller is further provided, which also has the above-mentioned technical effects.

[0028]

[0043] In order to clarify the objectives, technical solutions and advantages of the present disclosure, the technical solutions in the embodiments of the present disclosure are clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Of course, the embodiments described below are only some embodiments, not all embodiments of the present disclosure. Any other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts are included in the scope of protection of the present disclosure.

[0029]

[0044] EMBODIMENT 1

[0030]

[0045] Referring to Figure 1, Figure 1 is a schematic diagram of a system for controlling the skip mode of a switching power supply according to one embodiment of the present disclosure. As shown in Figure 1, the system includes a feedback signal detection circuit 10, a primary winding sampling circuit 20, a skip mode soft control circuit 30, and a comparison circuit 40.

[0031]

[0046] The system for controlling the skip mode of a switching power supply according to this embodiment is applied to a PWM controller in a network having a Flyback architecture as shown in Fig. 2. In addition to the system including a feedback signal detection circuit 10, a primary winding sampling circuit 20, a skip mode soft control circuit 30, and a comparison circuit 40, the PWM controller further includes an oscillator, an SR trigger, and a driver.

[0032]

[0047] The Comp pin of the PWM controller is connected to a feedback network, and the feedback network is connected to a secondary winding of the switching power supply. A feedback signal from the secondary winding of the switching power supply is input to the Comp pin of the PWM controller. After the feedback signal of the secondary winding is input to the feedback signal detection circuit 10, the feedback signal detection circuit 10 can output two feedback signals Comp_out1 and Comp_out2. Alternatively, after the feedback signal of the secondary winding is input to the feedback signal detection circuit 10, the feedback signal detection circuit 10 may output one feedback signal, that is, the feedback signals Comp_out1 and Comp_out2 may be combined into one feedback signal and output.

[0033]

[0048] In some embodiments, the feedback signal detection circuit 10 may include a voltage divider.

[0034]

[0049] The primary winding sampling circuit 20 is coupled to a primary winding of the switching power supply and configured to sample a voltage across the primary winding.

[0035]

[0050] In some embodiments, the primary winding sampling circuit 20 may include a compensator. A sampling voltage (hereinafter denoted as Vcs) of a sampling resistor (R115 as shown in FIG. 2) connected to the primary winding is input to the compensator.

[0036]

[0051] The skip mode soft control circuit 30 is configured to receive the feedback signal and to output an electrical signal based on the feedback signal.

[0037]

[0052] In some embodiments, the skip mode soft control circuit 30 includes a first comparator 301, a second comparator 302, a third comparator 303, a controller 304, and a multiplexer 305. The first comparator 301 is configured to compare the feedback signal with a soft start voltage threshold. The second comparator 302 is configured to compare the feedback signal with a predetermined voltage threshold. The third comparator 303 is configured to compare the feedback signal with a soft end voltage threshold. The controller 304 is configured to control the multiplexer 305 to output a first predetermined number of electrical signals when the feedback signal is greater than the soft start voltage threshold, the comparison circuit 40 outputs the first predetermined number of thresholds, the first predetermined number of thresholds increasing continuously, and the controller 304 is configured to control the multiplexer 305 to output a second predetermined number of electrical signals when the feedback signal is less than the predetermined voltage threshold and greater than the soft end voltage threshold, the comparison circuit 40 outputs the second predetermined number of thresholds, the second predetermined number of thresholds decreasing continuously.

[0038]

[0053] In this embodiment, the skip mode soft control circuit 30 includes a controller 304, a multiplexer 305, and three comparators. The positive input terminal of the first comparator 301, the positive input terminal of the second comparator 302, and the positive input terminal of the third comparator 303 are connected to the output terminal of the feedback signal detection circuit 10. A soft start voltage threshold is input to the negative input terminal of the first comparator 301, a predetermined voltage threshold is input to the negative input terminal of the second comparator 302, and a soft termination voltage threshold is input to the negative input terminal of the third comparator 303. The soft start voltage threshold is smaller than the predetermined voltage threshold, and the predetermined voltage threshold is smaller than the soft termination voltage threshold. The output terminal of the first comparator 301, the output terminal of the second comparator 302, and the output terminal of the third comparator 303 are connected to the controller 304. The controller 304 is connected to the multiplexer 305.

[0039]

[0054] 3, take the feedback signal detection circuit 10 including a voltage divider and outputting two feedback signals Comp_out1 and Comp_out2 as an example, Comp_out1 is input to the positive input terminal of a first comparator 301, the positive input terminal of a second comparator 302, and the positive input terminal of a third comparator 303. A soft-start voltage threshold (VrefH shown in FIG. 3) is input to the negative input terminal of the first comparator 301, and the output signal of the first comparator 301 (Y_Skip_H shown in FIG. 3) is input to a controller 304. A predetermined voltage threshold (VrefM shown in FIG. 3) is input to the negative input terminal of the second comparator 302, and the output signal of the second comparator 302 (Y_Skip_M shown in FIG. 3) is input to the controller 304. A soft-termination voltage threshold (VrefL shown in FIG. 3) is input to the negative input terminal of a third comparator 303, and an output signal of the third comparator 303 (Y_Skip_L shown in FIG. 3) is input to a controller 304.

[0040]

[0055] The controller 304 generates a control signal for controlling the oscillator. For example, the control signal can be represented as EN_OSC. EN_OSC is input to the oscillator and controls the oscillator to output a pulse or not to output a pulse. The output of the oscillator is input to the Set terminal of the SR trigger. The SR trigger is connected to a driver. The driver drives the gate of a switch tube (M120 shown in FIG. 2) connected to the PWM controller 304.

[0041]

[0056] Also, the controller 304 generates a number of pulse signals, represented by, for example, s1, s2, s3, s4, . . . , s(n-3), s(n-2), s(n-1), s(n), s(n+1), respectively. The pulse signals are input to the multiplexer 305. Then, the multiplexer 305 outputs a first predetermined number of electrical signals when the feedback signal is greater than a soft-start voltage threshold, the first predetermined number of electrical signals changing according to a first predetermined rule, and the multiplexer 305 outputs a second predetermined number of electrical signals when the feedback signal is less than a predetermined voltage threshold and greater than a soft-stop voltage threshold, the second predetermined number of electrical signals changing according to a second predetermined rule. The electrical signals are voltage signals or current signals.

[0042]

[0057] The comparison circuit 40 is configured to determine a sampling voltage threshold based on the electrical signal output by the skip mode soft control circuit 30 and the sampling voltage output by the primary winding such that the skip mode is activated when the feedback signal is greater than a soft start-up voltage threshold and the skip mode is terminated when the feedback signal is less than a predetermined voltage threshold and greater than a soft exit voltage threshold.

[0043]

[0058] In some embodiments, the comparison circuit 40 includes a fourth comparator 401 .

[0044]

[0059] When the feedback signal is greater than the soft-start voltage threshold, the multiplexer 305 outputs the first predetermined number of electrical signals, and then the comparison circuit 40 determines the first predetermined number of thresholds of Vcs based on the first predetermined number of electrical signals. The first predetermined number of thresholds increases continuously.

[0045]

[0060] Since the threshold of Vcs is continuously increased, Vcs increases gradually. It should be understood that Vcs has a positive correlation with the peak current of the primary winding, so the gradual increase of Vcs indicates that the peak current of the primary winding increases gradually. Therefore, when activating the skip mode, the peak current of the primary winding can be gradually increased by increasing the threshold of Vcs.

[0046]

[0061] When the feedback signal is less than the predetermined voltage threshold and greater than the soft-termination voltage threshold, the multiplexer 305 outputs a second predetermined number of electrical signals, and then the fourth comparator 401 determines a second predetermined number of thresholds of Vcs based on the second predetermined number of electrical signals. The second predetermined number of thresholds decreases continuously.

[0047]

[0062] Since the threshold value of Vcs is continuously decreased, Vcs is gradually decreased when the skip mode is going to end. Since Vcs has a positive correlation with the peak current of the primary winding, the gradual decrease of Vcs indicates that the peak current of the primary winding is gradually decreased. Therefore, when the skip mode is going to end, the peak current of the primary winding can be gradually decreased by decreasing the threshold value of Vcs.

[0048]

[0063] When the feedback signal is less than the soft-activation voltage threshold and greater than a predetermined voltage threshold, the sampling voltage threshold varies with the feedback signal.

[0049]

[0064] When the feedback signal is less than the soft-termination voltage threshold, the sampling voltage threshold varies with the feedback signal.

[0050]

[0065] In summary, in the system for controlling the skip mode of a switching power supply according to the present disclosure, by using the skip mode soft control circuit 30 and the comparison circuit 40, based on a feedback signal related to the output voltage of the switching power supply and the sampling voltage of the primary winding, the skip mode is initiated when the feedback signal is greater than a soft start voltage threshold, and the skip mode is terminated when the feedback signal is less than a predetermined voltage threshold and greater than a soft termination voltage threshold. After the skip mode is initiated, the peak current of the primary winding gradually increases, avoiding audio noise caused by a large jump in the peak current of the primary winding. After the skip mode is terminated, the peak current of the primary winding gradually decreases until the end of the skip mode, avoiding audio noise caused by a large jump in the peak current of the primary winding when the skip mode is terminated.

[0051]

[0066] EMBODIMENT 2

[0052]

[0067] In this embodiment, the multiplexer 305 outputs a voltage signal. The voltage signal output by the multiplexer 305 is input to the positive input terminal of the fourth comparator 401, and the sampling voltage is input to the negative input terminal of the fourth comparator 401. The signal terminal of the multiplexer 305 is connected to the output terminal of the feedback signal detection circuit 10. The multiplexer 305 outputs the feedback signal when the feedback signal is smaller than the soft start voltage threshold and larger than a predetermined voltage threshold.

[0053]

[0068] As shown in FIG. 3, Comp_out2 is input to terminal D0 of multiplexer 305, and voltage signals Vref1 to Vref_min are respectively input to terminals D1 to D(n + 1) of multiplexer 305. Controller 304 outputs pulse signals s1 to s(n + 1) to multiplexer 305. The output terminal of multiplexer 305 is connected to the positive input terminal of the fourth comparator 401, and the negative input terminal of the fourth comparator 401 is connected to the output terminal of the compensator. The threshold value of Vcs is equal to the voltage signal output by multiplexer 305.

[0054]

[0069] Taking the case where the first predetermined number is 4 and the second predetermined number is 4 as an example, when the skip mode is started, controller 304 outputs pulse signals s1 to s4 to multiplexer 305, and multiplexer 305 sequentially outputs voltage signals Vref1, Vref2, Vref3, and Vref4, where Vref1 < Vref2 < Vref3 < Vref4. Multiplexer 305 sequentially outputs voltage signals Vref1, Vref2, Vref3, and Vref4 to the positive input terminal of the fourth comparator 401. Vref1, Vref2, Vref3, and Vref4 sequentially function as the threshold value of Vcs, so Vcs gradually increases so as to approach the threshold value.

[0055]

[0070] When controller 304 outputs pulse signals s5 to s(n - 4) to multiplexer 305, multiplexer 305 continuously outputs Comp_out2 input to terminal D0. Also, when controller 304 outputs pulse signals s5 to s(n - 4) to multiplexer 305, multiplexer 305 continuously outputs Comp_out2 as the threshold value of Vcs to the positive input terminal of the fourth comparator 401.

[0056]

[0071] When the skip mode is about to end, the controller 304 outputs the pulse signals s(n-3) to s(n) to the multiplexer 305. The multiplexer 305 sequentially outputs the voltage signals Vref(n-3), Vref(n-2), Vref(n-1), and Vref(n), where Vref(n) < Vref(n-1) < Vref(n-2) < Vref(n-3). The multiplexer 305 sequentially outputs Vref(n-3), Vref(n-2), Vref(n-1), and Vref(n) to the positive input terminal of the fourth comparator 401. Vref(n-3), Vref(n-2), Vref(n-1), and Vref(n) function sequentially as the threshold value of Vcs. Therefore, Vcs gradually decreases so as to approach the threshold value.

[0057]

[0072] The change in the peak current of the primary winding at the start of the skip mode or when the skip mode is about to end is shown in FIG. 4, where ipeak represents the peak current of the primary winding. When Comp_out1 is greater than VrefH, the output terminal Comp_MUX of the multiplexer 305 sequentially outputs Vref1, Vref2, Vref3, and Vref4 to control the first several ipeaks. Thereafter, ipeak is controlled based on Comp_out2. When Comp_out1 is less than VrefM and greater than VrefL, Comp_MUX sequentially outputs Vref(n-3), Vref(n-2), Vref(n-1), and Vref(n) to control ipeak. Thereafter, ipeak is maintained as Vref_min or controlled based on Vref(n).

[0058]

[0073] Embodiment 3

[0059]

[0074] In this embodiment, the multiplexer 305 outputs a voltage signal. The feedback signal is input to the positive input terminal of the fourth comparator 401. The superposition of the voltage signal output by the multiplexer 305 and the sampling voltage is input to the negative input terminal of the fourth comparator 401. The signal terminal of the multiplexer 305 is not connected to the output terminal of the feedback signal detection circuit 10. When the feedback signal is smaller than the soft-activation voltage threshold and larger than the predetermined voltage threshold, the multiplexer 305 continuously outputs a voltage equal to 0.

[0060]

[0075] The voltage signal output by the multiplexer 305 is superimposed with the sampling voltage and then compared with the feedback signal, which is equivalent to using the difference between the feedback signal and the voltage signal output by the multiplexer 305 as the threshold for the sampling voltage.

[0061]

[0076] 5, Comp_out2 output by the feedback signal detection circuit 10 is input to the positive input terminal of the fourth comparator 401, and the voltage signals Vref1 to Vref_min are input to the terminals D1 to D(n+1) of the multiplexer 305, respectively. The controller 304 outputs pulse signals s1 to s(n+1) to the multiplexer 305. The voltage signal output by the multiplexer 305 is superimposed with Vcs and then input to the negative input terminal of the fourth comparator 401. In FIG. 5, the addition symbol represents the superposition of two voltage signals.

[0062]

[0077] Referring to FIG. 6, the voltage signal output by the multiplexer 305 can be superimposed on Vcs by converting the voltage signal output by the multiplexer 305 into a current signal and inputting the current signal to one terminal of a resistor Res (the other terminal of the resistor Res is connected to the output terminal of the compensator).

[0063]

[0078] It should be appreciated that in addition to performing voltage superposition as shown in FIG. 6, the two voltage signals can be superimposed on one another using an in-phase summing circuit, an anti-phase summing circuit, or the like.

[0064]

[0079] Taking the case where the first predetermined number is 4 and the second predetermined number is 4 as an example, the controller 304 outputs the pulse signals s1 to s4 to the multiplexer 305, and the multiplexer 305 sequentially outputs Vref1, Vref2, Vref3, and Vref4, where Vref1>Vref2>Vref3>Vref4. Vref1, Vref2, Vref3, and Vref4 are each superimposed with Vcs, and then sequentially input to the negative input terminal of the fourth comparator 401. Vref1, Vref2, Vref3, and Vref4 after superimposition with Vcs are each compared with Comp_out2. Since Vref1>Vref2>Vref3>Vref4, Vcs gradually increases so that the voltage after superposition approaches a value equal to Comp_out2.

[0065]

[0080] When the controller 304 outputs the pulse signals s5 to s(n-4) to the multiplexer 305, the multiplexer 305 continues to output a voltage equal to 0. Furthermore, when the controller 304 outputs the pulse signals s5 to s(n-4) to the multiplexer 305, the voltage equal to 0 output by the multiplexer 305 is superimposed with Vcs and then compared with Comp_out2, so that the threshold value of Vcs becomes equal to the value of Comp_out2.

[0066]

[0081] The controller 304 outputs s(n-3) to s(n) to the multiplexer 305, and the multiplexer 305 sequentially outputs Vref(n-3), Vref(n-2), Vref(n-1), and Vref(n), such that Vref(n)>Vref(n-1)>Vref(n-2)>Vref(n-3). Vref(n-3), Vref(n-2), Vref(n-1), and Vref(n) sequentially output by the multiplexer 305 are each superimposed with Vcs, and then sequentially input to the negative input terminal of the fourth comparator 401. Comp_out2 is input to the positive input terminal of the fourth comparator 401. Vref(n-3), Vref(n-2), Vref(n-1), and Vref(n) after superimposition with Vcs are each compared with Comp_out2. Since Vref(n)>Vref(n-1)>Vref(n-2)>Vref(n-3), Vcs gradually decreases so that the voltage after superposition approaches a value equal to Comp_out2.

[0067]

[0082] EMBODIMENT 4

[0068]

[0083] In this embodiment, the multiplexer 305 outputs a voltage signal. The superposition of the voltage signal output by the multiplexer 305 and the feedback signal is input to the positive input terminal of the fourth comparator 401. The sampling voltage is input to the negative input terminal of the fourth comparator 401. The signal terminal of the multiplexer 305 is not connected to the output terminal of the feedback signal detection circuit 10. When the feedback signal is smaller than the activation voltage threshold and larger than the predetermined voltage threshold, the multiplexer 305 continuously outputs a voltage equal to 0.

[0069]

[0084] The voltage signal output by the multiplexer 305 is superimposed with the feedback signal and then compared with the sampling voltage, which is equivalent to using the sum of the voltage signal output by the multiplexer 305 and the feedback signal as the threshold value of the sampling voltage.

[0070]

[0085] As shown in FIG. 7, Vcs is input to the negative input terminal of the fourth comparator 401, and voltage signals Vref1 to Vref_min are respectively input to terminals D1 to D(n + 1) of the multiplexer 305. The controller 304 outputs pulse signals s1 to s(n + 1) to the multiplexer 305. The voltage signal output by the multiplexer 305 is input to the positive input terminal of the fourth comparator 401 after being superimposed on Comp_out2.

[0071]

[0086] In FIG. 7, the plus sign represents the superposition of two voltage signals. The voltage signal output by the multiplexer 305 may be superimposed on Comp_out2 by performing an operation for superimposing the voltage signals described in the above embodiment (not repeated here).

[0072]

[0087] Taking the case where the first predetermined number is 4 and the second predetermined number is 4 as an example, the controller 304 outputs pulse signals s1 to s4 to the multiplexer 305, and the multiplexer 305 sequentially outputs Vref1, Vref2, Vref3, and Vref4, where Vref1 < Vref2 < Vref3 < Vref4. Vref1, Vref2, Vref3, and Vref4 sequentially output by the multiplexer 305 are respectively input to the positive input terminal of the fourth comparator 401 after being superimposed on Comp_out2. Vcs is input to the negative input terminal of the fourth comparator 401. Vref1, Vref2, Vref3, and Vref4 after being superimposed on Comp_out2 are respectively compared with Vcs. Since Vref1 < Vref2 < Vref3 < Vref4, Vcs gradually increases so as to approach the value of the voltage after superposition.

[0073]

[0088] When the controller 304 outputs the pulse signals s5 to s(n - 4) to the multiplexer 305, the multiplexer 305 continues to output a voltage equal to 0. Further, when the controller 304 outputs the pulse signals s5 to s(n - 4) to the multiplexer 305, Comp_out2 is superimposed on the voltage equal to 0 output by the multiplexer 305, and then compared with Vcs, so that the threshold value of Vcs becomes equal to the value of Comp_out2.

[0074]

[0089] The controller 304 outputs s(n - 3) to s(n) to the multiplexer 305, and the multiplexer 305 sequentially outputs Vref(n - 3), Vref(n - 2), Vref(n - 1), and Vref(n), where Vref(n) < Vref(n - 1) < Vref(n - 2) < Vref(n - 3). The Vref(n - 3), Vref(n - 2), Vref(n - 1), and Vref(n) sequentially output by the multiplexer 305 are each superimposed on Comp_out2 and then sequentially input to the positive input terminal of the fourth comparator 401. Vcs is input to the negative input terminal of the fourth comparator 401. The Vref(n - 3), Vref(n - 2), Vref(n - 1), and Vref(n) after being superimposed with Comp_out2 are each compared with Vcs. Since Vref(n) < Vref(n - 1) < Vref(n - 2) < Vref(n - 3), Vcs gradually decreases so as to approach the value of the voltage after superimposition.

[0075]

[0090] Embodiment 5

[0076]

[0091] In this embodiment, the multiplexer 305 outputs a current signal. The voltage signal converted from the current signal output by the multiplexer 305 is input to the positive input terminal of the fourth comparator 401. A sampling voltage is input to the negative input terminal of the fourth comparator 401.

[0077]

[0092] Referring to FIG. 8, Comp_out2 output by the feedback signal detection circuit 10 is input to terminal D0 of the multiplexer 305 after being converted into a current signal. Current signals Iref1 to Iref_min are respectively input to terminals D1 to D(n + 1) of the multiplexer 305. The controller 304 outputs pulse signals s1 to s(n + 1) to the multiplexer 305. The output terminal of the multiplexer 305 is connected to a current-voltage converter. The output terminal of the current-voltage converter is connected to the positive input terminal of the fourth comparator 401. The negative input terminal of the fourth comparator 401 is connected to the output terminal of the compensator.

[0078]

[0093] Taking the case where the first predetermined number is 4 and the second predetermined number is 4 as an example, the controller 304 outputs pulse signals s1 to s4 to the multiplexer 305, and the multiplexer 305 sequentially outputs Iref1, Iref2, Iref3, and Iref4, where Iref1 < Iref2 < Iref3 < Iref4. The multiplexer 305 sequentially outputs Iref1, Iref2, Iref3, and Iref4 to the input terminal of the current-voltage converter. The current-voltage converter sequentially outputs Vref1, Vref2, Vref3, and Vref4 obtained by converting Iref1, Iref2, Iref3, and Iref4 to the positive input terminal of the fourth comparator 401 as the threshold value for Vcs. Since Iref1 < Iref2 < Iref3 < Iref4, Vref1 < Vref2 < Vref3 < Vref4, and Vcs gradually increases.

[0079]

[0094] When the controller 304 outputs pulse signals s5 to s(n - 4) to the multiplexer 305, the multiplexer 305 continuously outputs the current signal obtained by converting Comp_out2. Next, the current-voltage converter converts the current signal into Comp_out2 and outputs Comp_out2. Further, when the controller 304 outputs pulse signals s5 to s(n - 4) to the multiplexer 305, Comp_out2 is input to the positive input terminal of the fourth comparator 401 as the threshold value of Vcs.

[0080]

[0095] The controller 304 outputs s(n - 3) to s(n) to the multiplexer 305. The multiplexer 305 sequentially outputs Iref(n - 3), Iref(n - 2), Iref(n - 1), and Iref(n), where Iref(n) < Iref(n - 1) < Iref(n - 2) < Iref(n - 3). The multiplexer 305 sequentially outputs Iref(n - 3), Iref(n - 2), Iref(n - 1), and Iref(n) to the current-voltage converter. Then, the current-voltage converter sequentially outputs Vref(n - 3), Vref(n - 2), Vref(n - 1), and Vref(n), which are respectively obtained by converting Iref(n - 3), Iref(n - 2), Iref(n - 1), and Iref(n), to the positive input terminal of the fourth comparator 401 as the threshold values of Vcs. Since Iref(n) < Iref(n - 1) < Iref(n - 2) < Iref(n - 3), Vref(n) < Vref(n - 1) < Vref(n - 2) < Vref(n - 3), and Vcs gradually decreases.

[0081]

[0096] Embodiment 6

[0082]

[0097] In this embodiment, the multiplexer 305 outputs a current signal. The feedback signal is input to the positive input terminal of the fourth comparator 401. The superposition of the voltage signal converted from the current signal output by the multiplexer 305 and the sampling voltage is input to the negative input terminal of the fourth comparator 401.

[0083]

[0098] The voltage signal converted from the current signal is superimposed on the sampling voltage and then compared with the feedback signal, which is equivalent to using the difference between the feedback signal and the voltage signal converted from the current signal as the threshold value of the sampling voltage.

[0084]

[0099] 9, the feedback signal detection circuit 10 outputs Comp_out2 to the positive input terminal of the fourth comparator 401, and the current signals Iref1 to Iref_min are input to the terminals D1 to D(n+1) of the multiplexer 305, respectively. The controller 304 outputs the pulse signals s1 to s(n+1) to the multiplexer 305. The current signal output by the multiplexer 305 is converted into a voltage signal, superimposed with Vcs, and then input to the negative input terminal of the fourth comparator 401.

[0085]

[0100] Referring to FIG. 10, the superposition of the voltage signals can be achieved by directly inputting the current signal output by the multiplexer 305 to one terminal of a resistor Res and connecting the other terminal of the resistor Res to the output terminal of the compensator.

[0086]

[0101] Taking the case where the first predetermined number is 4 and the second predetermined number is 4 as an example, the controller 304 outputs the pulse signals s1 to s4 to the multiplexer 305, and the multiplexer 305 sequentially outputs Iref1, Iref2, Iref3, and Iref4, where Iref1>Iref2>Iref3>Iref4. The multiplexer 305 sequentially outputs Iref1, Iref2, Iref3, and Iref4 to one terminal of the resistor Res, and the other terminal of the resistor Res is connected to the compensator, which is equivalent to converting the current signal into a voltage signal and then superimposing the voltage signal with Vcs. The voltage signal superimposed with Vcs is input to the negative input terminal of the fourth comparator 401. Comp_out2 is input to the positive input terminal of the fourth comparator 401. The voltage signals superimposed with Vcs are compared with Comp_out2, respectively. Since Iref1>Iref2>Iref3>Iref4, Vcs gradually increases so that the voltage after superposition approaches a value equal to Comp_out2.

[0087]

[0102] When the controller 304 outputs the pulse signals s5 to s(n-4) to the multiplexer 305, the multiplexer 305 continues to output a current equal to 0. Furthermore, when the controller 304 outputs the pulse signals s5 to s(n-4) to the multiplexer 305, Vcs is compared with Comp_out2, and the threshold value of Vcs is equal to the value of Comp_out2.

[0088]

[0103] The controller 304 outputs s(n-3) to s(n) to the multiplexer 305, which sequentially outputs Iref(n-3), Iref(n-2), Iref(n-1), and Iref(n), such that Iref(n)>Iref(n-1)>Iref(n-2)>Iref(n-3). The multiplexer 305 sequentially outputs Iref(n-3), Iref(n-2), Iref(n-1), and Iref(n) to one terminal of a resistor Res, the other terminal of which is connected to a compensator, which corresponds to converting a current signal to a voltage signal and then superimposing the voltage signal with Vcs. The voltage signal superimposed with Vcs is input to the negative input terminal of the fourth comparator 401. Comp_out2 is input to the positive input terminal of the fourth comparator 401. The voltage signals superimposed on Vcs are compared with Comp_out2. Since Iref(n)>Iref(n-1)>Iref(n-2)>Iref(n-3), Vcs is gradually decreased so that the voltage after superimposition approaches a value equal to Comp_out2.

[0089]

[0104] EMBODIMENT 7

[0090]

[0105] In this embodiment, the multiplexer 305 outputs a current signal. A voltage signal converted from the current signal output by the multiplexer 305 and a feedback signal are superimposed on each other and input to a positive input terminal of the fourth comparator 401. A sampling voltage is input to a negative input terminal of the fourth comparator 401.

[0091]

[0106] The voltage signal converted from the current signal is superimposed with the feedback signal and then compared with the sampled voltage, which is equivalent to using the sum of the feedback signal and the voltage signal converted from the current signal as the threshold for the sampled voltage.

[0092]

[0107] 11, Vcs is input to the negative input terminal of the fourth comparator 401, and the current signals Iref1 to Iref_min are input to the terminals D1 to D(n+1) of the multiplexer 305, respectively. The controller 304 outputs the pulse signals s1 to s(n+1) to the multiplexer 305. The current signal output by the multiplexer 305 is converted to a voltage signal and then superimposed with Comp_out2. The voltage signal superimposed with Comp_out2 is input to the positive input terminal of the fourth comparator 401.

[0093]

[0108] In Fig. 11, the addition symbol represents the superposition of two voltage signals. The superposition of the voltage signal converted from the current signal with Comp_out2 can be performed by inputting the current signal output by the multiplexer 305 to one terminal of a resistor and inputting the current signal converted from Comp_out2 to the other terminal of the resistor. Therefore, the current-to-voltage converter shown in Fig. 11 is not required.

[0094]

[0109] Taking the case where the first predetermined number is 4 and the second predetermined number is 4 as an example, the controller 304 outputs pulse signals s1 to s4 to the multiplexer 305, and the multiplexer 305 sequentially outputs Iref1, Iref2, Iref3, and Iref4, where Iref1 < Iref2 < Iref3 < Iref4. The multiplexer 305 sequentially outputs Iref1, Iref2, Iref3, and Iref4 to one terminal of the resistor, and the current signal converted from Comp_out2 is input to the other terminal of the resistor, which is equivalent to converting the current signal into a voltage signal and then superimposing the voltage signal on Comp_out2. The voltage signal superimposed on Comp_out2 is input to the positive input terminal of the fourth comparator 401. Vcs is input to the negative input terminal of the fourth comparator 401. The voltage signal superimposed on Comp_out2 is compared with Vcs respectively. Since Iref1 < Iref2 < Iref3 < Iref4, the voltage signal superimposed on Comp_out2 increases, and Vcs gradually increases so as to approach the value of the superimposed voltage.

[0095]

[0110] When the controller 304 outputs pulse signals s5 to s(n - 4) to the multiplexer 305, the multiplexer 305 continues to output a current equal to 0. Further, when the controller 304 outputs pulse signals s5 to s(n - 4) to the multiplexer 305, Vcs is compared with Comp_out2, and the threshold value of Vcs is equal to the value of Comp_out2.

[0096]

[0111] The controller 304 outputs s(n - 3) to s(n) to the multiplexer 305. The multiplexer 305 sequentially outputs Iref(n - 3), Iref(n - 2), Iref(n - 1), and Iref(n), where Iref(n) < Iref(n - 1) < Iref(n - 2) < Iref(n - 3). The multiplexer 305 sequentially outputs Iref(n - 3), Iref(n - 2), Iref(n - 1), and Iref(n) to one terminal of a resistor, and the current signal converted from Comp_out2 is input to the other terminal of the resistor, which is equivalent to converting the current signal into a voltage signal and then superimposing the voltage signal on Comp_out2. The voltage signal superimposed on Comp_out2 is input to the positive input terminal of the fourth comparator 401. Vcs is input to the negative input terminal of the fourth comparator 401. Since Iref(n) < Iref(n - 1) < Iref(n - 2) < Iref(n - 3), the voltage signal superimposed on Comp_out2 decreases, and Vcs gradually decreases so as to approach the value of the superimposed voltage.

[0097]

[0112] Embodiment 8

[0098]

[0113] Referring to FIG. 12, in this embodiment, a system for controlling the skip mode of a switching power supply further includes a first low-frequency signal generator 501. The first low-frequency signal generator 501 is connected to the output terminal of the feedback signal detection circuit 10. The low-frequency signal output by the first low-frequency signal generator 501 is superimposed on the signal output by the feedback signal detection circuit 10 and then input to the positive input terminal of the first comparator 301, the positive input terminal of the second comparator 302, and the positive input terminal of the third comparator 303.

[0099]

[0114] The low-frequency signal output by the first low-frequency signal generator 501 may be a triangular wave, a sine wave, a sawtooth wave, etc. A pulse is embedded in the envelope of the low-frequency signal to achieve a good effect. Taking the low-frequency signal as an example, which is a triangular wave, the combination of the pulse and the low-frequency signal has the following three cases: In the first case, both the upward soft ipeak and the downward soft ipeak are included in each cluster of the low-frequency signal and the pulse (as shown in FIG. 13); In the second case, only the upward soft ipeak is included in each cluster of the low-frequency signal and the pulse (as shown in FIG. 14); In the third case, only the downward soft ipeak is included in each cluster of the low-frequency signal and the pulse. T_low frequency in FIG. 13 and FIG. 14 indicates the frequency.

[0100]

[0115] EMBODIMENT 9

[0101]

[0116] 15, in this embodiment, the system for controlling the skip mode of a switching power supply further includes a second low-frequency signal generator 502. The second low-frequency signal generator 502 is connected to an input terminal of a feedback signal detection circuit 10. The low-frequency signal output by the second low-frequency signal generator 502 is superimposed on the signal input to the feedback signal detection circuit 10.

[0102]

[0117] The low-frequency signal output by the second low-frequency signal generator 502 may be a triangular wave, a sine wave, a sawtooth wave, etc. Taking the low-frequency signal as an example, the combination of the pulse and the low-frequency signal has the following three cases: In the first case, both the upward soft ipeak and the downward soft ipeak are included in each cluster of the low-frequency signal and the pulse (as shown in FIG. 13); In the second case, only the upward soft ipeak is included in each cluster of the low-frequency signal and the pulse (as shown in FIG. 14); In the third case, only the downward soft ipeak is included in each cluster of the low-frequency signal and the pulse.

[0103]

[0118] EMBODIMENT 10

[0104]

[0119] 16, in this embodiment, the system for controlling the skip mode of a switching power supply further includes a third low-frequency signal generator 503. The third low-frequency signal generator 503 is connected to the output terminal of the compensator. The low-frequency signal output by the third low-frequency signal generator 503 is superimposed with the signal output by the compensator.

[0105]

[0120] The low-frequency signal output by the third low-frequency signal generator 503 may be a triangular wave, a sine wave, a sawtooth wave, etc. Taking the low-frequency signal as an example, the combination of the pulse and the low-frequency signal has the following three cases: In the first case, both the upward soft ipeak and the downward soft ipeak are included in each cluster of the low-frequency signal and the pulse (as shown in FIG. 13); In the second case, only the upward soft ipeak is included in each cluster of the low-frequency signal and the pulse (as shown in FIG. 14); In the third case, only the downward soft ipeak is included in each cluster of the low-frequency signal and the pulse.

[0106]

[0121] According to the present disclosure, a PWM controller is further provided. The PWM controller includes the system for controlling the skip mode of the switching power supply according to any of the above embodiments. The PWM controller according to the present disclosure is not described in detail here, and the above embodiments are referred to.

[0107]

[0122] The embodiments in the present disclosure are described in a progressive manner, and each embodiment emphasizes the differences from other embodiments, and the same or similar parts among the embodiments can be referred to each other. The description of the apparatus, device, and computer-readable storage medium disclosed in the embodiments is simplified to correspond to the method disclosed in the embodiments, and the description of the method can be referred to for related descriptions.

[0108]

[0123] Furthermore, those skilled in the art should note that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented by electronic hardware, computer software, or a combination thereof. In order to clearly show that both hardware and software are possible, the above description generally describes the steps and elements of each embodiment in terms of their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use various methods to implement the above-mentioned functions for each specific application, and such implementations should not be considered as departing from the scope of the present disclosure.

[0109]

[0124] The steps of the method or algorithm described in the embodiments of this specification may be directly implemented by hardware, a software module executed by a processor, or a combination of both. The software module may be stored in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hardware disk, a removable magnetic disk, a CD-ROM, or any other form of storage medium known in the art.

[0110]

[0125] Above, the system and PWM control device for controlling the skip mode of a switching power supply according to the present disclosure have been described in detail. The principles and embodiments of the present disclosure are described herein by specific examples. The above description of the embodiments is merely used to facilitate the understanding of the method and concept of the present disclosure. It should be noted that improvements and modifications to the present disclosure are possible for those skilled in the art without departing from the concept of the present disclosure. Such improvements and modifications are intended to fall within the technical scope of the claims of the present disclosure.

Claims

1. 1. A system for controlling a skip mode of a switching power supply, comprising: a feedback signal detection circuit configured to detect an output voltage of the switching power supply and generate a feedback signal related to the output voltage; a primary winding sampling circuit coupled to a primary winding of the switching power supply and configured to obtain a sampled voltage of the primary winding; a skip mode soft control circuit configured to receive the feedback signal and output an electrical signal; a comparison circuit configured to determine a threshold value for the sampled voltage based on the electrical signal and the sampled voltage; Equipped with The skip mode is activated when the feedback signal is greater than a soft start voltage threshold, and the skip mode is terminated when the feedback signal is less than a predetermined voltage threshold and greater than a soft exit voltage threshold.

2. the skip mode soft control circuit comprises a first comparator, a second comparator, a third comparator, a controller, and a multiplexer; the first comparator is configured to compare the feedback signal to the soft-start voltage threshold; the second comparator is configured to compare the feedback signal with the predetermined voltage threshold; the third comparator configured to compare the feedback signal to the soft-end voltage threshold; The controller is configured to control the multiplexer to output a first predetermined number of electrical signals when the feedback signal is greater than the soft-start voltage threshold, the comparison circuit outputs the first predetermined number of threshold values, the first predetermined number of threshold values ​​increasing sequentially; 2. The system of claim 1, wherein the controller is configured to control the multiplexer to output a second predetermined number of electrical signals when the feedback signal is less than the predetermined voltage threshold and greater than the soft-termination voltage threshold, and the comparison circuit outputs the second predetermined number of threshold values, the second predetermined number of threshold values ​​sequentially decreasing.

3. 2. The system of claim 1, wherein the threshold of the sampling voltage is equal to the feedback signal when the feedback signal is less than the soft-start voltage threshold and greater than the predetermined voltage threshold.

4. 2. The system of claim 1, wherein when the feedback signal is less than the soft-termination voltage threshold, the threshold of the sampling voltage is equal to the feedback signal.

5. 2. The system of claim 1, wherein the voltage signal output by the skip mode soft control circuit is input to a first terminal of the comparison circuit, and the sampling voltage is input to a second terminal of the comparison circuit.

6. 2. The system of claim 1, wherein the feedback signal is input to a first terminal of the comparison circuit, and a superposition of the voltage signal output by the skip mode soft control circuit and the sampling voltage is input to a second terminal of the comparison circuit.

7. 2. The system of claim 1, wherein a superposition of a voltage signal output by the skip mode soft control circuit and the feedback signal is input to a first terminal of the comparison circuit, and the sampling voltage is input to a second terminal of the comparison circuit.

8. 2. The system of claim 1, wherein a voltage signal converted from the current signal output by the skip mode soft control circuit is input to a first terminal of the comparison circuit, and the sampling voltage is input to a second terminal of the comparison circuit.

9. 2. The system of claim 1, wherein the feedback signal is input to a first terminal of the comparison circuit, and a superposition of a voltage signal converted from a current signal output by the skip mode soft control circuit and the sampling voltage is input to a second terminal of the comparison circuit.

10. 2. The system of claim 1, wherein a superposition of a voltage signal converted from a current signal output by the skip mode soft control circuit and the feedback signal is input to a first terminal of the comparison circuit, and the sampling voltage is input to a second terminal of the comparison circuit.

11. 2. The system of claim 1, wherein the comparison circuit comprises a fourth comparator, a positive input terminal of the fourth comparator serving as a first terminal of the comparison circuit, a negative input terminal of the fourth comparator serving as a second terminal of the comparison circuit, and an output terminal of the fourth comparator serving as an output terminal of the comparison circuit.

12. 3. The system of claim 2, wherein a signal terminal of the multiplexer is connected to an output terminal of the feedback signal detection circuit, and the multiplexer outputs the feedback signal when the feedback signal is less than the soft-start voltage threshold and greater than the predetermined voltage threshold.

13. 3. The system of claim 2, wherein a signal terminal of the multiplexer is not connected to an output terminal of the feedback signal detection circuit, and the multiplexer continuously outputs a voltage equal to 0 or a current equal to 0 when the feedback signal is less than the soft-start voltage threshold and greater than the predetermined voltage threshold.

14. a first low-frequency signal generator configured to output a low-frequency signal to be superimposed with the signal output by the feedback signal detection circuit; The system of claim 1 further comprising:

15. a second low frequency signal generator configured to output a low frequency signal to be superimposed with the signal input to the feedback signal detection circuit; The system of claim 1 further comprising:

16. a third low frequency signal generator configured to output a low frequency signal to be superimposed with the signal output by the primary winding sampling circuit; The system of claim 1 further comprising:

17. A PWM controller comprising a system according to any one of claims 1 to 16 for controlling the skip mode of a switching power supply.

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