Silicon Etching with Organic Chlorides

Abstract

A method is provided for etching recessed features in a stack having a silicon-containing layer overlying a wafer on a substrate support. The substrate support is maintained at a temperature of less than about 30° C. Carbon tetrachloride (CCl4), C x H y Cl z (where x>0 and z>0), and combinations thereof. The etching gas is formed into a plasma. The stack is exposed to the plasma to etch recessed features into the stack.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of priority to U.S. Patent Application No. 63 / 279,901, filed November 16, 2021, which is incorporated herein by reference for all purposes. [Background technology]

[0002] One process frequently employed during the fabrication of semiconductor devices is the formation of cylinders or other recessed features etched into silicon-containing materials. The silicon-containing materials may be alternating / repeating layers in which the recessed features are formed. One exemplary context in which such processes are performed is in memory applications such as NAND. As the semiconductor industry advances and device dimensions become smaller, such recessed features become increasingly difficult to etch in a uniform manner, especially for high aspect ratio features having narrow widths and / or large depths.

[0003] The background discussion provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within the scope of what is described in this background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004] To achieve the above, and in accordance with the objectives of the present disclosure, a method is provided for etching recessed features in a stack having a silicon-containing layer overlying a wafer on a substrate support. The substrate support is maintained at a temperature of less than about 30° C. Carbon tetrachloride (CCl4), C x H y Cl zAn etching gas is flowed that includes an organic chloride source selected from the group consisting of: (where x>0 and z>0), a carbon source, a fluorine source, and a hydrogen source. The etching gas is formed into a plasma. The stack is exposed to the plasma to etch recessed features into the stack.

[0005] These and other features of the present disclosure are described in further detail below in conjunction with the detailed description and the following drawings. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 shows a flow chart illustrating a method for etching a recessed feature in a stack containing dielectric materials, according to various embodiments.

[0007] [Figure 2A] FIG. 2A shows a schematic cross-sectional view of a stack processed according to some embodiments. [Figure 2B] FIG. 2B shows a schematic cross-sectional view of a stack processed according to some embodiments.

[0008] [Diagram 3] FIG. 3 illustrates a reaction chamber that can be used to carry out the techniques described herein according to certain embodiments.

[0009] [Figure 4] FIG. 4 illustrates a computer system implementing a controller used in an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present disclosure will now be described in detail with reference to several preferred embodiments thereof, as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures have not been described in detail in order not to unnecessarily obscure the present disclosure.

[0011] The fabrication of certain semiconductor devices involves etching features in a stack of materials using a plasma-based etch process. In various embodiments herein, the stack of materials includes alternating / repeating layers of dielectric materials. Often, at least one of the layers in the stack is or includes a silicon-containing layer. The silicon-containing layer may contain silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, polysilicon, or silicon germanium. In one example, the stack includes alternating layers of silicon oxide and polysilicon.

[0012] The features etched in silicon-containing materials may be cylinders, trenches, or other concave features. The aspect ratio of such features is defined as the lateral critical dimension divided by the depth. As the aspect ratio of such features continues to increase, several problems arise, including: (1) twisting of the features, (2) non-circularity of the features, (3) aspect ratio dependence of the etch rate, (4) bowing of the etch profile, (5) poor mask selectivity, and (6) low etch rate. A twist refers to an irregular deviation between the intended bottom position of the feature and the actual final bottom position (e.g., the final position of the feature corresponds to the bottom position of the feature after the feature is etched). For example, in some cases, cylindrical features are intended to be etched in a regular array. If some or all of the features deviate irregularly at the bottom from this array, they are understood to have a twist.

[0013] Non-circularity of a feature refers to the deviation of the bottom hole shape from a circular hole shape. This problem is relevant when etching circular features such as cylinders, where it is desired that the bottom of the concave feature be circular. When the bottom hole shape deviates from circular, it is often formed into a shape that more closely resembles an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are undesirable.

[0014] The aspect ratio dependence of etch rate refers to the problem that as the aspect ratio of a feature increases, the etch rate decreases. In other words, the further a feature is etched into the dielectric material, the slower the etch process becomes. This problem is problematic because it leads to lower throughput and a corresponding increase in processing costs.

[0015] Bowing of an etch profile refers to the tendency of a feature to be etched laterally in a dielectric layer such that the final profile bows outward excessively somewhere along the depth of the feature, in other words, the actual maximum critical dimension of the feature may exceed the desired maximum critical dimension of the feature, compromising the integrity of the structure being formed or limiting the electrical performance of the final device.

[0016] Poor mask selectivity is a problem when an etch process removes too much of the mask, leaving no mask at the end of the process, or when the amount of mask that remains is insufficient to adequately transfer the pattern from the mask to one or more dielectric films.Poor mask selectivity often results in poor feature profile near the top of recessed features.

[0017] A low etch rate refers to an etch rate that is slower than desired for a particular application. A low etch rate is problematic because it increases etch times, reduces throughput, and increases processing costs.

[0018] Unfortunately, techniques that improve some of these problems often exacerbate others. As a result, these problems are balanced against one another when designing etch operations. For example, conventional commercial dielectric etch processes often result in substantial bowing. Low temperature etch processes have been recently developed to address the bowing problems associated with conventional commercial dielectric etch processes. Such low temperature processes may be performed while the substrate support is cooled to a temperature below about 25° C. Advantageously, low temperature processes result in relatively high etch rates and relatively reduced bowing. However, these low temperature processes substantially exacerbate problems related to twisting and non-circularity of features. Until now, such trade-offs have been difficult to avoid.

[0019] The techniques described herein may be used to etch recessed features in dielectric materials without some or all of the problems identified above. In other words, the techniques of the present disclosure may be used to etch recessed features in dielectric materials with little or no twisting, features that are reasonably circular, have acceptable aspect ratio dependence of etch rate, acceptable bowing, sufficient mask selectivity, and sufficient etch rate.

[0020] In various embodiments herein, a particular set of reactants is used. The reactants include an organic chloride source, a carbon source, a fluorine source, and a hydrogen source. Exemplary organic chloride sources include carbon tetrachloride (CCl4), and hydrochlorocarbons (C x H y Cl z ) (where x>0 and z>0). x H y Cl z Specific examples of materials include, but are not limited to, chloroform (CHCl3) and methylene chloride (CH2Cl2).y Cl z may be used. In various embodiments, the organic chloride source does not contain fluorine or other non-chlorine halogens.

[0021] Examples of carbon sources include fluorocarbons (C x F y )(where y ≧ x), and hydrofluorocarbons C x H y F z (where z > 0) or (CH x F y )(where 0 < x < 4 and x + y = 4), but are not limited thereto. Examples of fluorine sources include CH x F y (where 0 < x < 4 and x + y = 4), C x F y (where y ≧ x), C x H y F z (where z > 0), and nitrogen trifluoride (NF3), but are not limited thereto. Examples of hydrogen sources include hydrogen (H2), CH x F y (where 1 < x ≦ 4 and x + y = 4), C x H y (such as methane (CH4)), and C x H y F z (where z > 0), but are not limited thereto. In some embodiments, the reactants may further include one or more non-fluorine halogen sources. Examples thereof include chlorine (Cl2), hydrogen bromide (HBr), iodine (I2), and trifluoroiodomethane (CF3I), but are not limited thereto. The organic chloride source, like the carbon source, acts in combination with reactants that generate a large amount of H radicals and F radicals, resulting in the excellent etching results described herein.

[0022] In some embodiments, the reactants are CH2Cl2, H2, NF3, and CH x F y(Here, 0 < x ≤ 4, and x + y = 4) is included. In some embodiments, the reactants include at least one of CH2Cl2, H2, NF3, difluoromethane (CH2F2), carbon tetrafluoride (CF4), and hydrogen bromide (HBr) and trifluoroiodomethane (CF3I). Various other combinations of reactants are possible and are considered to be within the scope of the embodiments of the present disclosure.)

[0023] The substrate may be maintained at a low temperature during etching. This temperature control can be achieved by controlling the temperature of the substrate support on which the substrate is positioned during etching. In certain embodiments, the substrate support is maintained at a temperature of less than about 25°C, or less than about 0°C, or less than about -40°C, or less than about -55°C, or less than about -60°C. In some cases, the substrate support may be maintained at about -80°C, or in some cases even lower temperatures. In some embodiments, the substrate support may be maintained at a temperature between about -80°C and -40°C. By operating at a relatively low etching temperature, advantages associated with low-temperature etching can be obtained, such as low boiling, a relatively high etching rate, and an aspect ratio dependence of the etching rate that is low. Advantageously, by including an organochloride gas as a reactant, the etching selectivity to the mask can be increased without giving a large trade-off to other important process metrics.)

[0024] One application of the method of the present disclosure is in the context of forming a vertical NAND device. In this case, the material in which the features are etched may have a repeating layer structure. For example, the material may include alternating layers of silicon oxide and polysilicon. The alternating layers form pairs or groups of repeats of the material. In various cases, the number of pairs or groups of repeats may be between about 10 and 500 (e.g., about 20 to 1000 individual layers). The features etched within the stack of layers may have a depth between about 2 and 15 μm, for example between about 5 and 9 μm. The features may have a width between about 40 and 450 nm, for example between about 50 and 100 nm.)

[0025] As used herein, "high aspect ratio" as applied to features in a substrate refers to aspect ratios such as about 30:1 or greater. More preferably, the range may include ratios greater than or equal to 40:1, 50:1, 60:1, 70:1, 80:1, etc., although the processes described herein may be beneficial for lower aspect ratios such as 20:1, or 10:1.

[0026] There are many types of mask layers that can be used with the described embodiments and would include any layer known in the art that can function as an etch mask. For example, the mask may be a carbon hard mask, such as amorphous carbon. In other embodiments, the mask may be doped carbon.

[0027] The dimensional / parametric details provided herein, such as height, aspect ratio, thickness, width, depth, etc., are for illustrative and explanation purposes only, and it is to be understood that various dimensions / parameters may also be applied or used based on the disclosure set forth herein.

[0028] FIG. 1 is a flow chart illustrating a method of etching a stack according to various embodiments herein. A stack having a silicon-containing layer and a mask overlying a substrate is received in a process chamber (step 104). FIG. 2A is a schematic cross-sectional view of a stack 204 that may be processed according to an embodiment. In this embodiment, the stack 204 may be formed over a substrate 208. One or more layers may be disposed between the stack 204 and the substrate 208. In this embodiment, the stack 204 is a multiple bilayer having a layer of silicon oxide (SiO2) 216 overlaid on top of a layer of polysilicon (Si) 212. A mask 220 having mask features 222 may be formed over the stack 204. In this embodiment, the mask 220 is a carbon-containing mask, such as an organic mask, an example of which may be an amorphous carbon mask. The amorphous carbon mask may also contain some hydrogen and / or oxygen.

[0029] Next, an etching gas is supplied (step 108). The etching gas includes an organic chloride source, a carbon source, a fluorine source, and a hydrogen source, as further described below. The etching gas may also include one or more inert gases. In one example, the etching gas is 1 to 100 sccm of (C x H y Cl z )(where x > 0 and z > 0) (i.e., chloromethane (CH3Cl) or dichloromethane (CH2Cl2)), 0 to 100 sccm of CH4, 10 to 500 sccm of H2, 5 to 100 sccm of NF3, 0 to 25 sccm of CF3I, 0 to 80 sccm of Kr, 0 to 100 sccm of CH x F y (where 0 < x ≦ 4 and x + y = 4) (i.e., fluoromethane (CH3F), octafluorocyclobutane (C4F8), and CF4), and 0 to 50 sccm of sulfur hexafluoride (SF6). Additional gases may be added. In other embodiments, some of these gases may be removed or replaced with other gases. The substrate support is maintained at a temperature in the range of about -80°C to 150°C. The chamber pressure is maintained at a pressure of about 5 to 400 millitorr (mT).

[0030] The etching gas is converted into a plasma (step 112). In this embodiment, pulsed RF power is provided at different frequencies and power ranges. For example, during a first stage, 400 kilohertz (kHz) RF power may be provided at a power in the range of 0-1500 watts (W) and 60 megahertz (MHz) RF power may be provided at a power in the range of 0-1000 W. During a second stage, 400 kHz RF power may be provided at a power in the range of 1000-50000 W and 60 MHz RF power may be provided at a power in the range of 500-15000 W. The pulsing duty cycle between the first and second stages may be in the range of 5-60%. The pulses may have a repetition rate in the range of 100 Hz to 20 kHz. Often, the plasma is a capacitively coupled plasma. In various embodiments, the plasma may be generated with radio frequency (RF) power between about 5-200 kilowatts (kW), for example, between about 1-100 kW, or between about 10-100 kW, or in some embodiments, between about 10-65 kW. In some cases, dual frequency RF may be used to generate the plasma. Thus, RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For example, the first frequency component (e.g., about 400 kHz) may be provided with a power between about 10-40 kW, and the second frequency component (e.g., about 60 MHz) may be provided with a different power, for example, between about 0.5-8 kW. These power levels assume that the RF power is provided to a single 300 millimeter (mm) wafer. The power level may be linearly scalable based on the substrate area for additional substrates and / or substrates of other sizes (to maintain a uniform power density delivered to the substrate). In other cases, a triple frequency RF power may be used to generate the plasma. In some cases, the applied RF power may be pulsed at a repetition rate of 1-50,000 Hz. The RF power may be pulsed between two non-zero values ​​(e.g., between a higher and a lower power state) or between a zero value and a non-zero value (e.g., between an off state and an on state).When the RF power is pulsed between two non-zero values, the powers mentioned above relate to higher power states, and the lower power states may correspond to RF powers of about 4 kW or less. The maximum ion energy at the substrate may be relatively high, for example, between about 1-10 kilovolts (kV). The maximum ion energy is determined by the applied RF power in combination with the RF excitation frequency, electrode size, electrode arrangement, chamber geometry, and plasma interaction details.

[0031] Exposing the stack 204 to a plasma etches features in the stack. In some cases, the substrate may be exposed to the plasma for a duration between about 2000-3000 seconds (s). In some cases, process parameters such as power, pressure, and gas flows are adjusted in a series of recipe steps. The patterned mask layer protects the underlying stack material where the patterned mask layer is present. This ensures that recessed features are formed at the patterned openings in the mask layer that are desired for the recessed features.

[0032] FIG. 2B is a schematic cross-sectional view of the stack 204 after being processed according to an embodiment. A plasma is used to etch a feature 224 in the stack 204. In this embodiment, the plasma was able to etch through the stack 204 to the substrate 208. Bowing is indicated by an increase in the width of the feature, where the width at the top of the feature and the width at the bottom of the feature are smaller than the width where the bowing is present. In this embodiment, some bowing may occur, but in this embodiment, the width 228 of the bowing (bow CD) is reduced. This embodiment can etch different silicon-containing layers, such as polysilicon, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, and silicon nitride. As a result, high aspect ratio features with reduced bowing can be obtained. As used herein, CD refers to the critical dimension of a feature at a particular location within the feature (e.g., the width in a direction parallel to the surface of the substrate). The "bow CD - bottom CD" is defined as the difference between the maximum critical dimension width 248 of the feature and the critical dimension at the bottom of the feature. Embodiments can provide a bow CD minus bottom CD of less than 20 nm. Another metric may use the ratio of bow CD / bottom CD.

[0033] Additionally, the present embodiments provide improved selectivity. Selectivity refers to the ratio of the etch rate of the material to be removed to the etch rate of the mask material. The present embodiments can selectively etch silicon-containing layers relative to the carbon-containing mask. In some embodiments, the silicon-containing layers are selectively etched relative to the hard mask, allowing for significant improvements in selectivity of ≧10% without significant tradeoffs in other important process metrics. For a stack of alternating layers of silicon oxide and polysilicon, the embodiments provide an etch selectivity ratio of at least 3:1 for the stack relative to the etch of the carbon mask.

[0034] Ellipticity describes the degree to which the bottom of a cylindrical feature deviates from a perfect circle toward an ellipse, and is calculated as the ratio of the length of the minor axis to the length of the major axis of the ellipse that fits the bottom hole shape. A perfect circle feature has an ellipticity of 1.0. Since circular features are often desired (e.g., when etching a cylinder), an ellipticity close to 1.0 is preferred. In various embodiments, mask features with a circular cross section will result in features with an average ellipticity in the range of 1.0 to 1.1.

[0035] Torsion refers to the degree to which a feature deviates from the desired array pattern. The torsion reported herein is the standard deviation of the distance between the holes at the bottom of the feature multiplied by 3. Since tortion is not a desirable feature, it is preferable to have as little tortion as possible. Some embodiments provide tortion of less than 15 nm. Device

[0036] The various hardware and method embodiments described above can be used in conjunction with lithographic patterning tools or processes, for example, for the creation or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, although not necessarily, such tools / processes will be used or performed together in a common fabrication facility.

[0037] Lithographic patterning of a film typically includes some or all of the following steps, each of which may be accomplished with multiple available tools: (1) applying a photoresist onto a workpiece, e.g., a substrate having a silicon-containing film formed thereon, using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or ultraviolet (UV) or X-ray light using a tool such as a wafer stepper; (4) developing the resist to selectively remove and thereby pattern the resist using a tool such as a wet bench or spray developer; (5) transferring the resist pattern to the underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashing hardmask layer (e.g., an amorphous carbon layer) and another suitable hardmask (e.g., an antireflective layer) may be deposited prior to applying the photoresist.

[0038] In this application, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will appreciate that the term "partially fabricated integrated circuit" may refer to a silicon wafer during any of the many stages on which an integrated circuit is fabricated. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, 300 mm, or 450 mm. The above detailed description assumes that the embodiments are implemented on a wafer. However, the embodiments are not so limited. Workpieces may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize embodiments of the present disclosure include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0039] Unless otherwise defined for a particular parameter, the terms "about" and "approximately" as used herein are intended to mean ±10% relative to the associated value.

[0040] 3 is a schematic diagram of a plasma processing chamber 300 for plasma processing a substrate, in an embodiment. In one or more embodiments, the plasma processing chamber 300 includes a gas distribution plate 306 that provides a gas inlet and an electrostatic chuck (ESC) 316 in a plasma processing chamber 304, surrounded by a chamber wall 350. In the plasma processing chamber 304, the substrate 208 is positioned on top of the ESC 316. The ESC 316 may provide a bias from an ESC power supply 348. A gas source 310 is connected to the plasma processing chamber 304 through the gas distribution plate 306. An ESC temperature controller 351 is connected to the ESC 316 and provides temperature control of the ESC 316. A radio frequency (RF) power supply 330 provides RF power to the ESC 316 and the upper electrode. In this embodiment, the upper electrode is the gas distribution plate 306. In a preferred embodiment, 400 kilohertz (kHz), 13.56 megahertz (MHz), 1 MHz, 2 MHz, 60 MHz, and / or optionally 27 MHz power sources constitute the RF power source 330 and the ESC power source 348. A controller 335 is controllably connected to the RF power source 330, the ESC power source 348, the exhaust pump 320, and the gas source 310. The high flow liner 360 is a liner in the plasma processing chamber 304 that confines gas from the gas source and has slots 362. The slots 362 maintain a controlled flow of gas passing from the gas source 310 to the exhaust pump 320. An example of such a plasma processing chamber is the Flex® Etch system manufactured by Lam Research, Inc., Fremont, Calif. The processing chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0041] 4 is a high-level block diagram illustrating a computer system 400 implementing a controller 535 used in an embodiment of the present invention. Computer systems may have many physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to huge supercomputers. The computer system 400 may include one or more processors 402 and may further include an electronic display device 404 (for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), a storage device 408 (e.g., a hard disk drive), a removable storage device 410 (e.g., an optical disk drive), a user interface device 412 (e.g., a keyboard, touch screen, keypad, mouse, or other pointing device, etc.), and / or a communication interface 414 (e.g., a wireless network interface). The communication interface 414 allows software and / or data to be transferred between the computer system 400 and external devices via a link. The system may also include a communication infrastructure 416 (e.g., a communication bus, crossover bar, or network) to which the aforementioned devices / modules may be connected.

[0042] Information transferred through communications interface 414 may be in the form of signals, such as electronic, electromagnetic, optical, or other signals receivable by communications interface 414 over a communications link that carries the signals, and may be implemented using wire or cable, fiber optics, telephone lines, cellular phone links, radio frequency links, and / or other communications channels. It is contemplated that such communications interfaces may cause one or more processors 402 to receive information from a network or output information to a network in the course of performing the method steps described above. Additionally, method embodiments may be performed solely by the processor or may be performed over a network, such as the Internet, in conjunction with a remote processor that shares some of the processing.

[0043] The term "non-transient computer-readable medium" is generally used to refer to media such as storage devices, including main memory, secondary memory, removable storage devices, and hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and is not to be construed to cover transitory subject matter, such as transmitted waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing high-level code that are executed by a computer using an interpreter. A computer-readable medium may also be computer code embodied in transmitted waves and transmitted by a computer data signal representing a sequence of instructions executable by a processor.

[0044] It is to be understood that the configurations and / or approaches described herein are exemplary in nature, and numerous variations are possible, and therefore the specific embodiments or examples are not to be construed in a limiting sense. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, the various operations illustrated may be performed in the order illustrated, in other orders, in parallel, or in some cases omitted. Similarly, the order of the processes described above may be changed. Certain references are incorporated herein by reference. It is understood that any disclaimers or disclaimers made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described in such references as necessary may be omitted in the embodiments herein. The subject matter of the present disclosure includes novel and non-obvious combinations and subcombinations of the various processes, systems, and configurations disclosed herein, as well as other features, functions, acts, and / or properties, and any and all equivalents thereof.

[0045] conclusion Although the present disclosure has been described in terms of several preferred embodiments, there are changes, modifications, permutations, and various substitute equivalents that fall within the scope of the present disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. Therefore, the following appended claims are intended to be interpreted as including all such changes, modifications, permutations, and various substitute equivalents that fall within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be interpreted as meaning a logic ("A or B or C") using a non-exclusive logical "OR", and not as meaning "only one of A or B or C". Each step in a process may be an optional step and is not required. Different embodiments may eliminate one or more steps or provide steps in a different order. Furthermore, various embodiments may provide different steps simultaneously rather than sequentially.

Claims

1. 1. A method of etching a recessed feature in a stack having a silicon-containing layer overlying a wafer on a substrate support, the method comprising: a. maintaining the substrate support at a temperature less than about 30° C.; b. flowing an etching gas, the etching gas comprising: i. Carbon tetrachloride (CCl 4 ), C x H y C z where x>0 and z>0, and combinations thereof; ii. a carbon source; iii. a fluorine source; iv. a hydrogen source; and c. forming the etching gas into a plasma; d. exposing the stack to the plasma to etch recessed features in the stack; A method comprising:

2. 2. The method of claim 1 , The method, wherein the stack comprises alternating layers of silicon oxide and polysilicon.

3. 2. The method of claim 1 , The method wherein the substrate support is maintained at a temperature of less than about -40°C by maintaining the substrate support at a temperature of less than about 30°C.

4. 2. The method of claim 1 , The method, wherein the substrate support is maintained at a temperature of less than about -55°C by maintaining the substrate support at a temperature of less than about 30°C.

5. 2. The method of claim 1 , The method, wherein the plasma is a capacitively coupled plasma generated at an RF power of between about 1-100 kW.

6. 2. The method of claim 1 , The hydrogen source is H 2 , C.H. x F y (where 1<x≦4 and x+y=4), C x H y F z (where x>0 and z>0), C x H y and combinations thereof.

7. 2. The method of claim 1 , The hydrogen source is H 2 A method comprising:

8. 2. The method of claim 1 , The fluorine source is NF 3 , C.H. x F y (where 0<x<3 and x+y=4), C x F y (where y ≧ x), C x H y F z (wherein z>0), and combinations thereof.

9. 2. The method of claim 1 , The carbon source is CH x F y (where 0<x<4 and x+y=4), C x F y (where y ≧ x), C x H y F z (wherein x>0 and z>0), and combinations thereof.

10. 2. The method of claim 1 , The organic chloride source is CH 2 C 2 or CH 3 The method is Cl.

11. 2. The method of claim 1 , The method of claim 1, wherein the silicon-containing layer comprises at least one of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, polysilicon, or silicon germanium.

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