Wide-area heater for phase-change memory

Abstract

An embodiment of the present invention includes a phase change memory (PCM) array. The PCM array may include a plurality of PCM cells. Each PCM cell of the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a large area heater surrounding the plurality of PCM cells, the large area heater having a thermally conductive material in contact with each of the plurality of PCM cells. The large area heater may be configured to receive an electrical signal to heat the plurality of PCM cells simultaneously.

Description

[Technical field]

[0001] The present invention relates generally to the field of integrated circuits (i.e. computer chips, or simply chips), and more particularly to providing a large area heater for reducing the threshold voltage of phase change memories. [Background technology]

[0002] Phase-change memory (PCM) is a type of non-volatile random access memory. PCM cells utilize a chalcogenide glass as the resistive element between electrodes. In operation, a current is passed through the heating element of each PCM cell, heating the glass. The glass is then quenched or held at a temperature range for a period of time. Quenching the glass places the resistive element in an amorphous state with a certain resistance, while holding the glass within a temperature range places the resistive element in a crystalline state with a different resistance. PCM cells can also be heated and cooled to achieve different intermediate states, allowing multiple bits to be held in a single cell, although the difficulty of programming the cell in this way has meant that this capability has not been implemented in other technologies with the same capabilities. Summary of the Invention

[0003] According to one aspect of the present invention, a phase change memory (PCM) array is provided. The PCM array may include a plurality of PCM cells. Each PCM cell of the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a large area heater surrounding the plurality of PCM cells, the large area heater having a thermally conductive material in contact with each of the plurality of PCM cells. The large area heater may be configured to receive an electrical signal to heat the plurality of PCM cells simultaneously.

[0004] According to another aspect of the invention, there is provided a method of forming a phase change memory array. The method may include forming a plurality of phase change memory (PCM) cells. Each PCM cell of the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The method may also include forming a global heater having a thermally conductive material surrounding the plurality of PCM cells. The global heater may be configured to receive an electrical signal to simultaneously heat the plurality of PCM cells.

[0005] An embodiment of the invention may also include a method that may include signaling a global heater to heat a phase change memory (PCM) array, storing machine learning values ​​in the PCM array by propagating a signal through PCM cells of the PCM array to change resistances of the PCM cells, signaling the global heater to stop heating the PCM array, and inferring the PCM array. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional side view of a semiconductor structure 100, in accordance with one embodiment of the present invention. [Diagram 2] 1 is a flowchart of a workflow for using PCM arrays in training machine learning (ML) algorithms. [Diagram 3] 1 is a cross-sectional side view of a semiconductor structure, according to one embodiment of the present invention. [Figure 4] 4 is a cross-sectional side view of the semiconductor structure of FIG. 3 at a subsequent fabrication stage in accordance with one embodiment of the present invention. [Diagram 5] 4 is a cross-sectional side view of the semiconductor structure of FIG. 3 at a subsequent fabrication stage in accordance with one embodiment of the present invention. [Figure 6] 4 is a cross-sectional side view of the semiconductor structure of FIG. 3 at a subsequent fabrication stage in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Various embodiments of the present disclosure are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of the present disclosure. It should be noted that in the following description and drawings, various connections and relationships between elements are described (e.g., over, below, adjacent, etc.). These connections and / or relationships may be direct or indirect unless otherwise stated, and the present disclosure is not intended to be limiting in this respect. Thus, the coupling of entities may refer to either direct or indirect coupling, and the relationship between entities may be direct or indirect. As an example of an indirect relationship, reference in this description to forming layer "A" on layer "B" includes the situation where one or more intermediate layers (e.g., layers "C" and "D") are between layers "A" and "B", so long as the relevant properties and functions of layers "A" and "B" are not substantially altered by the intermediate layers.

[0008] The following definitions and abbreviations are to be used for interpreting the claims and the specification. As used herein, the words "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to those elements and may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or device. Also, any numerical ranges contained herein include their limits unless expressly stated otherwise.

[0009] For purposes of the remainder of the description herein, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives refer to the structures and methods described as shown in the drawings. The terms "overlying", "atop", "on top", "positioned on" or "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, and that an intervening element, such as an interface structure, may be between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements. Note that the term "selective to", such as for example "a first element selective to a second element", means that the first element can be etched and the second element can act as an etch stop.

[0010] For the sake of brevity, conventional techniques for the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Additionally, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, because the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps are only briefly mentioned or omitted entirely herein without providing details of the well-known processes.

[0011] Generally, the various steps used to form the microchips that are packaged into ICs fall into four general categories: deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0012] Deposition can be any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), among others. Another deposition technique is plasma enhanced chemical vapor deposition (PECVD), a process that uses the energy in a plasma to induce reactions on the wafer surface that would otherwise require higher temperatures associated with traditional CVD. Additionally, high energy ion bombardment during PECVD deposition can improve the electrical and mechanical properties of the film.

[0013] Removal / etching can be any process that removes material from the wafer. Examples include etching processes (either wet or dry), chemical mechanical planarization (CMP), etc. One example of a removal process is ion beam etching (IBE). In general, IBE (or milling) refers to a dry plasma etching method that utilizes a remote broad beam ion / plasma source to remove substrate material by physical inert gas means or chemical reactive gas means or both. IBE, like other dry plasma etching techniques, has advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimal substrate damage. Another example of a dry removal process is reactive ion etching (RIE). In general, RIE uses a chemically reactive plasma to remove material deposited on the wafer. With RIE, the plasma is generated under low pressure (vacuum) by an electromagnetic field. High energy ions from the RIE plasma bombard and react with the wafer surface, removing the material.

[0014] Semiconductor doping can be, for example, the modification of electrical properties by doping transistor sources and drains, typically by diffusion or ion implantation or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. To connect and insulate the transistors and their components, films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be changed by the application of a voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of modern microelectronic devices.

[0015] The present invention will now be described in detail with reference to the drawings.

[0016] FIG. 1 is a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present invention. FIG. 1 merely provides an illustration of one implementation and does not imply any limitation regarding different embodiments that may be implemented. Those skilled in the art can make many modifications to the illustrated embodiment without departing from the scope of the invention as defined in the claims. The semiconductor structure 100 may include a phase change memory (PCM) array 102 having a plurality of PCM cells 104. Although only two PCM cells 104 (i.e., a first PCM cell 104a and a second PCM cell 104b) are shown in the illustrated embodiment, the PCM array 102 may include thousands or millions of PCM cells 104, for example, for use in machine learning. In the illustrated embodiment, the PCM cell 104 includes a bottom wire 106, bottom electrodes 108a, 108b, a substrate 110, an insulator 112, PCM material 114a, 114b, spacers 116a, 116b, a global heater 118, an interlayer dielectric (ILD) 120, top electrodes 122a, 122b, top wires 124a, 124b, and a heater wire 126.

[0017] In the illustrated embodiment, the bottom of the bottom electrode 108 is in direct contact with and electrically connected to the top of the bottom wire 106, which can receive electrical signals from other components of the integrated circuit (not shown). The bottom of the PCM material 114a, 114b is in direct contact with and electrically and thermally connected to the top of the bottom electrode 108a, 108b. The bottom of the top electrode 122a, 122b is in direct contact with and electrically and thermally connected to the top of the PCM material 114a, 114b. The bottom of the top wire 124a, 124b is in direct contact with and electrically connected to the top of the top electrode 122a, 122b, which can transmit electrical signals from the PCM cell 104a, 104b to other components of the semiconductor structure 100 (not shown).

[0018] In the illustrated embodiment, the spacers 116a, 116b are in direct contact with and laterally surround the outer surfaces of at least a portion of the PCM material 114a, 114b and the top electrodes 122a, 122b. Thus, the spacers 116 surround the PCM material 114a, 114b on all parallel sides in at least one direction (e.g., the vertically extending sides, as shown in FIG. 1). In some embodiments, the spacers 116a, 116b laterally surround all sides of the top electrode 122, while in other embodiments, the spacers 116a, 116b abut the top of the PCM material 114.

[0019] In the illustrated embodiment, the substrate 110, insulator 112, and ILD 120 selectively structurally support and electrically insulate the other components of the PCM cell 104, and optionally fill the spaces therebetween. Thus, the outer surfaces of the bottom electrodes 108a, 108b are in direct contact with and laterally surrounded by the insulator 112, and the outer surfaces of the bottom wires 106 are in direct contact with and laterally surrounded by the substrate 110. In the illustrated embodiment, the cross-section of the PCM cells 104a, 104b (i.e., looking down on the PCM cells 104a, 104b from above) may be circular, but in other embodiments may be rectangular, square, oval, or any other suitable shape.

[0020] In the illustrated embodiment, the substrate 110, the insulator 112, and the ILD 120 are made of a material such as silicon nitride (SiN), silicon oxide (SiO 2 ), nitride-bonded silicon carbide (SiNC), or tetraethyl orthosilicate (TEOS). In some embodiments, the substrate 110, insulator 112, and ILD 120 may all comprise the same material, while in other embodiments, different materials are used for some or all of the substrate 110, insulator 112, and ILD 120. Additionally, the spacers 116a, 116b may be made of, for example, aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), or aluminum oxynitride (AlO x N yThe GaN- ...

[0021] In the illustrated embodiment, the PCM material 114a, 114b consists essentially of a phase change material such as germanium-antimony-tellurium (GST), gallium-antimony-tellurium (GaST), or silver-iridium-antimony-telluride (AIST) material, although other materials may be used as appropriate. Examples of other PCM materials include, but are not limited to, germanium-tellurium composites (GeTe), silicon-antimony-tellurium (Si-Sb-Te) alloys, gallium-antimony-tellurium (Ga-Sb-Te) alloys, germanium-bismuth-tellurium (Ge-Bi-Te) alloys, indium-tellurium (In-Se) alloys, arsenic-antimony-tellurium (As-Sb-Te) alloys, silver-indium-antimony-tellurium (Ag-In-Sb-Te) alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, Ge-Te alloys, and combinations thereof. The PCM materials 114a, 114b may be undoped or doped (e.g., doped with one or more of oxygen (O), nitrogen (N), silicon (Si), carbon (C), or titanium (Ti)). The terms "consisting essentially of" and "consisting essentially of" as used herein with respect to materials of different layers indicate that the presence of other materials does not substantially change the basic properties of the described materials. For example, if the PCM materials 114a, 114b consist essentially of GST material, then the PCM materials 114a, 114b do not include other materials that significantly change the basic properties of the GST material.

[0022] In the illustrated embodiment, the bottom electrodes 108a, 108b, the global heater 118, and the top electrode 122 may comprise conductive materials such as metals or metal compounds. Examples may include titanium nitride (TiN) and tungsten (W). The bottom electrode 108 and the global heater 118 may comprise compounds of more resistive metals such as titanium tungsten (TiW), tantalum nitride (TaN), or titanium aluminide (TiAI). The bottom electrodes 108a, 108b may also be fabricated with a relatively narrow cross-sectional area 128 that concentrates the current flowing through the PCM cell 100. This allows the bottom electrodes 108a, 108b to generate heat through resistive heating during a pulse of electricity, which can be used to selectively change the temperature of the PCM material 114a, 114b, for example, above the crystallization and melting temperatures of the PCM material 114a, 114b. The bottom electrodes 108a, 108b may also include multiple different conductive materials, which may be arranged in multiple layers.

[0023] The global heater 118 may include a thermally conductive material that enhances the ability of the bottom electrodes 108a, 108b to globally heat the PCM array 102, thereby changing the temperature of the PCM material 114a, 114b. The global heater 118 receives a current through the global heater wire 126, which heats the insulator 112 and the spacers 116a, 116b due to the resistance of the metallic compound. The heating may be carefully controlled so that the PCM material 114a, 114b is heated to a temperature close to, but still below, the melting point of the PCM material 114a, 114b. Thus, the bottom electrodes 108a, 108b need only increase the temperature of the PCM material 114a, 114b by a few degrees, rather than heating it from room temperature to its melting point, which can be accomplished using a signal with a lower current. The lower current requirements mean that the PCM cells 104a, 104b can perform at faster processing speeds and with lower power consumption.

[0024] After the melting signal passes through the PCM cells 104a, 104b, the PCM material 114a, 114b cools and solidifies with a resistance that depends on the signal strength and the material properties of the PCM material 114a, 114b. The semiconductor structure 100 may utilize these resistances to operate the PCM cells 104a, 104b as memory cells, for example, by passing a current pulse from the bottom electrodes 108a, 108b to the top electrodes 122a, 122b to program the PCM cells 104a, 104b. To read or write values ​​to the PCM cells 104a, 104b, this can be done at different voltages, or for different durations, or both. For example, to write, a high voltage (e.g., 1 volt (V) to 4 V) can be used for a short duration, causing the bottom electrodes 108a, 108b to locally heat the PCM material 114a, 114b above its melting point. When the current flow stops, the PCM material 114 can be rapidly cooled, which forms amorphous regions in a process called a "reset operation." The creation of amorphous regions can increase the electrical resistance between the PCM cells 104a, 104b compared to a polycrystalline-only configuration. For example, by sending a current pulse at a low voltage (e.g., 0.2 V) from the bottom electrodes 108a, 108b to the top electrodes 122a, 122b, the resistance of the PCM cells 104a, 104b can be read without changing the state of the PCM material 114a, 114b or the resistance of the PCM cells 104a, 104b.

[0025] The PCM material 114a, 114b can also be reprogrammed back to a polycrystalline-only configuration by "setting" the PCM cells 104a, 104b. One method of reprogramming the PCM material 114a, 114b is to use a high voltage electrical pulse (e.g., 1V-4V) for a short period of time (e.g., 10 nanoseconds (ns)) to heat the PCM material 114a, 114b above its crystallization point but below its melting point. Because the crystallization temperature is lower than the melting temperature, when the current flow is stopped, the PCM material 114a, 114b can anneal to form crystals. Another method of rewriting the PCM material 114a, 114b is to use an electrical pulse with a relatively long decay (e.g., 1 microsecond) (as opposed to a square pulse with a relatively short decay, on the order of nanoseconds) that is strong enough to heat the PCM material 114a, 114b above its melting point, and after heating, the PCM material 114a, 114b is cooled slowly, allowing it to form crystals. Either of these processes reduces the electrical resistance between the PCM cells 104a, 104b compared to having amorphous regions. This new resistance can then be read using a low voltage (e.g., 0.2 V) current without changing the state of the PCM material 114a, 114b or the resistance of the PCM cells 104a, 104b.

[0026] In some embodiments, the melting temperature of the PCM material 114a, 114b is about 600° C. In some embodiments, the crystallization temperature of the PCM material 114a, 114b is about 180° C. The process of setting and resetting the PCM cells 104a, 104b may also occur iteratively, and in some embodiments, different regions of the PCM material 114a, 114b may be created with different resistances (e.g., by varying the size of the amorphous regions or the amount of crystallization nuclei in the amorphous regions, or both). This allows the PCM cells 104a, 104b to have a variety of distinct resistances that may be created by varying the reset parameters. Thus, if the PCM cells 104a, 104b are viewed as representing information digits, these digits may be non-binary (as opposed to traditional bits). However, in some embodiments, the PCM cells 104a, 104b can be used as bits by either having or not having uniform regions in the PCM material 114a, 114b. In such embodiments, the PCM cells 104a, 104b can have a high resistance (also known as a low voltage output or a "0") or a low resistance (also known as a high voltage output or a "1").

[0027] Figure 2 is a workflow flowchart showing how a PCM array can be used in training a machine learning (ML) algorithm. The ML lifecycle can be divided into two main distinct parts. The first is the training phase, where an ML model is created or "trained" by running a specified subset of data through the model. ML inference is the second phase, where the model is put into action against real data to produce actionable output. Data processing by an ML model is often referred to as "scoring," so one can say that the ML model scores the data and the output is the score.

[0028] The method of the workflow is performed on a semiconductor structure having a global heater, such as the semiconductor structure 100 shown in FIG. 1. In one embodiment, the workflow is performed by a training program that controls signals to wires of the semiconductor structure (e.g., bottom wire 106, top wires 124a, 124b, and global heater wire 126 in FIG. 1). The training program sends signals to the global heater to heat a phase change memory (PCM) array (block 202). As described above, the training program may control the heating of the PCM array such that the PCM material has a temperature that is close to, but does not exceed, the melting temperature of the PCM material. The PCM array may be heated to a training temperature of 175° C., 160° C., or other temperature that is close to the crystallization temperature of the PCM material. In certain embodiments, the training temperature may be 590° C., 575° C., or other temperature that is close to the melting temperature (600° C.) of the PCM material.

[0029] The training program may also store ML values ​​in the PCM array (block 204). The stored ML values ​​are derived from training an ML algorithm and are stored by propagating a signal through each cell of the PCM array, melting the PCM material and changing the resistance of the cell. Training is the process of teaching an ML algorithm to perform a desired artificial intelligence task (e.g., image classification, speech-to-text) by feeding the ML algorithm with data to obtain a trained deep learning model. During the training process, known data is fed to the algorithm, and the algorithm makes a prediction about what the data represents. Errors in the prediction are used to update the connection strengths between the artificial neurons stored by the resistance values ​​of the PCM array. As the training process continues, the resistance values ​​are further adjusted until the ML algorithm makes predictions with sufficient accuracy. The resistance values ​​of each PCM cell of the PCM array may be adjusted at a lower current / voltage than would be required if the wide-area heater did not heat the PCM array to the training temperature.

[0030] Once training is complete, the training program sends a signal to the global heater to stop heating the PCM array (block 206). The heating is controlled by a signal to the global heater wires, and when the training program stops sending the heating signal, the global temperature of the semiconductor structure drops again from the training temperature to which it was heated. As the global temperature drops, the resistance values ​​stored in the PCM array become more resistant to noise because it requires more energy to change the phase state of the PCM material. Once the temperature drops, the training program infers the PCM array (block 208). ML inference is the process of running real data points through machine learning algorithms to calculate an output. When ML is in production, it is often described as artificial intelligence (AI) because it is performing functions similar to human thought and analysis. Since ML models are usually simply software code that implements mathematical algorithms, machine learning inference essentially involves deploying software applications in a production environment.

[0031] 3-6 illustrate side cross-sectional views of a process for fabricating a semiconductor device 300, according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of one embodiment of a semiconductor structure 300 during fabrication, such as after formation of a plurality of PCM cells 304. Each PCM cell of the plurality of PCM cells may include a top electrode 322, a resistive element 314, and a bottom electrode 308. The PCM cells 304 are formed on a substrate 310 and a bottom wire 306. The bottom electrode 308 may be formed by etching a hole in an insulator 312 and filling the hole with a highly resistive metal. The highly resistive metal may include, for example, titanium nitride, tantalum nitride, or a combination thereof. The resistive element 314 and the top electrode 322 may be formed as blanket layers and then patterned and etched.

[0032] 4 is a cross-sectional view of partially fabricated semiconductor structure 300, such as after the formation of spacers 316 that surround PCM cells 304. Spacers 316 insulate and protect PCM cells 304 during subsequent steps in the fabrication of semiconductor structure 300. Spacers 316 are formed using a deposit and etch-back technique whereby a blanket of spacer material (e.g., silicon nitride) is deposited as a blanket layer over semiconductor structure 300 and then etched away from the more horizontal portions of semiconductor structure 300, leaving the more vertical portions.

[0033] 5 is a cross-sectional view of the semiconductor structure 300 during fabrication, such as after formation of the global heater 318. The global heater 318 may be formed of a highly resistive metal that heats up when a current is applied through the global heater 318. The highly resistive metal may include, for example, titanium nitride, tantalum nitride, or a combination thereof. The global heater 318 may be formed by applying a blanket layer over the insulator 312. After application of the blanket layer, the top surface of the global heater 318 may be recessed below the top surface of the spacers 316.

[0034] FIG. 6 is a cross-sectional view of the semiconductor structure 300 during fabrication, such as after patterning and etching away at least a portion of the layer of highly resistive metal of the global heater 318. Semiconductor lithography can be the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed with a light-sensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated multiple times to build the numerous wires that connect the millions of transistors in the complex structures and circuits that make up the transistors. Each pattern printed on the wafer is aligned with the previous one, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0035] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The technical terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to allow other skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A phase change memory (PCM) array comprising: a plurality of PCM cells, each PCM cell of the plurality of PCM cells comprising a top electrode, a resistive element, and a bottom electrode; a large area heater surrounding the plurality of PCM cells, the large area heater including a thermally conductive material in contact with each of the plurality of PCM cells, the large area heater being configured to receive an electrical signal to simultaneously heat the plurality of PCM cells; 1. A phase change memory (PCM) array comprising:

2. 2. The PCM array of claim 1, wherein said bottom electrode comprises a highly resistive metal selected from the group consisting of titanium nitride, tantalum nitride, and combinations thereof.

3. The PCM array of claim 1 , wherein the thermally conductive material is selected from the group consisting of titanium nitride, tantalum nitride, and combinations thereof.

4. The PCM array of claim 1 , wherein each PCM cell of the plurality of PCM cells comprises a spacer between the PCM cell and the global heater.

5. The PCM array of claim 4 , wherein a top surface of the global heater is recessed below a top surface of the spacer.

6. The PCM array of claim 1 further comprising a via configured to supply current to the global heater.

7. The PCM array of claim 1 , wherein said bottom electrode protrudes into a nitride layer and said global heater is formed on a top surface of said nitride layer.

8. 2. The PCM array of claim 1, wherein said PCM cells change from a first phase to a second phase in response to a signal that heats said bottom electrode.

9. forming a plurality of phase change memory (PCM) cells, each PCM cell of the plurality of PCM cells comprising a top electrode, a resistive element, and a bottom electrode; forming a global heater including a thermally conductive material surrounding the plurality of PCM cells, the global heater configured to receive an electrical signal to simultaneously heat the plurality of PCM cells; A method comprising:

10. 10. The method of claim 9, wherein forming the bottom electrode comprises etching a hole in a nitride layer and filling the hole with a highly resistive metal.

11. The method of claim 10 , wherein the high-resistivity metal comprises a selection from the group consisting of titanium nitride, tantalum nitride, and combinations thereof.

12. The method of claim 10 , wherein said forming said global heater comprises forming a layer of high resistivity metal on top of said nitride layer.

13. 13. The method of claim 12, further comprising patterning and etching away at least a portion of said layer of highly resistive metal.

14. The method of claim 9 , further comprising forming a spacer between the PCM cell and the global heater.

15. The method of claim 14 , wherein a top surface of the global heater is recessed below a top surface of the spacer.

16. sending a signal to a global heater to heat a phase change memory (PCM) array, the global heater including a thermally conductive material in contact with each of the plurality of PCM cells; storing machine learning values ​​in the PCM array by propagating signals through PCM cells of the PCM array to change resistance of the PCM cells; sending a signal to the global heater to stop heating the PCM array; inferring said PCM array; A method comprising:

17. The method of claim 16 , wherein the global heater comprises a high resistivity metal surrounding the PCM cells of the PCM array.

18. The method of claim 16 , wherein training the PCM array comprises heating a local heater for each of the PCM cells of the PCM array.

19. 17. The method of claim 16, wherein training the PCM array includes changing at least one of the PCM cells from a first phase to a second phase.

20. 20. The method of claim 19, wherein the first phase is an amorphous phase and the second phase is a crystalline phase.

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