Hybrid Coatings for Integrated Circuit Devices

Abstract

An interconnect layer for an integrated circuit device includes a low radio frequency (RF) loss primary coating forming a major portion of the interconnect layer, an opening formed in the primary coating, a high aspect ratio patternable secondary coating within the opening, and a via formed in the secondary coating, the aspect ratio of the via being greater than the aspect ratio of the opening.

Description

[Background technology]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to integrated circuit devices, and more particularly to coatings for integrated circuit devices.

[0002] Integrated circuit devices have a wide range of applications in various industries. For example, a monolithic microwave integrated circuit (MMIC) is a type of integrated circuit device that is commonly used for microwave mixing, power amplification, low noise amplification, and high frequency switching. Integrated circuit devices can transmit and receive radio frequency (RF) signals. Therefore, integrated circuit devices may include various RF features on the device surface. Exposed features may be damaged by handling, so coatings may be used to protect integrated circuit devices. Summary of the Invention

[0003] In one example, an interconnect layer of an integrated circuit device includes a low radio frequency (RF) loss primary coating forming a major portion of the interconnect layer, an opening formed in the primary coating, a high aspect ratio patternable secondary coating within the opening, and a via formed in the secondary coating, where the aspect ratio of the via is greater than the aspect ratio of the opening.

[0004] In another example, an integrated circuit device includes a wafer, a low radio frequency (RF) loss primary coating at least partially covering the wafer, an opening formed in the primary coating to expose a feature located on the wafer, a high aspect ratio patternable secondary coating in the opening, and a via formed in the secondary coating, the aspect ratio of the via being greater than the aspect ratio of the opening.

[0005] In another example, a method for reducing radio frequency (RF) losses from an integrated circuit device includes depositing a low RF loss primary coating on an integrated circuit device wafer, forming openings in the primary coating to expose features located on the wafer, depositing a high aspect ratio patternable secondary coating in the openings, and forming vias in the secondary coating. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional side view of an integrated circuit device with a hybrid coating and a high aspect ratio via. [Diagram 2] 1 is a schematic cross-sectional view of an integrated circuit device having a hybrid coating and a tapered high aspect ratio via. [Diagram 3] FIG. 1 is a process flow diagram showing steps for manufacturing hybrid coatings and high aspect ratio vias for integrated circuit devices. [Figure 4A] 1A-1D are schematic cross-sectional side views illustrating steps for fabricating hybrid coatings and high aspect ratio vias for integrated circuit devices. [Figure 4B] 1A-1D are schematic cross-sectional side views illustrating steps for fabricating hybrid coatings and high aspect ratio vias for integrated circuit devices. [Figure 4C] 1A-1D are schematic cross-sectional side views illustrating steps for fabricating hybrid coatings and high aspect ratio vias for integrated circuit devices. [Figure 4D] 1A-1D are schematic cross-sectional side views illustrating steps for fabricating hybrid coatings and high aspect ratio vias for integrated circuit devices. [Figure 4E] 1A-1D are schematic cross-sectional side views illustrating steps for fabricating hybrid coatings and high aspect ratio vias for integrated circuit devices. [Figure 4F] 1A-1D are schematic cross-sectional side views illustrating steps for fabricating hybrid coatings and high aspect ratio vias for integrated circuit devices. [Diagram 5] 1 is a schematic top view of an integrated circuit device showing spacing of high aspect ratio vias in a hybrid coating. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] In accordance with the techniques of the present disclosure, a hybrid coating for an integrated circuit device includes a low radio frequency (RF) loss coating that defines a low aspect ratio opening, and a high aspect ratio patternable coating that fills the low aspect ratio opening and defines a high aspect ratio via therein. The hybrid coating with the high aspect ratio via reduces RF losses at high frequencies and enables solidification of features on the wafer surface of the integrated circuit device. The hybrid coating of the integrated circuit device disclosed herein and corresponding manufacturing methods are described below with reference to Figures 1-5.

[0008] Figure 1 is a schematic cross-sectional side view of an integrated circuit device 10 with a hybrid coating 15 and a high aspect ratio via 24. Integrated circuit device 10 includes a wafer 12, a contact 14, a hybrid coating 15, an interconnect 16, and a top feature 17. Hybrid coating 15 includes a primary coating 18 that defines an opening 20 and has a sidewall 21, and a secondary coating 22 that defines a via 24 and has a sidewall 26. Also shown in Figure 1 is a thickness A of the hybrid coating, a width B of the opening, and a width C of the via.

[0009] Wafer 12 is the first, or base, layer of integrated circuit device 10. Wafer 12 can be a thin slice of semiconductor such as crystalline silicon (Si), silicon carbide (SiC), gallium nitride on Si (GaN), or GaN on SiC, to name a few non-limiting examples. Wafer 12 can serve as a substrate for microelectronic features integrated within and / or on wafer 12. For example, radio frequency (RF) features or transmission lines can be formed on the top surface of wafer 12. RF features on the top surface of wafer 12 can transmit and / or receive RF signals. Wafer 12 can represent the completed circuitry of integrated circuit device 10, as shown generally in FIG. 1.

[0010] Hybrid coating 15 spreads across and coats the top surface of wafer 12. Thus, hybrid coating 15 is the second layer of integrated circuit device 10. Microelectronic features formed on the top surface of wafer 12 may be between wafer 12 and hybrid coating 15. Hybrid coating 15 may be a protective coating over the top surface of wafer 12 that prevents microelectronic features incorporated and / or located on wafer 12 from being exposed.

[0011] The hybrid coating 15 may also be an interconnect layer of the integrated circuit device 10. For example, a top feature 17 may be located on the top surface of the hybrid coating 15. The top feature 17 may be any microelectronic feature, such as a transformer, an inductor, other feature, or any combination of features. For simplicity, the top feature 17 is represented diagrammatically in FIG. 1 as a box behind a cross section. Although FIG. 1 shows the integrated circuit device 10 with two top features 17, other examples may include more or fewer top features 17. In still other examples, the integrated circuit device 10 may not include a top feature 17. The integrated circuit device 10 may include any suitable number of top features 17. The top features 17 form an additional functional layer of the integrated circuit device 10 on the top surface of the hybrid coating 15 and may have connections (e.g., interconnects 16, described below) that extend through the hybrid coating 15 to the wafer 12. In such examples, the hybrid coating 15 is configured to be located between the wafer 12 and the additional functional layer.

[0012] The hybrid coating 15 includes a primary coating 18 and a secondary coating 22. The primary coating 18 is the primary coating of the hybrid coating 15. The primary coating 18 can be a low RF loss material (i.e., a material having a low RF loss tangent). Specifically, the primary coating 18 can be a benzocyclobutene (BCB)-based polymer. The BCB-based polymer can be a photoimageable or photosensitive dielectric suitable for thin-film microelectronics applications. For example, one group of BCB-based polymers is commercially available under the trade name CYCLOTENE (a trademark of Dow Chemical Company) 4000 series, available from Kayaku Advanced Materials, Inc., 200 Flanders Road, Westborough, MA 01581 USA.

[0013] Primary coating 18 extends across the top surface of wafer 12 and forms a major portion of hybrid coating 15, and thereby a major portion of the interconnect layer of integrated circuit device 10. Primary coating 18 may cover a greater surface area of ​​the top surface of wafer 12 as compared to secondary coating 22. For example, primary coating 18 may cover all or nearly all of the top surface of wafer 12, except for portions or features exposed by openings 20, which are described in more detail below.

[0014] As shown in FIG. 1, the hybrid coating 15 has a thickness A. The thickness A is measured from the top surface (upper side) of the wafer 12 to the top surface of the hybrid coating 15 at the primary coating 18 (i.e., the top surface of the primary coating 18). Thus, the thickness A may represent the thickness of the primary coating 18. The thickness A may depend on the desired application of the integrated circuit device 10 and / or the properties of the hybrid coating 15 (i.e., the primary coating 18 and / or the secondary coating 22). For example, the thickness A may depend on the desired RF loss tangent of the primary coating 18. In some examples, the thickness A may be greater than 15 micrometers (μm). In some examples, the thickness A may be greater than 20 μm. In some examples, the thickness A may be about 20-30 μm. In some examples, the thickness A may be about 24-25 μm. In still other examples, the thickness A may be greater than 30 μm.

[0015] The opening 20 is a channel or trench formed in the primary coating 18 of the hybrid coating 15. The opening 20 may extend through the primary coating 18 to the top surface of the wafer 12 or may extend to a feature located on the top surface of the wafer 12 and exposed by the opening 20 (e.g., contact 14, described below). The height of the opening 20 measured from the top surface of the wafer 12, rather than from the top surface of the feature on the wafer 12, may be referred to as the effective height of the opening 20. The effective height of the opening 20 is a convenient measurement for purposes of determining aspect ratio because the thickness of features such as the contact 14 may vary. Furthermore, because the opening 20 extends through the primary coating 18, the effective height of the opening 20 may be generalized as a thickness A.

[0016] Opening 20 also defines a width B. Opening width B may depend on the properties of primary coating 18. In some examples, width B may be greater than 15 μm. In some examples, width B may be about 40-60 μm. Width B may be greater than thickness A. That is, opening 20 may have an aspect ratio (e.g., the ratio of thickness A to width B) that is less than 1.0. In some examples, opening 20 has an aspect ratio of about 0.6. Opening 20 may be referred to as a low aspect ratio opening.

[0017] The opening 20 is defined in the primary coating 18 by sidewalls 21. The sidewalls 21 are depicted generally in FIG. 1 as being straight and extending perpendicular to the wafer 12. That is, the opening 20 has a constant width (width B) along the height of the opening 20. In other examples, the sidewalls 21 can be angled or tapered (as described below with respect to FIG. 2). In yet other examples, the sidewalls 21 may have contoured or rounded edges near either end of the opening 20. In still other examples, the sidewalls 21 can have any suitable profile based on the properties of the primary coating 18.

[0018] Secondary coating 22 is a secondary coating of hybrid coating 15. Secondary coating 22 has a different composition than primary coating 18. Secondary coating 22 can be a high aspect ratio patternable material (i.e., a material that can be patterned to form high aspect ratio features). Secondary coating 22 can also be a relatively high RF loss material (i.e., a material that has a high RF loss tangent) compared to primary coating 18, i.e., secondary coating 22 can have a higher RF loss tangent than primary coating 18. Specifically, the secondary coating 22 may be a high contrast epoxy-based negative photoresist with an average of eight epoxy functional groups per portion commercially available under the trade name SU-8#### (collectively referred to herein as "SU-8" for brevity) with various viscosities (e.g., SU-85, SU-810, SU-825, SU-850, SU-8100, etc.) from Kayaku Advanced Materials, Inc., 200 Flanders Road, Westborough, MA 01581 USA. SU-8 material properties include suitability for high aspect ratio imaging with thick, nearly vertical sidewalls due to high optical transparency at wavelengths greater than 360 nanometers (nm) (near UV), and the ability to form films up to 200 micrometers (μm) thick in a single spin-coat process. The crosslinked portion of the SU-8 film is insoluble in liquid developers. SU-8 is typically used in permanent applications where high chemical and heat resistance is required, for example.

[0019] The secondary coating 22 is within the opening 20 of the primary coating 18. Thus, the secondary coating 22 can cover a reduced surface area of ​​the top surface of the wafer 12 as compared to the primary coating 18. For example, the secondary coating 22 can cover only the portion or feature of the top surface of the wafer 12 exposed by the opening 20. The secondary coating 22 can extend at least the full height of the opening 20. In this manner, the secondary coating can contact the top surface of the wafer 12 (as shown in FIG. 2 ) and / or features (e.g., contacts 14, described below) located on the top surface of the wafer 12. The thickness of the secondary coating 22 measured from the top surface of the wafer 12, rather than from the top surface of the features on the wafer 12, can be referred to as the effective thickness of the secondary coating 22. The effective thickness of the secondary coating 22 is a convenient measurement for purposes of determining aspect ratio because the thickness of features such as the contacts 14 can vary. In some examples, the secondary coating 22 is at least as thick as the primary coating 18 (based on the effective thickness of the secondary coating 22). In such instances, the effective thickness of secondary coating 22 may be generalized as thickness A. In other instances, secondary coating 22 extends above the top surface of primary coating 18, and the effective thickness of secondary coating 22 may be greater than thickness A.

[0020] The via 24 is an opening or channel formed in the secondary coating 22 of the hybrid coating 15. The via 24 can extend through the secondary coating 22 to the top surface of the wafer 12 or to a feature located on the top surface of the wafer 12 and exposed by the via 24 (e.g., contact 14, described below). The height of the via 24 measured from the top surface of the wafer 12, rather than from the top surface of the feature on the wafer 12, can be referred to as the effective height of the via 24. The effective height of the via 24 is a convenient measurement for purposes of determining the aspect ratio because the thickness of features such as the contact 14 can vary. Furthermore, because the via 24 extends through the secondary coating 22, in examples where the secondary coating 22 is at least as thick as the primary coating 18 (based on the effective thickness of the secondary coating 22), the effective height of the via 24 can be generalized as thickness A. In other examples where the secondary coating 22 extends above the top surface of the primary coating 18, the effective height of the via 24 can be greater than thickness A.

[0021] The via 24 also defines a width C. The via width C may depend on the characteristics of the secondary coating 22. In some examples, the width C may be less than 60 μm. In some examples, the width C may be less than 30 μm. In some examples, the width C may be less than 20 μm. In some examples, the width C may be about 15 μm. The width C may be large enough to accommodate a desired thickness of material to be coated on the sidewalls 26 of the via 24 (e.g., the interconnect 16 described below), while also providing an opening through the secondary coating 22. The aspect ratio of the via 24 (e.g., the ratio of the thickness A to the width C) may be greater than the aspect ratio of the opening 20. For example, the aspect ratio of the via 24 may be greater than 0.6. Additionally, the width C may be less than or equal to the thickness A. That is, the aspect ratio of the via 24 may be greater than or equal to 1.0. In some examples, the aspect ratio of the via 24 ranges from 5:1 to 25:1. Via 24 may be referred to as a high aspect ratio via.

[0022] The via 24 is defined in the secondary coating 22 by sidewalls 26. The sidewalls 26 are depicted generally in FIG. 1 as being straight and extending perpendicular to the wafer 12. That is, the via 24 has a constant width (width C) along the height of the via 24. In other examples, the sidewalls 26 can be angled or tapered (as described below with respect to FIG. 2). In yet other examples, the sidewalls 26 may have contoured or rounded edges near either end of the via 24. In still other examples, the sidewalls 26 can have any suitable profile based on the properties of the secondary coating 22.

[0023] The contact 14 is positioned on the top surface of the wafer 12. The contact 14 is an electrical contact material. For example, the contact 14 may be a metal. The contact 14 is positioned such that the opening 20 and the via 24 are above the contact 14. In other words, the opening 20 and the via 24 are openings through the hybrid coating 15 (through the primary coating 18 and the secondary coating 22, respectively) to the contact 14. The contact 14 may be any suitable size based on the desired spacing of features on the wafer 12. As shown in FIG. 1, the contact 14 may have a width that is greater than the via width C. Thus, a portion of the contact 14 may be between the wafer 12 and the hybrid coating 15. For example, a portion of the contact 14 may be between the wafer 12 and both the primary coating 18 and the secondary coating 22 (as shown in FIG. 1), or a portion of the contact 14 may be between the wafer 12 and the secondary coating 22 (as shown in FIG. 2), but not between the primary coating 18.

[0024] The contacts 14 form an electrical connection with the interconnects 16. The interconnects 16 are a conductive material. For example, the interconnects 16 may be metal. The interconnects 16 form a layer on the top surface of the hybrid coating 15 (opposite the surface of the hybrid coating 15 that contacts the wafer 12) and on the sidewalls 26, for example, the interconnects 16 may be a top metal layer. Specifically, the interconnects 16 extend from the top surface of the hybrid coating 15 through the vias 24 and along the sidewalls 26 to the contacts 14. The interconnects 16 provide electrical connections between microelectronic features on the top surface of the wafer 12 and other features, such as, for example, transformers and inductors, that may be located on the top surface of the hybrid coating 15.

[0025] In operation, a radio frequency (RF) signal (or multiple RF signals) may be transmitted or received by the integrated circuit device 10 through the hybrid coating 15. The RF signal may be a high frequency RF signal. For example, the integrated circuit device 10 may have an operating frequency greater than 10 GHz. In some examples, the integrated circuit device 10 may be a monolithic microwave integrated circuit (MMIC) operating at microwave frequencies. Because the primary coating 18 of the hybrid coating 15 covers a larger portion of the wafer 12 than the secondary coating 22, the RF signal from the integrated circuit device 10 encounters primarily the primary coating 18 as it travels in the plane of the wafer 12. The RF signal encounters the secondary coating 22 only in limited areas on the wafer 12 where the secondary coating 22 fills the opening 20. A portion of the RF signal may be lost in the primary coating 18 and / or the secondary coating 22. The RF loss tangent is a numerical value in the calculation of RF loss through a particular material, and energy is lost in proportion to the RF loss tangent. A lower RF loss tangent means less signal is lost in the material. The amount of RF loss from integrated circuit device 10 depends on the RF loss tangent of primary coating 18 and secondary coating 22 .

[0026] Hybrid coating 15 also protects features on the top surface of wafer 12 from being scratched or damaged by handling of integrated circuit device 10. Damage to features of integrated circuit device 10 can render integrated circuit device 10 unusable and require replacement, which is costly and time consuming.

[0027] Integrated circuit devices such as integrated circuit device 10 have a wide range of applications in many industries. Coatings are desirable to protect circuit features, but depending on the coating material used, there can be a significant tradeoff between feature spacing and device RF losses.

[0028] BCB-based polymers have a low RF loss tangent and allow for low resolution (i.e., low aspect ratio) patterning. More specifically, there is an inverse relationship between the RF loss tangent and the thickness of the BCB-based polymer. For example, a thicker BCB layer (e.g., primary coating 18) can be made thicker by doubling the thickness of the BCB-based polymer with a corresponding RF loss tangent. Thus, primary coating 18 is suitable for coating a large portion of wafer 12 and supports long distance end-to-end RF signal transmission. However, a thicker BCB layer requires a wider opening (e.g., opening 20) in the BCB layer due to the aspect ratio requirements of the material. The wider opening requires a larger wafer surface contact (e.g., contact 14) and increases inductance resulting in increased RF losses from the device.

[0029] On the other hand, SU-8 allows for high resolution (i.e., high aspect ratio) patterning. For example, SU-8 allows for patterning of features with aspect ratios up to about 200:1. However, the RF loss tangent of SU-8 is typically about an order of magnitude greater than the RF loss tangent of a BCB-based polymer of the same thickness. Increasing the thickness of the SU-8 layer (e.g., secondary coating 22) can significantly increase the RF loss. Thus, the secondary coating 22 is less effective than the primary coating 18 in covering the entire (or a large portion) of the wafer 12 due to increased RF loss over a larger portion of the device.

[0030] The hybrid coating 15 utilizes the combined properties of the primary coating 18 and the secondary coating 22 to improve the performance of the integrated circuit device 10. The integrated circuit device 10 maintains the advantage of low RF loss over most of the surface of the wafer 12 due to the low RF loss tangent of the primary coating 18 covering most of the surface of the wafer 12. That is, even if the RF loss tangent of the secondary coating 22 is relatively high, it does not significantly affect the loss of the final product because the distance that the RF signal line contacts the secondary coating 22 is very short compared to the primary coating 18. The integrated circuit device 10 also maintains the advantage of high aspect ratio patterning by strategically using the secondary coating 18 in limited locations (e.g., within the openings 20) to form high aspect ratio features (e.g., vias 24). Using only either the primary coating 18 or the secondary coating 22 instead of the hybrid coating 15 may increase the RF loss of the integrated circuit device 10, adversely affecting performance.

[0031] The hybrid coating 15 allows high aspect ratio vias 24 to be formed on the integrated circuit device 10, thereby allowing a layer of the hybrid coating 15 to be used as an interconnect layer to connect features on the wafer 12 to features on the hybrid coating 15 through the vias 24. Used in this manner, the hybrid coating 15 also allows for compression of features on the surface of the wafer 12. Specifically, the vias 24 must be placed within the exposed surface area of ​​the contacts 14 during fabrication, so that the contacts 14 must be wider than the openings of the vias 24. Thus, other connections (other vias) must be separated from the vias 24 based at least in part on the size of the contacts 14. Using larger contacts to accommodate wider (e.g., lower aspect ratio) vias would require greater spacing between individual vias, resulting in loss of signal strength on the wafer, especially at high frequencies. The high aspect ratio vias 24 can be narrower than conventional vias formed with materials such as BCB, so that adjacent vias and underlying features can be positioned closer to the vias 24 on the surface of the wafer 12. That is, adjacent vias 24 can be positioned closer together with the hybrid coating 15 than comparable vias on a wafer with only a primary coating 18 (e.g., BCB). This compression of features on the top surface of the wafer 12, made possible by the hybrid coating 15 with high aspect ratio vias 24, can allow for a higher density of features on the integrated circuit device 10 and / or a smaller overall device size.

[0032] RF losses can have the greatest impact on the performance of integrated circuit devices in applications that require high frequencies and the strongest possible signals. Thus, hybrid coating 15 with high aspect ratio vias 24 can be particularly useful for high frequency applications of integrated circuit devices 10. For example, hybrid coating 15 with high aspect ratio vias 24 can provide benefits for 5G broadband cellular network technologies and other high frequency GaN on SiC or GaN on Si MMICs.

[0033] 2 is a schematic cross-sectional view of an integrated circuit device 100 with a hybrid coating 115 and a tapered high aspect ratio via 124. The integrated circuit device 100 includes a wafer 112, contacts 114A-114C, a hybrid coating 115, an interconnect 116, and a top feature 117. The hybrid coating 115 includes a primary coating 118 that defines a tapered opening 120 and has angled sidewalls 121, and a secondary coating 122 that defines a tapered via 124 and has angled sidewalls 126. Also shown in FIG. 1 are a thickness D of the hybrid coating, a width E of the opening, and a width F of the via. Integrated circuit device 100 has essentially the same structure and functionality as described above with reference to integrated circuit device 10 of FIG. 1, except that integrated circuit device 100 includes a stack of contacts 114A-114C, a tapered opening 120 with angled sidewalls 121, and a tapered via 124 with angled sidewalls 126, rather than straight-walled openings and / or vias (e.g., as shown in FIG. 1).

[0034] Depending on the desired characteristics of the integrated circuit device 100, it may be desirable to utilize a stack of contacts 114A-114C instead of a single contact (e.g., contact 14 of FIG. 1). The stack of contacts 114A-114C has essentially the same structure and function in the integrated circuit device 100 as the contact 14 in the integrated circuit device 10 (shown in FIG. 1). The contacts 114A-114C are stacked on the top surface of the wafer 112. Each contact 114A-114C is an electrical contact material. For example, each contact 114A-114C may be a separate metal layer that together form the stack of contacts 114A-114C. The stack of contacts 114A-114C is positioned such that the openings 120 and vias 124 are above the contacts 114A-114C. The top one of the contacts 114A-114C (e.g., contact 114C in FIG. 2) is exposed by a via 124, and the top one of the contacts 114A-114C may form an electrical connection with the interconnect 116. Although FIG. 2 illustrates the integrated circuit device 100 having three contacts 114A-114C, other examples may include more or fewer contacts 114. The integrated circuit device 100 may include any suitable number of contacts 114.

[0035] The contacts 114A-114C may be any suitable size based on the desired spacing of features on the wafer 112. Each of the contacts 114A-114C may have the same or different dimensions. As shown in FIG. 2, the contacts 114A-114C may have a width that is greater than the via width F. Thus, a portion of the contacts 114A-114C may be between the wafer 112 and the hybrid coating 115. For example, a portion of the contacts 114A-114 may be between the wafer 112 and the secondary coating 122 but not the primary coating 118 (as shown in FIG. 2), and a portion of the contacts 114A-114C may be between the wafer 112 and both the primary coating 118 and the secondary coating 122 (as shown in FIG. 1). Each of the contacts 114A-114C may extend laterally the same distance or different distances into the secondary coating 122 and the primary coating 118.

[0036] Because the thickness of the contacts 114A-114C can vary, the height of the openings 120 and the height of the vias 124 (the effective height of the openings 120 and the effective height of the vias 124) can be measured from the top surface of the wafer 112, rather than from the top surfaces of the contacts 114A-114C. Furthermore, if the widths of the contacts 114A-114C are not equal (as shown in FIG. 2), then the height of the openings 120 will vary along the width (width E) of the openings 120. Thus, the effective height of the openings 120 and the effective height of the vias 124 are convenient measurements for determining the aspect ratios of the openings 120 and the vias 124.

[0037] The opening 120 is defined in the primary coating 118 by a sidewall 121. The sidewall 121 is angled or tapered. A first end of the opening 120 is wider than a second end of the opening 120 adjacent the top surface of the wafer 112 and / or a feature (such as contacts 114A-114C) located on the top surface of the wafer 112. In other words, the opening 120 narrows toward the wafer 112. The aspect ratio of the opening 120 can be determined as described above with respect to the opening 20 of FIG. 1, and the width of the opening 120 related to the aspect ratio (e.g., width E) can be measured at any point along the sidewall 121. For simplicity, the width E at the first end of the opening 120 is shown in FIG. 2. In some examples, the width E can be measured from a midpoint along the sidewall 121.

[0038] 1, the sidewall 121 can have contoured or rounded edges near either end of the opening 120. The sidewall 121 can have any suitable profile based on the properties of the primary coating 118. For example, the angle of the tapered sidewall 121 can depend on the material properties of the primary coating 118.

[0039] Similarly, the via 124 is defined in the secondary coating 122 by a sidewall 126. The sidewall 126 is angled or tapered. A first end of the via 124 is wider than a second end of the via 124 adjacent the top surface of the wafer 112 and / or a feature (such as contacts 114A-114C) located on the top surface of the wafer 112. In other words, the via 124 narrows toward the wafer 112. The aspect ratio of the via 124 can be determined as described above with respect to the via 24 in FIG. 1, and the width of the via 124 related to the aspect ratio (e.g., width F) can be measured at any point along the sidewall 126. For simplicity, the width F is shown at the first end of the via 124 in FIG. 2. In some examples, the width F can be measured from a midpoint along the sidewall 126.

[0040] Similar to sidewall 26 shown in FIG. 1, sidewall 126 can have contoured or rounded edges near both ends of via 124. Sidewall 126 can have any suitable profile based on the properties of secondary coating 122. For example, the angle of tapered sidewall 126 can depend on the material properties of secondary coating 122. Thus, the angle of tapered sidewall 126 can be the same as or different from the angle of tapered sidewall 121. In some examples (as shown in FIG. 2), tapered sidewall 126 can be steeper than tapered sidewall 121 (i.e., the angle of tapered sidewall 126 can be greater than the angle of tapered sidewall 121).

[0041] The hybrid coating 115 utilizes the combined properties of the primary coating 118 and the secondary coating 122 to improve the performance of the integrated circuit device 100. The integrated circuit device 100 maintains the advantage of low RF loss over most of the surface of the wafer 112 due to the low RF loss tangent of the primary coating 118 covering most of the surface of the wafer 112. The integrated circuit device 100 also maintains the advantage of high aspect ratio patterning by strategically using the secondary coating 118 in limited locations (e.g., within the openings 120) to form high aspect ratio features (e.g., vias 124). Using only either the primary coating 118 or the secondary coating 122 instead of the hybrid coating 115 may increase the RF loss of the integrated circuit device 100, adversely affecting performance.

[0042] The hybrid coating 115 allows for the formation of high aspect ratio vias 124 on the integrated circuit device 100, thereby allowing a layer of the hybrid coating 115 to be used as an interconnect layer to connect features on the wafer 112 to features on the hybrid coating 115 through the vias 124. Used in this manner, the hybrid coating 115 also allows for compression of features on the surface of the wafer 112. Specifically, the contacts 114A-114C must be wider than the opening of the via 124 because the via 124 must be placed within the exposed surface area of ​​the stack of contacts 114A-114C during fabrication. Thus, another connection (another via) must be separated from the via 124 based at least in part on the size of the contacts 114A-114C. Using larger contacts to accommodate wider (e.g., lower aspect ratio) vias would require greater spacing between individual vias, resulting in loss of signal strength on the wafer, especially at high frequencies. The high aspect ratio vias 124 can be narrower than conventional vias formed with materials such as BCB, such that adjacent vias and underlying features can be positioned closer to the vias 124 on the surface of the wafer 112. That is, adjacent vias 124 can be positioned closer together with the hybrid coating 115 than comparable vias on a wafer with only a primary coating 118 (such as BCB). This compression of features on the top surface of the wafer 112, enabled by the hybrid coating 115 with the high aspect ratio vias 124, can allow for a higher density of features on the integrated circuit device 100 and / or a smaller overall device size.

[0043] RF losses can have the greatest impact on the performance of an integrated circuit device at high frequencies and where the strongest possible signal is desired. Thus, the hybrid coating 115 with high aspect ratio vias 124 can be particularly useful for high frequency applications of the integrated circuit device 100. For example, the hybrid coating 115 with high aspect ratio vias 124 may provide benefits for 5G broadband cellular network technologies and other high frequency GaN on SiC or GaN on Si MMICs.

[0044] Fabrication of integrated circuit devices having hybrid top surface coatings and high aspect ratio vias (e.g., integrated circuit devices 10 and 100) is described with reference to Figures 3-4F. In this section, successive iterations of work-in-progress (WIP) features are designated with consecutive letters (e.g., "300A," "300B," etc.), and the WIP features may be generally referenced by a common reference number.

[0045] For ease of explanation, Figures 3-4F will be discussed together. Figure 3 is a process flow diagram illustrating steps of a process 200 for fabricating a hybrid coating and high aspect ratio vias for an integrated circuit device (e.g., integrated circuit devices 10 and 100 shown in Figures 1 and 2, respectively). Figures 4A-4F are schematic cross-sectional side views illustrating steps 210-222 for fabricating a hybrid coating 319 and high aspect ratio vias 322 for an integrated circuit device WIP 300. The integrated circuit device WIP 300 and its components are substantially similar in structure to the integrated circuit devices 10 and 100 and their components (described above with reference to Figures 1 and 2, respectively), except where in-process differences are noted.

[0046] 4A shows an integrated circuit device WIP 300A including a wafer 310 and contacts 312 positioned thereon. In step 210 of process 200, the wafer 310 is coated with a primary coating 314A to form an integrated circuit device WIP 300B (shown in FIG. 4B). For example, the primary coating 314A can be spin coated onto the wafer 310 or deposited by any other process suitable for depositing BCB. The primary coating 314A forms a layer on the top surface of the wafer 310 and the contacts 312.

[0047] In step 212, the primary coating 314A is exposed, developed, etched, or a combination of developed and etched to pattern the primary coating 314A and form the low aspect ratio openings 316. The choice of developing or etching process may depend on the properties of the primary coating 314A. After forming the low aspect ratio openings 316, the primary coating 314A may be cured. Additional processing steps of the primary coating 314A may be included prior to curing the primary coating 314A, depending on the desired yield. As shown in FIG. 4C, the resulting integrated circuit device WIP 300C includes a cured primary coating 314B patterned with the low aspect ratio openings 316.

[0048] In step 214, the primary coating 314B on the wafer 310 is coated with a secondary coating 318A to planarize the integrated circuit device WIP 300C and form an integrated circuit device WIP 300D with a hybrid coating 320A (shown in FIG. 4D). For example, the secondary coating 318A can be spin-coated on the wafer 310 (on top of the primary coating 314B) or deposited by other processes suitable for depositing SU-8, and then the secondary coating 318A can be soft-baked. The secondary coating 318A is deposited only after the low aspect ratio opening 316 is formed in the primary coating 314. The secondary coating 318A can completely fill the low aspect ratio opening 316. The hybrid coating 320A includes the primary coating 314B, the low aspect ratio opening 316, and the secondary coating 318A.

[0049] In step 216, the secondary coating 318A is exposed and developed (or etched) to pattern the secondary coating 318A to form high aspect ratio vias 322 and low aspect ratio openings 316 in the secondary coating 318A. The choice of developing or etching process may depend on the characteristics of the secondary coating 318A. The resulting integrated circuit device WIP 300E includes a secondary coating 318B patterned with high aspect ratio vias 322 (shown in FIG. 4E). Thus, the hybrid coating 320B includes the primary coating 314B, the low aspect ratio openings 316, the secondary coating 318B, and the high aspect ratio vias 322. As shown in FIG. 4E, the aspect ratio of the high aspect ratio vias 322 is greater than the aspect ratio of the low aspect ratio openings 316. The high aspect ratio vias 322 expose the contacts 312.

[0050] In step 218, topside metal 324 is patterned and plated onto wafer 310 over primary coating 314B, secondary coating 318B, and exposed portions of contacts 312. The resulting integrated circuit device WIP 300F includes hybrid coating 320B at least partially covered by topside metal 324 and high aspect ratio via 322 (shown in FIG. 4F).

[0051] The fully fabricated integrated circuit device WIP300F may be an embodiment of integrated circuit devices 10 and 100 of Figures 1-2 and may include any combination of the features described above with respect to Figures 1-2. Additionally, the patterning steps described in steps 212 and 216 of process 200 may be used to form multiple pairs of low aspect ratio openings and high aspect ratio vias across a wafer during the same fabrication process.

[0052] Figure 5 is a schematic top view of integrated circuit device 400 showing the spacing of high aspect ratio vias 414A-414D in hybrid coating 412. Integrated circuit device 400 includes wafer 410, hybrid coating 412, and interconnect 413. Hybrid coating 412 includes vias 414A-414D. Also shown in Figure 5 is center-to-center distance G. Integrated circuit device 400 has essentially the same structure and functionality as described above with reference to integrated circuit devices 10 and 100 of Figures 1-2, except that integrated circuit device 400 includes a plurality of vias 414A-414D connected by interconnect 413.

[0053] The vias 414A-414D are openings or channels formed in the hybrid coating 412. The vias 414A-414D are spaced apart within the hybrid coating 412. In some examples, the portions of the hybrid coating 412 between adjacent ones of the vias 414A-414D may include both a primary coating (e.g., primary coating 18 or 118 in FIGS. 1-2) and a secondary coating (e.g., secondary coating 22 or 122 in FIGS. 1-2). More specifically, adjacent ones of the vias 414A-414D may each be surrounded by a secondary coating, with the primary coating extending into the space between the surrounded vias. In other examples, the portions of the hybrid coating 412 between adjacent ones of the vias 414A-414D may include only a secondary coating. That is, multiple vias 414 may be formed in a secondary coating that fills a single opening (e.g., opening 20 or 120 in FIGS. 1-2) in the primary coating of the hybrid coating 412.

[0054] Each via 414A-414D may have essentially the same structure and function as described above with reference to via 24 of FIG. 1 and / or via 124 of FIG. 2. Although FIG. 5 illustrates integrated circuit device 400 with four vias 414A-414D, other examples may include more or fewer vias 414. Integrated circuit device 400 may include any number of vias 414 suitable for a desired circuit topology. Additionally, vias 414A-414D may be any suitable shape, such as circular (e.g., vias 414A and 414D), rectangular, square (e.g., vias 414B and 414C), or other suitable rounded, polygonal, or irregular shapes. Each of vias 414A-414D may have the same shape or different shapes. Any two or more vias 414 may be electrically connected by an interconnect (i.e., top metal) 413.

[0055] Adjacent ones of the vias 414A-414D are separated by a center-to-center distance G. For example, the distance G may be less than 90 micrometers (μm). In some examples, the distance G may be about 40 μm. If the portion of the hybrid coating 412 between adjacent ones of the vias 414A-414D includes both a primary coating and a secondary coating, the distance G may be about 40 μm. In some examples, the distance G may be about 20 μm. If the portion of the hybrid coating 412 between adjacent ones of the vias 414A-414D includes only a secondary coating, the distance G may be about 20 μm. The distance G may vary depending on the width of each via 414A-414D and / or the underlying contacts (e.g., contacts 14 or contacts 114A-114C in FIGS. 1-2) or the desired placement of microelectronic features on the surface of the wafer 410 (i.e., the design rules of the underlying circuitry).

[0056] As described above with reference to Figures 1 and 2, the hybrid coating 412 utilizes the combined properties of the primary and secondary coatings to improve the performance of the integrated circuit device 400. The integrated circuit device 400 maintains the advantage of low RF loss over most of the surface of the wafer 410 due to the low RF loss tangent of the primary coating of the hybrid coating 412 covering most of the surface of the wafer 410. The integrated circuit device 400 also maintains the advantage of high aspect ratio patterning to form high aspect ratio features (e.g., vias 414A-414D) by strategically using the secondary coating of the hybrid coating 412 in limited locations. Using only either the primary or secondary coatings instead of the hybrid coating 412 may increase the RF loss of the integrated circuit device 400, adversely affecting performance.

[0057] The hybrid coating 412 allows for the formation of high aspect ratio vias 414A-414D on the integrated circuit device 400, thereby allowing a layer of the hybrid coating 412 to be used as an interconnect layer to connect features on the wafer 410 to features on the hybrid coating 412 via the vias 414A-414D and the interconnects 413. Used in this manner, the hybrid coating 412 also allows for compression of features on the surface of the wafer 410. Specifically, because each via 414A-414D must be located within the contact surface area exposed during fabrication, the contacts (e.g., contact 14 shown in FIG. 1) must be wider than the opening of each corresponding via 414A-414D. Thus, the separate connections (separate vias) must be separated from the other connections of the vias 414A-414D based at least in part on the size of the contacts. Using larger contacts to accommodate wider (e.g., lower aspect ratio) vias would require greater spacing between individual vias, resulting in loss of signal strength on the wafer, especially at high frequencies. The high aspect ratio vias 414A-414D can be narrower than traditional vias formed with materials such as BCB, such that adjacent ones of the vias 414A-414D and underlying features can be positioned closer together on the surface of the wafer 410. That is, with the hybrid coating 412, the vias 414A-414D can be positioned closer together than comparable vias on a wafer with only a primary coating (e.g., BCB). This compression of features on the top surface of the wafer 410, enabled by the hybrid coating 412 with the high aspect ratio vias 414A-414D, allows for a higher density of features on the integrated circuit device 400 and / or a smaller overall device size.

[0058] RF losses can have the greatest impact on the performance of an integrated circuit device at high frequencies and where the strongest possible signal is desired. Thus, the hybrid coating 412 with high aspect ratio vias 414A-414D can be particularly useful for high frequency applications of the integrated circuit device 400. For example, the hybrid coating 412 with high aspect ratio vias 414A-414D may provide benefits for 5G broadband cellular network technologies and other high frequency GaN on SiC or GaN on Si MMICs.

[0059] Discussion of possible embodiments The following is a non-exclusive description of possible embodiments of the present invention.

[0060] An interconnect layer for an integrated circuit device includes a low radio frequency (RF) loss primary coating forming a major portion of the interconnect layer, an opening formed in the primary coating, a high aspect ratio patternable secondary coating within the opening, and a via formed in the secondary coating, the aspect ratio of the via being greater than the aspect ratio of the opening.

[0061] The interconnect layer of the preceding paragraph may optionally, additionally, and / or alternatively include any one or more of the following features, configurations, and / or additional components.

[0062] The primary coating can have a different composition than the secondary coating.

[0063] The primary coating may be a benzocyclobutene (BCB) based polymer.

[0064] The secondary coating may be a high contrast epoxy-based negative photoresist (SU-8) with an average of 8 epoxy functional groups per moiety.

[0065] The RF loss tangent of the primary coating may be less than the RF loss tangent of the secondary coating.

[0066] The effective thickness of the secondary coating may be at least as thick as the thickness of the primary coating.

[0067] The aspect ratio of the via 24 may be greater than 0.6.

[0068] The aspect ratio of the via 24 may be greater than 1.0.

[0069] The via diameter may be less than 60 micrometers (μm) and the primary coating thickness may be greater than 20 μm.

[0070] The via diameter may be less than 20 μm.

[0071] The thickness of the primary coating may be greater than 30 μm.

[0072] The integrated circuit device includes a wafer, a low radio frequency (RF) loss primary coating at least partially covering the wafer, an opening formed in the primary coating to expose a feature located on the wafer, a high aspect ratio patternable secondary coating within the opening, and a via formed in the secondary coating, the aspect ratio of the via being greater than the aspect ratio of the opening.

[0073] The integrated circuit device of the preceding paragraph may optionally, additionally, and / or alternatively include any one or more of the following features, configurations, and / or additional components.

[0074] The primary coating can have a different composition than the secondary coating.

[0075] The primary coating may be a benzocyclobutene (BCB) based polymer.

[0076] The secondary coating may be a high contrast epoxy-based negative photoresist (SU-8) with an average of 8 epoxy functional groups per moiety.

[0077] The integrated circuit device may be a monolithic microwave integrated circuit (MMIC).

[0078] Integrated circuit devices can have operating frequencies greater than 10 GHz.

[0079] A method for reducing radio frequency (RF) losses from an integrated circuit device includes depositing a low RF loss primary coating on an integrated circuit device wafer, forming openings in the primary coating to expose features located on the wafer, depositing a high aspect ratio patternable secondary coating in the openings, and forming vias in the secondary coating.

[0080] The method of the preceding paragraph may optionally, additionally, and / or alternatively include any one or more of the following features, configuration acts, and / or additional components.

[0081] The primary coating can have a different composition than the secondary coating.

[0082] The primary coating may be a benzocyclobutene (BCB) based polymer and the secondary coating may be a high contrast epoxy based negative photoresist (SU-8) with an average of 8 epoxy functional groups per moiety.

[0083] The method may further include operating the integrated circuit device at a frequency greater than 10 GHz.

[0084] Although the present invention has been described with reference to exemplary embodiment(s), those skilled in the art will recognize that various modifications can be made and equivalents can be substituted for elements of the embodiments without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the present invention not be limited to the particular embodiment(s) disclosed, but will include all embodiments falling within the scope of the appended claims.

Claims

1. An interconnect layer, a low radio frequency (RF) loss primary coating forming a major portion of said interconnect layer; an opening formed in the primary coating; a high aspect ratio patternable secondary coating within said opening; a via formed in the secondary coating; an aspect ratio of the via is greater than an aspect ratio of the opening; An interconnect layer for an integrated circuit device.

2. The interconnect layer of claim 1 , wherein the primary coating has a different composition than the secondary coating.

3. The interconnect layer of claim 2 , wherein the primary coating is a benzocyclobutene (BCB) based polymer.

4. The interconnect layer of claim 2, wherein said secondary coating is a high contrast epoxy-based negative photoresist (SU-8) with an average of 8 epoxy functional groups per moiety.

5. The interconnect layer of claim 1 , wherein the RF loss tangent of the primary coating is less than the RF loss tangent of the secondary coating.

6. The interconnect layer of claim 1 , wherein the effective thickness of the secondary coating is at least as thick as the thickness of the primary coating.

7. The interconnect layer of claim 1 , wherein the aspect ratio of the via is greater than 0.

6.

8. The interconnect layer of claim 7 , wherein the aspect ratio of the via is greater than 1.

0.

9. The interconnect layer of claim 1 , wherein the via has a diameter less than 60 micrometers (μm) and the primary coating has a thickness greater than 20 μm.

10. The interconnect layer of claim 9 , wherein the diameter of the via is less than 20 μm.

11. A wafer; a low radio frequency (RF) lossy primary coating at least partially covering the wafer; an opening formed in the primary coating to expose a feature located on the wafer; a high aspect ratio patternable secondary coating within said opening; a via formed in the secondary coating; wherein an aspect ratio of the via is greater than an aspect ratio of the opening.

12. The integrated circuit device of claim 11 , wherein the primary coating has a different composition than the secondary coating.

13. The integrated circuit device of claim 12 , wherein the primary coating is a benzocyclobutene (BCB) based polymer.

14. 13. The integrated circuit device of claim 12, wherein said secondary coating is a high contrast epoxy-based negative photoresist (SU-8) with an average of 8 epoxy functional groups per moiety.

15. The integrated circuit device of claim 11 , wherein the integrated circuit device is a monolithic microwave integrated circuit (MMIC).

16. The integrated circuit device of claim 11 , wherein the integrated circuit device has an operating frequency greater than 10 GHz.

17. 1. A method for reducing radio frequency (RF) losses from an integrated circuit device, comprising: depositing a low RF loss primary coating on an integrated circuit device wafer; forming an opening in the primary coating to expose a feature located on the wafer; depositing a high aspect ratio patternable secondary coating within said opening; forming a via in the secondary coating; Including, method.

18. The method of claim 17 , wherein the primary coating has a different composition than the secondary coating.

19. 20. The method of claim 18, wherein the primary coating is a benzocyclobutene (BCB) based polymer and the secondary coating is a high contrast epoxy-based negative photoresist (SU-8) with an average of 8 epoxy functional groups per moiety.

20. 20. The method of claim 17, further comprising operating the integrated circuit device at a frequency greater than 10 GHz.

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