On-chip distribution of test data to multiple dies

Abstract

A multi-die integrated circuit [102] uses an on-chip test distribution module to distribute test data [105] to different dies, such as processor chiplets 104, 106, 108, 110. The test distribution module receives test input data [220] from an external source [115] via one or more integrated circuit pins [112] and distributes the test input data to the different dies such that the different dies can apply the test data to one or more circuits simultaneously. Based on the application of the test input data, the different dies simultaneously generate corresponding test results [325] that are used to identify and address design or operational errors in the dies.

Description

[Background technology]

[0001] To improve processing performance and efficiency, some processors are implemented as integrated circuits having multiple functional dies, each functional die including circuitry for implementing a corresponding set of functions, such as processing functions, memory functions, etc. For example, some processors employ a chiplet-based design, where each of multiple processor dies implements a corresponding processor chiplet, and each chiplet is designed and configured to perform at least a subset of designated processor operations, such as central processing unit (CPU) operations, graphics processing unit (GPU) operations, etc. The chiplets and other processor dies (e.g., memory dies) are arranged in a three-dimensional stack, and the stack is placed in an integrated circuit package, which includes multiple pins that allow access to different signal paths of the dies. Because multiple functional dies are in the same integrated circuit package, the dies can communicate and coordinate processing operations efficiently and by consuming relatively little power. However, performing tests, such as tests to verify proper operation of individual functional dies, is typically inefficient and expensive.

[0002] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief description of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a processor test system including on-chip distribution of test data for multiple dies of a processor under test, according to some embodiments. [Diagram 2] 2 is a block diagram illustrating an example of the processor of FIG. 1 distributing test data to different processor chiplets in accordance with some embodiments. [Diagram 3] 3 is a block diagram illustrating an example of the chiplet of FIG. 2 that provides test output data for comparison with expected test results, in accordance with some embodiments. [Figure 4] 2 is a block diagram illustrating an example of a test distribution module of the processor of FIG. 1 according to some embodiments. [Diagram 5] 2 is a block diagram illustrating an example of the processor of FIG. 1 selectively distributing test data to different processor chiplets based on chiplet type, in accordance with some embodiments. [Figure 6] FIG. 2 is a flow diagram illustrating a method for distributing test data in a processor having multiple functional dies, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] 1-6 illustrate a technique for distributing test data to different dies, such as processor chiplets, of a multi-die integrated circuit using an on-chip test distribution module. The test distribution module receives test input data from an external source via one or more integrated circuit pins and distributes the test input data to the different dies such that the different dies can simultaneously apply the test data to one or more circuits. Based on the application of the test input data, the different dies simultaneously generate corresponding test results that are used to identify and address design or operational errors in the dies. Because the test input data is distributed via the on-chip module, test data can be provided to the integrated circuit relatively efficiently without requiring a large number of dedicated test pins, thus simplifying integrated circuit design and saving testing and development time and resources.

[0005] To explain, for conventional single-die integrated circuits, such as conventional processors, test data is applied to the integrated circuit in one of two ways: serially through a relatively small number of dedicated test pins, or in parallel through a larger number of dedicated test pins. For multi-die integrated circuits, it is desirable to test each individual die so that errors in any individual die can be identified and addressed. However, dedicating test pins to each individual die for parallel application of test data requires a large number of dedicated pins, which either increases the overall size of the integrated circuit or requires reuse of pins that may be used for operations other than testing. Furthermore, serially applying test data to a multi-die integrated circuit requires a relatively long time since the same test data is repeatedly applied to input pins for different individual dies. In contrast, using the techniques described herein, a multi-die integrated circuit can be tested using a relatively small number of dedicated test pins, without requiring a large amount of test time and other resources.

[0006] 1-6 are described with respect to an exemplary integrated circuit including multiple dies forming a processor, according to some embodiments. However, it will be understood that in other embodiments, the techniques described herein are implemented in other types of integrated circuits. For example, in some embodiments, the techniques described herein are implemented in an integrated circuit including a memory, such as a memory module having multiple integrated circuit dies. Additionally, as used in this disclosure, the terms "die" and "chip" are used interchangeably. Similarly, the terms "integrated circuit die" and "semiconductor die" are used interchangeably.

[0007] 1 illustrates a block diagram of a processor 102 including a test distribution module 105 generally configured to distribute test data received from an external test controller 115 and distribute the received test data to different semiconductor dies. The processor 102 is generally configured to execute a set of instructions to perform designated tasks on behalf of an electronic device. Thus, in different embodiments, the processor 102 is incorporated into any of a number of different types of electronic devices, including desktop computers, laptop computers, servers, smartphones, tablets, game consoles, etc.

[0008] The processor 102 is constructed as a multi-chip module (e.g., a semiconductor die package) that includes two or more base integrated circuit dies that are communicatively coupled together with a bridge chip such that the processor 102 is usable (e.g., addressable) like a single semiconductor integrated circuit. Those skilled in the art will recognize that conventional (e.g., non-multi-chip) semiconductor integrated circuits are manufactured as wafers or as dies (e.g., single-chip ICs) that are formed in a wafer and later separated from the wafer (e.g., when the wafer is diced), and often multiple ICs are manufactured simultaneously in a wafer. The ICs and possibly discrete circuits, and possibly other components (e.g., silicon interposers, non-semiconductor packaging substrates such as printed circuit boards, non-silicon, interposers, and possibly others, etc.) are assembled into a multi-die processor.

[0009] In various embodiments, the processor 102 includes one or more base IC dies (e.g., base die 101) that employ processing stacked die chiplets according to some embodiments. The base die is formed as a single semiconductor chip package that includes N communicatively coupled stacked die chiplets. For example, in the illustrated embodiment, the processor 102 includes four chiplets, designated chiplets 104, 106, 108, 110. For ease of illustration and explanation, various embodiments are described below in the specific context of CPU chiplets and GPU chiplets, however, it should be appreciated that the concepts described herein are similarly applicable to other processors, including accelerated processing units (APUs), discrete GPUs (dGPUs), artificial intelligence (AI) accelerators, other parallel processors, and the like. For example, in some embodiments, the processor 102 includes multiple dies connected via a silicon communications bridge, an embedded multi-die interconnect (EMIB), an embedded fanout bridge (EFB), etc.

[0010] In various embodiments, the term "chiplet" as used herein refers to any device that includes, but is not limited to, the following characteristics: 1) a chiplet includes active silicon dies that include at least a portion of the computational logic used to solve a complete problem (i.e., the computational workload is distributed across multiple of these active silicon dies); 2) the chiplets are packaged together as a monolithic unit on the same substrate; and 3) the programming model used to control a particular set of chiplets maintains the notion that the combination of these individual computational dies (e.g., a set of graphics processing stack die chiplets) is a single monolithic unit. That is, each chiplet of a particular set is not exposed as an individual device to an application that uses the set of chiplets to process a computational workload, but instead, the set of chiplets is exposed to the application such that it collectively appears as an integrated processing unit, such as a graphics processing unit (GPU) or central processing unit (CPU). For example, AMD Ryzen Threadripper includes multiple CPU chiplets. Furthermore, in some embodiments, the processor 102 includes multiple sets of chiplets that are exposed together to an application as distinct processing units. For example, in some embodiments, chiplets 104 and 110 form a set of CPU chiplets that together appear to applications as a single CPU, and chiplets 106 and 108 form a set of GPU chiplets that together appear to applications as a single GPU. As will be appreciated by those skilled in the art, although CPU chiplets and GPU chiplets are first and second die types, chiplets including other die types may also be included in various embodiments.For example, chiplets including one or more of digital signal processors (DSPs), field programmable gate arrays (FPGAs), neural processing units (NPUs), and others may be used.

[0011] In various embodiments, the processor 102 includes an inter-chip data fabric (not shown) that acts as a high-bandwidth die-to-die interconnect between the chiplets. Additionally, in various embodiments, each of the chiplets 104, 106, 108, 110 includes one or more levels of cache memory and one or more memory PHYs (not shown) for communicating with external system memory modules, such as dynamic random-access memory (DRAM) modules.

[0012] Test distribution module (TDM) 105 is a set of circuits generally and collectively configured to receive test data from an external test controller 115 via a set of integrated circuit (IC) pins 112. In different embodiments, IC pins 112 are any type of interconnect or terminal that allows for communication of electrical signals from an external device, such as test controller 115, to internal modules of the integrated circuit formed by processor 102.

[0013] In some embodiments, the test controller 115 is generally a computing device configured to generate test input data and corresponding expected test results. For example, in some embodiments, the test controller 115 simulates the operation of the chiplets 104, 106, 108, 110 to determine, based on a particular string of input data, corresponding output data that would be generated by the chiplet if the chiplet were operating properly. The test controller 115 uses the simulation to generate the test input data and corresponding expected test results. Furthermore, in some embodiments, the test input data generated by the test controller 115 includes multiple test input data strings, each test input data string corresponding to a different expected test result, and each input data string configured to test a different portion or operation of one or more of the chiplets 104, 106, 108, 110.

[0014] In some embodiments, the TDM 105 is configured to receive test input data from the test controller 115 via the IC pins 112. In response, the TDM distributes a copy of the test input data to each of the chiplets 104, 106, 108, 110 (chiplets 104-110). In response to the test data, each of the chiplets 104-110 generates a corresponding test output result for comparison to an expected test result. Thus, in at least some embodiments, the data provided at the IC pins 112 is distributed to multiple chiplets among the chiplets 104-110. In other words, the test input data provided at any of the IC pins 112 is copied and provided to multiple chiplets among the chiplets 104-110. The test controller 115 can provide the test data to each of the chiplets 104-110 using a relatively small set of the IC pins 112, in particular without requiring a different set of dedicated test pins for each of the chiplets 104-110.

[0015] For example, in some embodiments, TDM 105 applies copies of test input data to corresponding input terminals of each of chiplets 104-110. One or more clock signals (not shown) are applied to chiplets 105-110 by either test controller 115, TDM 105, or a combination thereof, causing chiplets 104-110 to perform one or more operations based on the test input data. This causes chiplets 104-110 to generate test output data at corresponding sets of output terminals after a designated number of clock signals. In some embodiments, TDM 105 receives the test output data from chiplets 104-110 and provides the test output data to test controller 115 via IC pins 112. In response, test controller 115 compares the test output data for each of chiplets 104-110 to expected test results and identifies any errors based on the comparison.

[0016] In another embodiment, test controller 115 provides the expected test results along with the test input data to TDM 105. In response to receiving the test output results from chiplets 104-110, TDM 105 compares the test output results to the expected test results. Based on the comparison, TDM 105 provides signals to test controller 115 (e.g., via IC pins 112) indicating any matches or mismatches. For example, in response to identifying a mismatch between the test output data generated by chiplet 106 and the expected test results and identifying a match between the test output data generated by chiplets 104, 108, 110 and the expected test results, TDM 105 provides signals to test controller 115 indicating an error in chiplet 106 and indicating satisfactory results in chiplets 104, 108, 110.

[0017] In some embodiments, test controller 115 provides one or more test masks to TDM 105 and provides control information indicating which of the one or more masks should be applied to the test output data. Based on the control information, TDM 105 selects one of the provided masks and applies the mask to the received test output data, thereby generating masked test output data. In some embodiments, TDM 105 then provides masked test input data to test controller 115 via IC pins 112. In other embodiments, TDM 105 uses the masked test data to compare to expected test results and indicates any errors to test controller 115 via IC pins 112 based on the comparison.

[0018] In some embodiments, the test controller 115 provides control information to the TDM 105 to select a subset (e.g., less than all) of the chiplets 104-110 for application of test input data. Based on the control information, the test controller 115 selects the indicated subset of the chiplets 104-110 and provides test input data to only the chiplets in the selected subset. This allows the test controller 115 to test only certain chiplets of the chiplets 104-110, such as only chiplets having the same chiplet type (e.g., only GPU chiplets or only CPU chiplets). This also allows the TDM 115 and the test controller 115 to test a processor that includes chiplets of one type (e.g., CPU chiplets) and also chiplets of a second type (e.g., GPU). In some embodiments, the chiplets 104-110 communicate with the TDM 115 via an interposer, such as a silicon interposer, a silicon bridge, or a silicon substrate, or the like, or any combination thereof.

[0019] 2 illustrates an example of a TDM 105 distributing test data to chiplets 104-110, according to some embodiments. In the illustrated example, test controller 115 provides test input data 220 to TDM 105 via input pins 112. In response, TDM 105 provides test input data 220 to each of chiplets 104, 106, 108, 110. In at least some embodiments, TDM 105 provides test data 220 to each of chiplets 104-106 simultaneously. This allows chiplets 104-106 to generate corresponding test output data simultaneously, resulting in reduced test time for processor 102.

[0020] 3 shows an example of providing chiplets 104-110 providing test output data to TDM 105, according to some embodiments. In the illustrated example, each of chiplets 104-110 has test output data generated based on test input data 220 (FIG. 2). Specifically, chiplet 104 generates test output data 324, chiplet 106 generates test output data 321, chiplet 108 generates test output data 323, and chiplet 110 generates test output data 322.

[0021] In the illustrated example, TDM 105 stores a set of expected test results 326. In at least some embodiments, the expected test results are provided to TDM 105 by test controller 115 via IC pins 112. In response to chiplets 104-110 generating test output data, TDM 105 compares each test output data to expected test results 326. That is, TDM 105 compares each of test output data 321, 322, 323, 324 to expected test results 326. Based on the comparison, TDM 105 generates chiplet test results 325. In at least some embodiments, chiplet test results 325 indicate which of test output data 321, 322, 323, 324 match expected test results 326. Thus, for example, in some embodiments, chiplet test results 325 include a four-bit field, with each bit corresponding to a different one of the chiplets 104-110, and the state of each bit indicating whether the corresponding test output data matches expected test results 326. TDM 105 provides chiplet test results 325 to test controller 115 via IC pins 112, and in response, test controller 115 uses chiplet test results 325 to identify any errors in the chiplets 104-110.

[0022] FIG. 4 illustrates a block diagram of TDM 105, according to some embodiments. In the illustrated example, TDM 105 includes a chiplet selection module 432, a mask control module 436, a set of test data registers 437, and a set of chiplet interconnects 438. Test data registers 437 are a set of registers configured to store test input data for distribution to chiplets 104-110 and to store the resulting test output data. Thus, in some embodiments, test data registers 437 store test input data 220 (FIG. 2) and store corresponding test output data 321, 322, 323, 324 (FIG. 3). In some embodiments, test data registers 437 store any control information provided by test controller 115, and further store any masks provided by test controller 115 for application to the test output data.

[0023] The chiplet interconnects 438 are a set of interconnects between the TDM 105 and the chiplets 104-110. Thus, the interconnects 438 enable the TDM to provide stored test input data to one or more of the chiplets 104-110 and receive resulting test output data from the chiplets 104-110. In some embodiments, the chiplet interconnects 438 are a set of dedicated electrical connections between the TDM 105 and the chiplets 104-110. In other embodiments, the interconnects 438 are a switching fabric or other controllable interconnects between the TDM 105 and the chiplets 104-110, and the TDM 105 controls the chiplet interconnects 438 to establish or disconnect individual connections to the chiplets 104-110.

[0024] The chiplet selection module 432 is a module that controls which of the chiplets 104-110 receive the test input data. For example, in some embodiments, the test controller 115 provides, along with the test input data, control information indicating a selected subset of the chiplets 104-110 that will receive the test input data. Based on the test input data, the chiplet selection module 432 controls the chiplet interconnects 438 such that the test input data is provided to only the selected subset of the chiplets 104-110.

[0025] Mask control module 434 is a module that applies a mask to the test output data in test data registers 437. For example, in some embodiments, test controller 115 provides test input data to one or more masks. Mask control module 434 identifies the provided mask and applies the provided mask to the test output data in test data registers 437. This allows TDM 105 to provide test controller 115 with finer control over the particular test output data that is used for comparison to expected test results. For example, by applying a mask to the test output data, TDM 115 can test particular portions of chiplets 104-110. In some embodiments, a mask is used to mask all test output data from particular ones of chiplets 104-110, such that only a selected subset of chiplets 104-110 is tested.

[0026] The result comparison module 436 is a module that compares the test output data generated by the chiplets 104-110 to the expected test results 326. For example, in some embodiments, the result comparison module 426 includes a set of comparators, with each comparator configured to compare a bit of the test output data for one of the chiplets 104-110 to a corresponding bit of the expected test results 326. Thus, the result comparison module generates a comparison for each bit of the generated test output data with the corresponding bit of the expected test results 326. In some embodiments, the result comparison module 436 logically combines the results of the comparisons (e.g., by performing an OR operation using the results of the comparisons for a given set of test output data) to generate a single comparison value for each of the chiplets 104-110. The result comparison module 436 collates the results of the logical combinations to generate the chiplet test results 325 for provision to the test controller 115.

[0027] As discussed above, in some cases, TDM 105 provides test input data to only a selected subset of chiplets 104-110. An example according to some embodiments is shown in FIG. 5. In the illustrated example, TDM 105 receives test input data 540 via IC pins 112. In addition, assume that test controller 115 provides control data (not shown) to TDM 105 indicating which of chiplets 104-110 should receive test data 540. Thus, in the example of FIG. 5, based on the control information, TDM provides test data 540 only to chiplets 106 and 108 and does not provide test data 540 to chiplets 104 and 110. Thus, TDM 105 supports selective testing of different chiplets 104-110. For example, in some embodiments, chiplets 104 and 110 are a particular type of chiplet, such as a CPU chiplet, and chiplets 106 and 108 are a different type of chiplet, such as a GPU chiplet. Thus, chiplets 104 and 110 have different circuitry and are tested with different test input data than chiplets 106 and 108. By allowing test controller 115 to select a subset of chiplets 104-110 to be tested independently, TDM 105 supports flexible testing of different chiplets without requiring a large number of dedicated test pins.

[0028] 6 illustrates a flow diagram of a method 600 for distributing test data in a multi-chip integrated circuit in accordance with some embodiments. For purposes of illustration, the method 600 is described with respect to an exemplary implementation in the processor 102 of FIG. 2, although it will be understood that in other embodiments, the method 600 is implemented in a different multi-chip integrated circuit.

[0029] In block 602, TDM 105 receives test input data 220 via IC pins 112. In response, in block 604, TDM 105 selects one of chiplets 104-110 to be tested. In some embodiments, TDM 105 selects the chiplet based on control information provided via IC pins 112. In block 606, TDM 105 distributes test input data 220 to each of the selected chiplets simultaneously.

[0030] In response to receiving the test input data 220, each of the selected chiplets generates corresponding test output data. At block 608, the TDM 105 receives the test output data from each of the selected chiplets. At block 610, the TDM 105 compares the received test output data to the expected test results 326. Based on the comparison, at block 612, the TDM 105 generates chiplet test results 325 and provides the chiplet test results to the test controller 115 via the IC pins 112.

[0031] As disclosed herein, in some embodiments, an integrated circuit includes a plurality of semiconductor dies in a multi-chip module, a set of pins configured to receive test input data, and a test distribution module configured to distribute the received test input data to at least a subset of the plurality of semiconductor dies. In one aspect, the test distribution module is configured to receive test output data from each of the plurality of semiconductor dies. In another aspect, the test distribution module provides chip test results based on the received test output data. In yet another aspect, the test distribution module determines chip test results based on a comparison of the test output data to a set of expected test results. In yet another aspect, the test distribution module is configured to receive the expected test results via the set of pins.

[0032] In one aspect, the test distribution module is configured to apply a mask to test output data generated by one or more of the plurality of semiconductor dies. In another aspect, the test distribution module is configured to receive the mask via a set of pins. In yet another aspect, the test distribution module is configured to select a plurality of semiconductor dies to receive the test input data based on the received control information. In yet another aspect, the test distribution module receives the control information via a set of pins. In another aspect, the plurality of dies comprises a set of processing unit chiplets.

[0033] In some embodiments, an integrated circuit includes a plurality of semiconductor dies in a multi-chip module, a set of pins configured to receive test input data, and a test distribution module configured to select a subset of the plurality of semiconductor dies and distribute the received test input data to the selected subset of the plurality of semiconductor dies. In one aspect, the test distribution module is configured to receive test output results from each of the selected subset of the plurality of semiconductor dies. In another aspect, the test distribution module provides chip test results based on the test output results received via the set of pins. In yet another aspect, the test distribution module is configured to apply a mask to the test output data generated by one or more of the plurality of semiconductor dies. In yet another aspect, the plurality of semiconductor dies communicate with the test distribution module via an interposer.

[0034] In one aspect, the interposer comprises one or more of a silicon interposer, a silicon bridge, or a silicon substrate. In another aspect, the plurality of semiconductor dies includes at least one die of a first type and at least one die of a second type. In yet another aspect, the plurality of semiconductor dies comprises at least one die of a third type.

[0035] In some embodiments, a method includes receiving test input data at a set of pins of an integrated circuit comprising a multi-chip module and distributing the test input data to at least a subset of a plurality of dies of the integrated circuit. In one aspect, the method includes generating test output data at each of the plurality of dies based on the test input data and generating test results based on a comparison of the test output data to expected test results.

[0036] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by the one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s), etc. The executable instructions stored in the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0037] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0038] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and features by which any benefit, advantage, or solution may occur or be manifested are not to be construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as set forth in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. a plurality of semiconductor dies in a multi-chip module; a set of pins configured to receive test input data; a test distribution module configured to distribute received test input data to at least a subset of the plurality of semiconductor dies. Integrated circuits.

2. the test distribution module configured to receive test output data from each of the plurality of semiconductor dies.

2. The integrated circuit of claim 1.

3. the test distribution module providing chip test results based on the received test output data; 3. The integrated circuit of claim 2.

4. the test distribution module determines the chip test results based on a comparison of the test output data to a set of expected test results.

3. The integrated circuit of claim 2.

5. the test distribution module is configured to receive the expected test results via the set of pins.

5. The integrated circuit of claim 4.

6. the test distribution module is configured to apply a mask to test output data generated by one or more of the plurality of semiconductor dies.

2. The integrated circuit of claim 1.

7. the test distribution module is configured to receive the mask via the set of pins.

7. The integrated circuit of claim 6.

8. the test distribution module is configured to select a number of semiconductor dies to receive the test input data based on the received control information.

8. An integrated circuit according to any one of claims 1 to 7.

9. the test distribution module receives the control information via the set of pins.

9. The integrated circuit of claim 8.

10. the plurality of dies comprises a set of processing unit chiplets; 2. The integrated circuit of claim 1.

11. a plurality of semiconductor dies in a multi-chip module; a set of pins configured to receive test input data; a test distribution module configured to select a subset of the plurality of semiconductor dies and distribute received test input data to the selected subset of the plurality of semiconductor dies. Integrated circuits.

12. the test distribution module configured to receive test output results from each of a selected subset of the plurality of semiconductor dies.

12. The integrated circuit of claim 11.

13. the test distribution module providing chip test results based on test output results received via the set of pins.

13. The integrated circuit of claim 12.

14. the test distribution module is configured to apply a mask to test output data generated by one or more of the plurality of semiconductor dies.

14. The integrated circuit according to any one of claims 11 to 13.

15. the plurality of semiconductor dies communicate with the test distribution module via an interposer; 12. The integrated circuit of claim 11.

16. the interposer comprises one or more of a silicon interposer, a silicon bridge, or a silicon substrate; 16. The integrated circuit of claim 15.

17. the plurality of semiconductor dies comprises at least one die of a first type and at least one die of a second type; 12. The integrated circuit of claim 11.

18. the plurality of semiconductor dies comprises at least one third type die; 20. The integrated circuit of claim 17.

19. receiving test input data at a set of pins of an integrated circuit comprising a multi-chip module; distributing the test input data to at least a subset of a plurality of dies of the integrated circuit. method.

20. generating test output data at each of the plurality of dies based on the test input data; generating test results based on a comparison of the test output data to expected test results.

20. The method of claim 19.

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