System and method for reducing induced ground bounce voltage in motor drivers - Patents.com

Abstract

A driver system (100) operable to provide a drive signal to a motor includes a system input (106) adapted to be coupled to an input voltage and a system output (110) adapted to be coupled to the motor. The driver system (100) includes a high-side transistor having a first terminal (104) coupled to the system input (106) and a second terminal (108) coupled to the system output (110) and having a control terminal (112). The driver system (100) includes a low-side transistor having a first terminal (120) coupled to the system output (110) and a second terminal (122) coupled to a reference potential terminal (124) and having a control terminal (126). The driver system (100) includes a low-side gate control circuit that provides a first level of current in response to a low-side digital control signal transitioning from a low state to a high state and that provides a second level of current when the output voltage is less than an upper reference voltage.

Description

[Technical field]

[0001] The present description relates generally to motor drivers. [Background technology]

[0002] Electric motors are found in automobiles, industrial fans and pumps, machine tools, household appliances, drones, gimble, and disk drives. Electric motors are generally operated by a motor driver circuit that may include high-side and low-side transistors arranged in a bridge configuration. In some configurations, a pair of high-side / low-side transistors is used for each phase of the motor. The high-side transistor is coupled between an input voltage terminal and an output voltage terminal, and the low-side transistor is coupled between the output voltage terminal and a common potential (e.g., ground) terminal. The high-side and low-side transistors have respective body diodes. When the motor driver circuit is implemented in an integrated circuit (IC), there is some bondwire inductance due to the bondwires connecting the input voltage terminal to an external connector (e.g., an external pin of the IC) and there is another bondwire inductance due to the bondwires connecting the ground terminal to the external connector.

[0003] When the low-side transistor turns on, the current through the high-side body diode begins to decrease while the current through the low-side transistor begins to increase due to the reverse recovery time of the high-side body diode. Because the high-side body diode is fully reverse biased to prevent current from flowing through the high-side body diode, the low-side transistor draws a current that may have a larger magnitude than the current through the motor (the motor current Im) to account for the reverse recovery charge stored in the high-side body diode. As a result, the current through the low-side transistor will be higher than the motor current Im, reach a positive peak and then drop to Im. Because the low-side transistor draws a current that is greater than the motor current Im, a portion of the current through the low-side transistor is drawn from the input voltage through the high-side body diode from the cathode to the anode (i.e., in the reverse direction). Therefore, the current through the high-side body diode drops below zero, reaches a negative peak and then rises back to zero. A rising current through the low-side transistor induces a positive voltage across the bondwire inductance, and a falling current through the low-side transistor induces a negative voltage across the bondwire inductance. The induced voltage across the bondwire is generally equal to the ground bounce voltage VB It's called INT.

[0004] Ground bounce voltage VB Since INT is present at the source of the low-side transistor, VB INT specifies the voltage that must be applied to the gate of the low-side transistor to turn it on. VB INT increases the voltage drop between the drain and source of the low-side transistor.

[0005] VB If INT is +5V, the driver circuit must apply (Vt+5V) to the gate to turn on the low-side transistor (Vt is the threshold voltage required to turn on the low-side transistor). So, if Vt is +5V, the driver circuit must apply +10V to the gate to turn on the low-side transistor. VB If INT is -4V, the driver circuit needs to apply +1V to the gate of the low-side transistor to turn it on. Also, if VB_INT is -4V and Vout is 15V, the voltage across the low-side transistor will rise to 19V.

[0006] Ground bounce voltage VB One approach to mitigate the impact of INT is to use VB The solution is to use additional circuitry that tracks INT and applies a corresponding gate-source voltage to turn on the low-side transistor, and to use a higher rated transistor that can withstand a high voltage drop between the drain and source. Summary of the Invention

[0007] In one aspect, a driver system operable to provide a drive signal to a motor includes a system input adapted to be coupled to an input voltage and a system output adapted to be coupled to the motor. The driver system includes a high-side transistor having a first terminal coupled to the system input, a second terminal coupled to the system output, and a control terminal. The driver system includes a low-side transistor having a first terminal coupled to the system output, a second terminal coupled to a reference potential terminal, and a control terminal. The driver system includes a low-side gate control circuit having a first input coupled to the system output, a second input adapted to receive an upper reference voltage, a third input adapted to receive a low-side digital control signal, a fourth input adapted to be coupled to a voltage source, and an output coupled to the control terminal of the low-side transistor. The low-side gate control circuit provides a first level of current at an output of the low-side gate control circuit in response to the low-side digital control signal transitioning from a low state to a high state, and provides a second level of current greater than the first level of current when the drive signal is less than the upper reference voltage.

[0008] In another aspect, the low side gate control circuit maintains a first level of current until the drive signal falls below an upper reference voltage to reduce an induced ground bounce voltage at the reference potential terminal.

[0009] In another aspect, the low side gate control circuit maintains a first level of current to reduce an induced ground bounce voltage at the reference potential terminal by reducing the rate of change of current through the low side transistor until the drive signal falls below the upper reference voltage.

[0010] In another aspect, the low side gate control maintains a first level of current lower than a second level of current to reduce the rate of change of current through the low side transistor until the drive signal falls below the upper reference voltage.

[0011] In another aspect, the low side gate control circuit provides a second level of current when the low side transistor transitions into the Miller region.

[0012] In another aspect, the low side gate control provides a third level of current to the control terminal of the low side transistor to turn off the low side transistor in response to the low side digital control signal transitioning from a high state to a low state.

[0013] In another aspect, the low side gate control circuit includes a first comparison circuit having a first input coupled to the system output and a second input adapted to receive an upper reference voltage, the first comparison circuit providing a slew start signal at an output in response to the drive signal falling below the upper reference voltage.

[0014] In another aspect, the low-side digital control circuit includes a reverse recovery current source having a first terminal adapted to be coupled to a voltage source and having a second terminal. The low-side gate control circuit includes a reverse recovery switch having a first terminal coupled to the second terminal of the reverse recovery current source, a second terminal coupled to the control terminal of the low-side transistor, a third terminal coupled to an output of the first comparison circuit, and a fourth terminal adapted to receive the low-side digital control signal. The reverse recovery switch couples the reverse recovery current source to the control terminal of the low-side transistor in response to the low-side digital control signal transitioning from a low state to a high state, and disconnects the reverse recovery current source from the control terminal of the low-side transistor in response to assertion of the slew start signal by the first comparison circuit.

[0015] In another aspect, the low side gate control circuit includes a first slew current source having a first terminal coupled to the voltage source and having a second terminal. The low side gate control circuit includes a first slew current switch having a first terminal coupled to the second terminal of the first slew current source, a second terminal coupled to the control terminal of the low side transistor, a third terminal coupled to the output of the first comparison circuit, and a fourth terminal adapted to receive a low side digital control signal. The first slew current switch couples the first slew current source to the control terminal of the low side transistor in response to assertion of the slew start signal by the first comparison circuit.

[0016] In another aspect, the low-side gate control circuit includes a second through current source having a first terminal coupled to the reference potential terminal and having a second terminal. The low-side gate control circuit includes a second through current switch having a first terminal coupled to the control terminal of the low-side transistor, a second terminal coupled to the second terminal of the second through current source, and a third terminal adapted to receive a low-side digital control signal. The second through current switch couples the second through current source to the control terminal of the low-side transistor to turn off the low-side transistor in response to the digital control signal transitioning from a high state to a low state.

[0017] In another aspect, a driver system operable to provide an output voltage to a motor includes a system input adapted to be coupled to an input voltage and a system output adapted to be coupled to the motor. The driver system includes a high-side transistor having a first terminal coupled to the system input and a second terminal coupled to the system output and having a control terminal. The driver system includes a low-side transistor having a first terminal coupled to the system output, a second terminal coupled to a reference potential terminal and a control terminal. The driver system includes a low-side gate control circuit having a first input coupled to the system output, a second input adapted to receive an upper reference voltage, a third input adapted to receive a low-side digital control signal, a fourth input adapted to be coupled to a voltage source, and an output coupled to the control terminal of the low-side transistor. The low side gate control circuit provides a first level of current to the control terminal of the low side transistor, maintains the first level of current at the control terminal of the low side transistor to reduce the ground bounce voltage at the reference potential terminal until the output voltage falls below the upper reference voltage, and provides a second level of current to the control terminal of the low side transistor in response to assertion of the slew start signal. [Brief description of the drawings]

[0018] [Figure 1] 1 is a schematic diagram of an example driver system.

[0019] [Diagram 2] 2 is an example waveform generated by the driver system of FIG. 1.

[0020] [Diagram 3] FIG. 2 is a block diagram of an example control circuit.

[0021] [Figure 4] FIG. 2 is an example schematic diagram of a comparison circuit.

[0022] In the drawings, the same reference numbers or other feature designators are used to denote the same or similar (functional and / or structural) features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] 1 illustrates an example driver system 100. The system 100 includes a high-side transistor MH having a first terminal 104 (e.g., drain) coupled to an input 106. The high-side transistor MH has a second terminal 108 (e.g., source) coupled to an output 110. The high-side transistor MH has a control terminal 112 (e.g., gate). The high-side transistor MH includes a body diode DHB with an anode coupled to the source 108 and a cathode coupled to the drain 104.

[0024] In some embodiments, the driver system 100 can be implemented in an integrated circuit (IC). A bondwire inductance LBH (e.g., 1 nanohenry) exists due to a bondwire connecting the first terminal 104 (e.g., drain) to an external connector (e.g., an external pin of an IC) designated as an input 106. A diode D1 has an anode coupled to the source 108 and a cathode coupled to the gate 112. In a bridge driver circuit, the diode D1 can be connected between the gate 112 and the source 108 of the high-side transistor MH to limit the gate-source voltage of MH from going too far below zero (i.e., becoming too negative), which can cause reliability issues when MH is turned off.

[0025] The system 100 includes a low-side transistor ML having a first terminal 120 (e.g., a drain) coupled to the second terminal 108 and to the output 110. The low-side transistor ML has a second terminal 122 (e.g., a source) coupled to a common potential terminal 124 (e.g., electrical ground). The low-side transistor ML has a control terminal 126 (e.g., a gate). The low-side transistor ML includes a body diode DLB with an anode coupled to the second terminal 122 (e.g., a source) and a cathode coupled to the first terminal 120 (e.g., a drain). A bond wire inductance LBL (e.g., 1 nanohenry) exists between the source 122 and an external connector designated as the common potential terminal 124.

[0026] The input 106 may be coupled to an input voltage Vm (eg, 12V, 25V, 40V) and the reference potential terminal 124 may be coupled to electrical ground.

[0027] In some examples, the transistors are n-channel field effect transistors (NFETs), and in other examples, the transistors are p-channel field effect transistors (PFETs). In some examples, the transistors may be bipolar transistors and / or other types of power transistors (e.g., drain-extended FETs). In some examples, the FETs are implemented in / on a silicon substrate. In other examples, the FETs are implemented using gallium nitride (GaN) and / or silicon carbide (SiC).

[0028] One phase of the motor, represented by the inductive load Lm, has a first terminal 130 coupled to the output 110 and a second terminal 132 that may be coupled to the input 106 via a first switch S1 or to ground via a second switch S2. Depending on the number of phases used to drive the motor (each phase may be determined by the number of winding pairs wound on a portion of the motor's stator), additional features (e.g., MH, ML, S1, and S2) are connected to drive each phase of the motor. To drive the motor Lm in one direction, a gate signal GATE_H is applied to gate 112 to turn on the high-side transistor MH and turn off the low-side transistor ML (in other words, no gate signal GATE_L is applied to gate 126), turn on switch S2 (i.e., closed / conducting), and turn off switch S1 (i.e., open / non-conducting). As a result, a current Im flows from Vm through MH, then through the motor Lm, and finally through switch S2 to ground. To drive the motor Lm in the reverse direction, a gate signal GATE_L is applied to the gate 126 of ML, the high-side transistor MH is turned off (in other words, the gate signal GATE_H is not applied to the gate 112), the switch S1 is turned on (i.e., closed / conducting), and the switch S2 is turned off (i.e., open / non-conducting). As a result, a current Im flows from Vm through switch S1, then through the motor Lm, and finally through ML to ground. In one example, the gate signals GATE_H and GATE_L may be pulse-width modulated (PWM) signals (which have a variable pulse width) or pulse-frequency modulated (PFM) signals (which have a variable frequency but fixed amplitude).

[0029] The system 100 includes a control circuit 140 having a first input 142 coupled to the output 110, a second input 144 coupled to receive an upper reference voltage VREF_H, a third input 146 coupled to receive a low-side digital control signal CNTR_L, a fourth input 148 coupled to receive a high-side digital control signal CNTR_H, and a fifth input 150 coupled to a voltage source VCC (e.g., 5V, 7V). In some examples, the signals 144, 146, and / or 148 are provided by an external input (e.g., a user-defined input) or by a controller (e.g., including a processor, a state machine, digital logic, analog circuitry, memory, and / or an application specific integrated circuit) that may be included on the same integrated circuit (IC) as MH and ML or may be implemented on a different IC. The low-side digital control signal CNTR L provides the timing for the low-side transistor ML, and the high-side digital control signal CNTR H provides the timing for the high side transistor MH. The control circuit 140 outputs a gate signal GATE at an output 152 that is coupled to the gate 126 of the low side transistor ML. L at output 154 which is coupled to the gate 112 of high side transistor MH. Control circuit 140 also provides a control signal CNTR at output 156 to control switch S1. and a control signal CNTR at output 158 ​​for controlling switch S2. Provide S2.

[0030] In some examples, the control circuit 140 may be configured to reduce the induced voltage VB without requiring additional circuit elements and / or higher rated transistors. The control circuit 140 applies a first level of current (also called reverse recovery current) to the gate 126 of the ML during the reverse recovery period, after which the output voltage Vout becomes lower than the upper reference voltage VREF. When it falls below H, the current increases to a second level of current (also called the through current) which indicates that ML has transitioned to the Miller region.

[0031] 2 illustrates waveforms used in or generated by the driver system 100. The x-axis represents time and the y-axis represents voltage for a voltage waveform and current for a current waveform. At time T1, the low-side digital control signal CNTR L204 transitions from a low state to a high state to initiate the process of turning on the low-side transistor ML. In response, the control circuit 140 applies a gate current I_GL 208 to the gate 126 of ML, the gate current having a magnitude equal to the first level of current I_RR (also referred to as the reverse recovery current I_RR). In some examples, I_RR is approximately five hundred microamperes (500 μA). In some examples, the magnitude of I_RR is selected such that I_RR is low enough to limit the reverse recovery period of the high-side body diode DHB, but is also sufficient to prevent significant propagation delay (the time required to turn on ML). As previously described, turning on ML closes S1 (conducting), turns MH off, and opens S2 (non-conducting).

[0032] In response to I_RR, the gate-source voltage V GSL 212 starts to rise. Since ML is still turned off at time T1, the motor current Im flows from anode to cathode through the high-side body diode DHB. Therefore, at time T1, the current I_HB 216 (flowing through the high-side body diode DHB) is equal to the motor current Im, and the current I LS220 (flowing through low-side transistor ML) is zero. At time T1, the output voltage Vout224 is equal to (Vm+VDH), where VDH is the voltage across the high-side body diode DHB. Depending on the size of the body diode DHB, the voltage VDH can vary (e.g., 0.7V, 0.9V, 1.2V).

[0033] At time T2, the gate-source voltage VGS L212 rises above the threshold voltage Vt required to turn on ML. Therefore, the current I through ML At time T2, ML is turned on, but due to the reverse recovery time of the high-side body diode DHB, the current I_HB 216 continues to flow through DHB, but the current I It starts to decrease as the LS220 starts to rise through the ML.

[0034] At time T2, the output voltage Vout 224 starts to decrease, and at time T3, Vout 224 falls below Vm. In response, at time T3, the control circuit 140 changes the gate current I_GL from a first level current (reverse recovery current I_RR) to a second level current (through current I Therefore, the control circuit 140 maintains the lower gate current (reverse recovery current I_RR) until Vout drops below Vm, and then increases the higher gate current (through current I In some cases, for a slew rate of about 100V / μs (100 volts per microsecond), I The SLEW is about 5mA.

[0035] At time T3, the high-side body diode DHB is reverse biased, so that the current I_HB 216 through the high-side body diode DHB drops to zero and the motor current Im flows from Vm through S1, then through Lm, and finally through ML. As mentioned above, turning on ML turns MH off, S1 is closed (conducting), and S2 is open (non-conducting).

[0036] The control circuit 140 slowly charges the gate 126 of ML by maintaining the lower gate current (reverse recovery current) until ML transitions to the Miller region at time T3 and DHB becomes reverse biased. As a result, the current I through ML This prevents the LS220 from rising too fast, which reduces the ground bounce voltage VB between T2 and T3. In the example of Figure 2, the ground bounce voltage VB INT228 refers to the ground bounce voltage at the ML source 122 (shown in FIG. 1), and in some examples, the ground bounce voltage is limited to about 1V.

[0037] At time T3, the low-side transistor ML transitions into the mirror region, which causes the gate-drain capacitance CGD (not shown) of ML to begin charging. As a result, at time T3, the gate-source voltage VGS L212 is flattened (eg, flat section).

[0038] At time T4, the gate-drain capacitor C GD At time T4, the gate-source voltage VGS L212 starts to rise again and reaches VCC (eg, about 5V) at time T5. At time T4, the gate current IG_L208 starts to fall as the gate-drain capacitor CGD charges.

[0039] At time T6, the low-side digital control signal CNTR L transitions from a high state to a low state, turning off low-side transistor ML. In response, at time T6, control circuit 140 controls a SLEW but negative polarity (e.g., -I SLEW), which is also called a "pull-down current." As a result, at time T7, VGS L212 drops to the same voltage level as in the mirror region (ie, between T3 and T4).

[0040] At time T7, the output voltage Vout 224 slews upward, and at time T8, Vout 224 rises above Vm, causing the current I HB216 (e.g. high side body diode I The current I through HB) starts to rise. As HB216 rises, the current IL S220 (e.g., the current through the low-side transistor ML) begins to decrease. At time T9, the current I The LS220 drops to zero, resulting in I HB216 would be equal to Im.

[0041] current I As LS220 decreases between T8 and T9, the negative rate of change of current through ML is increased by the negative ground bounce voltage VB between T8 and T9. In some examples, the magnitude of the negative ground bounce voltage is greater than the ground bounce voltage VB Just as the magnitude of INT228 is limited between T2 and T3, the pull-down current -I It can be limited by decreasing the magnitude of SLEW (ie, making it less negative).

[0042] 3 illustrates a low-side gate drive circuit 304 of an example control circuit 140. The low-side gate drive circuit 304 receives a gate signal GATE L to gate 126 to drive ML (shown in FIG. 1). Control circuit 140 includes a high-side gate drive circuit (not shown in FIG. 3) that drives gate signal GATE H is provided to drive MH (shown in FIG. 1).

[0043] The low-side gate drive circuit 304 includes a first comparison circuit 310 having a first input 312 (e.g., input 142 in FIG. 1) coupled to the system output 110 and an upper reference voltage VREF H (eg, input 144 in FIG. 1). The first comparison circuit 310 is adapted to receive the output voltage Vout relative to an upper reference voltage VREF If the voltage drops below H, a slew start signal SLEW is generated at output 316. Provide a START.

[0044] The low side gate drive circuit 304 includes a first current source 320 (also referred to as a reverse recovery current source 320) having a first terminal 322 coupled to a voltage source VCC. The first current source 320 provides a first level of current I_RR (also referred to as a reverse recovery current I_RR) at an output 324.

[0045] The low-side gate drive circuit 304 includes a first switch 326 (also referred to as a reverse recovery switch 326) having a first terminal 328 coupled to a second terminal 324 of a first level current source 320 (reverse recovery current source 320), a second terminal 330 coupled to a gate 126 of a low-side transistor ML (not shown in FIG. 3), a third terminal 332 coupled to an output 316 of the first comparison circuit 310, and a low-side digital control signal CNTR. and a fourth terminal 334 coupled to receive L. The first current switch 326 is configured to transition from a low state to a high state. In response to L, a first current source 320 is coupled to the gate 126 of ML to generate a slew start signal SLEW In response to the assertion of START, the first level current source 320 is disconnected from the gate 126 of ML.

[0046] The low side gate drive circuit 304 includes a second current source 340 (also referred to as a through current source 340) having a first terminal 342 coupled to a voltage source VCC. The second level current source 340 outputs a second level current I SLEW (Through current I (also called SLEW). The second level current I SLEW is greater than the first level current I_RR.

[0047] The low-side gate drive circuit 304 includes a second switch 346 (also referred to as a slew current switch 346) having a first terminal 348 coupled to the output 344 of the slew current source 340, a second terminal 350 coupled to the gate 126 of ML, a third terminal 352 coupled to the output 316 of the first comparison circuit 310, and a low-side digital control signal CNTR. and a fourth terminal 354 coupled to receive the slew start signal SLEW L by the first comparison circuit 310. In response to the assertion of START, a slew current source 340 is coupled to the gate 126 of ML.

[0048] The low side gate drive circuit 304 includes a third current source 360 ​​having a first terminal 362 coupled to a common potential (e.g., ground) terminal and a second terminal 364. The low side gate drive circuit 304 includes a third switch 368 having a first terminal 370 coupled to the gate 126 of ML, a second terminal 372 coupled to the second terminal 364 of the second current source 360, and a low side digital control signal CNTR. and a third terminal 374 coupled to receive the CNTR L. The third switch 368 is configured to transition from a high state to a low state. In response to L, a third current source 360 ​​is coupled to gate 126. As a result, gate 126 is discharged to ground by through current source 370 and ML is turned off.

[0049] The low-side gate drive circuit 304 detects that the output voltage Vout is VREF H. The low-side gate drive circuit 304 then maintains the gate current at a higher level (the through current I SLEW), which allows the gate-drain capacitor CGD (not shown in FIG. 3) to charge in the Miller region.

[0050] In some examples, the low-side gate drive circuit 304 slowly charges the gate 126 of ML by maintaining a lower gate current (reverse recovery current I_RR) until ML transitions into the mirror region and DHB is reverse biased. As a result, the current I through ML This prevents the LS220 (Figure 2) from rising too fast, which reduces the ground bounce voltage VB INT 224 is significantly reduced. The control circuit 140 also prevents the current I_BH 216 (FIG. 2) through the high-side body diode DHB from dropping below zero by slowly charging the gate 126 of ML by maintaining a reverse recovery current until the high-side body diode DHB is reverse biased. Thus, DHB is reverse biased relatively slowly without current having to flow in the reverse direction through DHB. As a result, in some instances, the current I through ML LS does not rise above Im (Figure 2) and therefore does not fall to Im. The current I Since LS does not have a negative rate of change, the induced ground bounce voltage VB INT cannot be negative. Therefore, the induced voltage VB INT is characterized by a positive pulse. This effect is caused by the induced ground bounce voltage VB Wide swings in INT are prevented and the voltage drop between the drain 120 and source 122 of ML is reduced.

[0051] In some examples, I_RR is set to allow LSI to rise above Im but limit the amount I_LS from rising above Im, and VB Allow INT to fall below zero, but the amount VB INT may be adjusted (eg, increased) to limit it from falling below zero.

[0052] CNTR In response to L transitioning from a high state (e.g., a binary "1", such as a higher voltage level) to a low state (e.g., a binary "0", such as a lower voltage level), the third switch 374 couples the through current source 360 ​​to the gate 126ML. As a result, the gate 126 is discharged to ground by the through current source 360.

[0053] 4 illustrates a comparison circuit 312 in one example. The comparison circuit 312 includes a first PMOS transistor MP1, which includes a source 404 coupled to an input voltage Vm, and includes a drain 406 and a gate 408. The comparison circuit 312 includes a second PMOS transistor MP2, which includes a source 410 coupled to the drain 406 of MP1, and includes a drain 412 and a gate 414. The comparison circuit 312 includes a third PMOS MP3, which includes a source 420 coupled to Vm and a gate 422, and includes a drain 424.

[0054] The comparison circuit 312 includes a fourth PMOS MP4, which includes a source 430 coupled to the drain 424 of MP3 and a gate 434 coupled to the gate 408 of MP1. MP4 is coupled to an upper reference voltage VREF H and coupled to the gate 414 of MP2. The comparison circuit 312 includes a fifth PMOS MP5 that includes a source 450 coupled to the gate 408 of MP1 and a source 452 coupled to the output voltage Vout through a resistor R1. MP5 is coupled to the upper reference voltage VREF H. The comparison circuit 312 includes an NMOS transistor MN1 that includes a drain 460 that is coupled to the drain 414 of MP2 and a source 464 that is coupled to ground through a resistor R2. MN1 includes a gate 466 that is adapted to receive an enable signal ENABLE. In some examples, the enable signal ENABLE is Derived from L. For example, CNTR An enable signal ENABLE may be asserted when CNTR L transitions from a low state to a high state. ENABLE may be deasserted when L transitions from a high to a low state.

[0055] The comparison circuit 312 includes a comparator 470 having a first input 472 coupled to the source 464 of MN1, a second input 474 coupled to a voltage source VDD, and a third input 476 coupled to ground. A resistor R2 is coupled between the first input 472 and ground.

[0056] In one example, comparator 470 is a Schmitt trigger with a hysteresis loop defined by VDD and ground. In some examples, MP2 may be implemented with a drain-extended MOSFET (DENMOS) to protect MP1, a low-voltage device. MN1 may be implemented with a DENMOS to protect the Schmitt trigger 470.

[0057] In some embodiments, VREF H is approximately equal to Vm minus 5 volts (Vm-5V). When Vout is greater than Vm plus the transistor threshold voltage minus 5 volts (Vm-5V+Vt), MP5 conducts, thus coupling the gate 408 of MP1 to Vout. As a result, MP1 conducts. When Vout begins to drop to approximately Vm, MP1 does not conduct and resistor R2 pulls the first input 472 of Schmitt trigger 470 down to ground. This causes the output 478 of Schmitt trigger 470 (SLEW START) goes to or near zero volts. In response, I_RR is applied to the gate 126 of low-side transistor ML by control circuit 140 (not shown in FIG. 4).

[0058] When Vout is less than Vm minus a transistor threshold voltage (Vm-Vt) (e.g., Vout is greater than Vt and less than Vm), MP1 conducts and the source 464 of MN1 is pulled up to approximately the enable signal voltage minus the gate-source voltage of MN1 (ENABLE-Vgs), which causes Schmitt trigger 470 to assert SLEW_START (e.g., SLEW_START). START goes to logic high or "1" value), and the through current I SLEW is provided to the gate 126 of low-side transistor ML. When Vout is less than Vm minus approximately 5 volts (Vm-5V), the body diode of MP4 (not shown in FIG. 4) keeps the source 450 of MP5 conductive and at one diode voltage drop below Vm-5V, thereby preventing the Vg of MP5 VGS from becoming too high (e.g., too positive).

[0059] In this specification and claims, the terms "including and comprising" are used in an open-ended manner, and therefore mean "including, but not limited to." An element or feature that is "configured" to perform a task or function may be configured (e.g., programmed or architecturally designed) by a manufacturer to perform that function at the time of manufacture and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the configuration and / or layout of the hardware components, through the device interconnections, or through a combination thereof. Additionally, use of "ground" or similar phrases in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings herein.

[0060] Unless otherwise stated, "about" preceding a value means + / - 10% of that value. As used herein, the term "modulate" can also mean "vary" or "alter."

[0061] For example, the terms "node," "terminal," "pin," and "interconnect" are used interchangeably and refer to any connection (or interconnection) between features. These terms are not meant to be limiting with respect to a certain type of physical structure. For example, a "terminal" of a circuit element refers to each connection to such circuit element. Thus, an integrated resistor may be said to have two terminals (ends) even though these "terminals" are the only two connections to the integrated resistor.

[0062] Although the use of certain transistors is described herein, other transistors (or equivalent devices) may be substituted with little or no change to the remaining circuit elements. For example, metal oxide silicon FETs ("MOSFETs") (e.g., n-channel MOSFET, nMOSFET, or p-channel MOSFET, pMOSFET), bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Additionally, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0063] While some examples suggest that certain elements are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (i) incorporated in / on a semiconductor substrate, (ii) incorporated in a single semiconductor package, (iii) incorporated in the same module, and / or (iv) incorporated in / on the same printed circuit board.

[0064] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. A driver, a high-side transistor having a first terminal and a control terminal; a low-side transistor having a first terminal coupled to the first terminal of the high-side transistor and a control terminal; a gate control circuit having a first input coupled to a first terminal of the high side transistor and a first terminal of the low side transistor, a reference voltage input, a digital control input, a power supply input, and an output coupled to a control terminal of the low side transistor; providing a first level of current to the output in response to a low-side digital control signal at the digital control input transitioning from a low state to a high state; providing a second level of current greater than the first level of current in response to a drive signal at the first terminal of the high side transistor and the first terminal of the low side transistor being less than a reference voltage at the reference voltage input; the gate control circuit being operable to: Including the driver.

2. 2. The driver of claim 1, the gate control circuit is further operable to maintain the first level of current to reduce induced ground bounce voltage at a reference potential terminal coupled to a second terminal of the low-side transistor until the drive signal drops below the reference voltage.

3. 2. The driver according to claim 1, the gate control circuit is further operable to maintain the first level of current to reduce an induced ground bounce voltage at a reference potential terminal coupled to a second terminal of the low-side transistor by reducing a rate of change of current through the low-side transistor until the drive signal drops below the reference voltage.

4. 2. The driver of claim 1, the gate control circuit is further operable to maintain the first level of current lower than the second level of current to reduce a rate of change of current through the low-side transistor until the drive signal drops below the reference voltage.

5. 2. The driver of claim 1, The driver, wherein the gate control circuit is further operable to provide the second level of current in response to the low-side transistor transitioning into a Miller region.

6. 2. The driver of claim 1, the gate control circuit is further operable to provide a third level of current to the control terminal of the low-side transistor to turn off the low-side transistor in response to the low-side digital control signal transitioning from the high state to the low state.

7. 2. The driver of claim 1, the gate control circuit includes a first comparator circuit having a first input coupled to a first terminal of the high side transistor and a first terminal of the low side transistor, a second input as the reference voltage terminal, and an output terminal, the first comparator circuit operable to provide a slew start signal at the output in response to the drive signal falling below the reference voltage.

8. 8. A driver according to claim 7, The gate control circuit a reverse recovery current source having a first terminal; a reverse recovery switch having a first terminal coupled to a first terminal of the reverse recovery current source, a second terminal coupled to a control terminal of the low-side transistor, a third terminal coupled to an output of the first comparison circuit, and a fourth terminal coupled to the digital control input; coupling the reverse recovery current source to a control terminal of the low-side transistor in response to the low-side digital control signal transitioning from the low state to the high state; disconnecting the reverse recovery current source from the control terminal of the low-side transistor in response to the slew start signal; the reverse recovery switch, The driver further includes:

9. 8. A driver according to claim 7, The gate control circuit a first through current source having a first terminal; a first slew current switch having a first terminal coupled to the first terminal of the first slew current source, a second terminal coupled to a control terminal of the low-side transistor, a third terminal coupled to an output of the first comparison circuit, and a fourth terminal coupled to the digital control input, the first slew current switch operable to couple the first slew current source to the control terminal of the low-side transistor in response to the slew start signal; The driver further includes:

10. 10. A driver according to claim 9, The gate control circuit a second through current source having a first terminal; a second through current switch having a first terminal coupled to a control terminal of the low-side transistor, a second terminal coupled to a first terminal of the second through current source, and a third terminal coupled to the digital control input, the second through current switch operable to couple the second through current source to the control terminal of the low-side transistor to turn off the low-side transistor in response to the digital control signal transitioning from the high state to the low state; Also includes a driver.

11. 2. The driver of claim 1, a high-side body diode having a cathode coupled to the second terminal of the high-side transistor and an anode coupled to the first terminal of the high-side transistor; a low-side body diode having a cathode coupled to the second terminal of the low-side transistor and an anode coupled to the first terminal of the low-side transistor; The driver further includes:

12. A driver, a high-side transistor having a first terminal and a control terminal; a low-side transistor having a first terminal coupled to the first terminal of the high-side transistor and a control terminal; a gate control circuit having a first input coupled to a first terminal of the high-side transistor and a first terminal of the low-side transistor, a reference voltage input, a digital control input, a power supply input, and an output coupled to a control terminal of the low-side transistor; applying a first level of current to a control terminal of the low-side transistor; maintaining the first level of current to the control terminal of the low-side transistor until an output voltage at the first terminal of the high-side transistor and the first terminal of the low-side transistor falls below a reference voltage at the reference voltage input; applying a second level of current greater than the first level of current to the control terminal of the low-side transistor in response to a slew start signal; the gate control circuit being operable to: Including the driver.

13. 13. The driver of claim 12, the gate control circuit is further operable to maintain the first level of current less than the second level of current to reduce a rate of change of current through the low-side transistor until the output voltage drops below the reference voltage.

14. 13. A driver according to claim 12, the gate control circuit is further operable to provide a third level of current to turn off the low-side transistor in response to a low-side digital control signal at the digital control input transitioning from a high state to a low state.

15. 13. A driver according to claim 12, the gate control circuit includes a first comparator circuit having a first input coupled to a first terminal of the high side transistor and a first terminal of the low side transistor, a reference voltage input, and an output, the first comparator circuit operable to provide the slew start signal at the output in response to the output voltage falling below the reference voltage.

16. 13. A driver according to claim 12, The gate control circuit a reverse recovery current source having a first terminal; a reverse recovery switch having a first terminal coupled to a first terminal of the reverse recovery current source, a second terminal coupled to a control terminal of the low-side transistor, a third terminal coupled to an output of the first comparison circuit, and a fourth terminal coupled to the digital control input; coupling the reverse recovery current source to the control terminal of the low-side transistor in response to a low-side digital control signal at the digital control input transitioning from a low state to a high state; disconnecting the reverse recovery current source from the control terminal of the low-side transistor in response to the slew start signal; the reverse recovery switch, Including the driver.

17. 13. A driver according to claim 12, The gate control circuit a first through current source having a first terminal; a first slew current switch having a first terminal coupled to the first terminal of the first slew current source, a second terminal coupled to a control terminal of the low-side transistor, a third terminal coupled to an output of the first comparison circuit, and a fourth terminal coupled to the digital control input, the first slew current switch operable to couple the first slew current source to the control terminal of the low-side transistor in response to the slew start signal; Including the driver.

18. 18. A driver according to claim 17, The gate control circuit a second through current source having a first terminal; a second through current switch having a first terminal coupled to the control terminal of the low-side transistor, a second terminal coupled to the first terminal of the second through current source, and a third terminal coupled to the digital control input, the second through current switch operable to couple the second through current source to the control terminal of the low-side transistor to turn off the low-side transistor in response to a digital control signal at the digital control input transitioning from a high state to a low state; The driver further includes:

19. A driver, a high-side transistor having a first terminal, a second terminal, and a control terminal; a low-side transistor having a first terminal coupled to the second terminal of the high-side transistor, a second terminal, and a control terminal; a high-side body diode having a cathode coupled to the first terminal of the high-side transistor and an anode coupled to the second terminal of the high-side transistor; a low-side body diode having a cathode coupled to the first terminal of the low-side transistor and an anode coupled to the second terminal of the low-side transistor; a gate control circuit having a first input coupled to a second terminal of the high side transistor, a reference voltage input, a digital control input, a power supply input, and an output coupled to a control terminal of the low side transistor; applying a first level of current to a control terminal of the low-side transistor in response to a digital control signal at the digital control input transitioning from a low state to a high state; maintaining the first level of current into the control terminal of the low-side transistor to reduce a ground bounce voltage at a reference potential terminal coupled to the second terminal of the low-side transistor by reducing a rate of change of current through the low-side transistor until an output voltage at the second terminal of the high-side transistor falls below a reference voltage at the reference voltage input; applying a second level of current greater than the first level of current to the control terminal of the low-side transistor in response to a slew start signal; the gate control circuit being operable to: Including the driver.

20. 20. A driver according to claim 19, the gate control circuit is further operable to apply a third level of current to the control terminal of the low-side transistor to turn off the low-side transistor in response to the digital control signal transitioning from the high state to the low state.

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