Semiconductor device and manufacturing method of the same

Abstract

To provide a semiconductor device capable of reducing bowing.SOLUTION: According to one embodiment, a semiconductor device includes: a stacked film including a plurality of electrode layers and a plurality of first insulating films alternately stacked in a first direction and including a first portion having a non-stepped shape and a second portion having a stepped shape; and a second insulating film provided on the second portion. The device further includes: a columnar portion extending through the first portion in the first direction and including a charge storage layer and a semiconductor layer; a third insulating film extending through the second portion and the second insulating film in the first direction; a plug provided on any of the electrode layers in the second portion; and a first region provided in the second portion and the second insulating film and including a first element. A concentration of the first element in the first region is higher than a concentration of the first element in a region outside the first region in the second insulating film. The third insulating film or the plug is in contact with the first region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] When forming a recess in or on a stacked film of a 3D semiconductor memory, the bowing of the recess may become large. For example, when forming a hole for a beam part in a staircase part of a stacked film, the bowing of the hole often becomes large. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication US2022 / 0293529 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of reducing bowing and a manufacturing method thereof are provided. [Means for solving the problem]

[0005] According to one embodiment, the semiconductor device includes a laminated film including a plurality of electrode layers and a plurality of first insulating films alternately stacked in a first direction, the laminated film including a first portion having a non-step-like shape and a second portion having a step-like shape, and a second insulating film provided on the second portion. The device further includes a columnar portion extending in the first direction in the first portion and including a charge storage layer and a semiconductor layer, a third insulating film extending in the first direction in the second portion and the second insulating film, a plug provided on any of the electrode layers in the second portion, and a first region provided in the second portion and the second insulating film and including a first element. The concentration of the first element in the first region is higher than the concentration of the first element in a region of the second insulating film outside the first region. The third insulating film or the plug is in contact with the first region. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. [Diagram 2] 1 is an enlarged cross-sectional view showing a structure of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view (1 / 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 11 is a cross-sectional view (2 / 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 3 is a cross-sectional view (3 / 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 4 is a cross-sectional view (4 / 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 5 is a cross-sectional view (5 / 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 6 is a cross-sectional view (6 / 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 7 is a cross-sectional view (7 / 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 8 is a cross-sectional view (8 / 11) showing the method for manufacturing the semiconductor device according to the first embodiment; [Figure 11] 9 is a cross-sectional view (9 / 11) showing the method for manufacturing the semiconductor device according to the first embodiment; [Figure 12] 1 is a cross-sectional view (10 / 11) showing the method for manufacturing the semiconductor device according to the first embodiment; [Figure 13] 11 is a cross-sectional view (11 / 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 11 is a cross-sectional view (1 / 7) showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 15] 13 is a cross-sectional view (2 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 16] 13 is a cross-sectional view (3 / 7) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 17] 13 is a cross-sectional view (4 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. [Figure 18] 13 is a cross-sectional view (5 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 19] 6 is a cross-sectional view (6 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 20] 7 is a cross-sectional view (7 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 21] FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. [Figure 22] 13 is a cross-sectional view (1 / 4) showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 23] 13 is a cross-sectional view (2 / 4) showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. [Figure 24] 13 is a cross-sectional view (3 / 4) illustrating a method for manufacturing a semiconductor device according to a third embodiment. [Diagram 25] 13 is a cross-sectional view (4 / 4) showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In Fig. 1 to Fig. 25, the same components are given the same reference numerals, and duplicated explanations will be omitted.

[0008] (First embodiment) 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. The semiconductor device according to the present embodiment includes, for example, a three-dimensional semiconductor memory.

[0009] The semiconductor device of this embodiment includes a substrate 1, a laminated film 2, an interlayer insulating film 3, a plurality of columnar portions 4, a plurality of beam portions 5, a plurality of impurity regions 6, an interlayer insulating film 7, and a plurality of contact plugs 8. The laminated film 2 includes a plurality of insulating films 2a and a plurality of electrode layers 2b. Each impurity region 6 includes an impurity region 6a and an impurity region 6b. The insulating film 2a, the interlayer insulating film 3, and the beam portions 5 are examples of the first, second, and third insulating films, respectively. The impurity regions 6, 6a, and 6b are examples of the first region, the upper region, and the lower region, respectively.

[0010] The substrate 1 is, for example, a semiconductor substrate such as a Si (silicon) substrate. FIG. 1 shows an X direction and a Y direction parallel to the surface of the substrate 1 and perpendicular to each other, and a Z direction perpendicular to the surface of the substrate 1. The X direction, the Y direction, and the Z direction intersect with each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity. The Z direction is an example of a first direction.

[0011] The laminated film 2 is formed on the substrate 1. The laminated film 2 may be formed directly on the substrate 1, or may be formed on the substrate 1 via another film. The laminated film 2 includes a plurality of insulating films 2a and a plurality of electrode layers 2b alternately stacked in the Z direction. Each insulating film 2a is, for example, a SiO2 film (silicon oxide film). Each electrode layer 2b is, for example, a metal layer including a W (tungsten) layer. Each electrode layer 2b functions, for example, as a word line or a selection line of a three-dimensional semiconductor memory.

[0012] The laminated film 2 includes a flat portion R1 having a non-step-like shape and a step portion R2 having a step-like shape. The flat portion R1 has a flat upper surface. The step portion R2 has an upper surface and a side surface processed into a step-like shape. Each of the flat portion R1 and the step portion R2 includes the above-mentioned multiple insulating films 2a and multiple electrode layers 2b. The flat portion R1 and the step portion R2 are examples of the first and second portions, respectively.

[0013] The semiconductor device of this embodiment may be manufactured by forming the laminated film 2 on the substrate 1, bonding the substrate 1 to another substrate, and then removing the substrate 1. In this case, the semiconductor device of this embodiment may not include the substrate 1. In this case, the +Z direction may be the downward direction, and the -Z direction may be the upward direction.

[0014] The interlayer insulating film 3 is formed on the stepped portion R2 of the laminated film 2. The interlayer insulating film 3 is, for example, a SiO2 film. In this embodiment, the upper surface of the interlayer insulating film 3 is located at the same height as the upper surface of the flat portion R1 of the laminated film 2.

[0015] Each columnar portion 4 is formed in a memory hole MH penetrating the flat portion R1, and has a columnar shape extending in the Z direction. As described later, each columnar portion 4 includes a block insulating film, a charge storage layer, a tunnel insulating film, a channel semiconductor layer, and a core insulating film, which are formed in this order on the side surface of the memory hole MH. Each columnar portion 4, together with the above-mentioned multiple electrode layers 2b, forms multiple memory cells of the three-dimensional semiconductor memory. The memory hole MH is an example of a first recess.

[0016] Each beam portion 5 is formed in a beam hole HR penetrating the step portion R2 and the interlayer insulating film 3, and has a columnar shape extending in the Z direction. Each beam portion 5 is, for example, an insulating film such as a SiO2 film. Each beam portion 5 functions as a beam for preventing the laminated film 2 from collapsing when replacing a plurality of sacrificial layers in the laminated film 2 with a plurality of electrode layers 2b (replacement process), as described below. The beam hole HR is an example of a second recess.

[0017] Each impurity region 6 is formed in the step portion R2 and the interlayer insulating film 3, and contains a predetermined element. The predetermined element is, for example, an impurity element in the step portion R2 and the interlayer insulating film 3. Each impurity region 6 is formed, for example, by implanting ions of the predetermined element into the step portion R2 and the interlayer insulating film 3. The predetermined element is, for example, P (phosphorus). The predetermined element may be another element, for example, B (boron), As (arsenic), Si (silicon), or N (nitrogen). The predetermined element is an example of the first element.

[0018] FIG. 1 shows the outline of each impurity region 6 with a dashed line. FIG. 1 shows three impurity regions 6 formed around three beam portions 5. Each beam portion 5 is in contact with a corresponding impurity region 6, and more specifically, is formed in the corresponding impurity region 6. FIG. 1 shows the P atoms in each impurity region 6 with dot hatching in each impurity region 6. As can be seen from the dot hatching in FIG. 1, the P atoms in this embodiment are contained in the interlayer insulating film 3 and the insulating film 2a, but are not contained in the electrode layer 2b. This is because the sacrificial layer is replaced by the electrode layer 2b after the P atoms are implanted into the insulating film 2a and the sacrificial layer. Therefore, each impurity region 6 is divided into a plurality of impurity regions by the electrode layer 2b, but since these impurity regions were one impurity region before the division, in this embodiment, the region surrounded by the dashed line in FIG. 1 (= each impurity region 6) is treated as one impurity region.

[0019] Each impurity region 6 includes at least an impurity region 6a formed in the interlayer insulating film 3 and at least an impurity region 6b formed in the step portion R2. In each impurity region 6, the impurity region 6b is located below the impurity region 6a. In this embodiment, the impurity region 6a is formed only in the interlayer insulating film 3, and the impurity region 6b is formed in the interlayer insulating film 3 and the step portion R2. However, the impurity region 6a may be formed in the interlayer insulating film 3 and the step portion R2. The impurity region 6b may be formed only in the interlayer insulating film 3. Each beam portion 5 contacts the impurity region 6a and the impurity region 6b in the corresponding impurity region 6, and more specifically, is formed in the impurity region 6a and the impurity region 6b of the corresponding impurity region 6.

[0020] The impurity region 6a contains P atoms at a high concentration, and the impurity region 6b contains P atoms at a low concentration. Therefore, the concentration of P atoms in the impurity region 6b is lower than the concentration of P atoms in the impurity region 6a. The concentration of P atoms in the impurity region 6a is, for example, 1.0×10 21 ~1.0×10 22 atoms / cm 3 The concentration of P atoms in the impurity region 6b is, for example, 1.0×10 20 ~5.0×10 21 atoms / cm 3 The concentrations of P atoms in the impurity regions 6a and 6b are examples of a first and a second concentration, respectively.

[0021] Note that the region outside the impurity region 6 in the interlayer insulating film 3 may not contain any P atoms at all, or may contain a lower concentration of P atoms than the impurity regions 6a and 6b. Similarly, the region outside the impurity region 6 in the laminated film 2 may not contain any P atoms at all, or may contain a lower concentration of P atoms than the impurity regions 6a and 6b. This also applies to the case where the impurity atoms are other than P atoms.

[0022] The interlayer insulating film 7 is formed on the stacked film 2, the interlayer insulating film 3, the columnar portion 4, the beam portion 5, and the impurity region 6. The interlayer insulating film 7 is, for example, a SiO2 film.

[0023] Each contact plug 8 is formed in a contact hole CC penetrating one of the insulating films 2a and the interlayer insulating films 3 and 7 in the staircase portion R2, and has a columnar shape extending in the Z direction. Therefore, each contact plug 8 is formed on one of the electrode layers 2b in the staircase portion R2 and is electrically connected to this electrode layer 2b. However, the leftmost contact plug 8 in FIG. 1 penetrates one of the insulating films 2a and the interlayer insulating film 7 in the staircase portion R2, but does not penetrate the interlayer insulating film 3. The insulating film 2a through which this contact plug 8 penetrates may be treated as the insulating film 2a in the flat portion R1. Each contact plug 8 is, for example, a metal layer including a W layer, an Al (aluminum) layer, or a Cu (copper) layer. The contact hole CC is an example of a third recess.

[0024] In this embodiment, each contact plug 8 is in contact with a corresponding impurity region 6 (except for the contact plug 8 on the leftmost side in FIG. 1). Each contact plug 8 may be in contact with only one of the impurity regions 6a and 6b, or may be in contact with both the impurity regions 6a and 6b. Each contact plug 8 may be formed in the corresponding impurity region 6, or may not be formed in the corresponding impurity region 6. In the former case, each contact plug 8 may be formed in the impurity region 6a and the impurity region 6b, or may be formed in the impurity region 6a or the impurity region 6b. In FIG. 1, two contact plugs 8 are formed in the impurity region 6b, and one contact plug 8 is in contact with the impurity region 6b but is formed outside the impurity region 6b. That is, two contact plugs 8 are surrounded by the impurity region 6b in an annular shape, but one contact plug 8 is not surrounded by the impurity region 6b in an annular shape.

[0025] Each contact plug 8 does not have to be formed in the interlayer insulating film 7. That is, each contact plug 8 may be formed in a contact hole CC penetrating one insulating film 2a in the staircase portion R2 and the interlayer insulating film 3, or in a contact hole CC penetrating one insulating film 2a in the staircase portion R2. An example of such a contact plug 8 will be described in the third embodiment described later.

[0026] Next, still referring to FIG. 1, the bowing of the memory hole MH and the beam hole HR will be described.

[0027] When forming memory holes MH by etching such as RIE (Reactive Ion Etching), bowing may occur, in which the side of the memory hole MH protrudes in the radial direction. Bowing occurs when side etching progresses on the side of the memory hole MH. This is also the case when forming beam holes HR. In FIG. 1, the bowing of the memory hole MH is indicated by arrow B1, and the bowing of the beam hole HR is indicated by arrow B2. More specifically, arrow B1 indicates the height at which the diameter of the memory hole MH is maximum, and arrow B2 indicates the height at which the diameter of the beam hole HR is maximum. When bowing occurs in the memory hole MH or the beam hole HR, the shapes of the columnar portion 4 and the beam portion 5 are affected by the bowing.

[0028] Generally, bowing is more likely to occur in a SiO2 film than in a SiN film (silicon nitride film). On the other hand, the memory hole MH of this embodiment is formed in the insulating film 2a and the sacrificial layer of the laminated film 2, and the beam hole HR of this embodiment is formed in the insulating film 2a and the sacrificial layer of the laminated film 2 and in the interlayer insulating film 3. As described above, the insulating film 2a and the interlayer insulating film 3 are, for example, SiO2 films. On the other hand, the sacrificial layer is, for example, a SiN film. Therefore, as shown in FIG. 1, bowing is more likely to occur in the beam hole HR than in the memory hole MH. This is because the proportion of the SiO2 film in the region where the beam hole HR is formed is generally greater than the proportion of the SiO2 film in the region where the memory hole MH is formed.

[0029] Therefore, the beam hole HR in this embodiment is formed after the impurity region 6 is formed in the staircase portion R2 and the interlayer insulating film 3, as described later, and is formed in the impurity region 6. In this case, the etching rate of the staircase portion R2 and the interlayer insulating film 3 in the impurity region 6 is higher than the etching rate of the staircase portion R2 and the interlayer insulating film 3 outside the impurity region 6. Therefore, according to this embodiment, by forming the beam hole HR in the impurity region 6, it is possible to reduce the bowing of the beam hole HR. The reason is that the beam hole HR can be formed at high speed, and therefore the beam hole HR can be completed before the bowing becomes large.

[0030] The etching rate of the step portion R2 and the interlayer insulating film 3 in the impurity region 6 increases as the P concentration increases. From this viewpoint, it is desirable to increase the P concentration in the impurity region 6 as a whole. However, if the P concentration in the step portion R2 increases, the breakdown voltage of the semiconductor device may deteriorate.

[0031] Therefore, the impurity region 6 of this embodiment may be formed to include an impurity region 6a having a high P concentration and an impurity region 6b having a low P concentration. The bowing of the beam hole HR is likely to occur near the upper surface of the interlayer insulating film 3 as shown in FIG. 1. Therefore, by forming the impurity region 6a near the upper surface of the interlayer insulating film 3, it is possible to effectively suppress the bowing of the beam hole HR. On the other hand, although the bowing of the beam hole HR also occurs in the staircase portion R2, it is difficult to become large in the staircase portion R2 compared to in the interlayer insulating film 3. Therefore, by forming the impurity region 6b below the impurity region 6a, it is possible to suppress the bowing of the beam hole HR while suppressing the deterioration of the breakdown voltage of the semiconductor device. In this way, according to this embodiment, it is possible to simultaneously suppress the bowing of the beam hole HR and the deterioration of the breakdown voltage of the semiconductor device.

[0032] There are various reasons why impurity atoms such as P atoms increase the etching rate of the step portion R2 and the interlayer insulating film 3. For example, when impurity atoms are implanted into the SiO2 film, the Si-O bonds in the SiO2 film are reduced, and the etching rate of the SiO2 film is increased. Also, when N atoms are implanted into the SiO2 film, the properties of the SiO2 film approach those of a SiN film, and the etching rate of the SiO2 film is increased. The impurity element used in this embodiment may be any element, such as B, As, Si, or N, as long as it can increase the etching rate of the step portion R2 and the interlayer insulating film 3.

[0033] In this embodiment, the height of the lower end of the impurity region 6a is set to be, for example, about 1 μm lower than the height of the upper surface of the interlayer insulating film 3. Furthermore, according to this embodiment, it is possible to reduce the maximum diameter of the beam hole HR indicated by the arrow B2 by, for example, several tens of percent compared to the diameter in the case where the impurity region 6 is not formed. That is, according to this embodiment, it is possible to reduce bowing of the beam hole HR.

[0034] The bowing in this embodiment may also occur when forming the contact holes CC. To reduce such bowing, it is preferable to form the contact holes CC in the impurity regions 6a and 6b. In this case, the impurity regions 6a and 6b for the contact holes CC may be formed separately from the impurity regions 6a and 6b for the beam holes HR. Moreover, the size of the impurity regions 6a and 6b for the beam holes HR may be increased to form the contact holes CC in the impurity regions 6a and 6b for the beam holes HR.

[0035] FIG. 2 is an enlarged cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0036] FIG. 2 shows one of the multiple columnar portions 4 shown in FIG. 1. Each columnar portion 4 in this embodiment includes a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e, which are formed in this order on the side surface of the stacked film 2. The block insulating film 4a is, for example, a SiO2 film. The charge storage layer 4b is, for example, an insulating film such as a SiN film. The charge storage layer 4b may be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 4c is, for example, a SiO2 film. The channel semiconductor layer 4d is, for example, a polysilicon layer. The core insulating film 4e is, for example, a SiO2 film.

[0037] 3 to 13 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0038] First, the laminated film 2 is formed on the substrate 1 (FIG. 3). The laminated film 2 is formed by alternately forming a plurality of insulating films 2a and a plurality of sacrificial layers 2b' on the substrate 1. The sacrificial layers 2b' are, for example, SiN films. The sacrificial layers 2b' are an example of the first layer. In this embodiment, the laminated film 2 is formed while processing the laminated film 2 into a staircase shape. As a result, the laminated film 2 is formed to include a flat portion R1 and a staircase portion R2. In FIG. 3, each of the flat portion R1 and the staircase portion R2 includes a plurality of insulating films 2a and a plurality of sacrificial layers 2b' alternately stacked in the Z direction.

[0039] Next, the interlayer insulating film 3 is formed on the stepped portion R2 (FIG. 3). The interlayer insulating film 3 is formed by forming the interlayer insulating film 3 on the flat portion R1 and the stepped portion R2, and polishing the surface of the interlayer insulating film 3 by CMP (Chemical Mechanical Polishing).

[0040] Next, a hard mask layer 11 is formed on the flat portion R1 and the interlayer insulating film 3 (FIG. 3). The hard mask layer 11 is, for example, a C (carbon) layer. The hard mask layer 11 is an example of a mask layer.

[0041] Next, a plurality of openings H1 are formed in the hard mask layer 11 by lithography and RIE (FIG. 4). In FIG.

[0042] Next, P ions are implanted into the interlayer insulating film 3 through the opening H1 (FIG. 5). As a result, a plurality of impurity regions 6a containing P atoms are formed in the interlayer insulating film 3 below the opening H1. At least one of these impurity regions 6a may also be formed in the stepped portion R2.

[0043] Next, P ions are further implanted into the interlayer insulating film 3 through the openings H1 (FIG. 6). As a result, a plurality of impurity regions 6b containing P atoms are formed in the interlayer insulating film 3 and the stepped portion R2 below the impurity regions 6a.

[0044] In this manner, a plurality of impurity regions 6 are formed in the interlayer insulating film 3 and the step portion R2 under the opening H1. Each impurity region 6 is formed to include an impurity region 6a containing a high concentration of P atoms and an impurity region 6b containing a low concentration of P atoms. The value of the P concentration in the impurity region 6a is, for example, 1.0×10 21 ~1.0×10 22 atoms / cm 3 The value of the P concentration in the impurity region 6b is, for example, 1.0×10 20 ~5.0×10 21 atoms / cm 3 In this embodiment, the etching rate of the staircase portion R2 and the interlayer insulating film 3 in the impurity region 6 is greater than the etching rate of the staircase portion R2 and the interlayer insulating film 3 outside the impurity region 6. Also, the etching rate of the staircase portion R2 and the interlayer insulating film 3 in the impurity region 6a is greater than the etching rate of the staircase portion R2 and the interlayer insulating film 3 in the impurity region 6b.

[0045] 5 and 6, P ions are implanted using a source gas containing P atoms. Examples of the source gas are PF3 gas and PH3 gas (F stands for fluorine and H stands for hydrogen). In the staircase portion R2, P ions are implanted into the insulating film 2a and the sacrificial layer 2b'. Therefore, each impurity region 6 in the staircase portion R2 is formed not only in the insulating film 2a but also in the sacrificial layer 2b'.

[0046] In the steps of Figures 5 and 6, ions other than P ions may be implanted. Examples of such ions include B ions, As ions, Si ions, and N ions. Examples of source gases in these cases include BF3 gas, B2H6 gas, AsH3 gas, SiF4 gas, and N2 gas.

[0047] Next, a plurality of openings H2 are formed in the hard mask layer 11 by lithography and RIE (FIG. 7). In FIG. 7, these openings H2 are formed on the flat portion R1.

[0048] Next, the stacked film 2 and the interlayer insulating film 3 are processed by RIE using the hard mask layer 11 (FIG. 8). As a result, a plurality of memory holes MH are formed in the flat portion R1 below the opening H2, and a plurality of beam holes HR are formed in the interlayer insulating film 3 and the stepped portion R2 below the opening H1. In this embodiment, the memory holes MH and the beam holes HR are simultaneously formed by this RIE.

[0049] In the process of FIG. 8, each beam hole HR is formed in the corresponding impurity region 6. According to this embodiment, by forming the beam hole HR in the impurity region 6a, it is possible to reduce the bowing of the beam hole HR. The reason is that by forming the impurity region 6a with a high P concentration in the interlayer insulating film 3 where the bowing is likely to be large, it is possible to effectively suppress the bowing of the beam hole HR. Also, according to this embodiment, by forming the beam hole HR in the impurity region 6b, it is possible to suppress the deterioration of the breakdown voltage of the semiconductor device while suppressing the bowing of the beam hole HR. The reason is that by forming the impurity region 6b with a low P concentration in the step portion R2 where P atoms are likely to cause the deterioration of the breakdown voltage, it is possible to achieve both the suppression of the deterioration of the breakdown voltage and the suppression of the bowing.

[0050] Next, a pillar portion 4 is formed in each memory hole MH, and a beam portion 5 is formed in each beam hole HR (FIG. 9). The pillar portion 4 is formed by sequentially burying a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e in each memory hole MH (see FIG. 2). The beam portion 5 is formed by burying an insulating film (e.g., a SiO2 film) in each beam hole HR. As a result, the beam portion 5 is formed so as to contact the corresponding impurity regions 6a, 6b. The beam portion 5 may be formed before the pillar portion 4 is formed, or after the pillar portion 4 is formed. In addition, the hard mask layer 11 may be removed before the pillar portion 4 and / or the beam portion 5 are formed, or after the pillar portion 4 and / or the beam portion 5 are formed.

[0051] Next, an interlayer insulating film 7 is formed on the laminated film 2, the interlayer insulating film 3, the columnar portion 4, the beam portion 5, and the impurity region 6 (FIG. 10).

[0052] Next, a plurality of contact holes CC are formed in the interlayer insulating films 7 and 3 and the laminated film 2 by lithography and RIE (FIG. 11). Each contact hole CC is formed so as to reach the upper surface of the corresponding sacrificial layer 2b'. In FIG. 11, each contact hole CC is formed at a position adjacent to the corresponding impurity region 6 (excluding the contact plug 8 on the far left in FIG. 11).

[0053] Next, contact plugs 8 are formed in each contact hole CC (FIG. 12). The contact plugs 8 are formed by burying a metal layer in each contact hole CC. As a result, the contact plugs 8 are formed so as to be in contact with the corresponding impurity regions 6 (except for the leftmost contact plug 8 in FIG. 12).

[0054] Next, each sacrificial layer 2b' in the laminated film 2 is replaced with an electrode layer 2b (FIG. 13). As a result, a structure including a plurality of insulating films 2a and a plurality of electrode layers 2b alternately is formed in the laminated film 2. Furthermore, each contact plug 8 is electrically connected to a corresponding electrode layer 2b. In the process of FIG. 13, the sacrificial layer 2b' is removed from the laminated film 2 by wet etching to form a plurality of cavities in the laminated film 2, and a metal layer is embedded in these cavities to form the electrode layers 2b in these cavities. This is called a replacement process.

[0055] The replacement step may be performed before the formation of the contact holes CC. For example, the replacement step may be performed between the step of Fig. 9 and the step of Fig. 10, or between the step of Fig. 10 and the step of Fig. 11. In this case, each contact hole CC is formed to reach the upper surface of the corresponding electrode layer 2b.

[0056] 13, P atoms are contained in the insulating film 2a but not in the electrode layer 2b. This is because the sacrificial layer 2b' is replaced with the electrode layer 2b after the formation of the impurity region 6. However, after the formation of the electrode layer 2b, P atoms may diffuse from the insulating film 2a or the interlayer insulating film 3 to the electrode layer 2b, so that the electrode layer 2b may contain a small amount of P atoms.

[0057] In this manner, the semiconductor device shown in FIG. 1 is manufactured.

[0058] As described above, each beam portion 5 in this embodiment is formed to contact the corresponding impurity region 6a, 6b. The P concentration in the impurity region 6b is set lower than the P concentration in the impurity region 6a. Therefore, according to this embodiment, it is possible to form the beam portion 5 in the beam hole HR with a small bowing by suppressing the bowing of the beam hole HR by a suitable process. For example, it is possible to suppress the bowing of the beam hole HR while suppressing the deterioration of the breakdown voltage of the semiconductor device.

[0059] In this embodiment, the impurity region 6 includes two regions (impurity regions 6a and 6b) with different P concentrations, but may include three or more regions with different P concentrations. The P concentration in the impurity region 6 may vary continuously depending on the position in the impurity region 6. For example, the impurity region 6 may include the impurity regions 6a and 6b in a form in which the boundary between the impurity region 6a and the impurity region 6b is not clear. In this case, the impurity regions 6a and 6b may be treated as two regions or as one region. This is the same in the second and third embodiments described later.

[0060] Second embodiment 14 to 20 are cross-sectional views showing a method for manufacturing the semiconductor device of the second embodiment. The method shown in Fig. 14 to 20 is a different process from the method shown in Fig. 3 to Fig. 13 for manufacturing the semiconductor device shown in Fig. 1.

[0061] First, the steps of Fig. 3 to Fig. 6 are carried out. Fig. 14 shows the same state as that shown in Fig. 6.

[0062] Next, the stacked film 2 and the interlayer insulating film 3 are processed by RIE using the hard mask layer 11 (FIG. 15). As a result, a plurality of beam holes HR are formed in the interlayer insulating film 3 and the stepped portion R2 under the opening H1.

[0063] In the process of Fig. 15, similarly to the process of Fig. 8, each beam hole HR is formed in the corresponding impurity region 6. According to this embodiment, by forming the beam hole HR in the impurity region 6a, it is possible to reduce the bowing of the beam hole HR. Also, according to this embodiment, by forming the beam hole HR in the impurity region 6b, it is possible to suppress the bowing of the beam hole HR while suppressing the deterioration of the breakdown voltage of the semiconductor device.

[0064] Next, the beam portion 5 is formed in each beam hole HR (FIG. 16). The beam portion 5 is formed by filling each beam hole HR with an insulating film (e.g., a SiO2 film). As a result, the beam portion 5 is formed so as to contact the corresponding impurity regions 6a, 6b. The hard mask layer 11 may be removed before the beam portion 5 is formed, or may be removed after the beam portion 5 is formed.

[0065] Next, a hard mask layer 12 is formed on the flat portion R1 and the interlayer insulating film 3 (FIG. 17). The hard mask layer 12 is, for example, a C layer.

[0066] Next, a plurality of openings H2 are formed in the hard mask layer 12 by lithography and RIE (FIG. 18). In FIG. 18, these openings H2 are formed on the flat portion R1.

[0067] Next, the laminated film 2 is processed by RIE using the hard mask layer 12 (FIG. 19). As a result, a plurality of memory holes MH are formed in the flat portion R1 below the opening H2. In this embodiment, the memory holes MH and the beam holes HR are formed in this order, and further, the contact holes CC are formed in a later process.

[0068] Next, a columnar portion 4 is formed in each memory hole MH (FIG. 20). The columnar portion 4 is formed by sequentially burying a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e in each memory hole MH (see FIG. 2). The hard mask layer 12 may be removed before or after the columnar portion 4 is formed.

[0069] 10 to 13 are then carried out, thus completing the manufacture of the semiconductor device shown in FIG.

[0070] According to this embodiment, similarly to the first embodiment, by suppressing the bowing of the beam hole HR by a suitable process, it becomes possible to form the beam portion 5 in the beam hole HR having a small bowing. Note that, although the beam hole HR in this embodiment is formed before the memory hole MH is formed, it may be formed after the memory hole MH is formed instead.

[0071] Third embodiment FIG. 21 is a cross-sectional view showing the structure of the semiconductor device of the third embodiment.

[0072] The semiconductor device of this embodiment (FIG. 21) has a structure similar to that of the semiconductor device of the first embodiment (FIG. 1). However, the semiconductor device of this embodiment does not include an interlayer insulating film 7. Therefore, each contact plug 8 of this embodiment does not include a portion provided in the interlayer insulating film 7. In this embodiment, as described later, the memory hole MH, the beam hole HR, and the contact hole CC are simultaneously formed by the same RIE.

[0073] 22 to 25 are cross-sectional views showing a method for manufacturing the semiconductor device of the third embodiment.

[0074] 3 to 6, a plurality of openings H2 and a plurality of openings H3 are formed in the hard mask layer 11 by lithography and RIE (FIG. 22). In FIG. 22, the openings H2 are formed on the flat portion R1, and the openings H3 are formed on the interlayer insulating film 3.

[0075] Next, the stacked film 2 and the interlayer insulating film 3 are processed by RIE using the hard mask layer 11 (FIG. 23). As a result, a plurality of memory holes MH are formed in the flat portion R1 below the opening H2, a plurality of beam holes HR are formed in the interlayer insulating film 3 and the staircase portion R2 below the opening H1, and a plurality of contact holes CC are formed in the interlayer insulating film 3 and the staircase portion R2 below the opening H3. In this embodiment, the memory holes MH, the beam holes HR, and the contact holes CC are simultaneously formed by this RIE.

[0076] In the process of Fig. 23, similarly to the process of Fig. 8 and the process of Fig. 15, each beam hole HR is formed in the corresponding impurity region 6. According to this embodiment, by forming the beam hole HR in the impurity region 6a, it is possible to reduce the bowing of the beam hole HR. Also, according to this embodiment, by forming the beam hole HR in the impurity region 6b, it is possible to suppress the bowing of the beam hole HR while suppressing the deterioration of the breakdown voltage of the semiconductor device.

[0077] Next, a columnar portion 4 is formed in each memory hole MH, a beam portion 5 is formed in each beam hole HR, and a contact plug 8 is formed in each contact hole CC (FIG. 24). The columnar portion 4 is formed by sequentially burying a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e in each memory hole MH (see FIG. 2). The beam portion 5 is formed by burying an insulating film in each beam hole HR, and is formed so as to contact the corresponding impurity region 6a, 6b. The contact plug 8 is formed by burying a metal layer in each contact hole CC, and is formed so as to contact the corresponding impurity region 6 (excluding the contact plug 8 on the far left in FIG. 24). The columnar portion 4, the beam portion 5, and the contact plug 8 may be formed in any order. In addition, the hard mask layer 11 may be removed before the columnar portion 4, the beam portion 5, and / or the contact plug 8 are formed, or may be removed after the columnar portion 4, the beam portion 5, and / or the contact plug 8 are formed.

[0078] Next, each sacrificial layer 2b' in the laminated film 2 is replaced with an electrode layer 2b (FIG. 25). As a result, a structure including a plurality of insulating films 2a and a plurality of electrode layers 2b alternately is formed in the laminated film 2. Furthermore, each contact plug 8 is electrically connected to the corresponding electrode layer 2b. The process of FIG. 25 can be performed in the same manner as the process of FIG. 13.

[0079] In this manner, the semiconductor device shown in FIG. 21 is manufactured.

[0080] According to this embodiment, similarly to the first and second embodiments, by suppressing the bowing of the beam hole HR by a suitable process, it becomes possible to form the beam portion 5 in the beam hole HR with a small bowing.

[0081] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel device and method described in this specification can be implemented in various other forms. In addition, various omissions, substitutions, and modifications can be made to the forms of the device and method described in this specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0082] 1: substrate, 2: laminated film, 2a: insulating film, 2b: electrode layer, 2b': sacrificial layer, 3: interlayer insulating film, 4: columnar portion, 4a: block insulating film, 4b: charge storage layer, 4c: tunnel insulating film, 4d: channel semiconductor layer, 4e: core insulating film, 5: Beam portion, 6: Impurity region, 6a: Impurity region, 6b: Impurity region, 7: interlayer insulating film; 8: contact plug; 11: hard mask layer, 12: hard mask layer

Claims

1. a laminated film including a plurality of electrode layers and a plurality of first insulating films alternately laminated in a first direction, the laminated film including a first portion having a non-step-like shape and a second portion having a step-like shape; A second insulating film provided on the second portion; a columnar portion extending in the first direction within the first portion and including a charge storage layer and a semiconductor layer; a third insulating film extending in the first direction through the second portion and the second insulating film; a plug provided on any of the electrode layers of the second portion; a first region provided in the second portion and the second insulating film and including a first element; a concentration of the first element in the first region is higher than a concentration of the first element in a region of the second insulating film outside the first region, the third insulating film or the plug is in contact with the first region; Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the first region includes an upper region containing the first element at a first concentration, and a lower region provided below the upper region and containing the first element at a second concentration lower than the first concentration.

3. The semiconductor device according to claim 1 , wherein said third insulating film or said plug is provided in said first region.

4. 3. The semiconductor device according to claim 2, wherein said third insulating film or said plug is in contact with said upper region and said lower region.

5. the upper region includes at least the second insulating film, The lower region includes at least the second portion. The semiconductor device according to claim 2 .

6. The semiconductor device according to claim 1 , wherein said first region includes said first insulating film of said second portion.

7. 2. The semiconductor device according to claim 1, wherein said first element is an impurity element in said second portion and said second insulating film.

8. The semiconductor device according to claim 1 , wherein the first element is P (phosphorus).

9. The first concentration is 1.0×10 ２１ ~1.0 x 10 ２２ atoms / cm ３ and The second concentration is 1.0×10 ２０ ~5.0 x 10 ２１ atoms / cm ３ That is, The semiconductor device according to claim 1 .

10. forming a laminated film including a plurality of first layers and a plurality of first insulating films alternately laminated in a first direction, the laminated film including a first portion having a non-step-like shape and a second portion having a step-like shape; forming a second insulating film on the second portion; forming a first region including a first element in the second portion and the second insulating film; forming a columnar portion extending in the first direction within the first portion and including a charge storage layer and a semiconductor layer; forming a third insulating film extending in the first direction in the second portion and in the second insulating film; replacing the first layers in the film stack with a plurality of electrode layers; forming a plug on either the first layer or the electrode layer of the second portion; Including, a concentration of the first element in the first region is set higher than a concentration of the first element in a region of the second insulating film outside the first region; the third insulating film or the plug is formed so as to be in contact with the first region; A method for manufacturing a semiconductor device.

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the first region is formed to include an upper region containing the first element at a first concentration, and a lower region provided below the upper region and containing the first element at a second concentration lower than the first concentration.

12. The method for manufacturing a semiconductor device according to claim 10 , wherein the third insulating film or the plug is formed after the first region is formed.

13. The method of claim 11 , wherein the lower region is formed after the upper region is formed.

14. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the first region is formed in the first layer of the second portion and in the first insulating film.

15. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the first region is formed by implanting ions of the first element into the second insulating film and the second portion.

16. 16. The method for manufacturing a semiconductor device according to claim 15, wherein after implantation of ions of the first element, an etching rate of the second insulating film and the second portion in the first region is greater than an etching rate of the second insulating film and the second portion outside the first region.

17. forming a mask layer on the second insulating film; forming an opening in the mask layer; Further including:

16. The method for manufacturing a semiconductor device according to claim 15, wherein the first region is formed by implanting ions of the first element into the second insulating film and the second portion through the opening.

18. forming a recess in the second insulating film and the second portion after forming the first region; 18. The method for manufacturing a semiconductor device according to claim 17, wherein the third insulating film or the plug is formed in the recess so as to be in contact with the first region.

19. forming a first recess extending in the first direction within the first portion; forming a second recess extending in the first direction in the second portion and the second insulating film; forming a third recess on either the first layer or the electrode layer of the second portion; Further including:

11. The method for manufacturing a semiconductor device according to claim 10, wherein the columnar portion, the third insulating film, and the plug are formed in the first recess, the second recess, and the third recess, respectively.

20. 20. The method of claim 18, wherein two or more of the first recess, the second recess, and the third recess are formed simultaneously.

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