Semiconductor device

Abstract

To provide a semiconductor device with improved reliability, a semiconductor device with stable characteristics, a transistor with small current at non-conduction, a transistor with large current at conduction, a novel semiconductor device, a novel electronic appliance, or the like.SOLUTION: In a semiconductor device, a first semiconductor is formed on a substrate, a second semiconductor is formed on and in contact with the first semiconductor, a first layer is formed on the second semiconductor, a third semiconductor is formed on and in contact with the second semiconductor by performing oxygen plasma processing and then removing the first layer so as to expose at least a part of a surface of the second semiconductor, a first insulator is formed on and in contact with the third semiconductor, and a first conductor is formed on the first insulator.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. Therefore, one aspect of the present invention disclosed in the present specification more specifically relates to a The technical fields of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, imaging devices, and memory devices. , their driving methods, or their manufacturing methods can be cited as examples.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. An example of such a device is a semiconductor element such as a transistor or a diode. In another example, a circuit having a semiconductor element is a semiconductor device. As another example, a device including a circuit having a semiconductor element is a semiconductor device. do. [Background technology]

[0004] In recent years, metal oxides that exhibit semiconducting properties have been used in transistors instead of silicon semiconductors. This technology is attracting attention.

[0005] Patent Document 1 describes a transistor using an oxide semiconductor. Oxygen is added to the film in contact with the semiconductor or oxide semiconductor using oxygen plasma or the like, and the film is oxidized. The idea of ​​improving the characteristics of transistors by supplying oxygen to semiconductors has been presented. do.

[0006] In addition, Non-Patent Document 1 states that the absorption observed in the ESR spectrum near g value = 1.93 is The main cause is carriers generated when hydrogen is captured by oxygen vacancies in oxide semiconductors. It has been suggested that this is the case. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2010-080947 A [Non-patent literature]

[0008] [Non-Patent Document 1] Yusuke Nonaka et. al, “Investigation of defects in In-Ga-Zn oxide thin film using electron spin resonance signals”, JOURNAL OF APPLIED PHYSICS, 2014, 115, pp. 163707-1-163707-5 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a highly reliable semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device having stable characteristics. .

[0010] Another object of one embodiment of the present invention is to reduce oxygen vacancies in an oxide semiconductor. Another object of one embodiment of the present invention is to reduce the hydrogen concentration in an oxide semiconductor. Another embodiment of the present invention is a transistor including an oxide semiconductor with few oxygen vacancies. Another object of the present invention is to provide an oxide semiconductor having a low hydrogen concentration. Another object of the present invention is to provide a transistor including a conductor. The object of the present invention is to control the fluctuation, variation, or decrease in the threshold voltage of a transistor. Another embodiment of the present invention provides a transistor that has a small current when off. Another object of one embodiment of the present invention is to provide a transistor that has a large current when turned on. Another object of the present invention is to provide a transistor comprising: One object of the present invention is to provide a method.

[0011] Another embodiment of the present invention is to provide a method for reducing oxygen vacancies in an oxide semiconductor. Another object of one embodiment of the present invention is to provide a method for reducing the hydrogen concentration in an oxide semiconductor. One of our goals is to provide a method for

[0012] Another object of one embodiment of the present invention is to provide a novel semiconductor device, a novel electronic device, or the like. Another aspect of the present invention is to provide a method for manufacturing a novel semiconductor device. This is one of the challenges.

[0013] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. However, this does not preclude the existence of other problems. The other problems are described below. The issues not mentioned in this section are issues that are not mentioned in the description of the specification or drawings, etc. These can be derived from the above and can be appropriately extracted from these descriptions. One aspect of the present invention is to solve at least one of the above-listed problems and / or other problems. This is what is decided. [Means for solving the problem]

[0014] According to one aspect of the present invention, a first semiconductor is formed on a substrate, and a second semiconductor is disposed on the first semiconductor so as to be in contact with the first semiconductor. After forming a second semiconductor, forming a first layer on the second semiconductor, and performing oxygen plasma treatment, removing the first layer to expose at least a portion of a surface of the second semiconductor; A third semiconductor is formed so as to be in contact with the first insulator. The present invention relates to a method for manufacturing a semiconductor device, in which a first conductor is formed on a first insulator.

[0015] Alternatively, one embodiment of the present invention is a method for forming a first semiconductor on a substrate, A second semiconductor is formed so as to be in contact with an upper surface of the second semiconductor, and a pair of conductors is formed. a first layer is formed so as to be in contact with the upper surfaces of the pair of conductors and the upper surface of the second semiconductor; After performing the oxygen plasma treatment, the first layer is removed to expose the surface of the second semiconductor. A third semiconductor is formed so as to be in contact with the upper surface of the conductor and the upper surface of the second semiconductor. forming a first insulator on the semiconductor and in contact with the first insulator; and forming a first conductor on the first insulator. The present invention relates to a method for manufacturing a semiconductor device.

[0016] Alternatively, one embodiment of the present invention is a method for forming a first semiconductor on a substrate, A second semiconductor is formed so as to contact an upper surface of the second semiconductor, and a first layer is formed so as to contact an upper surface of the second semiconductor. After the nitrogen plasma treatment, the first layer is removed to expose the surface of the second semiconductor. A pair of conductors is formed so as to contact the upper surface of the semiconductor, and the upper surfaces of the pair of conductors and the second semiconductor A third semiconductor is formed so as to be in contact with the upper surface of the conductor, and a second semiconductor is formed so as to be in contact with the third semiconductor. A method for manufacturing a semiconductor device, comprising forming a first insulator and forming a first conductor on the first insulator. be.

[0017] In the above-mentioned configuration, the first layer has a higher water resistance than the first semiconductor or the third semiconductor. It is preferable that the material has permeability.

[0018] In the above structure, the first layer is made of boron, carbon, fluorine, magnesium, aluminum, etc. Aluminum, silicon, phosphorus, chlorine, argon, titanium, vanadium, chromium, manganese, cobalt Baltic, Nickel, Copper, Zinc, Gallium, Germanium, Yttrium, Zirconium, Niobium, molybdenum, ruthenium, indium, tin, lanthanum, neodymium, hafnium It is preferred that the oxide comprises tantalum or tungsten.

[0019] In the above structure, the second semiconductor includes indium, the element M, and zinc. M is aluminum, gallium, yttrium, tin, boron, silicon, titanium, iron, Nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium Preferably, the metal is aluminum, neodymium, hafnium, tantalum, or tungsten.

[0020] Other aspects of the present invention will be described in the following embodiments and As shown in the drawings. Effect of the Invention

[0021] According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment, a semiconductor device having stable characteristics can be provided.

[0022] According to one embodiment of the present invention, oxygen vacancies in an oxide semiconductor can be reduced. According to one embodiment of the present invention, the hydrogen concentration in the oxide semiconductor can be reduced. According to one embodiment of the present invention, a transistor including an oxide semiconductor with few oxygen vacancies is provided. According to one embodiment of the present invention, a transistor including an oxide semiconductor with a low hydrogen concentration can be manufactured. According to one embodiment of the present invention, a threshold voltage of a transistor can be set. In addition, the present invention provides a method for controlling the fluctuation, variation, or decrease in the voltage of a power supply. This makes it possible to provide a transistor that has a small current when non-conducting. According to one embodiment, a transistor that has a large current when conducting can be provided. According to one embodiment of the present invention, a method for manufacturing the transistor can be provided.

[0023] According to another embodiment of the present invention, there is provided a method for reducing oxygen vacancies in an oxide semiconductor. According to one embodiment of the present invention, a method for reducing the hydrogen concentration in an oxide semiconductor can be provided. can be provided.

[0024] According to one embodiment of the present invention, a novel semiconductor device, a novel electronic device, or the like can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided. Cut.

[0025] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. However, this does not preclude the existence of other effects. Other effects may be affected by this item, as described below. Effects not mentioned in this section are effects not mentioned in the description of the specification or drawings, etc. These can be derived from the above and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the above-listed effects and / or other effects. Therefore, in some cases, one embodiment of the present invention may not have the effects listed above. In some cases, this is not possible. [Brief description of the drawings]

[0026] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Diagram 2] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Diagram 3] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Diagram 5] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 7] 1 is a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 8] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 9] 1 is a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 10] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 11] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 12] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 16]1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 17] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 18] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 19] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 20] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 21] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 22] 1A to 1C illustrate a method for manufacturing a transistor of one embodiment of the present invention. [Figure 23] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 25] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 26] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 27] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 28] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 29] Electron diffraction pattern of CAAC-OS. [Diagram 30] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 31] Schematic diagram explaining the film formation model of CAAC-OS and nc-OS. [Diagram 32] A diagram explaining InGaZnO4 crystals and pellets. [Diagram 33] Schematic diagram explaining a film formation model of CAAC-OS. [Diagram 34] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 35]FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 36] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 39] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 40] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 41] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 42] 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 43] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 44] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 45] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 46] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 47] FIG. 1 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Figure 48] FIG. 1 shows spin density evaluated by electron spin resonance. [Figure 49] FIG. 4 is a diagram for explaining the hydrogen concentration depth profile of a sample in an example. [Figure 50] FIG. 1 shows spin density evaluated by electron spin resonance. [Figure 51] FIG. 4 is a diagram for explaining the hydrogen concentration depth profile of a sample in an example. [Figure 52] FIG. 4 is a diagram for explaining the hydrogen concentration depth profile of a sample in an example. [Figure 53] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 54] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 55] 1A and 1B are cross-sectional views showing stacked layers of semiconductors and diagrams showing band structures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details are possible. In addition, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used It is used commonly across different drawings. Note that when referring to similar objects, the hatch pattern is used in the same way. In some cases, no particular symbol is given.

[0028] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where this is the case.

[0029] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it includes the case where the angle is between 85° and 95°. refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0030] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. do.

[0031] The ordinal numbers 1 and 2 are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. For example, "first" should not be changed to "second" or "third" etc. In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. However, the ordinal numbers used to identify an aspect of the present invention may not be consistent.

[0032] Even if a material is described as a "semiconductor," it may be considered an "insulator" if, for example, its electrical conductivity is sufficiently low. In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. In some cases, the distinction cannot be made precisely. Therefore, the term "semiconductor" as used herein means "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." In some cases, this can be rephrased as "body."

[0033] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and not strictly defined. In some cases, the distinction may not be clear. Therefore, the term "semiconductor" as used herein means "conductor" or "electroconductor". Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor In some cases, this can be rephrased as "body."

[0034] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements present at less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the conductor and carrier movement The degree of conductivity may decrease, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, , hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies can be eliminated by the inclusion of impurities such as hydrogen. In addition, when the semiconductor is silicon, there are cases where a defect that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0035] In the following embodiments, unless otherwise specified, the insulator is, for example, boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing one or more of hafnium and tantalum may be used in a single layer or a multilayer structure. Alternatively, resin may be used as the insulator. For example, polyimide, polyamide, Resin containing acrylic, silicone, etc. can be used. By using resin, the upper surface of the insulator In some cases, it may not be necessary to perform flattening treatment on the surface. Also, resin can form a thick film in a short time. As a result, productivity can be improved. The insulator is preferably aluminum oxide. , silicon oxide nitride, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide Insulators containing tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used in a single layer or in a laminate.

[0036] In the following embodiments, unless otherwise specified, the conductor is, for example, boron. element, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, Cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, Conductors containing one or more of ruthenium, silver, indium, tin, tantalum, or tungsten For example, an alloy film or a compound film may be used. Conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese Conductors containing indium, tin and oxygen, and conductors containing titanium and nitrogen are used. This is also fine.

[0037] In this specification, when it is stated that A has a region of concentration B, for example, If the concentration in the entire depth direction of a certain area is B, the average concentration in the depth direction of the area of ​​A is If the average value is concentration B, then the median value in the depth direction in a region of A is concentration B, If the maximum value in the depth direction in a region of A is concentration B, then If the minimum value in the direction is concentration B, then the convergence value in the depth direction in a region of A is concentration B. This includes cases where the area where the most likely value of A is obtained is concentration B. .

[0038] In this specification, A represents an area of ​​size B, length B, thickness B, width B or distance B. When describing something as having a certain area, for example, the whole of A has size B, length B, thickness B, etc. If B, width B or distance B, the average value in a certain area of ​​A is size B, length B, thickness B If the length, width or distance of A is B, the median value of the area of ​​A is B, B If thickness B, width B, or distance B, the maximum value in a certain area of ​​A is size B, length B , thickness B, width B or distance B, the minimum value of an area of ​​A is the size B, length If A has a size B, thickness B, width B or distance B, then the convergence value in a region of A is size B, length B When the length B, thickness B, width B or distance B is measured, the most likely value of A itself can be obtained. This includes cases where the area has size B, length B, thickness B, width B or distance B.

[0039] The words "membrane" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be replaced with "conductive Alternatively, for example, the term "insulating film" may be used. In some cases, the terminology may be changed to the term "insulating layer."

[0040] (Embodiment 1) In this embodiment, a transistor according to one embodiment of the present invention and a semiconductor device including the transistor The manufacturing method thereof will be described.

[0041] <Transistor structure> FIG. 1A is an example of a top view of a transistor 490. An example of a cross-sectional view corresponding to the line A2 and the dashed line A3-A4 is shown in FIG. In order to facilitate understanding, some insulators and other parts are omitted in FIG. 1(A).

[0042] The transistor 490 shown in FIG. 1 includes a conductor 413, an insulator 402 on the conductor 413, and , a semiconductor 406a on the insulator 402, a semiconductor 406b on the semiconductor 406a, and a semiconductor 4 The conductors 416a and 416b are in contact with the side of the semiconductor 406a and the top and side of the semiconductor 406b. and the conductor 416b, the side surface of the semiconductor 406a, the top surface and side surface of the semiconductor 406b, and the conductor The semiconductor 416a and the conductor 416b are in contact with each other. 406c, an insulator 412 on the semiconductor 406c, and a conductor 404 on the insulator 412. Note that the conductor 413 is a part of the transistor 490. For example, the conductor 413 may be a separate component from the transistor 490. It is also possible to use the following.

[0043] Here, the transistor 490 is provided, for example, on the substrate 442 as shown in FIG. The substrate 442 may be a semiconductor substrate, an SOI substrate, a glass substrate, a quartz substrate, or a plastic substrate. , metal substrate, stainless steel substrate, substrate with stainless steel foil, tantalum Tungsten substrate, substrate with tungsten foil, flexible substrate, lamination film, Paper containing fibrous materials or base film can be used as the semiconductor substrate. For example, elemental semiconductors such as silicon and germanium, or silicon carbide and silicon gel Al, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, gallium oxide, etc. The substrate 442 may be made of an amorphous semiconductor or a crystalline semiconductor. As the crystalline semiconductor, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, etc. can be used. Crystalline semiconductors.

[0044] Here, an insulator may be provided between the substrate 442 and the conductor 413 .

[0045] Alternatively, the transistor 490 may be provided on a substrate, as will be described later in the description of FIG. The transistor 491 and the transistor 492 may be stacked on the stomach.

[0046] The conductor 413 functions as a gate electrode of a transistor. 2 functions as a gate insulator of the transistor 490. and the conductor 416b serves as a source electrode and a drain electrode of the transistor 490. The insulator 412 also functions as a gate insulator for the transistor 490. The conductor 404 also functions as a gate electrode of the transistor 490. do.

[0047] Note that the conductor 413 and the conductor 404 are both used as gate electrodes of transistors. The electric potentials applied to each of the conductors may be different. The threshold voltage of the transistor 490 is adjusted by applying a negative or positive gate voltage to the transistor 13. Alternatively, the conductor 413 and the conductor 404 may be arranged as shown in FIG. The same potential may be applied by electrically connecting the electrodes using a body 421 or the like. Since the effective channel width can be increased, the current when the transistor 490 is turned on In addition, the electric field can be guided to a region where the electric field is difficult to reach with only the conductor 404. Since the insulator 413 can cover the subthreshold of the transistor 490, The switching value (also called S value) of the transistor 490 can be reduced. The electric current can be reduced by the conductor 421. Please refer to the descriptions in a etc.

[0048] Alternatively, transistor 490 may not have conductor 413 as shown in FIG. stomach.

[0049] Note that the insulator 402 is preferably an insulator containing excess oxygen.

[0050] For example, an insulator containing excess oxygen can be used as an insulator that has the function of releasing oxygen by heat treatment. For example, silicon oxide containing excess oxygen releases oxygen when heated. Therefore, the insulator 402 is a silicon oxide that can move oxygen through the film. That is, the insulator 402 may be an insulator having oxygen permeability. For example, The insulator 402 may be an insulator having higher oxygen permeability than the semiconductor 406a.

[0051] The insulator containing excess oxygen may have a function of reducing oxygen vacancies in the semiconductor 406b. In the semiconductor 406b, oxygen vacancies form DOS, which become hole traps, etc. In addition, hydrogen can enter the oxygen vacancy site, generating electrons as carriers. Therefore, by reducing oxygen vacancies in the semiconductor 406b, the transistor 490 It is possible to impart stable electrical characteristics to the

[0052] Here, the insulator that releases oxygen by heat treatment is analyzed by thermal desorption spectroscopy (TDS). Thermal Desorption Spectroscopy (TDS) analysis at 100℃ 1×10 in the range of surface temperature from 700℃ to 700℃ or from 100℃ to 500℃ 18 at oms / cm 3 That's it, 1×10 19 atoms / cm 3 or more than 1×10 20 atom s / cm3 It may even release more than this amount of oxygen (calculated as the number of oxygen atoms).

[0053] Here, a method for measuring the amount of released oxygen using TDS analysis will be described below.

[0054] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated by the integral value of the ion intensity of the released gas. and by comparison with a standard sample the total amount of gas released can be calculated.

[0055] For example, the results of a TDS analysis of a silicon substrate containing a standard sample of hydrogen with a given density, From the results of the TDS analysis of the measured sample, the amount of oxygen molecules released from the measured sample (N O2 ) is shown below Here, the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis is We assume that all of the oxygen molecules are derived from CH3OH. This is not considered here as it is unlikely. Also, the mass number of the isotope of the oxygen atom is 17. The existence of oxygen atoms with mass number 18 and oxygen molecules with mass number 18 in nature is also Not taken into consideration as the ratio is extremely small.

[0056] N O2 =N H2 / S H2 ×S O2 ×α

[0057] N H2 is the density of hydrogen molecules desorbed from the standard sample. H2 is the standard This is the integral value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let us assume that S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. Details of the above formula For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. 1×10 16 atoms / cm 2 The measurements were performed using a silicon substrate containing hydrogen atoms.

[0058] In addition, some of the oxygen is detected as oxygen atoms in the TDS analysis. The ratio of atoms can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate of the molecules, the amount of released oxygen molecules can be evaluated to determine the amount of released oxygen atoms. It is also possible to estimate.

[0059] In addition, N O2 is the amount of oxygen molecules released. The amount of oxygen released when converted to oxygen atoms is This is twice the amount of offspring released.

[0060] Alternatively, insulators that release oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to the peroxide radical is 5×10 17 spins / cm 3 Insulators that contain peroxide radicals have an ESR g value of 2 or more. It may also have an asymmetric signal around .01.

[0061] Alternatively, an insulator containing excess oxygen can be called silicon oxide (SiO X (X>2) Silicon oxide (SiO X (X>2) is the number of silicon atoms It contains more than twice as many oxygen atoms per unit volume as silicon per unit volume. The number of atoms and the number of oxygen atoms were measured by Rutherford backscattering (RBS). The values ​​were measured using Backscattering Spectrometry.

[0062] The insulator 412 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or oxide. Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, silicon nitride Silicon or the like may be used, and the film may be provided as a laminate or a single layer.

[0063] The insulator 412 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), high-k materials such as yttrium oxide may also be used. .

[0064] The insulator 412 may be aluminum oxide, magnesium oxide, silicon oxide, or oxide. Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Oxide insulation such as titanium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide Films such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride. The insulating film can be formed using a nitride insulating film or a film made of a mixture of the above materials.

[0065] In addition, as the insulator 412, similar to the insulator 402, a material having a stoichiometric composition other than oxygen is used. It is preferable to use an oxide insulating film containing as much oxygen as possible.

[0066] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. For example, hafnium oxide, aluminum oxide, and oxide are mixed in the gate insulating film. By using a material with many electron capture levels, such as tantalum, and by using a material that can withstand higher temperatures (the operating temperature of semiconductor devices), Or higher than the storage temperature, or 125°C to 450°C, typically 1 At a temperature of 50°C or higher and 300°C or lower, the potential of the gate electrode is set to the potential of the source electrode or drain electrode. By maintaining the higher temperature for at least one second, typically at least one minute, the gate voltage is released from the semiconductor layer. Electrons move toward the pole, some of which are captured by the electron capture level.

[0067] In this way, a transistor that has captured the necessary number of electrons in the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The treatment for adding the conductive layer may be performed during the manufacturing process of a transistor.

[0068] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After, or after the completion of the pre-process (wafer processing), or after the wafer dicing process It is advisable to carry out the inspection at any stage before shipment from the factory, after packaging, etc. It is preferred that the subsequent exposure to temperatures above 125° C. is not allowed for more than one hour.

[0069] In addition, nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2, Generally speaking, NO2 or NO forms a level in the insulator 412. The nitroxide is located in the energy gap of the insulator 412 and the When the charge-transfer level diffuses to the interface between the insulator 412 and the semiconductor 406, the charge-transfer level traps electrons on the insulator 412 side. As a result, the trapped electrons may move to the interface between the insulator 412 and the semiconductor 406. Since they remain in the vicinity, they shift the threshold voltage of the transistor in the positive direction.

[0070] As the insulator 412, an oxide insulating film having a low nitrogen oxide content and a low density of defect states is used. By doing so, it is possible to reduce the shift in the threshold voltage of the transistor. This can reduce the fluctuation in the electrical characteristics of the stator.

[0071] Heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher but below the substrate distortion point. By heat treatment, the insulator 412 is measured by ESR (electron spin resonance) below 100K. In the obtained spectrum, the first signal, g A second signal with a g value between 2.001 and 2.003, and a second signal with a g value between 1.964 and 1.9 The third signal of 66 or less is not observed. The split width, the second signal, and the third signal split width are set to the X-band The ESR measurement shows that the g value is about 5 mT. The first a signal with a g value between 2.001 and 2.003, and a second signal with a g value between 1.9 The sum of the spin densities of the third signal, which is greater than or equal to 64 and less than or equal to 1.966, is below the detection limit. Typically, it is 1×10 17 spins / cm 3 The ESR measurement temperature is as follows. Must be 100K or less.

[0072] In the ESR spectrum, the first signal with a g value of 2.037 to 2.039 , the second signal with a g value of 2.001 to 2.003, and the second signal with a g value of 1.964 to 1. The third signal, below .966, corresponds to the signal due to nitrogen dioxide. The first signal is between 2.037 and 2.039, and the g value is between 2.001 and 2.003. and the third signal having a g value of 1.964 or more and 1.966 or less. The lower the total density of the pins, the lower the nitrogen oxide content in the oxide insulating film. Hereinafter, these three signals will be referred to as "NOx-induced signals."

[0073] In addition, the oxide insulating film has a low density of nitrogen oxides and a low density of defect levels. The nitrogen concentration measured by ondary ion mass spectrometry 2×10 20 atoms / cm 3 Less than 7×10 19 atoms / cm 3 Less than 2×10 19 atoms / cm 3 The higher the deposition temperature of the insulator 412, the greater the insulating The nitrogen oxide content of the insulator 412 can be reduced. The deposition temperature of the insulator 412 is 450°C or higher but lower than the substrate distortion point, 500°C or higher but lower than the substrate distortion point, or 500°C or higher but lower than 55°C A temperature below 0°C is preferred.

[0074] As shown in FIG. 1, the side surfaces of the conductor 416a and the conductor 416b are The electric field of the conductor 404 electrically surrounds the semiconductor 406b. (The electric field of a conductor can electrically surround a semiconductor, forming a transistor structure. This is called the surrounded channel (s-channel) structure. Therefore, a channel may be formed in the entire (bulk) of the semiconductor 406b. In the n-type transistor, a large current can flow between the source and drain of the transistor, and the The current (on-state current) can be increased.

[0075] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. For example, The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. More preferably, the transistor has a channel width of 20 nm or less. or less than 40 nm, more preferably less than 30 nm, and even more preferably less than 20 nm. It has a range.

[0076] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part through which current flows when the transistor is on). The source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum value, minimum value, and The value is the average value.

[0077] The channel width is the width of the semiconductor (or transistor) when it is in the on state. In the region where the gate electrode overlaps with the gate electrode (where the current flows) or in the region where the channel is formed, This refers to the length of the part where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum value, minimum value, and maximum value in the region where the channel is formed. The value is the average value.

[0078] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in transistors with a fine, three-dimensional structure, the lateral surface of the semiconductor In this case, the ratio of the channel region formed in the top view may be large. The effective channel width of the channel is actually formed rather than the apparent channel width shown. will be larger.

[0079] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width unless the exact channel conditions are known. .

[0080] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is defined as the "surrounded channel width (SCW)". In this specification, when it is simply referred to as the channel width, In some cases, this refers to the enclosed channel width or apparent channel width. In the detailed description, when the term "channel width" is used simply, it may refer to the effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, enclosure The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. , values ​​can be determined.

[0081] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0082] Next, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c will be described.

[0083] The semiconductor 406b is, for example, an oxide semiconductor containing indium. For example, when indium is contained, the carrier mobility (electron mobility) increases. The body 406b preferably contains the element M. The element M is preferably aluminum, gallium, or the like. Other elements that can be used for element M include: Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, These include lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, the element M may be a combination of two or more of the above elements. For example, it is an element with a high bond energy with oxygen. Alternatively, the element M may be, for example, an element having an energy higher than that of an oxide semiconductor. It is an element that has the function of widening the gap. In addition, when the semiconductor 406b contains zinc, It is preferable that the oxide semiconductor be easily crystallized when it contains zinc.

[0084] However, the semiconductor 406b is not limited to an oxide semiconductor containing indium. 06b does not contain indium, such as zinc tin oxide, gallium tin oxide, etc. Oxide semiconductors containing zinc, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It's okay if there is.

[0085] The semiconductor 406b is made of, for example, an oxide having a large energy gap. The energy gap of 6b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2. The potential is set to 8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0086] For example, the semiconductor 406a and the semiconductor 406c contain oxygen other than that constituting the semiconductor 406b. The semiconductor 406b is an oxide semiconductor including one or more of the following elements: The semiconductor 406a and the semiconductor 406b are made of one or more elements other than oxygen. 6c is formed, the interface between the semiconductor 406a and the semiconductor 406b and the semiconductor 406 At the interface between the semiconductor 406c and the semiconductor 406b, an interface state is unlikely to be formed.

[0087] The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c each contain at least indium. When the semiconductor 406a is an In-M-Zn oxide, the sum of In and M is When In is 100 atomic %, it is preferable that In is less than 50 atomic % and M is 5. 0 atomic % or more, more preferably In is less than 25 atomic % and M is 7 5 atomic % or more. Also, the semiconductor 406b is an In-M-Zn oxide. When the sum of In and M is 100 atomic %, In is preferably 25 atomic %. mic%, M is less than 75 atomic%, and more preferably In is 34 atomic%. % and M is less than 66 atomic %. In the case of M-Zn oxide, when the sum of In and M is 100 atomic %, it is preferable Preferably, In is less than 50 atomic % and M is greater than 50 atomic %. In is less than 25 atomic % and M is greater than 75 atomic %. The semiconductor 406c may be made of the same oxide as the semiconductor 406a.

[0088] The semiconductor 406b is an acid having a higher electron affinity than the semiconductor 406a and the semiconductor 406c. For example, the semiconductor 406b is a compound having a higher conductivity than the semiconductors 406a and 406c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. V or less, more preferably, an oxide having a larger energy than the above by 0.15 eV to 0.4 eV is used. , electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0089] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the semiconductor 406c preferably contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 100% or more. More preferably, it is 90% or more.

[0090] At this time, when an electric field is applied to the gate electrode, the semiconductor 406a, the semiconductor 406b, and the semiconductor Of the semiconductor layers 406c, a channel is formed in the semiconductor layer 406b having a large electron affinity.

[0091] Here, between the semiconductor 406a and the semiconductor 406b, In addition, between the semiconductor 406b and the semiconductor 406c, In some cases, the semiconductor 406b and the semiconductor 406c may have a mixed region. The level density is reduced. Therefore, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c In the laminate, the energy changes continuously near each interface (continuous junction). 55A shows a band structure of the semiconductor 406a and the semiconductor 406b. FIG. 55(B) is a cross-sectional view of a semiconductor 406c laminated in this order. The energy (Ec) of the conduction band edge corresponding to the dashed line P1-P2 in A is the energy of the semiconductor 4 FIG. 55(C) shows a case where the electron affinity of the semiconductor 406c is larger than that of the semiconductor 406a. This shows a case where the electron affinity of the semiconductor 406c is smaller than that of the conductor 406a.

[0092] At this time, the electrons are not in the semiconductor 406a and the semiconductor 406c but in the semiconductor 406 As described above, the electrons move mainly through the interface between the semiconductor 406a and the semiconductor 406b. , and the interface state density at the interface between the semiconductor 406b and the semiconductor 406c. By lowering the temperature, the movement of electrons in the semiconductor 406b is less hindered, and the The on-current of the transistor 490 can be increased.

[0093] The on-current of the transistor 490 is increased so that the factors that hinder the movement of electrons are reduced. For example, if there is no factor that inhibits the movement of electrons, the electrons can move efficiently. It is presumed that the electron movement is hindered, for example, when the physical unevenness of the channel formation region is large. This also occurs in cases where

[0094] Therefore, in order to increase the on-current of the transistor 490, for example, the semiconductor 40 6b (surface to be formed, semiconductor 406a in this case) in a range of 1 μm×1 μm The root mean square (RMS) roughness at less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0. The average surface roughness (Ra) in an area of ​​1 μm x 1 μm should be less than 4 nm. ) is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, More preferably, it is set to less than 0.4 nm. The peak-to-peak difference (PV) is less than 10 nm, preferably less than 9 nm, and more preferably less than 8 The RMS roughness, Ra and PV are: Scanning probe microscope system SPA-50 manufactured by SII NanoTechnology Inc. 0, etc.

[0095] Alternatively, for example, when the density of defect states in the region where the channel is formed is high, the electron Movement is hindered.

[0096] Here, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c are made of an insulator or a conductor. The transistor 490 may be made of either the semiconductor 406a or the semiconductor 406c. It may be possible to have neither one nor both.

[0097] The impurity concentration in the semiconductor 406 can be measured by SIMS.

[0098] For example, consider a case where the semiconductor 406b has an oxygen vacancy. Hydrogen enters the oxygen vacancy. In this case, the oxygen vacancy is represented as Vo. The hydrogen that enters the oxygen vacancy is sometimes expressed as VoH. Also, when some of the hydrogen is replaced by a metal atom, By combining with oxygen, electrons, which are carriers, may be generated. A transistor using an oxide semiconductor containing hydrogen tends to be normally-on. In addition, hydrogen contained in the semiconductor 406b reacts with oxygen that bonds with metal atoms to form water. At the same time, oxygen vacancies are formed in the lattice from which oxygen has been removed (or in the portion from which oxygen has been removed). There is.

[0099] Therefore, in the semiconductor 406b, hydrogen is reduced as much as possible along with oxygen vacancies. Specifically, in the semiconductor 406b, the hydrogen concentration obtained by SIMS analysis is Degrees, 5 x 10 19 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 Below Down, or 5×10 18atoms / cm 3 or less, or 1×10 18 atoms / cm 3 or less, or 5×10 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 As a result, the transistor 490 is electrically connected to the positive threshold voltage. This characteristic is also called a normally-off characteristic.

[0100] In addition, the semiconductor 406b contains silicon and carbon, which are group 14 elements. As a result, oxygen vacancies increase in the semiconductor 406b, and an n-type region is formed. The concentration of silicon and carbon in the semiconductor 406b (obtained by secondary ion mass spectrometry) Concentration) is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 As a result, the transistor 490 is electrically connected to the positive threshold voltage. This characteristic is also called a normally-off characteristic.

[0101] In addition, in the semiconductor 406b, an alkali metal or or alkaline earth metal concentration, 1×10 18 atoms / cm 3 Below, preferably 2x 10 16 atoms / cm 3 The alkali metals and alkaline earth metals are oxidized When they combine with semiconductors, they can generate carriers, increasing the off-state current of transistors. For this reason, the alkali metal or alkaline earth metal of the semiconductor 406b As a result, the threshold voltage of transistor 490 is The device has a normally-off characteristic, which is a typical characteristic of the device.

[0102] In addition, when the semiconductor 406b contains nitrogen, electrons that act as carriers are generated, and the carriers The density increases and an n-type region is formed. As a result, the oxide semiconductor containing nitrogen Therefore, the transistor using the oxide semiconductor film tends to be normally-on. In the membrane, it is preferable that nitrogen is reduced as much as possible. For example, the secondary ion species The nitrogen concentration obtained by quantitative analysis is 5×10 18 atoms / cm 3 What you can do is preferable.

[0103] By reducing impurities in the semiconductor 406b, the carrier density in the oxide semiconductor film is reduced. Therefore, the semiconductor 406b has a carrier density of 1×10 17 pieces / cm 3 Below Lower, preferably 1×10 15 pieces / cm 3 Less than 1×10, more preferably 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 It is preferable that:

[0104] The semiconductor 406b is an oxide semiconductor film having a low impurity concentration and a low density of defect states. By using the above-mentioned method, a transistor having even better electrical characteristics can be manufactured. The term "high purity intrinsic" refers to a material that has a low impurity concentration and a low defect level density (low oxygen vacancy). The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. In the case of GaN, the carrier density can be reduced because the carrier generation source is small. Therefore, the threshold voltage of a transistor in which a channel region is formed in the oxide semiconductor film is It is easy for the electrical characteristics to become positive (also called normally-off characteristics). Since a highly pure or substantially highly intrinsic oxide semiconductor film has a low density of defect states, Also, the level density may be lower. The off-state current of the nitride semiconductor film is extremely small, and the voltage between the source and drain electrodes (drain When the on-state voltage is in the range of 1V to 10V, the off-state current is Below the measurement limit, i.e. 1×10 -13 A characteristic of less than A can be obtained. A transistor in which a channel region is formed in the oxide semiconductor film has small fluctuation in electrical characteristics. In some cases, this can result in a highly reliable transistor.

[0105] When the transistor 490 has an s-channel structure, the semiconductor 406b A channel is formed throughout the entire semiconductor layer. Therefore, the thicker the semiconductor layer 406b, the larger the channel region. That is, the thicker the semiconductor 406b, the higher the on-current of the transistor 490. For example, it can be 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more. m or more, more preferably 60 nm or more, and even more preferably 100 nm or more However, the productivity of the semiconductor device may be reduced. For example, the thickness is 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less. The semiconductor 406b may have a region with a thickness of nm or less.

[0106] In order to increase the on-current of the transistor 490, the thickness of the semiconductor 406c is small. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 The semiconductor 406c may have a region of 1 nm or less. The semiconductor 406b on which the insulator is formed is charged with elements other than oxygen (hydrogen, silicon) that constitute the adjacent insulator. Therefore, the semiconductor 406c It is preferable that the thickness of the film is 0.3 nm or more, preferably 1 nm or more. The semiconductor 406c may have a thickness of at least 100 nm, and more preferably at least 2 nm. In addition, the semiconductor 406c suppresses outward diffusion of oxygen released from the insulator 402, etc. Therefore, it is preferable that the material has an oxygen blocking property.

[0107] In order to increase reliability, the semiconductor 406a is thick and the semiconductor 406c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. The semiconductor 406a may have a thickness of at least 60 nm, more preferably at least 60 nm. By increasing the thickness of the semiconductor 406a, the interface between the adjacent insulator and the semiconductor 406a The distance from the semiconductor 406b where the channel is formed can be increased. For example, the thickness is set to 200 nm or less, preferably 120 nm or less, because the productivity of the device may decrease. If the semiconductor 406a has a region with a thickness of 80 nm or less, more preferably 80 nm or less, good.

[0108] For example, a secondary ion mass spectrometry (SIMS) method is used to measure the distance between the semiconductor 406b and the semiconductor 406a. :Secondary Ion Mass Spectrometry) at 1× 10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, More preferably, 2×10 18 atoms / cm 3 having a region with a silicon concentration of less than In addition, between the semiconductor 406b and the semiconductor 406c, SIMS showed that 19 a toms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 2×10 18 atoms / cm 3 The silicon concentration is less than 100 nm.

[0109] In order to reduce the hydrogen concentration in the semiconductor 406b, the semiconductor 406a and the semiconductor 406b are It is preferable to reduce the hydrogen concentration in the semiconductor 406a and the semiconductor 406c. At S, 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 More preferably, 5×10 18 atoms / cm 3 The semiconductor 40 has a hydrogen concentration of 0.1 to 1.0 μm. In order to reduce the nitrogen concentration of the semiconductor 406b, the nitrogen concentration of the semiconductor 406a and the semiconductor 406c is reduced. The semiconductor 406a and the semiconductor 406c are preferably 5×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 More details below. Preferably 1 x 10 18 atoms / cm 3 Less than 5×10, more preferably 17 ato ms / cm 3 The nitrogen concentration ranges as follows:

[0110] The above three-layer structure is an example. For example, a two-layer structure without semiconductor 406a or semiconductor 406c Alternatively, the semiconductor 406 may be formed on or under the semiconductor 406a, or on or under the semiconductor 406. 406a, 406b, and 406c are shown above and below the semiconductor 406. Alternatively, the semiconductor 406a may have a four-layer structure having any one of the above semiconductors. , at least two of the following locations: under the semiconductor 406a, over the semiconductor 406c, and under the semiconductor 406c In addition, any of the semiconductors exemplified as semiconductor 406a, semiconductor 406b, and semiconductor 406c Alternatively, it may have an n-layer structure (n is an integer of 5 or more) having one of these layers.

[0111] At least a portion (or all) of the conductor 416a (or / and the conductor 416b) At least one of the surfaces, the side surfaces, the top surface, and / or the bottom surface of a semiconductor, such as semiconductor 406b, are also provided in some (or all) of the facilities.

[0112] Alternatively, at least a portion (or (all of the above) may refer to the surface, side, top, and / or bottom surfaces of a semiconductor, such as semiconductor 406b. Or, the conductor 416a (or / and At least a portion (or all) of the conductors 416b and 416c may be semiconductors such as semiconductor 406b. In contact with at least part (or all) of the body.

[0113] Alternatively, at least a portion (or (all of the above) may refer to the surface, side, top, and / or bottom surfaces of a semiconductor, such as semiconductor 406b. Or, the conductor 416a is electrically connected to at least a part (or the whole) of the conductor 416a. At least a portion (or all) of the semiconductor 406 (or the conductor 416b) b) is electrically connected to at least a part (or the whole) of a semiconductor such as

[0114] Alternatively, at least a portion (or (all of which are referenced herein) may refer to the surface, side, top, or bottom surfaces of a semiconductor, such as semiconductor 406b. At least a part (or the whole) of the conductor 416a ( or / and conductor 416b) is at least partially (or entirely) a semiconductor 406b The semiconductor device is disposed adjacent to at least a portion (or all) of the semiconductor.

[0115] Alternatively, at least a portion (or (all of which are referenced herein) may refer to the surface, side, top, or bottom surfaces of a semiconductor, such as semiconductor 406b. At least a part (or all) of the conductor 416a (or conductor 416b) is disposed on the lateral side. At least a portion (or all) of the conductive material 416b is a semiconductor 406b, etc. The semiconductor layer is disposed on at least a portion (or all) of the side of the semiconductor layer.

[0116] Alternatively, at least a portion (or (all of which are referenced herein) may refer to the surface, side, top, or bottom surfaces of a semiconductor, such as semiconductor 406b. At least a part (or the whole) of the conductor 416a ( or / and conductor 416b) is at least partially (or entirely) a semiconductor 406b The semiconductor device is disposed obliquely above at least a part (or the whole) of the semiconductor.

[0117] Alternatively, at least a portion (or (all of which are referenced herein) may refer to the surface, side, top, or bottom surfaces of a semiconductor, such as semiconductor 406b. At least a part (or the whole) of the conductor 416a (or At least a portion (or all) of the conductive material 416b is a semiconductor 406b, etc. The semiconductor layer is disposed on at least a portion (or all) of the semiconductor.

[0118] Here, transistor 490 may have an insulator 408 and an insulator 418 thereon. The details of the insulators 408 and 418 will be described later in the structure of a semiconductor device. He explains.

[0119] In addition, an oxide semiconductor that can be used for the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c The structure will be described in the embodiment below.

[0120] <Modifications of Transistor Structure> Next, as a modification of the transistor 490 in FIG. 1, a transistor 490 shown in FIG. I will explain this in more detail.

[0121] FIG. 2A is an example of a top view of a transistor 490. An example of a cross-sectional view corresponding to the dashed line E3-E4 is shown in FIG. In order to facilitate understanding, some insulators and other parts are omitted in FIG. 2(A).

[0122] In FIG. 1, the conductor 416a and the conductor 4 In this example, 16b contacts the upper and side surfaces of the semiconductor 406b and the upper surface of the insulator 402. However, the structure of a transistor according to one embodiment of the present invention is not limited to this. As shown in FIG. 1, the conductor 416a and the conductor 416b are in contact only with the upper surface of the semiconductor 406b. It is acceptable for the structure to be similar.

[0123] In the transistor shown in FIG. 2, the conductor 416a and the conductor 416b are semiconductors 406b. Therefore, the conductor 404 having the function of a gate electrode does not contact the semiconductor layer. An electric field applied toward the side of the conductor 406b is generated by the conductor 416a and the conductor 416b. The conductor 416a and the conductor 416b are made of an insulating material. Therefore, the excess oxygen (oxygen) released from the insulator 402 is not introduced. The insulating material 416a and the insulating material 416b are not consumed to oxidize the conductive material 416a and the conductive material 416b. Excess oxygen (oxygen) released from the body 402 is used to reduce oxygen vacancies in the semiconductor 406b. That is, the transistor having the structure shown in FIG. High on-current, high field effect mobility, low subthreshold swing, high reliability, etc. It is a transistor with excellent electrical characteristics such as

[0124] In addition, in FIG. 1, a semiconductor 406c and an insulator 412 are provided on the entire surface in the transistor. 3, the semiconductor 406c, the insulator 412, and the conductor 404 Alternatively, either end of the conductor may have a shape that does not protrude (stick out). 3A is a top view of a transistor 490. An example of a cross-sectional view corresponding to the dashed line A3-A4 is shown in FIG. 3(B). To simplify the analysis, some parts such as insulators are omitted.

[0125] 4A is an example of a top view of a transistor 490. An example of a cross-sectional view corresponding to the line B1-B2 and the dashed line B3-B4 is shown in FIG. In FIG. 4(A), some insulators and the like are omitted for ease of understanding.

[0126] 5A is an example of a top view of a transistor 490. An example of a cross-sectional view corresponding to the line C1-C2 and the dashed line C3-C4 is shown in FIG. In FIG. 5(A), some insulators and the like are omitted for ease of understanding.

[0127] The semiconductor 406c, the insulator 412, and the conductor 404 are shown in the top view of FIG. In this way, the semiconductor 406c covers the channel formation region of the transistor and the surrounding region. The insulator 412 is disposed so as to cover the semiconductor 406c. In the cross-sectional view of FIG. 4B, the semiconductor 406c is a conductor. The shape has an area where the end protrudes (pushes out) from 404. As shown in the top view of FIG. 1, the semiconductor 406c and the insulator 412 form a channel shape of the transistor. The insulating layer 11 may be provided so as to cover the surrounding area from the forming area. In the plan view, the semiconductor 406c and the insulator 412 have ends protruding beyond the conductor 404. The shape is as follows:

[0128] When the transistor has the structure shown in FIG. 1, FIG. 4, or FIG. 5, In some cases, leakage current through the surface, the surface of the insulator 412, etc. can be reduced. In other words, the off-state current of the transistor can be made smaller. In addition, since the conductor 404 does not need to be used as a mask when etching the semiconductor 406c, The conductive body 404 is not exposed to the plasma. Electrostatic breakdown of the stator is unlikely to occur, and semiconductor devices can be produced with a high yield. As the degree of freedom in designing semiconductor devices increases, LSIs (Large Scale Integrated Circuits) with complex structures are becoming available. cale Integration) and VLSI (Very Large Scale) The present invention is suitable for integrated circuits such as MOS FETs.

[0129] 6A is an example of a top view of the transistor 490. An example of a cross-sectional view corresponding to the line D1-D2 and the dashed line D3-D4 is shown in FIG. In FIG. 6(A), some insulators and the like are omitted for ease of understanding.

[0130] 1, 2, and the like, the conductors 416a and 416b functioning as the source and drain electrodes. A structure having a region where the conductor 416b overlaps with the conductor 404 functioning as a gate electrode. However, the structure of a transistor according to one embodiment of the present invention is not limited to this. For example, As shown in FIG. 6, the area where the conductor 416a and the conductor 416b overlap with the conductor 404 A structure having no region may be used. By adopting such a structure, the parasitic capacitance is small. Therefore, it has good switching characteristics and low noise. This results in a high-speed transistor.

[0131] In addition, since the conductor 416a and the conductor 416b do not overlap with the conductor 404, In this case, the resistance between the conductor 416a and the conductor 416b may become high. Since the on-current of the transistor may become small, it is preferable to make the resistance as low as possible. For example, the distance between the conductor 416a (conductor 416b) and the conductor 404 is preferably small. For example, the distance between the conductor 416a (conductor 416b) and the conductor 404 is set to 0. μm or more and 1 μm or less, preferably 0 μm or more and 0.5 μm or less, and more preferably 0 μm or more and 1 μm or less. The thickness may be set to at most 0.2 μm, and more preferably, to at least 0 μm and at most 0.1 μm.

[0132] Alternatively, the semiconductor 406 between the conductor 416a (conductor 416b) and the conductor 404 b) or / and a low resistance region 423a (low resistance region 423b) is provided in the semiconductor 406a The low resistance region 423a and the low resistance region 423b may be, for example, a semiconductor 406. b and / or have regions with a higher carrier density than other regions of the semiconductor 406a. Alternatively, the low resistance region 423a and the low resistance region 423b may be a semiconductor 406b or / and and a region having a higher impurity concentration than the other regions of the semiconductor 406a. The low resistance region 423a and the low resistance region 423b are semiconductor 406b and / or semiconductor 406a. The low resistance region 423a and the low resistance region 423b have a higher carrier mobility than the other regions. The resistive region 423b is, for example, a mask for the conductor 404, the conductor 416a, the conductor 416b, etc. The semiconductor 406b and / or the semiconductor 406a are doped with impurities to form the semiconductor 406b. That's good.

[0133] In addition, the distance between the conductor 416a (conductor 416b) and the conductor 404 is made small, and The semiconductor 406b or / and the semiconductor 406b between the conductor 416a (conductor 416b) and the conductor 404 In addition, a low resistance region 423a (low resistance region 423b) may be provided in the semiconductor 406a. .

[0134] Alternatively, for example, the transistor 490 may have a low resistance region 423 as shown in FIG. The low resistance region 423a and the low resistance region 423b may not be provided. By not having 423b, the on-current of transistor 490 may be reduced. In this case, the transistor 490 is less susceptible to the short channel effect. The regions corresponding to the low resistance regions 423a and 423b (conductors 416a (conductive The region between the conductive body 416b and the conductive body 404 is defined as the Loff1 region and the Loff2 region, respectively. For example, the length of the Loff1 and Loff2 regions is 50 nm. When the distance is shortened to 20 nm or less or 10 nm or less, the low resistance region 423a and the low resistance region 423b are Even without resistor region 423b, there is almost no reduction in the on-current of transistor 490. It is preferable that the Loff1 region and the Loff2 region have different sizes. It's okay.

[0135] Or, for example, the transistor 490 may be a Loff1 region as shown in FIG. The absence of the Loff2 region may result in a loss of the trangenesis. The transistor 490 is designed to be less susceptible to the short channel effect while minimizing the decrease in the on-state current. The region where the conductor 416b and the conductor 404 overlap is called the Lov region. For example, the length of the Lov region is set to 50 nm or less, 20 nm or less, or 10 nm or less. When the parasitic capacitance is reduced to 0.5 V, the switching characteristics of transistor 490 are hardly degraded. This is preferable because it does not cause

[0136] Alternatively, for example, the transistor 490 may be configured such that the conductor 404 is a transistor as shown in FIG. In that case, for example, the low resistance region 423a and the low The resistance region 423b may have a shape with a gradient in the depth direction. In other drawings, the conductor 404 may have a tapered shape. stomach.

[0137] 8A is an example of a top view of the transistor 490. An example of a cross-sectional view corresponding to the line F1-F2 and the dashed line F3-F4 is shown in FIG. In FIG. 8A, some of the insulators and the like are omitted for ease of understanding.

[0138] Transistor 490 includes conductor 416a and conductor 416b as shown in FIG. The conductor 426a and the conductor 426b are in contact with the semiconductor 406b. In this case, at least the semiconductor 406b and / or the semiconductor 406a may be conductive. A low resistance region 423a (low resistance region 423b) is provided in a region in contact with the conductor 426a and the conductor 426b. It is preferable to provide the low resistance region 423a and the low resistance region 423b, for example. The conductor 404 or the like is used as a mask, and impurities are implanted into the semiconductor 406b and / or the semiconductor 406a. The conductor 426a and the conductor 426b may be formed by adding a semiconductor The body 406b is provided with a hole (through hole) or a depression (not through hole). The conductor 426a and the conductor 426b may be formed in a hole or a depression in the semiconductor 406b. By providing the conductor 426a and the conductor 426b in the semiconductor 406b, the conductor 426a and the conductor 426b are in contact with each other. Since the area is large, the effect of contact resistance can be reduced. The on-state current can be increased.

[0139] Alternatively, for example, the transistor 490 may have a low resistance region 423 as shown in FIG. The low resistance region 423a and the low resistance region 423b may not be provided. By not having 423b, the on-current of transistor 490 may be reduced. This results in a transistor 490 that is less susceptible to the short channel effect. The region between the conductor 426b and the conductor 404 is called the Loff region. When the length of the region is shortened to 50 nm or less, 20 nm or less, or 10 nm or less, the low resistance region is Even if the transistor 490 does not have the low-resistance region 423a and the low-resistance region 423b, the on-current of the transistor 490 is There may be little or no decrease in

[0140] Alternatively, for example, the transistor 490 may be configured such that the conductor 404 is a transistor as shown in FIG. In that case, for example, the low resistance region 423a and the low The resistance region 423b may have a shape that has a gradient in the depth direction.

[0141] 10A and 10B are a top view and a cross-sectional view of a transistor 490. FIG. 10(A) is a top view, and FIG. 10(B) is a diagram showing the structure of the dashed line G1-G1 shown in FIG. 2, and a cross-sectional view corresponding to the dashed line G3-G4. In the drawings, some elements are omitted for clarity of the drawing.

[0142] The transistor 490 shown in FIGS. 10A and 10B is a conductor on a substrate 442. 413, an insulator 402 having a protrusion on the substrate 442 and on the conductor 413, and an insulator 4 02, a semiconductor 406a on the protruding portion, a semiconductor 406b on the semiconductor 406a, and a semiconductor 406 b, and the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c are in contact with each other. , a conductor 416a and a conductor 416b are spaced apart, and on the semiconductor 406c, The insulator 412 on the conductor 416a and the conductor 416b, and the conductor 4 on the insulator 412 04, on the conductor 416a, on the conductor 416b, on the insulator 412, and on the conductor 404 It has an insulator 408 and an insulator 418 on the insulator 408 .

[0143] In addition, the insulator 412 is in contact with at least the side surface of the semiconductor 406b in the G3-G4 cross section. In addition, the conductor 404 is in contact with the insulator 412 at least at the G3-G4 cross section. The conductor 413 faces at least the top and side surfaces of the semiconductor 406b. The insulator 402 faces the lower surface of the semiconductor 406b via a protrusion. The semiconductor 406c may be omitted. The insulator 408 may be omitted. Also, the insulator 418 may be omitted.

[0144] Thus, transistor 490 shown in FIG. 10 is similar to transistor 490 shown in FIG. Only a part of the structure is different. Specifically, the semiconductor of the transistor 490 shown in FIG. The structures of the semiconductor 406a, the semiconductor 406b and the semiconductor 406c and the transistor 4 shown in FIG. 90, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c are different in structure. Therefore, the transistor shown in FIG. 10 is the same as the transistor shown in FIG. can be referred to as appropriate.

[0145] FIG. 11A is an example of a top view of the transistor 490. An example of a cross-sectional view corresponding to the dashed dotted line H1-H2 and the dashed dotted line H3-H4 is shown in FIG. In order to make it easier to understand, some parts such as the insulator are omitted in Figure 11(A). .

[0146] Note that in the top view shown in FIG. 10A, the insulator 412 has the same shape as the conductor 404. However, the structure of a transistor according to one embodiment of the present invention is not limited to this example. For example, as shown in FIG. 11(A) and FIG. 11(B), an insulator 412 is disposed on an insulator 402, It may be disposed on conductor 406c, on conductor 416a, and on conductor 416b.

[0147] <Transistor manufacturing method 1> Next, an example of a method for manufacturing the transistor 490 shown in FIG. 1 will be described with reference to FIGS. I will explain this in more detail.

[0148] First, a substrate 442 is prepared. An insulator may be formed on the substrate 442.

[0149] Next, a conductor that will become the conductor 413 is formed. The conductor that will become the conductor 413 is formed by sputtering. The film may be formed by using a method such as the ring method, the CVD method, the MBE method, the PLD method, or the ALD method.

[0150] Next, a part of the conductor that is to become the conductor 413 is etched to form the conductor 413.

[0151] Next, the insulator 402 is formed. The insulator 402 is formed by a sputtering method, a CVD method, or a MB method. The insulator 4 may be formed by the PLD method, the ALD method, or the like. 02 will be described in the case where the upper surface is planarized by a CMP method or the like. By planarizing the top surface of the transistor 490, the subsequent process becomes easier and the yield of the transistor 490 is increased. For example, the RMS roughness of the insulator 402 can be increased to 1 nm by the CMP method. The thickness is preferably 0.5 nm or less, and more preferably 0.3 nm or less. Ra in the range of 1 μm×1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably or less than 0.5 nm, more preferably less than 0.4 nm. PV in the range of less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm However, the thickness of the transistor 4 according to one embodiment of the present invention is preferably less than 7 nm. 90 is not limited to the case where the top surface of the insulator 402 is flattened.

[0152] The insulator 402 may be formed to contain excess oxygen. Oxygen may be added after the film is formed. The addition of oxygen is performed, for example, by ion implantation using an accelerated The voltage is set to 2 kV or more and 100 kV or less, and the dose is set to 5 × 10 14 ions / cm 2 More than 5× 10 16 ions / cm 2 This can be done as follows.

[0153] When the insulator 402 is made of a laminated film, each film is formed as described above. For example, the first layer may be formed by a CVD method, and the second layer may be formed by a CVD method. The second layer may be deposited by the ALD method. Alternatively, the first layer may be deposited by the sputtering method, and the second layer may be deposited by the ALD method. The first and second layers may be formed by ALD. By doing so, it is possible to give each layer of film different functions and properties. By doing so, a more suitable film can be formed as the entire laminated film.

[0154] In other words, the nth layer (n is a natural number) is formed by sputtering, CVD, MBE, or The n+1th layer is formed by at least one of the PLD method, ALD method, etc. At least one of the following methods: sputtering, CVD, MBE, PLD, ALD, etc. The film is formed by one method. Note that the film formation method for the nth layer and the n+1th layer may be the same. The film forming method may be the same for the nth layer and the n+2th layer. Alternatively, the deposition method may be the same for all the films.

[0155] Next, the semiconductor 436a which becomes the semiconductor 406a and the semiconductor 436b which becomes the semiconductor 406b are The semiconductor 406a and the semiconductor 406b are formed in this order (see FIG. 12A). The semiconductor that becomes the conductor 406b is formed by sputtering, CVD, MBE, or PLD. The film may be formed by using an ALD method or the like.

[0156] The semiconductor 436a and the semiconductor 436b are formed of an In-Ga-Zn oxide layer. When forming a film by the CVD method, trimethylindium and trimethylgallium are used as raw material gases. The combination of the source gases is not limited to the above. Instead of trimethylindium, triethylindium or the like may be used. Triethylgallium may be used in place of trimethylgallium. Diethyl zinc or the like may be used in place of lead.

[0157] Next, a first heat treatment is preferably performed. The excess oxygen contained in the semiconductor 406 is transferred to the semiconductor 406b through the semiconductor 406a. In this case, the semiconductor 406a is preferably a semiconductor having an oxygen vacancy. It is preferable that the layer is permeable (a layer that allows oxygen to pass through or permeate).

[0158] Oxygen is released from the insulator 402 by heat treatment or the like and is taken into the semiconductor 406a. In addition, oxygen may be present in a free state between atoms in the semiconductor 406a, or may be present in a free state between atoms in the semiconductor 406a. The lower the density of the semiconductor 406a, the more gaps there are between the atoms. The more the number of the oxygen atoms, the higher the oxygen permeability. However, if oxygen does not move across the layers easily, the semiconductor 406a will have a moderately crystalline structure. A lower layer is preferred.

[0159] The first heat treatment is performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower. The first heat treatment may be performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at a concentration of 10 ppm or less. The first heat treatment is carried out in an atmosphere containing 1% or more or 10% or more of the above. Alternatively, the first heat treatment may be performed in an inert gas atmosphere, followed by removing the desorbed oxygen. In order to supplement oxygen, the gas is heated in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. Heat treatment may be performed. The first heat treatment may convert the semiconductor 436a and the semiconductor 436 It is possible to increase the crystallinity of b and remove impurities such as hydrogen and water.

[0160] Next, a mask is formed, and the semiconductor 436a and the semiconductor 436b are etched using the mask. The mask is then patterned to form the semiconductor 406a and the semiconductor 406b (see FIG. 12B). A photoresist can be used as the mask. A hard mask can be used as the mask. A specific example of using a hard mask will be described later in the explanation of FIG.

[0161] Next, a conductor 416 is formed. The conductor 416 is formed by a sputtering method, a CVD method, or a MB method. The film may be formed by the E method, PLD method, ALD method or the like.

[0162] The conductor 416a and the conductor 416b are formed by depositing the conductor 416. Therefore, when the conductor 416 is formed, the semiconductor It is preferable to use a deposition method that does not damage the conductive body 406b. It is preferable to use the MCVD method for the film.

[0163] When the conductor 416 is made of a laminated film, each film is formed by a sputtering method. , CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), MBE The film may be formed by a different deposition method such as a deposition method, a PLD method, an ALD method, etc. For example, the first layer may be formed by MOCVD and the second layer may be formed by sputtering. Alternatively, the first layer may be formed by the ALD method, and the second layer may be formed by the MOCVD method. Alternatively, the first layer may be formed by the ALD method and the second layer may be formed by the sputtering method. The first layer is deposited by the ALD method, the second layer is deposited by the sputtering method, and the third layer is deposited by the ALD method. In this way, by using different film forming methods, the films of each layer can be formed. By stacking these films, As a result, a more suitable film can be formed as the entire laminated film.

[0164] That is, when the conductor 416 is made of a laminated film, for example, the n-th layer is formed by sputtering. Ring method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.) The n+1 layer is formed by at least one of the following methods: MBE, PLD, ALD, etc. The eye membrane is made by sputtering, CVD (plasma CVD, thermal CVD, MCVD, At least one of the following methods: MOCVD method, MBE method, PLD method, ALD method, etc. The film formation method may be different between the n-th film and the n+1-th film (n is an integer of 1 to 10). The film forming method may be the same for the nth layer and the n+2th layer. The deposition method may be the same for all the films.

[0165] In addition, the conductor 416 or at least one of the laminated films of the conductor 416 and the semiconductor The semiconductor that becomes the body 406a and the semiconductor that becomes the semiconductor 406b are formed by the same film formation method. For example, the ALD method may be used for both. This allows the deposition of the As a result, the inclusion of impurities can be prevented.

[0166] In addition, the conductor 416 or at least one of the laminated films of the conductor 416 and the semiconductor A semiconductor that becomes the body 406a or a semiconductor that becomes the semiconductor 406b and an insulator 402 or At least one of the laminated films of the insulator 402 may be formed by the same film formation method. For example, a sputtering method may be used for any of the above methods. This allows the deposition of the film without exposing it to the air. As a result, it is possible to prevent the inclusion of impurities. The manufacturing method of the semiconductor device is not limited to the above.

[0167] Next, a mask is formed, and the mask is used to form the conductor 416a and the conductor 416b. The conductor is etched to form conductor 416a and conductor 416b (FIG. 13(A) reference.).

[0168] Next, a semiconductor film that becomes the semiconductor 406c is formed (see FIG. 13B). The semiconductors that become c are produced by sputtering, CVD, MBE, PLD, ALD, etc. The film may be formed using, for example,

[0169] As a semiconductor for the semiconductor 406c, an In-Ga-Zn oxide layer was grown by MOCVD. When forming a film by this method, trimethylindium, trimethylgallium and The combination of raw material gases is not limited to the above, and may be any combination of Triethylindium may be used instead of trimethylindium. Triethylgallium may be used instead of zinc. Alternatively, diethyl zinc or the like may be used.

[0170] Next, a second heat treatment may be performed. A semiconductor having a higher oxygen permeability than the semiconductor 406c is selected. As the semiconductor, a semiconductor having a lower oxygen permeability than the semiconductor 406a is selected. Then, a semiconductor having a function of transmitting oxygen is selected as the semiconductor 406a. A semiconductor having an oxygen blocking function is selected as the semiconductor for the body 406c. In this case, by performing a second heat treatment, the semiconductor 406a is transferred to the insulator 402 through the semiconductor 406a. The excess oxygen migrates to the semiconductor 406b, which becomes the semiconductor 406c. Because the body is covered, it is difficult for excess oxygen to diffuse outward. By performing the second heat treatment at 406b, defects (oxygen vacancies) in the semiconductor 406b are efficiently reduced. Note that the second heat treatment is performed to convert excess oxygen (oxygen) in the insulator 402 into the semiconductor 4. For example, see the description of the first heat treatment. Alternatively, the second heat treatment may be performed at a temperature lower than that of the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20° C. or more and 150° C. or less, preferably 40° C. or less. The temperature is set to 100° C. or higher. This allows excess oxygen (oxygen) to be released from the insulator 402. It can prevent waste from coming out.

[0171] Here, in the semiconductor 406b, hydrogen is reduced as much as possible along with oxygen vacancies. For example, it is preferable to reduce hydrogen contained in the semiconductor 406b by performing heat treatment. A higher heat treatment temperature is preferable because the hydrogen concentration can be reduced as the heat treatment temperature is higher.

[0172] On the other hand, for example, when a heat treatment is performed after the formation of the conductors 416a and 416b, The heat treatment may cause the wiring material to be oxidized and become highly resistive. In addition, it may be preferable to keep the heat treatment temperature after the formation of the conductor 416b low. Also in terms of production costs, it is preferable that the heat treatment temperature is as low as possible.

[0173] Here, let us consider the case where hydrogen trapped in oxygen vacancies in the semiconductor 406b is removed. The hydrogen trapped in the oxygen vacancies of 406b is desorbed from the trapping sites and is transported to the outside of the semiconductor 406b. It is preferable to diffuse the

[0174] Here, for example, excess oxygen is added to the semiconductor 406b and the semiconductor 406c, In some cases, oxygen can enter the oxygen vacancies where atoms are trapped, making it easier to release hydrogen. In addition, excess oxygen is added to the semiconductor 406c, and the oxygen in the semiconductor 406c is transferred to the semiconductor 406b. By adding oxygen, oxygen vacancies can be reduced and the In some cases, hydrogen can be reduced at low temperatures. Conductor 406b may have a lower hydrogen concentration.

[0175] In addition, the added oxygen and hydrogen combine to form water, which facilitates the removal of hydrogen from the semiconductor 406b. It may become easier.

[0176] Here, the addition of oxygen causes the semiconductor 406b and the semiconductor 406c on the semiconductor 406b to have a high concentration When forming a region having oxygen in the semiconductor, damage may occur in the region. A high acceleration voltage is applied by using an ion implantation method or the like to ionize the semiconductor 406b and the semiconductor on the semiconductor 406b. When oxygen is implanted into 406c, defects may occur during the implantation process.

[0177] Here, for example, a layer 420 is provided above the semiconductor 406b, and the oxygen-rich region is formed in the layer 420. By forming the semiconductor 406b in this manner, damage to the semiconductor 406b may be reduced. For example, a high concentration of oxygen is added to the layer 420 disposed above the semiconductor 406b, and then The oxygen in layer 420 is diffused into semiconductor 406b, thereby forming a semiconductor 406 This can reduce damage to b.

[0178] In addition, by adding oxygen after providing the layer 420 on the semiconductor 406b, for example, Contamination during the process of adding the element can be prevented. This can prevent the adhesion or intrusion of elements other than oxygen from the treatment chamber or transport system.

[0179] In the example shown in FIG. 13C, a semiconductor 406c is provided over a semiconductor 406b. A layer 420 is deposited on the conductor 406c. Here, the layer 420 is a semiconductor 406, as described below. The film may be formed before providing c.

[0180] Layer 420 is preferably highly permeable to hydrogen.

[0181] The layer 420 may be made of an insulator, a semiconductor, or the like. For example, the layer 420 may be made of gold. Examples of the metal oxides include oxides of boron, carbon, fluorine, ma, etc. Magnesium, aluminum, silicon, phosphorus, chlorine, argon, titanium, vanadium, Chromium, manganese, cobalt, nickel, copper, zinc, gallium, germanium, yttrium Zirconium, Niobium, Molybdenum, Ruthenium, Indium, Tin, Lanthanum, Ne Oxides containing ozimium, hafnium, tantalum or tungsten, either in a single layer or multilayer For example, the layer 420 may be made of titanium oxide, manganese oxide, zinc oxide, or oxide. Gallium oxide, molybdenum oxide, indium oxide, tin oxide, tungsten oxide, etc. The layer 420 may be made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. Silicon, silicon oxide nitride, etc. can be used.

[0182] The layer 420 may further include at least one of indium, element M, and zinc, or For example, the layer 420 may be an In-Ga oxide. In-Zn oxide, Zn-Ga oxide, Zn-Sn oxide, In-Ga-Zn oxide, I n-Sn-Zn oxide, In-Hf-Zn oxide, etc. may be used. , In-Ga-Zn oxides having more Ga than In, and In-Ga-Zn oxides having more than twice as much Ga as In. In-Ga-Zn oxides with Ga more than three times the amount of In, It is preferred to use the n-oxide.

[0183] Also, the material described as the insulator 412 can be used for the layer 420 .

[0184] Next, oxygen is added (see FIG. 14(A)). The oxygen is added by ion implantation or plasma. In addition, in the ion implantation method, a mass separation method is used. Here, the ions are mainly, e.g., O + Or O2 + can be used.

[0185] After the oxygen addition, a heat treatment may be performed. By performing the heat treatment, oxygen is converted into the semiconductor 4 It may be easier to spread up to 06b.

[0186] Next, the layer 420 is removed (see FIG. 14(B)). The layer 420 is removed by wet etching. For example, wet etching is used to remove the plate. This method is preferable because it does not cause damage such as Zuma and is a simple method.

[0187] In addition, in the wet etching, the film under the layer 420, such as the semiconductor 406c and the semiconductor When the selection ratio with respect to the conductor 406b is low, it is preferable to use dry etching. By performing dry etching of the layer 420 under conditions of high selectivity, the layer 4 There are cases where 20 eliminations can be performed.

[0188] Next, an insulator that will become the insulator 412 is formed (see FIG. 14C). The insulating material is formed by sputtering, CVD, MBE, PLD, ALD, etc. The film may be formed using the above.

[0189] In addition, when the insulator 412 is made of a laminated film, each film is CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.) (e.g., MBE, PLD, ALD, etc.) For example, the first layer may be formed by MOCVD and the second layer by sputtering. Alternatively, the first layer may be deposited by the ALD method and the second layer may be deposited by the MOCVD method. Alternatively, the first layer may be formed by the ALD method, and the second layer may be formed by the sputtering method. Alternatively, the first layer can be deposited by ALD, the second layer by sputtering, and the third layer by The film may be formed by the ALD method. By stacking these films, it is possible to give each layer a different function or property. By doing so, a more suitable film can be formed as the entire laminated film.

[0190] That is, when the insulator 412 is made of a laminated film, for example, the n-th film The sputtering method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOC The film is formed by at least one of the following methods: VD method, MBE method, PLD method, ALD method, etc. The n+1th layer is then deposited by sputtering, CVD (plasma CVD, thermal CVD, At least one of the following methods: MCVD method, MOCVD method, MBE method, PLD method, ALD method, etc. Even if the deposition methods for the nth layer and the n+1th layer are different, (n is a natural number). The film formation method may be the same for the nth layer and the n+2th layer. Alternatively, the deposition method may be the same for all the films.

[0191] Next, oxygen may be added from above the insulator 412. The method of adding oxygen is as follows: The above-mentioned oxygen addition method can be referred to.

[0192] Next, a third heat treatment may be performed. A semiconductor having a higher oxygen permeability than the semiconductor 406c is selected. As the semiconductor, a semiconductor having a lower oxygen permeability than the semiconductor 406a is selected. A semiconductor having an oxygen blocking function is selected as the semiconductor that will become the conductor 406c. Alternatively, for example, the semiconductor 406a may be made of an insulator having a higher oxygen permeability than the insulator that becomes the insulator 412. That is, the insulator 412 is selected to have a higher conductivity than the semiconductor 406a. A semiconductor with low oxygen permeability is selected. In other words, a semiconductor 406a that is permeable to oxygen is selected. In addition, a semiconductor that can block oxygen is selected as the insulator 412. At this time, a third heat treatment is performed to make the insulator have a function of blocking the semiconductor. Excess oxygen contained in the insulator 402 moves to the semiconductor 406b via the body 406a. The semiconductor 406b is covered with a semiconductor that will become the semiconductor 406c and an insulator that will become the insulator 412. Therefore, the outward diffusion of excess oxygen is unlikely to occur. By carrying out the heat treatment, it is possible to efficiently reduce defects (oxygen vacancies) in the semiconductor 406b. Note that the third heat treatment is performed so that excess oxygen (oxygen) in the insulator 402 is transported to the semiconductor 406b. The heat treatment may be performed at a temperature at which the diffusion occurs. For example, the description of the first heat treatment may be referred to. Alternatively, the third heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the first and second heat treatments is 20° C. to 150° C., preferably 40° C. to 100° C. 0° C. or less. This prevents excess oxygen (oxygen) from being released from the insulator 402. In addition, the insulator serving as the insulator 412 has a function of blocking oxygen. In this case, the semiconductor to be the semiconductor 406c does not need to have a function of blocking oxygen. stomach.

[0193] Next, a conductor that will become the conductor 404 is formed. The conductor that will become the conductor 404 is formed by sputtering. The film may be formed by using a method such as the ring method, the CVD method, the MBE method, the PLD method, or the ALD method.

[0194] The insulator 412 serves as a gate insulator for the transistor 490. Therefore, when the conductor that becomes the conductor 404 is formed, the insulator that becomes the insulator 412 is not damaged. It is preferable to use a film formation method that does not give rise to a conductor. That is, the film formation of the conductor is performed using the MCVD method or the like. It is preferable to have one.

[0195] In addition, when the conductor 404 is made of a laminated film, each film is CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.) (e.g., MBE, PLD, ALD, etc.) For example, the first layer may be formed by MOCVD and the second layer by sputtering. Alternatively, the first layer may be deposited by the ALD method and the second layer may be deposited by the MOCVD method. Alternatively, the first layer may be formed by the ALD method, and the second layer may be formed by the sputtering method. Alternatively, the first layer can be deposited by ALD, the second layer by sputtering, and the third layer by The film may be formed by the ALD method. By stacking these films, it is possible to give each layer a different function or property. By doing so, a more suitable film can be formed as the entire laminated film.

[0196] That is, when the conductor 404 is made of a laminated film, for example, the n-th film The sputtering method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOC The film is formed by at least one of the following methods: VD method, MBE method, PLD method, ALD method, etc. The n+1th layer is then deposited by sputtering, CVD (plasma CVD, thermal CVD, At least one of the following methods: MCVD method, MOCVD method, MBE method, PLD method, ALD method, etc. Even if the deposition methods for the nth layer and the n+1th layer are different, (n is a natural number). The film formation method may be the same for the nth layer and the n+2th layer. Alternatively, the deposition method may be the same for all the films.

[0197] In addition, the conductor that becomes the conductor 404 or a small amount of the laminated film of the conductor that becomes the conductor 404 At least one film and an insulator that becomes the insulator 412 or a product of the insulator that becomes the insulator 412 At least one of the layers may be formed by the same deposition method. The ALD method may be used. This allows the film to be formed without being exposed to the air. As a result, it is possible to prevent the inclusion of impurities. A conductor that is to be the conductor 404 in contact with the insulator 412 that is to be the conductor 404 The insulating material may be formed by the same deposition method. As a result, the inclusion of impurities can be prevented.

[0198] In addition, the conductor that becomes the conductor 404 or a small amount of the laminated film of the conductor that becomes the conductor 404 At least one film and an insulator that becomes the insulator 412 or a product of the insulator that becomes the insulator 412 At least one of the layers may be formed by the same deposition method. A tar-coating method may also be used, which allows the film to be formed without being exposed to the air. As a result, the inclusion of impurities can be prevented.

[0199] Next, a part of the conductor that will become the conductor 404 is etched to form the conductor 404 (FIG. 15(A). Note that the conductor 404 overlaps at least a part of the semiconductor 406b. It is formed as follows.

[0200] Next, the insulator 408 is formed. The insulator 408 is formed by a sputtering method, a CVD method, or a MB method. The film may be formed by the E method, PLD method, ALD method or the like.

[0201] Next, a fourth heat treatment may be performed. A semiconductor having a higher oxygen permeability than that of semiconductor 406c is selected. A semiconductor having a lower oxygen permeability than that of 406a is selected. Alternatively, for example, a semiconductor 406a may be selected as the semiconductor 406b. In this case, a semiconductor having a higher oxygen permeability than the insulator 412 is selected. Select a semiconductor that is less oxygen permeable than semiconductor 406a. For 6a, a semiconductor having higher oxygen permeability than the insulator 408 is selected. 8, a semiconductor having a lower oxygen permeability than the semiconductor 406a is selected. The body 406a is made of a semiconductor that is permeable to oxygen. As the insulating layer, an insulating material having a function of blocking oxygen is selected. By performing the above, the excess oxygen contained in the insulator 402 is oxidized to the semiconductor 406 through the semiconductor 406a. The semiconductor 406b is connected to the semiconductor 406c, the insulator 412, and the insulator 408. Since the oxygen is covered by either the oxygen or the oxygen ions, the outward diffusion of excess oxygen is difficult. By performing the fourth heat treatment with a dipping method, defects (oxygen vacancies) in the semiconductor 406b are efficiently reduced. Note that the fourth heat treatment is performed to convert excess oxygen (oxygen) in the insulator 402 into a semiconductor. The temperature may be set to a temperature at which the fluorine-containing gas diffuses to the substrate 406b. For example, see the description of the first heat treatment. Alternatively, the fourth heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the first heat treatment and the fourth heat treatment is 20° C. or more and 150° C. or less, preferably The temperature is set to 40° C. or higher and 100° C. or lower. This allows excess oxygen (oxygen) to be released from the insulator 402. The insulator 408 has a function of blocking oxygen. In this case, the semiconductor 406c and / or the insulator 412 has a function of blocking oxygen. It's okay if you don't.

[0202] All of the first, second, third and fourth heat treatments Or some of it may not be done.

[0203] Next, an insulator 418 is formed (see FIG. 15B). The insulator 418 is formed by sputtering. The film may be formed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0204] In the above manner, the transistor 490 shown in FIG. 20 can be manufactured.

[0205] After the step shown in FIG. 14C, the insulator 4 is A part of the transistor 12 and a part of the semiconductor 406c may be etched. The shape of the stanchion 490 is, for example, as shown in FIG. 15(C), The end face of the semiconductor 406c is connected to the end face of the semiconductor 412 in a generally smooth manner. In addition, the conductor that becomes the conductor 404, the insulator that becomes the insulator 412, and the semiconductor 40 When etching a part of the semiconductor that will become 6c, the same photolithography process is used. Alternatively, the conductor 404 may be used as a mask to mask the insulator and the insulator 412. The semiconductor 406c may be etched. The body 412 and the semiconductor 406c have the same shape in the top view. As shown in the enlarged cross section in FIG. 4, the insulator 412 and / or the semiconductor 404 are more conductive than the conductor 404. In some cases, 6c may have a protruding (pushing out) shape, or as shown in the enlarged cross section of Figure 17(D), The conductor 404 protrudes from the insulator 412 and / or the semiconductor 406c. By making the shape as shown above, the occurrence of defective shapes is reduced. This may reduce the gate leakage current.

[0206] <Transistor manufacturing method 2> Next, as a modification of the above-described manufacturing method 1, a manufacturing method of a transistor 490 shown in FIG. The method will be described with reference to FIGS.

[0207] In the manufacturing method 1, an example in which the layer 420 is formed after the semiconductor 406c is provided is shown. 4 shows an example in which the layer 420 is formed before the semiconductor 406c is provided.

[0208] First, a substrate 442 and a conductor 44 are formed by the steps described with reference to FIGS. 13, the insulator 402, the semiconductor 406a, the semiconductor 406b, the conductor 416a and the conductor 41 Form 6b.

[0209] Next, a layer 420 is formed. Next, oxygen is added (see FIG. 16(B)).

[0210] After the oxygen addition, a heat treatment may be performed. By performing the heat treatment, oxygen is converted into the semiconductor 4 It may be easier to spread up to 06b.

[0211] Next, the layer 420 is removed (see FIG. 16(C)). The material, the deposition of layer 420, the subsequent oxygen addition, and the subsequent removal of layer 420 are described above. The preparation method can be referred to.

[0212] Next, the semiconductor 406c is formed.

[0213] In the transistor 490, in order to improve the characteristics of the transistor, the semiconductor 40 It may be preferable to use a film that is denser than the semiconductor 406b as 6c. It is preferable to use a film having a lower hydrogen permeability than the semiconductor 406b as the semiconductor 406c. Alternatively, the semiconductor 406c may have a lower oxygen permeability than the semiconductor 406b. On the other hand, if such a film is used for the semiconductor 406c, The hydrogen desorbed from the semiconductor 406a and the semiconductor 406b is blocked by the semiconductor 406c. In this case, it may be difficult to reduce the hydrogen concentration in the semiconductor 406a and the semiconductor 406b. It may be difficult to diffuse oxygen from the layers above body 406c.

[0214] Therefore, as shown in FIG. 16(A) to FIG. 16(C), the semiconductor 406a and the semiconductor 40 After forming the semiconductor 406b, the layer 420 is provided, oxygen is added, and the semiconductor 406a and the semiconductor 406b are After reducing the oxygen vacancies and hydrogen in b, the layer 420 is removed and a semiconductor 406c is provided. As a result, the hydrogen concentrations in the semiconductors 406a and 406b can be reduced. I wish.

[0215] Here, the layer 420 is formed on the semiconductor 406b, and oxygen is added thereto. Then, as shown in FIG. As shown, when etching is used to remove layer 420, the etching removes the semiconductor It is preferable that the layer 420 is etched at a rate that is less likely to remove the semiconductor layer 406b. It is preferable that the etching rate of the semiconductor 40 is faster than that of the semiconductor 40b. It is preferable that damage to the surface of 6b is small.

[0216] Alternatively, in the etching process of layer 420, the very surface of semiconductor 406b is etched. For example, when the layer 420 is formed, damage may occur or the elements contained in the layer 420 may be decomposed into the semiconductor 4 If they get near the surface of 06b, they will be removed by etching the extreme surface. It is possible.

[0217] Here, for example, the layer 420 and the semiconductor 406b are selected from the group consisting of indium, element M, and zinc. Consider the case where a membrane having at least one, or more than one, is used.

[0218] The difference between the percentage of indium in layer 420 and the percentage of indium in semiconductor layer 406b is For example, the ratio of indium in layer 420 is preferably 0.6 or less. It is preferable that the ratio is 0.3 times or less, and more preferable that the ratio is 1.5 times or more, and more preferable that the ratio is 3 times or more. is more preferred.

[0219] Here, the ratio of indium is the ratio of indium to the sum of the numbers of indium, element M, and zinc atoms. The ratio of the number of atoms of element M to that of zinc is the same.

[0220] Alternatively, the difference between the ratio of element M in layer 420 and the ratio of element M in semiconductor 406b is For example, the ratio of element M in layer 420 is preferably 0.6 times or less. More preferably, the ratio is 0.3 times or less. Alternatively, the ratio is preferably 1.5 times or more, and more preferably 3 times or more. It is.

[0221] Alternatively, the zinc content of layer 420 may differ significantly from the zinc content of semiconductor layer 406b. For example, the ratio of zinc in layer 420 is preferably 0.6 times or less, and more preferably 0. More preferably, the ratio is 3 times or less, or 1.5 times or more, and more preferably, 3 times or more.

[0222] The difference between the ratio of indium, element M, or zinc in layer 420 and that in semiconductor 406b is large. This increases the selectivity when removing layer 420 by, for example, dry etching. In addition, the difference in the ratio of these elements is large, so that the thickness loss of the semiconductor 406b can be suppressed. By doing so, it may be possible to improve the processing accuracy. For example, dry etching When monitoring etching by spectroscopic analysis of the plasma emission from reactive species, At this point, etching of layer 420 is largely complete and etching of the underlying semiconductor layer 406b begins. The timing of the change becomes easier to detect, and the amount of etching of the semiconductor 406b can be reduced. There is a match.

[0223] By making layer 420 have a higher ratio of zinc than semiconductor 406b, e.g. When an acid or alkali is used as the etching solution, the layer 420 is wet etched. In some cases, the etching speed can be made higher than that of the semiconductor 406b. For example, a liquid containing phosphoric acid or a liquid containing oxalic acid can be used. For example, a mixture of phosphoric acid, acetic acid, nitric acid, and pure water can be used. The mixture ratio of acid, acetic acid, nitric acid, and pure water may be, for example, 85:5:5:5 by volume. In addition, the alkaline chemical solution is ammonia hydrogen peroxide (a mixture of ammonia water and hydrogen peroxide solution). (things) can be used.

[0224] The conductors 416a and 416b may be made of a metal nitride such as tantalum nitride or a platinum nitride. By using platinum-based materials such as gold, ruthenium, and iridium, the wet etching of layer 420 can be achieved. This is more preferable since it can increase the resistance to etching.

[0225] In addition, the layer 420 is preferably made of a film having a higher hydrogen permeability than the semiconductor 406c. I wish.

[0226] For example, layer 420 may include indium and semiconductor 406c may include no indium. It is also preferable to use gallium oxide as the semiconductor 406c. For example, By using gallium oxide as the semiconductor 406c, a transistor with a lower off-current can be obtained. It is possible to realize the above.

[0227] Next, an insulator 412 is deposited.

[0228] Next, oxygen may be added from above the insulator 412. The method of adding oxygen is as follows: The above-mentioned oxygen addition method can be referred to.

[0229] Next, a heat treatment may be carried out.

[0230] Next, the conductor 404 is formed (see FIG. 17A). Note that the conductor 404 is a semiconductor It is formed to overlap at least a portion of body 406b.

[0231] Next, the insulator 408 is formed. After the insulator 408 is formed, heat treatment may be performed. Next, an insulator 418 is formed (see FIG. 17B). A transistor 490 can be fabricated.

[0232] <Transistor manufacturing method 3> Next, as a modification of the above two manufacturing methods, a transistor 490 shown in FIG. The manufacturing method will be described with reference to Figures 18 and 19. In the manufacturing method described below, the layer 420 is removed. After that, the conductor 416a and the conductor 416b are formed.

[0233] The substrate 442, the conductor 413, the insulator 402, the semiconductor 406a, and the semiconductor 406b are shown in FIG. 12(A) and 12(B) are used to form the semiconductor device (see FIG. 18(A)). .

[0234] Next, a layer 420 is formed (see FIG. 18(B)). Next, oxygen is added (see FIG. 18(C)). See C). ).

[0235] After the oxygen addition, a heat treatment may be performed. By performing the heat treatment, oxygen is converted into the semiconductor 4 It may be easier to spread up to 06b.

[0236] Next, layer 420 is removed. For the subsequent oxygen addition and subsequent removal of layer 420, please refer to the above-mentioned fabrication method. can.

[0237] Next, the conductor 416a and the conductor 416b are formed (see FIG. 19A). By forming the conductor 416a and the conductor 416b in a step subsequent to the oxygen addition, The conductive material 416a and the conductive material 416b react with oxygen, and the reacted area is prevented from being insulated. In addition, for example, the etching conditions for the layer 420 may be such that the conductor 416a and the conductor 4 Since it is no longer necessary to consider etching conditions with a high selectivity to 16b, wet etching is possible. This allows for more options for conditions such as chemicals used in etching and gases used in dry etching. This may make etching easier.

[0238] Next, the steps from FIG. 19B onward will be described. The steps from FIG. 19B onward will be described in the same manner as in the above-mentioned manufacturing method. You can refer to the method.

[0239] First, the semiconductor 406c is formed. After the semiconductor 406c is formed, heat treatment may be performed. stomach.

[0240] Next, an insulator 412 is deposited.

[0241] Next, oxygen may be added from above the insulator 412. The method of adding oxygen is as follows: The above-mentioned oxygen addition method can be referred to.

[0242] Next, a heat treatment may be carried out.

[0243] Next, the conductor 404 is formed. Note that the conductor 404 is formed by forming at least Next, the insulator 408 is formed. After the insulator 408 is formed, Heat treatment may be performed. Next, the insulator 418 is formed (see FIG. 19B). In the above manner, the transistor 490 shown in FIG. 1 can be fabricated.

[0244] <Transistor manufacturing method 4> Next, an example of a manufacturing method of the transistor 490 shown in FIG. 2 will be described with reference to FIGS. explain.

[0245] First, the insulator 552, the conductor 413, the insulator 402, and the semiconductor 43 which will become the semiconductor 406a are 6a and the semiconductor 436b which will become the semiconductor 406b are formed by the process described with reference to FIG. and form.

[0246] Next, a conductor 416 is formed. The conductor 416 is formed by the above-mentioned manufacturing method. Next, a mask 427 is formed (see FIG. 20(A)). The mask 427 may be made of a photoresist. Bottom Anti Reflective Coa (BARC) By providing an anti-reflection film, defects caused by halation can be suppressed. Therefore, a fine shape can be obtained.

[0247] Next, the conductor 416 is etched using the mask 427, and the conductor 417 is Here, the conductor 417 may be called a hard mask. In order to form the conductor 417 having a fine shape, a micro-machined conductor having a fine shape is used. If the mask 427 having a fine shape is too thick, it may collapse. Therefore, it is preferable that the mask 42 has a region thick enough to be able to stand on its own. The conductor 416 is etched using the mask 427 under conditions that the mask 427 can withstand. However, the conductor 416 is preferably thin enough to be covered by the transistor 49 later. Conductor 416a and conductor 416b functioning as a source electrode and a drain electrode of 16b, a certain thickness is required to increase the on-current of the transistor 490. Therefore, for example, it is preferable that the thickness is 5 nm or more and 30 nm or less, and preferably 5 nm or less. A conductive region having a thickness of 0.05 nm or more and 20 nm or less, more preferably 5 nm or more and 15 nm or less. The conductor may be designated as conductor 416.

[0248] Next, the semiconductor 436b and the semiconductor 436a are etched using the conductor 417 as a mask. At this time, the insulator 402 is Etching makes it easier to form an s-channel structure (see FIG. 20(C)). ).

[0249] Next, a part of the conductor 417 is etched to form the conductor 416a and the conductor 416b. In this manner, the semiconductor 436a and the semiconductor 436b are formed (see FIG. 21(A)). The conductor 416, formed as a mask for etching, is the source of the transistor 490. Conductors 416a and 416b functioning as a source electrode and a drain electrode, The conductor 416 that becomes the conductor 416a and the conductor 416b is also used as a mask. Therefore, the number of steps required to manufacture the transistor 490 can be reduced. The conductor 490 can reduce the area occupied by the conductor 416a and the conductor 416b. Therefore, this structure is suitable for fine semiconductor devices.

[0250] Next, the steps from FIG. 21B onwards will be described. The preparation method can be referred to.

[0251] First, the layer 420 is formed. The material that can be used for the layer 420 is the same as that described above. Please refer to the description of the manufacturing method. Next, oxygen is added (see FIG. 21(B)).

[0252] After the oxygen addition, a heat treatment may be performed. By performing the heat treatment, oxygen is converted into the semiconductor 4 It may be easier to spread up to 06b.

[0253] Next, the layer 420 is removed. Next, a semiconductor film that becomes the semiconductor 406c is formed. After the film is formed, a heat treatment may be performed.

[0254] Next, an insulating film that will become the insulator 412 is formed.

[0255] Next, oxygen may be added from above the insulator 412. The method of adding oxygen is as follows: The above-mentioned oxygen addition method can be referred to.

[0256] Next, a heat treatment may be carried out.

[0257] Next, a conductive film that becomes the conductor 404 is formed.

[0258] Next, a part of the conductive film that will become the conductor 404 is etched to form the conductor 404. The conductor 404 is formed so as to overlap at least a portion of the semiconductor 406b.

[0259] Next, like the conductive film that becomes the conductor 404, a part of the insulating film that becomes the insulator 412 is etched. 412 is formed by etching.

[0260] Next, the conductive film that becomes the conductor 404 and the insulating film that becomes the insulator 412 are formed on the semiconductor 4 A part of the semiconductor 406c is etched to form the semiconductor 406c (see FIG. 21(C)). Light. ).

[0261] Next, the insulator 408 is formed. After the insulator 408 is formed, heat treatment may be performed. Next, an insulator 418 is formed (see FIG. 22). A dial 490 can be created.

[0262] <Structure of Semiconductor Device> Next, an example of a semiconductor device including the transistor 490 will be described with reference to FIG.

[0263] 23 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Different cross sections are shown in.

[0264] The semiconductor device shown in FIG. 23 includes a transistor 491 and an insulator 5 on the transistor 491. 52 and a transistor 490 on an insulator 552. Note that the insulator 552 is an oxide. It is an insulator that has the function of blocking atoms and hydrogen.

[0265] The transistor 491 is formed by an insulator 462 on a semiconductor substrate 400 and a conductive layer on the insulator 462. The conductive body 454, the insulator 470 in contact with the side of the conductive body 454, and the conductive body in the semiconductor substrate 400 454 and region 476 which is a region that does not overlap with insulator 470; and and region 474.

[0266] The semiconductor substrate 400 may be, for example, a single semiconductor such as silicon, germanium, or a carbide. Silicon, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, oxide A compound semiconductor such as zinc oxide or gallium oxide may be used for the semiconductor substrate 400. An amorphous semiconductor or a crystalline semiconductor may be used. As the crystalline semiconductor, a single crystal semiconductor , polycrystalline semiconductors, and microcrystalline semiconductors.

[0267] The insulator 462 functions as a gate insulator of the transistor 491. The insulator 454 functions as a gate electrode of the transistor 491. 70 functions as a sidewall insulator (also called a sidewall) of the conductor 454. Region 476 also functions as a source or drain region of transistor 491. The region 474 also functions as an LDD (Lightly Doped) transistor 491. It functions as a ped drain area.

[0268] The region 474 can be formed by doping impurities using the conductor 454 as a mask. Then, the insulator 470 is formed, and the conductor 454 and the insulator 470 are mass-produced. Region 476 can be formed by implanting impurities at a specific depth. If the regions 74 and 476 are formed with the same type of impurity, the region 474 will be thicker than the region 476. The impurity concentration is lower than that of the other regions.

[0269] Transistor 491 suppresses short channel effects by including region 474. Therefore, it is clear that this structure is suitable for miniaturization.

[0270] The transistor 491 is connected to the other transistors in the semiconductor substrate 400 and to the region 46. 0. Region 460 is an insulating region. The region 460 is called STI (Shallow Trench Isolation). For example, instead of the region 460, Formed by the LOCOS (Local Oxidation of Silicon) method A thin insulating material may be used to separate the transistors.

[0271] In FIG. 23, a transistor having the same polarity as the transistor 491 is adjacent to the transistor 491. In FIG. 23, the transistor 491 is disposed in the same manner as in FIG. 4 shows an example in which the transistor 492 is electrically connected to the region 476 . The transistor 491 and the transistor 492 have different polarities. In that case, the transistor 491 and the transistor 492 may be connected to the region 46 0, and transistors 491 and 492 are connected to region 474 and region The type of impurity contained in 476 is changed, and the transistors 491 and 492 A semiconductor substrate 400 overlapping a conductor that functions as one or both of the gate electrodes. In this case, a well region of a different conductivity type may be formed in a part of the region.

[0272] The transistors 491 and 492 have different polarities, so that the complementary metal Oxide Semiconductor (CMOS: Complementary Metal Oxide Semiconductor By constructing CMOS, it is possible to construct a semiconductor The power consumption of the device can be reduced, or the operating speed can be increased.

[0273] The structures of the transistors 491 and 492 are similar to those shown in FIG. For example, a transistor 491 and a transistor 492 shown in FIG. As shown in FIG. 1, the semiconductor substrate 400 has a protruding portion (also called a protrusion, a fin, etc.). The structure of the transistor 491 and the transistor 492 shown in FIG. In comparison with the structures of transistors 491 and 492 shown in FIG. The effective channel width relative to the area can be increased. This allows the current of the transistor 491 and the transistor 492 to be large when they are conductive.

[0274] Or, for example, transistor 491 and transistor 492 shown in FIG. Alternatively, a structure in which an insulating region 452 is provided in the semiconductor substrate 400 may be used. By using the structure of the transistor 491 and the transistor 492, the transistors are driven independently. This allows the transistors to be more reliably isolated from each other, and the leakage current can be suppressed. As a result, the current flowing through the transistors 491 and 492 when they are not conducting can be reduced. In addition, the current when the transistors 491 and 492 are turned on can be increased. It can be made easier.

[0275] As shown in FIG. 23, the transistors 491 and 492 , and the transistor 490. 552 preferably has a function of blocking oxygen and hydrogen. 552 is a semiconductor 406a or / and a semiconductor 406c that is more effective at blocking oxygen and hydrogen. The insulating material 552 is preferably made of, for example, aluminum oxide or oxide. Aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride tritium, hafnium oxide, hafnium oxynitride, tantalum oxide, zirconium oxide, Lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (B a,Sr)TiO3(BST) and the like can be used in a single layer or laminated layer. The insulating film may be nitrided to form an oxynitride film. This is preferable because it has an excellent barrier property against oxygen.

[0276] The insulator 552 is formed by sputtering, chemical vapor deposition (CVD), or the like. poration method, molecular beam epitaxy (MBE) Beam Epitaxy (PLD) or Pulsed Laser Deposition (PLD) ser Deposition) method, Atomic Layer Deposition (ALD) method The film may be formed by using a deposition method or the like.

[0277] The CVD method is a process that uses plasma (PECVD). Enhanced CVD method, Thermal CVD (TCVD) Furthermore, depending on the source gas used, it can be classified into metal CVD (MCVD:Me tal CVD) method, Metal Organic CVD (MOCVD) method D) can be divided into two methods.

[0278] The plasma CVD method can produce high-quality films at relatively low temperatures. Thermal CVD uses plasma. Since no plasma is used, no plasma damage occurs and a film with few defects can be obtained.

[0279] In the CVD method, the composition of the resulting film can be controlled by adjusting the flow rate ratio of the source gases. For example, in the MCVD and MOCVD methods, the flow rate ratio of the source gases can be adjusted to produce a film of any composition. In the MCVD method and the MOCVD method, for example, By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the transistor 490 can be improved.

[0280] For example, the transistor 491 and the transistor 492 are silicon transistors. In the case of a silicon wafer, hydrogen is supplied from an external source to reduce the dangling bonds of silicon. The supply of hydrogen can be, for example, For example, the heat treatment may be performed in an atmosphere containing hydrogen. An insulator including By performing the above, the hydrogen is diffused and supplied to the transistor 491 and the transistor 492. Specifically, the insulators on the transistors 491 and 492 may be It is preferable that the insulator 464 is an insulator containing hydrogen. The insulator 464 may have a single-layer structure or For example, a silicon oxynitride or silicon oxide and an oxynitride may be used. For example, a laminate structure having a silicon oxide or a silicon nitride may be used.

[0281] For example, insulators containing hydrogen are heated to temperatures between 100°C and 700°C or 10 1×10 in the surface temperature range of 0℃ to 500℃ 18 atoms / cm 3 That's it, 1×1 0 19 atoms / cm 3 or more than 1×10 20 atoms / cm 3 More than hydrogen (hydrogen In some cases, the electrons emitted may be equivalent to the number of atoms.

[0282] By the way, hydrogen diffused from the insulator 464 is absorbed by the conductive material provided at the opening of the insulator 464. through the insulator 472, the wiring layer 467 on the insulator 464, the wiring layer 469 on the wiring layer 467, etc. However, the insulator 552 blocks the hydrogen. Because of this function, only a small amount of hydrogen reaches the transistor 490. In the oxide semiconductor, it becomes a carrier trap or a carrier source, and the electrical characteristics of the transistor 490 Therefore, blocking hydrogen with the insulator 552 is not practical. It is important to improve the performance and reliability of conductor devices. The conductor that fills the openings electrically connects elements such as transistors and capacitors. In addition, the wiring layers 467 and 469 have a function of connecting to the The hatched areas indicate conductors, and the unhatched areas indicate insulators. The wiring layers such as 67 and the wiring layer 469 are provided by filling the openings of the conductor 472. It has the function of electrically connecting conductors.

[0283] On the other hand, for example, when oxygen is supplied to the transistor 490 from the outside, Since oxygen vacancies can be reduced, the electrical characteristics of the transistor may be improved. The supply of oxygen may be performed, for example, by a heat treatment in an atmosphere containing oxygen. Alternatively, for example, an insulator containing excess oxygen (oxygen) is placed near the transistor 490 and heated. The oxygen may be diffused by heat treatment and supplied to the transistor 490 . Here, the insulator 402 of the transistor 490 is an insulator containing excess oxygen.

[0284] The diffused oxygen reaches the transistor 491 and the transistor 492 through each layer. However, since the insulator 552 has a function of blocking oxygen, Only a small amount of oxygen reaches the transistors 491 and 492. If the transistor 492 is a silicon-based transistor, the oxide in the silicon The inclusion of these elements reduces the crystallinity of silicon and inhibits the movement of carriers. Therefore, blocking oxygen with the insulator 552 is a semiconductor This has important implications for improving the performance and reliability of body equipment.

[0285] In addition, in FIG. 23 and the like, the semiconductor device has an insulator 408 on a transistor 490. This is preferable. The insulator 408 has a function of blocking oxygen and hydrogen. Or, For example, the insulator 408 is more oxygen-rich than the semiconductor 406a or / and the semiconductor 406c. The insulator 408 has a high blocking function for hydrogen. Please refer to the description.

[0286] The semiconductor device includes an insulator 408, which prevents oxygen from diffusing out of the transistor 490. Therefore, the amount of excess oxygen (oxygen) contained in the insulator 402 can be suppressed. In contrast, oxygen can be effectively supplied to the transistor 490. 8 includes hydrogen that is mixed in from layers provided above the insulator 408 or from the outside of the semiconductor device. To block impurities, the electrical characteristics of the transistor 490 are degraded by the inclusion of impurities. This can prevent the above from happening.

[0287] For convenience, the insulator 552 and / or the insulator 408 are distinguished from the transistor 490. However, it may be a part of the transistor 490.

[0288] Note that the semiconductor device preferably has an insulator 418 over the insulator 408. In addition, the semiconductor device includes a conductor provided in an opening in the insulator 418 and the insulator 408. A conductor 424 electrically connects to the transistor 490 via the conductor 416b. It is okay to have one.

[0289] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0290] (Embodiment 2) In this embodiment, the semiconductor 406a, the semiconductor 406b, and the semiconductor The structure of an oxide semiconductor according to one embodiment of the present invention that can be applied to the semiconductor device 406c or the like will be described. In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0291] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0292] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Examples of the oxide semiconductor include a semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor.

[0293] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- These include OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0294] <caac-os> First, let me explain about CAAC-OS. The oxide semiconductor has axially aligned nanocrystals. It is also possible.

[0295] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0296] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly confirm the presence of the CAAC-OS at the grain boundaries. It can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0297] The CAAC-OS observed by TEM is described below. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration corrector function was used. , specifically called a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images are obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0298] A Cs-corrected high-resolution TEM image of the enlarged area (1) in Figure 26(A) is shown in Figure 26(B). From FIG. 26(B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0299] As shown in FIG. 26(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the inclination is about 0.8 nm. The pellets may also be referred to as nanocrystals (nc).

[0300] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 26(D)). Between the pellets observed in FIG. 26(C), The portion where the inclination occurs corresponds to an area 5161 shown in FIG.

[0301] FIG. 27(A) shows the C 27(A) shows the s-corrected high-resolution TEM images of regions (1), (2) and (3) in FIG. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 27(B), (C) and (D), respectively. As shown in Figure 27(D), Figure 27(B), Figure 27(C) and Figure 27(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0302] Next, C was analyzed by X-ray diffraction (XRD). We will explain AAC-OS. For example, CAAC-O with InGaZnO4 crystals When the out-of-plane structural analysis is performed on S, the result is as shown in Figure 28(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal has a c-axis orientation. It can be seen that the crystal has a c-axis oriented in a direction substantially perpendicular to the surface on which the crystal is formed or to the upper surface.

[0303] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31 In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is a structure obtained by the out-of-plane method. The analysis shows a peak at 2θ around 31° and no peak at 2θ around 36°.

[0304] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I It is attributed to the (110) plane of the crystal of nGaZnO4. In the case of CAAC-OS, 2θ is set to 5 The sample was fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in FIG. 28(B). On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 28(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and the b-axis is irregular.

[0305] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, a probe diameter of 300 nm was used parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the InGaZnO4 The spots due to the (009) plane of the crystal are included. Therefore, even by electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. 9(B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. In addition, the first ring in FIG. 29(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface, etc.

[0306] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. The defects include, for example, defects caused by impurities and oxygen vacancies. AC-OS can also be considered an oxide semiconductor with a low impurity concentration. S can also be said to be an oxide semiconductor with few oxygen vacancies.

[0307] Impurities contained in oxide semiconductors can act as carrier traps or as carrier generation sources. In addition, oxygen vacancies in an oxide semiconductor may become carrier traps or By capturing hydrogen, it can become a carrier generation source.

[0308] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0309] In addition, an oxide semiconductor with a low density of defect states (few oxygen vacancies) has a low carrier density. Such an oxide semiconductor can be a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. CAAC-OS is called an oxide semiconductor. It has a low impurity concentration and a low density of defect states. Therefore, the oxide semiconductor is likely to be a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. A transistor using AC-OS has electrical characteristics in which the threshold voltage is negative (normal Also, it is rare for the product to be pure or substantially pure. Oxide semiconductors have few carrier traps. The charge that is stored in the material takes a long time to be released and behaves like a fixed charge. Therefore, a transistor using an oxide semiconductor with a high impurity concentration and a high density of defect states is required. On the other hand, transistors using CAAC-OS can have unstable electrical characteristics. The resulting transistor has small fluctuations in electrical characteristics and is highly reliable.

[0310] In addition, because the density of defect states in CAAC-OS is low, the defects generated by light irradiation can be easily removed. Therefore, the carriers are less likely to be captured by the defect states. The electrical characteristics of a transistor vary little when irradiated with visible light or ultraviolet light.

[0311] <Microcrystalline oxide semiconductor> Next, a microcrystalline oxide semiconductor will be described.

[0312] Microcrystalline oxide semiconductors have regions where crystals can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a crystal structure including a region in which a crystal part is not clearly observed and a region in which a crystal part is not clearly observed. The crystal part contained is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, fine crystals with sizes between 1 nm and 10 nm or between 1 nm and 3 nm are often The oxide semiconductor with nanocrystals is called nc-OS (nanocrystallin The nc-OS is called NC-Oxide Semiconductor. In some cases, the grain boundaries cannot be clearly seen in the TEM images. It is possible that the origin of the pellets in C-OS is the same as that of the pellets in C-OS. The crystalline part of the OS is sometimes called a pellet.

[0313] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS may be used. When the structure was analyzed using the out-of-plane method, the crystal plane was not shown. In addition, the probe diameter ( For example, electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 50 nm or more. On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron circuits are used that use an electron beam with a probe diameter close to the size of the pellet or smaller than the pellet. When the nc-OS is folded, spots are observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a ring-like region.

[0314] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) The oxide semiconductor or NANC (Non-Aligned Nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0315] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. However, the density of defect states in the nc-OS is lower than that in the amorphous oxide semiconductor. In the case of S, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS is The defect density is higher than that of AAC-OS.

[0316] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0317] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0318] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0319] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductor, a halo pattern is observed. When nanobeam electron diffraction was performed on the specimen, no spots were observed, only a halo pattern was observed. Observed.

[0320] There are various views on amorphous structures. For example, A structure that does not have this property is called a completely amorphous structure. In addition, the distance between the nearest neighbors or the second nearest neighbors is called the structure. A structure that has order at the interface and no long-range order is sometimes called an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called a non-crystalline oxide semiconductor. In addition, it cannot be called an crystalline oxide semiconductor. Amorphous oxide semiconductors cannot be called amorphous oxide semiconductors. For example, CAAC-OS and nc-OS can be used as amorphous oxide semiconductors or completely amorphous It cannot be called an oxide semiconductor.

[0321] <Amorphous-like oxide semiconductor> Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (alumina-like oxide semiconductor). ike OS:amorphous-like Oxide Semiconducto It is called r).

[0322] In a-like OS, voids are observed in high-resolution TEM images. In addition, crystals may be clearly visible in high-resolution TEM images. and regions where no crystalline portion can be confirmed.

[0323] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0324] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as sample B) and CAAC-OS (hereinafter referred to as sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0325] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0326] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are layered in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing between the crystals is 0.28 nm to 0.30 nm are considered to be crystal parts of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0327] Figure 30 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes is the size of the crystal part. It can be seen that the crystalline part of the ke OS grows in size according to the cumulative dose of electron irradiation. Specifically, as shown by (1) in Figure 30, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus), which was 4.2×10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 30, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that.

[0328] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not seen as a nc-OS or CAAC-OS. It is clear that it has an unstable structure compared to the OS.

[0329] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0330] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0331] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be used in any ratio. By combining single crystals of the desired composition, the density equivalent to that of a single crystal of the desired composition can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate the size of the single crystal by combining different types of single crystals.

[0332] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a compound semiconductor and a CAAC-OS.

[0333] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0334] FIG. 31A shows a process in which a CAAC-OS film is formed by a sputtering method. FIG. 1 is a schematic diagram of the inside of a membrane chamber.

[0335] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130 through the magnets. The magnetic field is generated by a number of magnets. The magnetic field of the magnets is used to increase the deposition speed. The sputtering method used is called magnetron sputtering.

[0336] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The deposition chamber is mostly filled with deposition gas (e.g., oxygen, argon, or a mixture containing 5% or more by volume of oxygen) and The pressure is controlled to be 1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, a discharge starts and a plasma is generated. It is confirmed that a high density plasma region is generated near the target 5130 by the magnetic field. In the high-density plasma region, the deposition gas is ionized, and ions 5101 The ion 5101 is, for example, an oxygen cation (O + ) and argon cations ( Ar + ) etc.

[0337] Here, the target 5130 has a polycrystalline structure having multiple crystal grains, The crystal grains include cleavage planes. FIG. 32(A) shows an example of a cleavage plane included in a target 5130. The crystal structure of InGaZnO4 is shown in Fig. 32(A). This is the structure of InGaZnO4 crystals observed from the outside. In the Ga-Zn-O layers, the oxygen atoms in each layer are arranged in close proximity. The negative charge of the oxygen atom causes the two adjacent Repulsion occurs between the Ga-Zn-O layers. As a result, the InGaZnO4 crystals are The cleavage plane is between the two Ga-Zn-O layers.

[0338] Ions 5101 generated in the high-density plasma region are attracted to the target 5130 by the electric field. The cleavage plane is then accelerated and collides with the target 5130. At this time, flat or planar particles are generated from the cleavage plane. Pellet 5100a and pellet 5100b, which are pellet-shaped sputtered particles, are peeled off, The pellets 5100a and 5100b are ejected by the ions 5101. The impact of a collision can cause distortion of the structure.

[0339] The pellet 5100a is a flat plate or pellet having a triangular, for example equilateral, plane. The pellet 5100b is a sputtered particle having a hexagonal shape, for example, a regular hexagonal plane. The pellets 5100a and 5100b are sputtered particles having a plate-like or pellet-like shape. The term pellets refers to flat or pellet-shaped sputter particles such as pellet 5100b. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon, but may be any shape, e.g. For example, a shape may be formed by combining multiple triangles. In some cases, the shape may be a quadrilateral (for example, a rhombus) made up of two joined sides.

[0340] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason will be explained later. It is preferable that the thickness of the pellet 5100 is uniform. A pellet shape with no lumps is preferable to a thick cube shape. The thickness of the 5100 is 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less. The diameter of the pellet 5100 is 1.2 nm or more and 2.5 nm or less. For example, the target 5 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded with the Ga-Zn-O layer 130, as shown in FIG. A pellet 5100 having three layers, an In-O layer and a Ga-Zn-O layer, is peeled off. FIG. 2(C) shows the structure of the exfoliated pellet 5100 observed from a direction parallel to the c-axis. The ret 5100 has two Ga-Zn-O layers (pan) and an In-O layer (fixing). It can also be called a nano-sized sandwich structure.

[0341] As the pellet 5100 passes through the plasma, it picks up an electric charge, causing the sides to become negative. The pellet 5100 may be, for example, a pellet with negatively charged oxygen atoms on the side. The sides of the object can be charged with the same polarity, resulting in repulsion between the charges. This allows the pellets to maintain their flat or pellet-like shape. When the OS is an In-Ga-Zn oxide, the oxygen atom bonded to the indium atom is negatively charged. It may become electrically charged or may bond with indium, gallium or zinc atoms. The oxygen atoms may become negatively charged. Also, the pellet 5100 may become charged by passing through the plasma. When the electrons enter the plasma, they bond with indium atoms, gallium atoms, zinc atoms, and oxygen atoms in the plasma. The difference in size between (2) and (1) in Figure 30 above is This corresponds to the growth in the plasma. Here, when the substrate 5120 is at room temperature, Since the growth of pellet 5100 on 120 is difficult, it becomes nc-OS (Figure 31 (See FIG. 1B). Since the film can be formed at room temperature, even if the substrate 5120 has a large area, It is possible to form a film of nc-OS. In addition, pellet 5100 is grown in plasma. In order to achieve this, it is effective to increase the deposition power in the sputtering method. This makes it possible to stabilize the structure of the pellet 5100.

[0342] As shown in FIG. 31(A) and FIG. 31(B), for example, a pellet 5100 is It flies like a kite through the air and flutters up to the top of the board 5120. Since the pellet 100 is electrically charged, it will be attracted to the area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, a vertical magnetic field (also called a horizontal magnetic field) is generated between the substrate 5120 and the target 5120. Since a potential difference is applied between the electrodes 130, the electric field from the substrate 5120 to the target 5130 Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120 in the following manner: The magnetic field and the electric current act on the object, resulting in a force (Lorentz force). This is what Fleming This can be understood by the left-hand rule.

[0343] The pellet 5100 has a large mass compared to a single atom. In order to move the surface, it is important to apply some kind of force from the outside. One of these forces is It is possible that the force is generated by the action of a magnetic field and an electric current. To provide sufficient force to move the top surface of 5120, the top surface of the substrate 5120 must be The magnetic field parallel to the upper surface of the substrate 5120 is 10 G or more, preferably 20 G or more, and more preferably It is preferable to provide a region where the resistance is 30 G or more, and more preferably 50 G or more. At the top surface of the plate 5120, a magnetic field parallel to the top surface of the substrate 5120 At least 1.5 times, preferably at least 2 times, more preferably at least 3 times the magnetic field perpendicular to the top surface. It is preferable to provide an area where the thickness is 5 times or more.

[0344] At this time, the magnet and the substrate 5120 move or rotate relatively. The direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. On the upper surface of the plate 5120, the pellet 5100 is subjected to forces from various directions. You can move to.

[0345] Also, when the substrate 5120 is heated as shown in FIG. 31(A), the pellet 510 0 and the substrate 5120, the resistance due to friction is small. The pellet 5100 glides over the top surface of the substrate 5120. The transfer occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches its side surface, the sides of the pellet 5100 are joined together. The oxygen atom on the side of 00 is removed. The removed oxygen atom causes the Since oxygen vacancies may be filled, the CAAC-OS has a low density of defect states. The temperature of the upper surface of the plate 5120 is, for example, 100° C. or more and less than 500° C., 150° C. or more and 450° C. The temperature may be set to 170° C. or higher and lower than 400° C. Even in such a case, it is possible to form a CAAC-OS film.

[0346] In addition, the pellet 5100 is heated on the substrate 5120, whereby the atoms are rearranged. The distortion of the structure caused by the collision of the ions 5101 is relieved. Pellet 5100 is almost single crystal. Even if the pellets 5100 are heated after being bonded to each other, the pellets 5100 themselves do not expand. Therefore, the gaps between the pellets 5100 widen, and the crystals Defects such as grain boundaries do not form, and crevasses do not form.

[0347] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The pellets are made of nano-crystals, and the aggregates resemble bricks or blocks stacked together. In addition, there are no grain boundaries between the pellets 5100. Heating during and after film formation, or bending, can cause deformation such as shrinkage in CAAC-OS. Even if the deformation occurs, it is possible to relieve the local stress or release the strain. This structure is suitable for use in flexible semiconductor devices. The result is an arrangement in which Ret 5100 (nanocrystals) are randomly stacked.

[0348] When the target 5130 is sputtered by ions 5101, not only the pellet 5100 but also Zinc oxide may peel off. Zinc oxide is lighter than pellet 5100. Therefore, it reaches the upper surface of the substrate 5120 first. A zinc oxide layer 5102 having a thickness of 2 nm or more and 5 nm or less, or 0.5 nm or more and 2 nm or less, is formed. A schematic cross-sectional view is shown in Figure 33.

[0349] As shown in FIG. 33(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are deposited. The pellets 5105c and 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, it slides on pellet 5105b. In another aspect of FIG. 05a, a plurality of particles 510 detached from the target along with zinc oxide. 3 is crystallized by heating from the substrate 5120 to form a region 5105a1. The number of particles 5103 may include oxygen, zinc, indium, and gallium, among others.

[0350] As shown in FIG. 33(B), the region 5105a1 is integral with the pellet 5105a. The pellet 5105c is formed by condensing the pellet 5105a2. Place it so that it is in contact with another side of 5105b.

[0351] Next, as shown in FIG. 33(C), a pellet 5105d is further added to the pellet 5105a2. After being deposited on pellet 5105a2 and pellet 5105b, It slides on the pellet 5105b. It also slides toward the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0352] As shown in FIG. 33(D), the pellet 5105d has a side surface similar to that of the pellet 51. The pellet 5105e is placed so that its side is in contact with the pellet 5105a2. Also, the other side of the pellet 5105d is placed in contact with the other side of the pellet 5105c. On the surface, a plurality of particles 5103 peeled off from the target 5130 together with zinc oxide are formed. Heat from plate 5120 causes crystallization, forming region 5105d1.

[0353] As described above, the piled pellets are arranged so that they come into contact with each other, and the pellets are The growth occurs to form a CAAC-OS on the substrate 5120. The individual pellets of AC-OS are larger than those of nc-OS. The difference in size between 3) and (2) corresponds to the growth that occurred after deposition.

[0354] In addition, the gaps between the pellets become extremely small, so that one large pellet is formed. One large pellet may have a single crystal structure. For example, The size is 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, as viewed from the top. In some cases, the size of the transistors used is between 20nm and 50nm. In an oxide semiconductor, a channel formation region may be contained within one large pellet. That is, a region having a single crystal structure can be used as a channel forming region. As the gap grows, the region with a single crystal structure becomes the channel formation region of the transistor. , may be used as source and drain regions.

[0355] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0356] Based on the above model, it is considered that the pellet 5100 is deposited on the substrate 5120. CAAC-OS can be deposited even on a surface that does not have a crystalline structure. This indicates that the growth mechanism is different from epitaxial growth. AC-OS does not require laser crystallization and can achieve uniform growth even on large glass substrates. For example, the structure of the upper surface (surface to be formed) of the substrate 5120 is an amorphous structure (e.g. It is possible to form a CAAC-OS film even on amorphous silicon oxide.

[0357] In addition, even if the upper surface of the substrate 5120 on which the CAAC-OS is to be formed is uneven, It can be seen that the pellets 5100 are arranged along the shape of the substrate 5120. If the surface is atomically flat, the pellet 5100 will have a flat surface that is parallel to the ab plane. If the pellet 5100 has a uniform thickness, it is flat and has a uniform thickness. A layer with high crystallinity is formed. Then, the layer is stacked in n steps (n is a natural number). By doing so, CAAC-OS can be obtained.

[0358] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 51 The structure is made up of n layers (n is a natural number) of layers in which 00 are arranged along the unevenness. Since the surface of the pellet 5100 is uneven, gaps tend to form between the pellets 5100 in the CAAC-OS. However, even in this case, intermolecular forces act between the pellets 5100, causing unevenness. Even if the pellets are arranged in a way that the gaps between them are as small as possible. It is possible to obtain a CAAC-OS having high crystallinity.

[0359] Since the CAAC-OS film is formed by such a model, the sputtered particles are distributed evenly throughout the film. It is preferable that the sputtered particles are in the form of thick pellets. In this case, the surface facing the substrate 5120 is not uniform, and the thickness and crystal orientation cannot be made uniform. There is.

[0360] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface having an amorphous structure. Thus, a CAAC-OS having the above properties can be obtained.

[0361] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0362] (Embodiment 3) In this embodiment, a circuit of a semiconductor device including a transistor according to one embodiment of the present invention will be described. An example of the path will now be described.

[0363] <CMOSインバータ> The circuit diagram shown in FIG. 34A includes a p-channel transistor 2200 and an n-channel The transistors 2100 are connected in series and the gates of the transistors are connected together. 1 shows the configuration of an OS inverter.

[0364] <Structure of semiconductor device 2> 35 is a cross-sectional view of the semiconductor device corresponding to FIG. 34(A). The device includes a transistor 2200 and a transistor 2100. The transistor 2100 is disposed above the transistor 2200. In this embodiment, the transistor shown in FIG. 1 is used. The semiconductor device according to the embodiment is not limited to this. For example, the semiconductor device shown in FIG. A transistor such as the above may be used as the transistor 2100. For the transistor 2100, the above-mentioned description of the transistor may be referred to as appropriate.

[0365] The transistor 2200 shown in FIG. 35 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450 and a region 472b in the semiconductor substrate 450. The transistor shown in FIG. As the transistor 2200, for example, the transistor 491 and the transistor 492 shown in FIG. You may also illuminate the

[0366] In transistor 2200, regions 472a and 472b are source and The insulator 462 also functions as a gate insulator. The conductor 454 also functions as a gate electrode. The resistance of the channel formation region can be controlled by the potential applied to the electrode 454 . That is, the electric potential applied to the conductor 454 causes electrical conduction between the region 472a and the region 472b. Non-conduction can be controlled.

[0367] For the semiconductor substrate 450, the description of the semiconductor substrate 400 can be referred to.

[0368] The semiconductor substrate 450 is a semiconductor substrate having impurities that impart n-type conductivity. However, a semiconductor substrate having impurities that impart p-type conductivity is used as the semiconductor substrate 450. In that case, the region that will become the transistor 2200 is given n-type conductivity. Alternatively, if the semiconductor substrate 450 is an i-type, That's fine.

[0369] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The on-characteristics of the transistor 2200 can be improved.

[0370] Regions 472a and 472b are regions having impurities that impart p-type conductivity. In this manner, the transistor 2200 constitutes a p-channel transistor.

[0371] Note that transistor 2200 is separated from adjacent transistors by region 460, etc. The region 460 is an insulating region.

[0372] The semiconductor device shown in FIG. 35 includes an insulator 464, an insulator 466, an insulator 468, and a conductive Conductor 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478 b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 49 6c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, It has an insulator 493, an insulator 495, and an insulator 494.

[0373] An insulator 464 is disposed on the transistor 2200. Also, an insulator 466 is disposed on the transistor 2200. 464. Insulator 468 is disposed on insulator 466. Insulator 493 is disposed on the insulator 468. Also, the transistor 2100 is disposed on the insulator 493. An insulator 495 is disposed on the transistor 2100. 494 is disposed on insulator 495 .

[0374] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings each include a conductor 480a, Conductor 480b or conductor 480c is embedded.

[0375] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a mouth and an opening that reaches the conductor 480c. The conductive body 478a, the conductive body 478b, or the conductive body 478c is embedded therein.

[0376] Additionally, insulator 468 has an opening reaching conductor 478b and an opening reaching conductor 478c. The openings each include a conductor 476a and a conductor 476b. It is embedded.

[0377] The insulator 493 has an opening overlapping with a channel formation region of the transistor 2100 and The conductor 476 has an opening that reaches the conductor 476a and an opening that reaches the conductor 476b. The openings are filled with a conductor 474a, a conductor 474b, or a conductor 474c. It is being done.

[0378] The conductor 474a may function as a gate electrode of the transistor 2100. For the conductor 474a, the description of the conductor 413 can be referred to.

[0379] The insulator 495 is connected to one of the source and drain electrodes of the transistor 2100. An opening through conductor 416b, which is a transistor 210, to conductor 474b. An opening reaching the conductor 416a, which is the other of the source electrode or drain electrode of 0, and An opening reaching the conductor 404, which is the gate electrode of the transistor 2100, and a The openings are provided with a conductor 496a and a conductor 496b. b, the conductor 496c or the conductor 496d is embedded. The portion may also be connected through an opening in any of the components, such as the transistor 2100. There is a match.

[0380] The insulator 494 also has an opening that reaches the conductor 496a, and an opening that reaches the conductor 496b and the conductor The opening reaches the conductor 496d, and the opening reaches the conductor 496c. The conductive body 498a, the conductive body 498b, and the conductive body 498c are embedded in the conductive body 498a, the conductive body 498b, and the conductive body 498c, respectively. There are.

[0381] Insulator 464, insulator 466, insulator 468, insulator 493, insulator 495 and insulator The description of the insulator 552 may be referred to for the body 494 .

[0382] Insulator 464, Insulator 466, Insulator 468, Insulator 493, Insulator 495 or Insulator At least one of the bodies 494 is an insulator having a function of blocking impurities such as hydrogen and oxygen. It is preferable to have impurities such as hydrogen and oxygen near the transistor 2100. By disposing an insulator having a blocking function, the electrical The characteristics can be stabilized.

[0383] Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b , conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b , conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d The conductor 498a, the conductor 498b, and the conductor 498c may be, for example, boron, nitrogen, or the like. Elements, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt Nickel, Copper, Zinc, Gallium, Yttrium, Zirconium, Molybdenum, Ruthenium Conductors containing one or more of aluminum, silver, indium, tin, tantalum and tungsten are used. It may be used in layers or laminates. For example, it may be an alloy or compound, such as aluminum. Conductors containing copper and titanium, conductors containing copper and manganese, indium Conductors containing titanium, tin and oxygen, and conductors containing titanium and nitrogen may also be used.

[0384] In the semiconductor device shown in FIG. 35, the structure of the transistor 2200 is the same as that shown in FIG. The transistor 491 or 492 shown in FIG. The fin 491 and the transistor 492 have a fin-type structure.

[0385] In the semiconductor device shown in FIG. 35, the structure of the transistor 2200 is The transistor 491 or 492 shown in FIG. The stator 491 and the transistor 492 are provided on a semiconductor substrate 400, which is an SOI substrate. This shows the case where

[0386] The semiconductor device shown in FIG. 35 is a semiconductor substrate having a p-channel transistor. Since an n-channel transistor is fabricated above it, the area occupied by the element is reduced. In other words, the integration degree of the semiconductor device can be increased. Compared to the case where a p-channel transistor and a p-channel transistor are fabricated using the same semiconductor substrate, In this way, the process can be simplified, and the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. The data is based on the LDD (Lightly Doped Drain) region and shallow trench structure. In some cases, complex processes such as distortion design can be omitted. The productivity and yield of the laser can be increased compared to when a semiconductor substrate is used for manufacturing the laser. It may be possible to do this.

[0387] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 34B shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called CMOS analog switch.

[0388] <Storage device 1> A memory device using a transistor according to one embodiment of the present invention, capable of storing stored contents even when power is not supplied An example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written is shown in Figure 3. Shown in 6.

[0389] The semiconductor device shown in FIG. 36A includes a transistor 3200 using a first semiconductor and a The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 can be any of the transistors described above.

[0390] The transistor 3300 is preferably a transistor with low off-state current. For example, a transistor including an oxide semiconductor can be used as the transistor 300. The low off-state current of the 3300 allows a specific node of the semiconductor device to be It is possible to retain the stored contents. In other words, no refresh operation is required. This allows the frequency of refresh operations to be reduced significantly, resulting in a low power consumption semiconductor It becomes a conductor device.

[0391] In FIG. 36A, a first wiring 3001 is electrically connected to the source of a transistor 3200. , and the second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 3 005 is electrically connected to the other electrode of the capacitor 3400 .

[0392] The semiconductor device shown in FIG. 36A is capable of holding a gate potential of the transistor 3200. This characteristic makes it possible to write, retain, and read information, as shown below. be.

[0393] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is set to a potential at which the transistor 3300 is turned on. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and The signal is applied to a node FG electrically connected to one of the electrodes of the capacitor 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). The charges that give two potential levels are called the low-level charge and the high-level charge. ) is applied. Then, the potential of the fourth wiring 3004 is applied to the transistor The potential at which transistor 3300 is turned off is set to a potential at which transistor 3300 is turned off. This causes charge to be held (retained) at node FG.

[0394] Since the off-state current of the transistor 3300 is small, the charge of the node FG is maintained for a long period of time. Retained.

[0395] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, The line 3002 takes on a potential according to the amount of charge held in the node FG. If the transistor 3200 is an n-channel type, a high-level voltage is applied to the gate of the transistor 3200. The apparent threshold voltage V under load th_H is a transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate of th_L Here, the apparent threshold voltage is the threshold voltage of the transistor 3200. The potential of the fifth wiring 3005 required to make the fifth wiring 3005 in a "conductive state" is referred to as the potential of the fifth wiring 3005 required to make the fifth wiring 3005 in a "conductive state". Then, the potential of the fifth wiring 3005 is V th_H and V th_L The potential between them is V0. For example, in a write, the charge applied to node FG can be determined by When a high-level charge is applied to G, the potential of the fifth wiring 3005 becomes V0 ( >V th_H ), transistor 3200 is in a "conducting state." On the other hand, node F When a low-level charge is applied to G, the potential of the fifth wiring 3005 becomes V0 (< V th_L ), transistor 3200 remains in a "non-conducting state." Therefore, the potential of the second wiring 3002 is determined, and the data stored in the node FG is read. It can be seen.

[0396] When memory cells are arranged in an array, the information of a desired memory cell is read out. In order not to read information from other memory cells, The voltage applied to the FG terminal is such that the transistor 3200 is in a "non-conducting state." V th_H A lower potential may be applied to the fifth wiring 3005. A voltage that causes transistor 3200 to be in a "conducting state" regardless of the charge applied to the gate FG. V th_L A higher potential may be applied to the fifth wiring 3005 .

[0397] <Structure of semiconductor device 3> FIG. 37 is a cross-sectional view of the semiconductor device corresponding to FIG. 36(A). The device includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are disposed above the transistor 3200. The transistor 3300 is arranged in the same manner as the transistor 2100 described above. The transistor 3200 may be the transistor shown in FIG. Please refer to the description of the transistor 2200 in FIG. Although the case where the transistor 3200 is a p-channel transistor has been described, A channel type transistor may also be used.

[0398] The transistor 3200 shown in FIG. 37 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 472a in the semiconductor substrate 450 and a region 472b in the semiconductor substrate 450. region 472b, an insulator 462, and a conductor 454.

[0399] The semiconductor device shown in FIG. 37 includes an insulator 464, an insulator 466, an insulator 468, and a conductive Conductor 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478 b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 49 6c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, It includes a conductor 498d, an insulator 493, an insulator 495, and an insulator 494.

[0400] An insulator 464 is disposed on the transistor 3200. Also, an insulator 466 is disposed on the transistor 3200. 464. Insulator 468 is disposed on insulator 466. Insulator 493 is disposed on the insulator 468. Also, the transistor 3300 is disposed on the insulator 493. An insulator 495 is disposed on the transistor 3300. 494 is disposed on insulator 495 .

[0401] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings each include a conductor 480a, Conductor 480b or conductor 480c is embedded.

[0402] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a mouth and an opening that reaches the conductor 480c. The conductive body 478a, the conductive body 478b, or the conductive body 478c is embedded therein.

[0403] Additionally, insulator 468 has an opening reaching conductor 478b and an opening reaching conductor 478c. The openings each include a conductor 476a and a conductor 476b. It is embedded.

[0404] The insulator 493 has an opening overlapping with a channel formation region of the transistor 3300 and The conductor 476 has an opening that reaches the conductor 476a and an opening that reaches the conductor 476b. The openings are filled with a conductor 474a, a conductor 474b, or a conductor 474c. It is being done.

[0405] The conductor 474a may function as a bottom gate electrode of the transistor 3300. Alternatively, for example, a constant potential may be applied to the conductor 474a to turn on the transistor. The electrical properties of the transistor 3300, such as the threshold voltage, may be controlled. The body 474a is electrically connected to the conductor 404 which is the top gate electrode of the transistor 3300. This can increase the on-current of the transistor 3300. In addition, the punch-through phenomenon can be suppressed, so that the transistor 330 The electrical characteristics in the saturation region of 0 can be stabilized.

[0406] The insulator 495 is connected to one of the source and drain electrodes of the transistor 3300. An opening through conductor 416b, which is a transistor 330, to conductor 474b. 0 through the conductor 416a, which is the other of the source electrode or drain electrode, and the insulator 412. An opening reaching the overlapping conductor 414 and the conductor that is the gate electrode of the transistor 3300 An opening reaching 404 and the other of the source electrode or drain electrode of transistor 3300 and an opening through the conductor 416a, which is the opening, to the conductor 474c. The mouth of the wire is provided with a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 49 However, each opening is filled with a transistor 3300 and the like. This may be through an opening in any of the components.

[0407] In addition, the insulator 494 has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b. a mouth portion, an opening extending to conductor 496c, and an opening extending to conductor 496d. In addition, the openings are provided with a conductor 498a, a conductor 498b, a conductor 498c, or Conductor 498d is embedded therein.

[0408] Insulator 464, Insulator 466, Insulator 468, Insulator 493, Insulator 495 or Insulator At least one of the bodies 494 is an insulator having a function of blocking impurities such as hydrogen and oxygen. It is preferable to have impurities such as hydrogen and oxygen near the transistor 3300. By disposing an insulator having a blocking function, the electrical The characteristics can be stabilized.

[0409] As a material that can be used for the conductor 498d, see, for example, the description of the conductor 480a. It can be lit up.

[0410] The source or drain of the transistor 3200 is connected to the conductor 480a and the conductor 478a. , the conductor 476a, the conductor 474b, and the conductor 496c. Electrically connect to the conductor 416b, which is one of the source electrode or drain electrode of 300. In addition, the conductor 454, which is the gate electrode of the transistor 3200, is connected to the conductor 480c. Through the conductor 478c, the conductor 476b, the conductor 474c, and the conductor 496d, The conductor 416a, which is the other of the source electrode and the drain electrode of the transistor 3300, and Connect emotionally.

[0411] The capacitor 3400 is connected to the other of the source electrode and the drain electrode of the transistor 3300. The electrode is electrically connected to the conductor 414 and the insulator 412. Since the gate insulator 12 can be formed in the same process as the gate insulator of the transistor 3300, the productivity is improved. In addition, the conductor 414 may be a transistor 3. By using a layer formed through the same process as the gate electrode of 300, productivity can be improved. In some cases, this may be preferable.

[0412] For other structures, please refer to the descriptions in Figure 35 etc. as appropriate. In FIG. 35, the transistor 2200 is a p-channel transistor. However, the transistor 3200 may be an n-channel transistor.

[0413] In FIG. 37, the structure of the transistor 3200 is the same as that of the transistor 4 shown in FIG. The transistor 491 and the transistor 492 shown in FIG. The transistor 492 shown has a fin-type structure.

[0414] 37, the structure of the transistor 3200 is the same as that of the transistor 4 shown in FIG. The transistor 491 and the transistor 492 shown in FIG. The transistor 492 is shown to be provided on a semiconductor substrate 450, which is an SOI substrate. .

[0415] <Storage device 2> The semiconductor device shown in FIG. 36B differs from the semiconductor device shown in FIG. 36A in that it does not include the transistor 3200. This is different from the semiconductor device shown in FIG. 36(A). This enables the operation of writing and retaining information.

[0416] The reading of data in the semiconductor device shown in FIG. When the capacitor 3300 is turned on, the third wiring 3003 and the capacitor element 340, which are in a floating state, 0 is electrically connected, and charge is redistributed between the third wiring 3003 and the capacitor element 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is The potential of one of the electrodes of the capacitance element 3400 (or the charge stored in the capacitance element 3400) The values ​​are different depending on the

[0417] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 is denoted by CB, and the capacitance of the third wiring 3003 before the charge is redistributed is denoted by If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0+C×V) / (CB+C). Therefore, the state of the memory cell is Assume that the potential of one of the electrodes of element 3400 takes two states: V1 and V0 (V1>V0). and the potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C× V1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held ( =(CB×VB0+C×V0) / (CB+C)).

[0418] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0419] In this case, the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied as the transistor 3300. may be stacked on the drive circuit.

[0420] The above-described semiconductor device includes a transistor including an oxide semiconductor and having low off-state current. By using the refresh function, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store the potential for a long time. It is possible to retain the content.

[0421] In addition, the semiconductor device does not require a high voltage to write information, so there is no risk of element deterioration. For example, unlike conventional non-volatile memory, the flow of electrons to the floating gate is Since there is no injection or extraction of electrons from the floating gate, there is no degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the above-mentioned problems. There is no limit to the number of times that data can be rewritten, which is a problem in the past, and the reliability of semiconductor devices has improved dramatically. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0422] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0423] (Embodiment 4) An imaging device according to an aspect of the present invention will be described below.

[0424] <Imaging device> 38A is a plan view showing an example of an imaging device 200 according to one embodiment of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral The pixel section 210 has p rows and q The pixel array has a plurality of pixels 211 arranged in a matrix of columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are A signal supply circuit is connected to a plurality of pixels 211 and has a function of supplying signals for driving the plurality of pixels 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as the "peripheral circuit" or the "drive circuit." For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0425] The imaging device 200 preferably also includes a light source 291. The light source 291 is a detection light It can emit P1.

[0426] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel section 210 is formed. Also, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuits. The peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280 and peripheral circuit 29. One or more of the 0's may be omitted.

[0427] As shown in FIG. 38B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel count in the row direction and the pixel count in the row direction can be increased. This allows the pixel interval (pitch) in the column direction to be shortened. This can further improve the quality of imaging in the imaging device.

[0428] <Pixel configuration example 1> The imaging device 200 has one pixel 211 that is composed of multiple sub-pixels 212. Sub-pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By doing so, it is possible to obtain information for realizing a color image display.

[0429] FIG. 39(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 39(A) is provided with a color filter that transmits the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") transmits the green (G) wavelength band. A subpixel 212 (hereinafter also referred to as "subpixel 212G") provided with a color filter corresponding to the and a subpixel 212 (hereinafter, “ The subpixel 212 functions as a photosensor. It is possible.

[0430] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 2 31, the wiring 247, the wiring 248, the wiring 249, and the wiring 250. The subpixels 212R, 212G, and 212B are each connected to an independent wiring 2. 53. In this specification, for example, the pixel 211 in the nth row is connected to The wiring 248 and the wiring 249 are respectively designated as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the mth column is represented as wiring 253[m In FIG. 39A, the sub-pixel 212 of the pixel 211 in the m-th column is written as The wiring 253 connected to R is the wiring 253[m]R, and the wiring 253 connected to the subpixel 212G is the wiring 253[m]R. The wiring 253[m]G and the wiring 253 connected to the subpixel 212B are called wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0431] In addition, the imaging device 200 has color filters that transmit the same wavelength band for adjacent pixels 211. The sub-pixels 212 in which the filters are provided are electrically connected to each other via the switches. In Figure 39(B), the matrix is ​​arranged in n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). A sub-pixel 212 of a pixel 211 arranged in the n+1th row and the mth column adjacent to the pixel 211 is arranged in the n+1th row and the mth column. 39B shows an example of a connection of sub-pixels 212 of a pixel 211 arranged in the nth row. The sub-pixel 212R arranged in the mth column and the sub-pixel 212R arranged in the n+1th row and the mth column are switched. In addition, the sub-pixels 212G arranged in the nth row and the mth column are connected via the n+ The sub-pixels 212G arranged in the first row and the mth column are connected via the switches 202. The sub-pixels 212B arranged in the nth row and the mth column and the sub-pixels 212B arranged in the n+1th row and the mth column are 203.

[0432] The color filters used for the subpixel 212 are limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A sub-pixel for detecting light of three different wavelength bands may be provided in one pixel 211. By providing the element 212, a full color image can be obtained.

[0433] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are used. In addition to the sub-pixel 212, a color filter that transmits yellow (Y) light is provided. Alternatively, a pixel 211 having a subpixel 212 may be used. The subpixel 212 is provided with a color filter that transmits light of blue (Y) and magenta (M). In addition, a pixel 212 having a sub-pixel 212 provided with a color filter that transmits blue (B) light is 11 may be used. A single pixel 211 may have four sub-pixels for detecting light of different wavelength bands. By providing 212, the color reproducibility of the acquired image can be further improved.

[0434] Also, for example, in FIG. 39A, a subpixel 212 for detecting the red wavelength band and a subpixel 213 for detecting the green wavelength band are Ratio of the number of sub-pixels 212 that detect the long wavelength band and the number of sub-pixels 212 that detect the blue wavelength band (or light receiving area ratio) does not have to be 1:1:1. For example, The ratio of red to green to blue may be 1:2:1. Alternatively, the pixel ratio ( The light receiving area ratio may be red:green:blue=1:6:1.

[0435] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. For example, by providing two or more sub-pixels 212 that detect the same wavelength band, redundancy can be increased and imaging can be performed more efficiently. The reliability of the device 200 can be improved.

[0436] In addition, there are IR (Infrared) filters that absorb or reflect visible light and transmit infrared light. ) filter, an imaging device 200 that detects infrared light can be realized.

[0437] In addition, ND (Neutral Density) filters (neutral density filters) are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, The dynamic range of the device can be increased.

[0438] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described with reference to the cross-sectional view of the pixel 211. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 40A, a lens 255 and a filter 256 are formed in a pixel 211. 54 (filter 254R, filter 254G and filter 254B), and the pixel circuit A structure in which light 256 is incident on the photoelectric conversion element 220 through 230 or the like can be used.

[0439] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is connected to the wiring 257. Therefore, as shown in Figure 40(B), the light is blocked by a part of the A lens 255 and a filter 254 are arranged on the photoelectric conversion element 220 side. A structure in which the light 256 is efficiently received by the photoelectric conversion element 220 is preferable. By making the light incident on the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity can be provided. This can be done.

[0440] As the photoelectric conversion element 220 shown in FIG. 40, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0441] The photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be, for example, Selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy There is gold etc.

[0442] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, A photoelectric conversion element that has an optical absorption coefficient over a wide wavelength range, including X-rays and gamma rays. 220 can be achieved.

[0443] Here, one pixel 211 included in the imaging device 200 is added to a sub-pixel 212 shown in FIG. In addition, there may be a subpixel 212 having a first filter.

[0444] <Pixel configuration example 2> In the following, a transistor including silicon, a transistor including an oxide semiconductor, and An example of configuring a pixel using the above will be described.

[0445] 41(A) and 41(B) are cross-sectional views of elements constituting an imaging device. The imaging device shown in FIG. 1 has a silicon transistor 300 formed on a silicon substrate 300. 51, a transistor 3 using an oxide semiconductor stacked over a transistor 351 52 and a transistor 353, and a photodiode provided on the silicon substrate 300. Each transistor and photodiode 360 ​​is connected to a different plug 37. 0 and the wiring 371. Also, the anode of the photodiode 360 361 has an electrical connection with plug 370 via low resistance region 363 .

[0446] The imaging device includes a transistor 351 and a photodiode 352 disposed on a silicon substrate 300. A layer 310 having a diode 360 ​​and a layer 371 provided in contact with the layer 310. 320, a transistor 352 and a transistor 353 are provided in contact with the layer 320. a layer 330 having a wiring 372 and a wiring 373 provided in contact with the layer 330; It is equipped with 340.

[0447] In the example of the cross-sectional view of FIG. 41(A), the transistor 3 is disposed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is disposed on the opposite side to the surface on which the photodiode 51 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. Alternatively, the light receiving surface of the gate 360 ​​may be the same as the surface on which the transistor 351 is formed.

[0448] In addition, when a pixel is formed using a transistor, the layer 310 is Alternatively, the layer 310 may be omitted, and the pixel may be formed only by a transistor. stomach.

[0449] When a pixel is formed using a transistor, the layer 330 may be omitted. An example of a cross-sectional view in which 30 is omitted is shown in FIG.

[0450] The silicon substrate 300 may be an SOI substrate. Instead of germanium, silicon germanium, silicon carbide, gallium arsenide, and arsenide A substrate having aluminum gallium phosphide, indium phosphide, gallium nitride or an organic semiconductor is It can also be used.

[0451] Here, a layer 310 having a transistor 351 and a photodiode 360, A layer 330 having a transistor 352 and a transistor 353 is provided between the layer 330 and an insulator 380. However, the position of the insulator 380 is not limited.

[0452] The hydrogen in the insulator provided near the channel formation region of the transistor 351 is This has the effect of terminating dangling bonds and improving the reliability of the transistor 351. On the other hand, the water in the insulator provided near the transistor 352 and the transistor 353 is The element is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 352 and the transistor 353. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When the stator is laminated, an insulator 380 having a function of blocking hydrogen is provided between the stator and the stator. It is preferable to provide an insulator 380. By confining hydrogen below the insulator 380, The reliability of the capacitor 351 can be improved. Since hydrogen diffusion to layers above the body 380 can be suppressed, the transistor 352 and the transistor The reliability of the transistor 353 and the like can be improved.

[0453] For the insulator 380, see, for example, the description of the insulator 408.

[0454] In addition, in the cross-sectional view of FIG. 41(A), a photodiode 360 ​​is provided in the layer 310, The transistors in the layer 330 can be formed to overlap each other. In other words, the resolution of the imaging device can be increased.

[0455] Also, as shown in FIG. 42(A1) and FIG. 42(B1), a part or the whole of the imaging device 42(A1) shows the imaging device in the direction of the dashed line X1-X2 in the figure. FIG. 42(A2) shows a state where the lens is bent along the dashed line X1- in FIG. FIG. 42(A3) is a cross-sectional view of the portion indicated by X2. This is a cross-sectional view of the portion indicated by -Y2.

[0456] FIG. 42(B1) shows a case where the imaging device is bent in the direction of the dashed line X3-X4 in the same figure, and The figure shows a state where the wire is bent in the direction of the dashed line Y3-Y4 in the figure. FIG. 42(B3) is a cross-sectional view of a portion indicated by a dashed line X3-X4 in FIG. 43 is a cross-sectional view of a portion indicated by dashed line Y3-Y4 in FIG. 42(B1).

[0457] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it possible to facilitate the optical design of lenses and the like that are used in combination with an imaging device. For example, Since the number of lenses required for aberration correction can be reduced, it is possible to miniaturize electronic devices using imaging devices. It is possible to realize a smaller and lighter camera. It is also possible to improve the quality of the captured image. do.

[0458] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0459] (Embodiment 5) In this embodiment, a semiconductor device such as the above-described transistor or the above-described memory device is Explain about the CPU.

[0460] <cpu> FIG. 43 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. It is.

[0461] The CPU shown in FIG. 43 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 1199 and the ROM interface 1189 may be provided on a separate chip. The CPU shown in FIG. 43 is merely an example of a simplified configuration. For example, the CPU or arithmetic circuit shown in FIG. A configuration including a path is considered as one core, and multiple such cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is , for example 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0462] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0463] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0464] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0465] In the CPU shown in FIG. 43, a memory cell is provided in the register 1196. The above-mentioned transistors and memory devices can be used as memory cells of the memory cell 1196. Cut.

[0466] In the CPU shown in FIG. 43, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 6, data is held by a flip-flop or a capacitance element. Select whether to hold data by flip-flops. When selected, the power supply voltage is applied to the memory cells in the register 1196 . When data retention in the capacitive element is selected, data rewrite to the capacitive element is This allows the supply of power supply voltage to the memory cells in register 1196 to be stopped.

[0467] FIG. 44 is a circuit diagram of a storage element 1200 that can be used as a register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a A circuit 1202 that prevents stored data from volatilizing when cut off, a switch 1203, and a switch 1204 A logic element 1206, a capacitor 1207, and a circuit 1220 having a selection function are provided. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 210. The memory element 1200 may include a diode, a resistor, etc., as necessary. , and may further include other elements such as an inductor.

[0468] Here, the above-mentioned memory device can be used for the circuit 1202. When the supply of power supply voltage to GND is stopped, the gate of transistor 1209 in circuit 1202 is The input voltage is set to GND (0V) or a voltage that turns off the transistor 1209. For example, the gate of the transistor 1209 is grounded via a load such as a resistor. do.

[0469] The switch 1203 is a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 2 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected to each other by a control signal RD input to the gate of the transistor 1213. (i.e., the conductive or non-conductive state of transistor 1213) The first terminal of the switch 1204 is connected to the source of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether the first terminal and the second terminal are electrically connected or not (i.e., , the conductive or non-conductive state of transistor 1214) is selected.

[0470] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The other of the two is electrically connected to the gate of the transistor 1210. One of the source and drain of the transistor 1210 is connected to a low power supply voltage The other is electrically connected to a wiring (e.g., a GND line) that can supply a switch voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (the first terminal of the transistor 1214) is electrically connected to the The other of the source and drain is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) a first terminal of the switch 1204 (one of the source and drain of the transistor 1214) one of a pair of electrodes of a capacitor 1207, and an input terminal of a logic element 1206. , are electrically connected. Here, the connection point is designated as node M1. The other electrode of the pair may be configured to have a constant potential input thereto. For example, It can be configured so that the power supply potential (GND, etc.) or high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a power supply that can supply a low power potential. The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND A power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.) can be input to the capacitance element 12. The other of the pair of electrodes of 08 is a wiring that can supply a low power supply potential (for example, GN D line).

[0471] The capacitors 1207 and 1208 are parasitic capacitances of transistors and wirings, etc. It is also possible to omit it by making active use of the above.

[0472] A control signal WE is input to the gate of the transistor 1209. and the switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first and second terminals of one switch is selected. When the first and second terminals of the other switch are in a non-conductive state, the second and third terminals of the other switch are in a non-conductive state. It becomes a state of mind.

[0473] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 44, the signal output from the circuit 1201 corresponds to the In the example shown, the other of the source and drain of the switch 1203 is connected to the source of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value of the inverted signal is inverted by the logic element 1206 and is output via the circuit 1220. The signal is then input to the circuit 1201.

[0474] In FIG. 44, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the drain (the other drain) is passed through the logic element 1206 and the circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the circuit 1201. The signal output from the other terminal of the transistor 1213 (the other of the source and drain of the transistor 1213) is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverted value of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0475] In addition, in FIG. 44, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 11 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed in a silicon film or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include any other element other than the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may be a transistor that is connected to the gate of the transistor.

[0476] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0477] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0478] Further, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is The off-state current is significantly lower than that of a transistor in which the channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 12 Even when power supply voltage is not supplied to 00, the signal held in the capacitance element 1208 is retained for a long period of time. In this way, the memory element 1200 can maintain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to hold the data.

[0479] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operations, after the power supply voltage is resumed, the circuit 1201 This can shorten the time it takes to restore the original data.

[0480] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the signal is released, the signal held by the capacitive element 1208 is transferred to the transistor 1210 in the state (conducting state or non-conducting state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original The signal can be read out accurately.

[0481] Such a memory element 1200 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0482] Although the memory element 1200 has been described as being used as a CPU, the memory element 1200 may also be used as a DSP. (Digital Signal Processor), Custom LSI, PLD(P programmable logic device), RF (Radio It can also be applied to (frequency) devices.

[0483] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0484] (Embodiment 6) A display device according to one embodiment of the present invention will be described below with reference to FIGS. 45 and 46. do.

[0485] <Display device> Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the The following are examples of display devices: Display devices using EL elements (EL display devices) and display devices using liquid crystal elements (LCD This section explains the display device.

[0486] The display device described below is a panel in which a display element is sealed, and a display device in which a display element is sealed. This includes modules in which ICs including a controller are mounted.

[0487] Moreover, the display device described below refers to an image display device or a light source (including a lighting device). In addition, connectors, such as FPC, modules with TCP, and TCP with plugs A module or display element with a printed wiring board is mounted with an IC (integrated circuit) by the COG method. All directly mounted modules are also included in the display device.

[0488] FIG. 45 shows an example of an EL display device according to one embodiment of the present invention. 45(A) is a circuit diagram of a pixel of the EL display device, and FIG. 45(B) is a top view showing the entire EL display device. FIG. 45(C) is a cross section taken along a dashed line MN in FIG. 45(B). do.

[0489] FIG. 45(A) is an example of a circuit diagram of a pixel used in an EL display device.

[0490] In this specification, the terms "active elements (transistors, diodes, etc.)" and "passive elements" are used interchangeably. For all terminals (capacitive elements, resistive elements, etc.), the connection destination must be specified. Even if the invention is not a single-particular invention, a person skilled in the art may be able to construct one aspect of the invention. Even if the connection destination is not specified, one aspect of the invention is clear. When the content is described in this specification, etc., one aspect of the invention that does not specify a connection destination is the present invention. In some cases, it may be possible to determine that the information is written in the detailed instructions. If multiple locations are expected, there is no need to limit the connection of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitors, resistors, etc.) By specifying the connection destinations of only some of the terminals of a device (such as a semiconductor device), This may constitute an aspect of the invention.

[0491] In this specification, if at least the connection destination of a certain circuit is specified, the circuit is considered to be A person skilled in the art may be able to identify the invention. Or, a person skilled in the art may be able to identify the invention by a few words. In some cases, a person skilled in the art may be able to identify the invention by simply specifying the function. In other words, if a function is specified, one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in this specification, etc. Therefore, even if the function of a certain circuit is not specified, if the connection destination is specified, it can be regarded as an invention. The present invention is disclosed as an embodiment, and can be implemented as one embodiment of the present invention. For a certain circuit, even if the connection destination is not specified, specifying the function is considered as one aspect of the invention. and can be construed as one embodiment of the invention.

[0492] The EL display device shown in FIG. 45(A) includes a switch element 743, a transistor 741, and The pixel includes a capacitor 742 and a light-emitting element 719 .

[0493] Note that FIG. 45(A) is an example of a circuit configuration, so if a transistor is added, Conversely, at each node in FIG. It is also possible to avoid adding switches, passive elements, etc.

[0494] The gate of the transistor 741 is connected to one end of a switch element 743 and one end of a capacitance element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. The transistor is electrically connected to one electrode of the light-emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other end of the switch element 743 is connected to a signal line The other electrode of the light-emitting element 719 is electrically connected to the light-emitting element 744. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0495] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. In addition, the switching element 743 is a transistor manufactured through the same process as the transistor 741. The use of transistors can improve the productivity of EL displays. 41 and / or the switch element 743, for example, the above-mentioned transistor is applied. It is possible.

[0496] 45B is a top view of the EL display device. The EL display device includes a substrate 700 and a 750, a sealant 734, a driving circuit 735, a driving circuit 736, a pixel 737, and F The sealing material 734 covers the pixels 737, the driving circuit 735, and the driving circuit 736. The driving circuit 73 is disposed between the substrate 700 and the substrate 750 so as to surround the path 736. 5 and / or the driving circuit 736 may be disposed outside the sealing material 734 .

[0497] FIG. 45(C) is a cross section of an EL display device corresponding to a part of the dashed line MN in FIG. 45(B). FIG.

[0498] In FIG. 45C, a conductor 704 a on a substrate 700 and a conductor An insulator 712a on the insulator 704a, an insulator 712b on the insulator 712a, and an insulator 71 2b and overlapping with the conductor 704a, and a conductor 71 6a and conductor 716b, and on the semiconductor 706, on the conductor 716a and conductor 716b. Insulator 718a on top, insulator 718b on insulator 718a, and insulator 718b on insulator 718b. and a conductor 714a on the insulator 718c and overlapping the semiconductor 706. Note that the structure of the transistor 741 is just an example, and the structure shown in FIG. It is acceptable for the structure to be different from that shown in FIG.

[0499] Therefore, in the transistor 741 shown in FIG. The insulators 712a and 712b function as gate insulators. The conductor 716a functions as a source electrode, and the conductor 716b functions as a drain electrode. The insulators 718a, 718b, and 718c function as insulator electrodes. The conductor 714 functions as a gate insulator, and the conductor 714a functions as a gate electrode. Note that the electrical characteristics of the semiconductor 706 may vary when exposed to light. At least one of the conductor 704a, the conductor 716a, the conductor 716b, and the conductor 714a It is preferable that the film has a light-shielding property.

[0500] The interface between the insulator 718a and the insulator 718b is shown by a dashed line. For example, the insulators 718a and 718b may not have a clear field. Therefore, when the same type of insulator is used, it may be difficult to distinguish between the two depending on the observation method. .

[0501] In FIG. 45C, a conductor 704b and a conductor 704 b, an insulator 712a on the insulator 712a, and an insulator 712b on the insulator 712b. A conductor 716a overlapping the conductor 704b, an insulator 718a on the conductor 716a, and an insulating An insulator 718b on the edge 718a, an insulator 718c on the insulator 718b, and an insulator 71 8c and overlapping the conductor 716a, and In the overlapping region of the conductor 714b, a portion of the insulator 718a and the insulator 718b are removed. The structure shown is as follows:

[0502] In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode. 716a serves as the other electrode.

[0503] Therefore, the capacitor 742 can be formed using a film common to the transistor 741. In addition, it is preferable that the conductor 704a and the conductor 704b are made of the same type of conductor. In this case, the conductor 704a and the conductor 704b may be formed through the same process. In addition, the conductor 714a and the conductor 714b are preferably made of the same type of conductor. In this case, the conductor 714a and the conductor 714b can be formed through the same process. do.

[0504] The capacitance element 742 shown in FIG. 45C is a capacitance element having a large capacitance per occupied area. Therefore, the EL display device shown in FIG. 45(C) has high display quality. The capacitive element 742 shown in FIG. 1 is formed by thinning the overlapping area of ​​the conductor 716a and the conductor 714b. Therefore, the insulator 718a and the insulator 718b are partially removed. The capacitor according to this embodiment is not limited to this. A part of the insulator 718c is removed to thin the overlapping area of ​​the conductor 714b. It is acceptable for the

[0505] An insulator 720 is provided over the transistor 741 and the capacitor 742. The insulator 720 reaches the conductor 716a, which functions as the source electrode of the transistor 741. The insulator 720 may have an opening. A conductor 781 is disposed on the insulator 720. 81 may be electrically connected to transistor 741 through an opening in insulator 720 .

[0506] A partition 784 having an opening reaching the conductor 781 is disposed above the conductor 781 . A light-emitting layer 782 is disposed over the partition 784 so as to be in contact with the conductor 781 at an opening of the partition 784. A conductor 783 is disposed over the light-emitting layer 782. The overlapping region of the light-emitting element 719 and the conductor 783 forms the light-emitting element 719 .

[0507] So far, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described. Reveal.

[0508] 46(A) is a circuit diagram showing an example of the configuration of a pixel of a liquid crystal display device. The pixel includes a transistor 751, a capacitor 752, and an element ( Liquid crystal element) 753.

[0509] In the transistor 751, one of the source and drain is electrically connected to a signal line 755. , the gate is electrically connected to the scan line 754 .

[0510] In the capacitor 752, one electrode is connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential.

[0511] In the liquid crystal element 753, one electrode is connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential. The common potential given to the wiring to which the other electrode of the capacitor 752 is electrically connected is The potential applied to the other electrode of the liquid crystal element 753 may be different from the common potential applied to the other electrode of the liquid crystal element 753 .

[0512] The liquid crystal display device will be described assuming that the top view is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dashed line MN is shown in FIG. In the FPC 732, the FPC 732 is connected to the wiring 733a via the terminal 731. 33a is a conductor of the same type as the conductor or semiconductor that constitutes the transistor 751. Alternatively, a semiconductor may be used.

[0513] For the transistor 751, refer to the description of the transistor 741. For the capacitor 752, refer to the description of the capacitor 742. 5(C) shows the structure of the capacitor element 752 corresponding to the capacitor element 742, do not have.

[0514] Note that when an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current is extremely small. Therefore, the charge held in the capacitor 752 can be It is difficult to leak, and the voltage applied to the liquid crystal element 753 can be maintained for a long period of time. Therefore, when displaying a moving image or a still image with little movement, the transistor 751 is turned off. By this, power for the operation of the transistor 751 is not required, and the power consumption is small. In addition, the area occupied by the capacitor 752 can be reduced. Therefore, it is possible to provide a liquid crystal display device having a high aperture ratio or a high-definition liquid crystal display device. .

[0515] An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening that reaches the transistor 751. A conductor 791 is disposed. The conductor 791 is connected to the transistor through an opening in the insulator 721. The input terminal 751 is electrically connected to the input terminal 752.

[0516] An insulator 792 functioning as an alignment film is disposed over the conductor 791. A liquid crystal layer 793 is disposed on the liquid crystal layer 793. An insulating layer functioning as an alignment film is disposed on the liquid crystal layer 793. 794 is disposed on the insulator 794. A spacer 795 is disposed on the insulator 794. A conductor 796 is disposed on the substrate 75 and the insulator 794. 97 will be placed.

[0517] By using the above-mentioned structure, a display device having a capacitance element with a small occupancy area is provided. Alternatively, a display device with high display quality can be provided. It is possible to provide a thin display device.

[0518] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting A light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms, or A display element, a display device, a light-emitting element, or a light-emitting device can have various elements. For example, light emitting diodes (LEDs) that are white, red, green or blue ting Diode), transistor (transistor that emits light according to electric current), electronic Emission element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV ), plasma display panels (PDP), MEMS (Micro-Electro-Mechanical Systems) Display elements using the Digital Micromirror Device (DMD), DM S (Digital Micro Shutter), IMOD (Interference Modulation shutter type MEMS display element, optical interference type MEMS display element, Using electrowetting elements, piezoelectric ceramic displays, and carbon nanotubes In addition to these, the display element has at least one electric or magnetic The display medium has a contrast, brightness, reflectance, transmittance, etc. that change depending on the action of the light. Good too.

[0519] An example of a display device using an EL element is an EL display. An example of a display device using electrons is a field emission display (FED). or SED type flat panel display (SED: Surface-conduction Display using liquid crystal elements. An example of a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Spray, reflective LCD, direct-view LCD, projection LCD ) Display using electronic ink, electronic liquid powder, or electrophoretic elements An example of such a device is electronic paper. In order to realize a liquid crystal display, a part or all of the pixel electrodes are made to be reflective electrodes. For example, a part or the whole of the pixel electrode may be made of aluminum. In this case, the SRA may be provided under the reflective electrode. It is also possible to provide a memory circuit such as M. This further reduces power consumption. It is possible.

[0520] When using LEDs, graphene or graphene is placed under the LED electrodes or nitride semiconductor. Graphene and graphite can be arranged in layers to form a multilayer film. In this way, by providing graphene or graphite, it is possible to form a nitride layer on the graphene or graphite. This makes it easy to form a film of a semiconductor such as an n-type GaN semiconductor having a crystal structure. Furthermore, a p-type GaN semiconductor having crystals is placed on top of it to form an LED. In addition, it is possible to form a crystalline n-type GaN semiconductor with graphene or graphite. Alternatively, an AlN layer may be provided. The GaN semiconductor of the LED is formed by MOCVD. However, by providing graphene, the GaN semiconductor of the LED may be It is also possible to form the film by a sputtering method.

[0521] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0522] (Embodiment 7) In this embodiment, an electronic device or the like equipped with a semiconductor device according to one embodiment of the present invention will be described. Reveal.

[0523] <Electronic equipment> The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, An image playback device equipped with a DVD: Digital Versatile Disk c) a device having a display capable of reproducing a recording medium and displaying the image. In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras cameras, digital still cameras, goggle-type displays (head-mounted displays) Play), navigation systems, audio playback devices (car audio, digital audio copiers, fax machines, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. show.

[0524] FIG. 47A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 47(A) has two display units 903 and However, the number of display units that the portable game machine has is not limited to this. stomach.

[0525] FIG. 47B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit. The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 91 and the second display unit 912. At least one of the third and second display units 913 and 914 is provided with a function as a position input device. A display device may be used. The function as a position input device may be implemented by adding a touch to the display device. The function as a position input device can be added by providing a touch panel. Alternatively, a photoelectric conversion element, also called a photosensor, may be provided in the pixel portion of the display device. It is possible.

[0526] FIG. 47C shows a notebook personal computer, which includes a housing 921, a display unit 922, It has a keyboard 923, a pointing device 924, and the like.

[0527] FIG. 47(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 933. 33 etc.

[0528] FIG. 47E shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. The operation key 944, the lens 945, the connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0529] FIG. 47(F) shows an automobile, which includes a body 951, wheels 952, a dashboard 953, and a lighter. To954 etc.

[0530] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. EXAMPLES

[0531] In this example, the spin density in the oxide semiconductor film was evaluated by ESR.

[0532] A method for preparing the samples used in this example will be described.

[0533] First, a quartz substrate having a thickness of 0.5 mm was prepared as a substrate. Next, an oxide semiconductor film and Then, a 50 nm thick In-Ga-Zn oxide film was formed. Heat treatment was performed at 450°C for 1 hour. Next, heat treatment was performed at 450°C for 1 hour in an oxygen atmosphere. Next, a silicon oxynitride film was formed to a thickness of 10 nm on the oxide semiconductor film. Next, plasma treatment was performed. The plasma treatment was oxygen (O2) plasma treatment or Nitrous oxide (N2O) plasma treatment was performed for 90, 180 or 300 seconds.

[0534] In-Ga-Zn oxide has an atomic ratio of In:Ga:Zn=1:1:1. The film was formed by sputtering using an n-Ga-Zn oxide target. The gas used was a mixture of argon and oxygen such that the volume of oxygen was 33%. The pressure during deposition was 0.7 Pa measured using a Canon Anelva miniature gauge MG-2. The deposition power was adjusted to 0.5 kW using a DC power source. The substrate temperature was 300 The temperature was set to °C.

[0535] The silicon oxynitride film was formed by the PECVD method. The gas used was a mixture of 1 part nosilane and 800 parts nitrous oxide by volume. The pressure was adjusted to 200 Pa. The deposition power was a 60 MHz high-frequency power source. The power was set to 150 W. The substrate temperature was set to 350°C.

[0536] In addition, oxygen (O2) plasma treatment was performed using the PECVD method with an oxygen flow rate of 800 sccm. The source material was supplied into the reaction chamber of the PECVD device. The pressure during supply was adjusted to 200 Pa. The deposition power was 150 W using a 60 MHz high-frequency power source. The substrate temperature was 350 The temperature was set to °C.

[0537] Nitrous oxide (N2O) plasma treatment was performed using the PECVD method with a flow rate of 800 sc cm of nitrous oxide was supplied into the reaction chamber of the PECVD apparatus. The pressure during supply was 200 Pa. The deposition power was adjusted to 150 W using a 60 MHz high-frequency power source. The plate temperature was 350°C.

[0538] Next, the samples were evaluated by ESR. The sample was also evaluated by the magnetic field. The signal in the oxide semiconductor film where the g value is around 1.93 (hereinafter referred to as "Vo The spin density of the ZnO-induced signal in the insulating film was determined by the spin density of the ZnO-induced signal in the insulating film. The related spin density is shown in Figure 48. The ESR evaluation was performed using a quartz crystal manufactured by JEOL Ltd. The electron spin resonance spectrometer JES-FA300 was used.

[0539] As shown in Figure 48, the VoH in the oxide semiconductor film is detected as a spin density by performing plasma treatment. Lower limit (here 2.6×10 17 spins / cm 3 ) or less. It was also confirmed that the longer the plasma treatment, the more the spin density caused by VoH decreased. In addition, oxygen (O2) plasma treatment and nitrous oxide (N2O) plasma treatment were compared. However, oxygen (O2) plasma treatment is more preferable because it reduces the spin density caused by NOx. It was confirmed that:

[0540] In addition, among the above samples, oxygen (O2) plasma treatment was performed for 0 seconds (none), 90 seconds, or 1 The hydrogen concentration was evaluated for the samples that were heated for 80 seconds. The hydrogen concentration depth profile of the sample was measured using an MS analyzer and is shown in Figure 49. The condition where the plasma treatment was performed for 0 seconds is indicated by a solid line, and the other conditions are indicated by dashed lines.

[0541] As shown in FIG. 49, the hydrogen concentration in the oxide semiconductor film can be reduced by oxygen (O2) plasma treatment. In addition, it was confirmed that the VoH It was suggested that the spin density caused by the lattice constant can be reduced. EXAMPLES

[0542] In this example, a stacked film was formed on an oxide semiconductor film, and a plasma treatment was performed on the stacked film. The spin density in the nitride semiconductor film was evaluated.

[0543] A method for preparing the samples used in this example will be described.

[0544] First, a quartz substrate having a thickness of 0.5 mm was prepared as a substrate. Next, an oxide semiconductor film and Then, a 50 nm thick In-Ga-Zn oxide film was formed. Heat treatment was performed at 450°C for 1 hour. Next, heat treatment was performed at 450°C for 1 hour in an oxygen atmosphere. Heat treatment was performed. Next, a metal oxide film having a thickness of 5 nm was formed. Next, a silicon oxynitride film with a thickness of 10 nm was formed on the metal oxide film. O2) plasma treatment was performed.

[0545] The In-Ga-Zn oxide used in the oxide semiconductor film has an atomic ratio of In:Ga:Zn=1. Deposited by sputtering using an In-Ga-Zn oxide target with a ratio of 1:1. The deposition gas was a mixture of argon and oxygen with the volume of oxygen being 33%. The pressure during film formation was measured using a Canon Anelva miniature gauge MG-2F. The pressure was adjusted to 0.7 Pa. The film formation power was set to 0.5 kW using a DC power source. The substrate-target distance was 60 mm, and the substrate temperature was 300°C.

[0546] In addition, two types of conditions, Condition 1 and Condition 2, were used for the metal oxide film. The sample prepared under condition 1 is designated as sample A, and the sample prepared under condition 2 is designated as sample B.

[0547] Condition 1: In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2 The film was formed by sputtering using an In-Ga-Zn oxide target. The membrane gas was a mixture of argon and oxygen with the volumetric oxygen content being 33%. The pressure during film formation was 0.4, measured using a Canon Anelva BA gauge BRG-1B. The deposition power was adjusted to 0.5 kW using a DC power source. The target distance was 60 mm and the substrate temperature was 200°C.

[0548] In condition 2, gallium oxide was sputtered using a gallium oxide target. The deposition gas was argon and 100% oxygen by volume. The gas used was mixed with oxygen. The pressure during film formation was measured using a Canon Anelva miniature gauge M. The pressure was adjusted to 0.4 Pa using G-2L. The deposition power was set to 0. The power was 4 kW. The substrate-target distance was 130 mm, and the substrate temperature was 200°C.

[0549] The silicon oxynitride film was formed by the PECVD method. The gas used was a mixture of 1 part nosilane and 800 parts nitrous oxide by volume. The pressure was adjusted to 200 Pa. The deposition power was a 60 MHz high-frequency power source. The power was set to 150 W. The substrate temperature was set to 350°C.

[0550] In addition, oxygen (O2) plasma treatment was performed using the PECVD method with an oxygen flow rate of 800 sccm. The source material was supplied into the reaction chamber of the PECVD device. The pressure during supply was adjusted to 200 Pa. The deposition power was 150 W using a 60 MHz high-frequency power source. The substrate temperature was 350 The plasma treatment time for sample A was 0 seconds (none), 90 seconds, and 180 seconds. For sample B, the three conditions were 0 seconds (none), 90 seconds, or 180 seconds. The conditions were:

[0551] Next, the sample A was evaluated by ESR. The sample was In-Ga-Zn The oxide film surface was set perpendicular to the magnetic field. The g value in the oxide semiconductor film was around 1.93. The spin density of the defect level (VoH origin) related to the signal appearing in is shown in FIG. The ESR evaluation was performed using an electron spin resonance apparatus JES-FA300 manufactured by JEOL Ltd. there was.

[0552] As shown in FIG. 50, the spin density caused by VoH in the oxide semiconductor film is reduced by plasma treatment. By performing plasma treatment for 180 seconds or more, the V The spin density due to oH is at the detection limit (7.4 × 10 17 spins / cm 3 )below It was confirmed that this is the case.

[0553] In addition, oxygen (O2) plasma treatment was performed for 0 seconds (none), 90 seconds, or 180 seconds on sample A. The conditions for sample B were 0 seconds (none), 90 seconds, or 180 seconds. The hydrogen concentration was evaluated using a SIMS analyzer. The depth profile of hydrogen concentration in sample A was measured in Figure 51, and the depth profile of hydrogen concentration in sample B was measured in Figure 52. The profile is shown in Figure 52. The condition where the plasma treatment was performed for 0 seconds is shown by a solid line, and the others are shown by dashed lines.

[0554] As shown in FIG. 51, in sample A, the longer the oxygen (O2) plasma treatment time, the smaller the first It was confirmed that the hydrogen concentration in the oxide semiconductor film of Sample B was reduced. In the experiment, the first oxide semiconductor film was heated to 180 seconds for the longest plasma treatment time. This result suggests that oxygen (O2) plasma treatment after the deposition of the insulating film reduces the hydrogen concentration. It was confirmed that the hydrogen concentration in the oxide semiconductor film can be reduced by performing In addition, by reducing the hydrogen concentration in the oxide semiconductor film, the spin density caused by VoH can be reduced. It was suggested that it is possible to reduce

[0555] In addition, compared to the case where gallium oxide was used as the metal oxide, the In:Ga:Zn=1 In-Ga-Zn oxide formed using an In-Ga-Zn oxide target with a ratio of 1:1 This suggests that the oxide is more permeable to hydrogen.

[0556] In addition, in comparison with Example 1, the silicon oxynitride film 10n is formed on the first oxide semiconductor film. The second oxide semiconductor film is 5 nm thick on the first oxide semiconductor film. In addition, the hydrogen concentration is lower than that in the case where a 10 nm silicon oxynitride film is laminated. For this reason, the silicon oxynitride film is more likely to be reduced than the second oxide semiconductor film. The membrane may be more permeable to hydrogen. [Explanation of symbols]

[0557] 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 Pixel Circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 Silicon substrate 310 layers 320 layers 330 layers 340 layers 351 Transistor 352 Transistor 353 Transistor 360 Photodiode 361 Anode 363 Low resistance region 370 Plug 371 Wiring 372 Wiring 373 Wiring 380 Insulator 400 Semiconductor Substrates 402 Insulator 404 Conductors 406 Semiconductors 406a Semiconductors 406b Semiconductors 406c Semiconductors 408 Insulator 412 Insulators 413 Conductors 414 Conductors 416 Conductors 416a Conductor 416b Conductor 417 Conductors 418 Insulator 420 layers 421 Conductors 423a Low resistance area 423b Low resistance region 424 Conductors 426a Conductors 426b Conductors 427 Mask 436a Semiconductors 436b Semiconductors 442 Substrate 450 Semiconductor Substrate 452 Insulator Region 454 Conductors 460 areas 462 Insulator 464 Insulator 466 Insulators 467 Wiring layer 468 Insulator 469 Wiring layer 470 Insulator 472 Conductors 472a area 472b area 474 area 474a Conductors 474b Conductors 474c Electrical conductors 476 area 476a Conductors 476b Conductors 478a Conductors 478b Conductor 478c Conductor 480a Conductor 480b Conductor 480c conductor 490 Transistors 491 Transistor 492 Transistors 493 Insulators 495 Insulators 494 Insulators 496a Conductors 496b Conductors 496c Conductors 496d Conductors 498a Conductors 498b Conductor 498c Electrical conductor 498d Conductor 552 Insulator 700 Substrates 704a Conductor 704b Conductor 706 Semiconductors 712a Insulator 712b Insulator 714a Conductor 714b Conductor 716a Conductor 716b Conductor 718a Insulator 718b Insulator 718c Insulator 719 Light emitting element 720 Insulator 721 Insulators 731 Terminal 732 FPC 733a Wiring 734 Sealing material 735 Drive Circuit 736 Drive Circuit 737 pixels 741 Transistor 742 Capacitive element 743 Switching element 744 Signal Line 750 Board 751 Transistor 752 Capacitive element 753 Liquid crystal element 754 scan lines 755 Signal Line 781 Conductors 782 Light-emitting layer 783 Conductors 784 Bulkhead 791 Conductors 792 Insulators 793 Liquid crystal layer 794 Insulators 795 Spacer 796 Conductors 797 Circuit Board 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 5100 pellets 5100a Pellet 5100b Pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellet 5105a1 area 5105a2 Pellet 5105b Pellet 5105c Pellet 5105d Pellet 5105d1 area 5105e Pellet 5120 PCB 5130 Target 5161 area< / cpu>

Claims

1. a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; A capacitance element, a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitor element are electrically connected to each other, a first conductive layer having a function as one electrode of the capacitor; a second conductive layer having a region located above the first conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having the second channel formation region; a third conductive layer having a region overlapping with the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a first insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a second insulating layer having an area located above the first insulating layer and having at least a first opening and a second opening; a fourth conductive layer having a region located in the first opening of the second insulating layer; a fifth conductive layer having a region located in the second opening of the second insulating layer; a sixth conductive layer having a region located above the fourth conductive layer; the fourth conductive layer has a region in contact with an upper surface of the second conductive layer and a region in contact with a lower surface of the sixth conductive layer, the fifth conductive layer is electrically connected to one of the source region and the drain region of the first transistor and the other of the source region and the drain region of the second transistor; the second opening has a region overlapping with the oxide semiconductor layer, the sixth conductive layer has a region overlapping with the oxide semiconductor layer.

2. a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor; A capacitance element, a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitor element are electrically connected to each other, a first conductive layer having a function as one electrode of the capacitor; a second conductive layer having a region located above the first conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having the second channel formation region; a third conductive layer having a region overlapping with the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a first insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a second insulating layer having an area located above the first insulating layer and having at least a first opening and a second opening; a fourth conductive layer having a region located in the first opening of the second insulating layer; a fifth conductive layer having a region located in the second opening of the second insulating layer; a sixth conductive layer having a region located above the fourth conductive layer; the fourth conductive layer has a region in contact with an upper surface of the second conductive layer and a region in contact with a lower surface of the sixth conductive layer, the fifth conductive layer is electrically connected to one of the source region and the drain region of the first transistor and the other of the source region and the drain region of the second transistor; the second opening has a region overlapping with the oxide semiconductor layer, the sixth conductive layer has a region overlapping with the oxide semiconductor layer and a region overlapping with the first channel formation region.

Images