Semiconductor device

Abstract

To provide a semiconductor device which is configured using unipolar transistors, does not allow a steady current to flow, and can represent a high level or a low level using a high power supply potential and a low power supply potential.SOLUTION: A semiconductor device includes multiple unipolar transistors, a capacitive element, first and second input terminals, and an output terminal, and a signal whose logic is inverted from that of the signal input to the first input terminal is input to the second input terminal. This circuit configuration is called bootstrap, in which two unipolar transistors are connected in series between a high power supply potential and a low power supply potential, and a capacitance is provided between the output terminal and the gate of one of the transistors, and reliable bootstrap can be performed by generating a delay in the signal output from the gate of the transistor and the output terminal.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] One embodiment of the present invention relates to a logic circuit configured using unipolar transistors.

[0002] One embodiment of the present invention relates to a semiconductor device. In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, an electronic component in which a chip is housed in a package, and an electronic device including an integrated circuit are examples of a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] CMOS (Complementary Metal Oxide Semiconductor) circuits are widely used as circuits (also called digital circuits or logic circuits) that handle digital signals represented as high or low levels (which can be expressed as High or Low, H or L, 1 or 0, etc.).

[0005] In many cases, a logic circuit is supplied with a high power supply potential and a low power supply potential, and a high level is represented by the high power supply potential and a low level is represented by the low power supply potential. In addition, a CMOS circuit is composed of, for example, n-channel transistors and p-channel transistors formed on a single crystal silicon substrate.

[0006] A CMOS circuit has a circuit configuration in which an n-channel transistor and a p-channel transistor are connected in series between a high power supply potential and a low power supply potential, and when the n-channel transistor is in a conductive state, the p-channel transistor is in a non-conductive state, and when the n-channel transistor is in a non-conductive state, the p-channel transistor is in a conductive state. In other words, after a high level or a low level is determined, a through current does not flow from the high power supply potential to the low power supply potential (excluding an off current of a transistor, etc.).

[0007] Here, in cases where it is not possible to manufacture both n-channel transistors and p-channel transistors, or in cases where it is desired to reduce the transistor manufacturing process in order to reduce costs, etc., a logic circuit may be constructed using only n-channel transistors or only p-channel transistors (also referred to as unipolar transistors or single-channel transistors).

[0008] For example, Patent Document 1 and Patent Document 2 disclose examples of semiconductor devices and display device driver circuits configured using unipolar transistors. In Patent Document 1 and Patent Document 2, two unipolar transistors are connected in series between a high power supply potential and a low power supply potential, and a first signal and a second signal obtained by inverting the logic (high level or low level) of the first signal are input to the gates of the transistors, respectively, resulting in a circuit configuration in which no through current flows from the high power supply potential to the low power supply potential. The method of using the first signal and the second signal obtained by inverting the logic of the first signal is sometimes called a dual rail.

[0009] In addition, in Patent Document 1 and Patent Document 2, the problem that either the high level or the low level of the output signal does not reach the high power supply potential or the low power supply potential is solved by providing a capacitance between the output terminal and the gate of one of the transistors. The method of providing a capacitance between the output terminal and the gate of one of the transistors is sometimes called bootstrap.

[0010] Meanwhile, transistors having a metal oxide in a channel formation region (also referred to as oxide semiconductor transistors or OS transistors) have been attracting attention in recent years. As OS transistors, n-channel transistors have been put to practical use and have characteristics such as a very small off-current, the ability to apply a high voltage between the source and drain (also referred to as having high withstand voltage), and the ability to be formed as a stacked thin film transistor. In addition, OS transistors have characteristics such as their off-current is unlikely to increase even in a high-temperature environment and their ratio of on-current to off-current is large even in a high-temperature environment, and semiconductor devices formed using OS transistors have high reliability.

[0011] For example, Patent Document 3 discloses a semiconductor device having a plurality of memory cells using OS transistors on a semiconductor substrate on which peripheral circuits such as a drive circuit and a control circuit are formed, and an example in which OS transistors are used in memory cells of a DRAM (Dynamic Random Access Memory). For example, peripheral circuits can be configured using Si transistors formed on a single crystal silicon substrate, and memory cells using OS transistors can be stacked above the peripheral circuits. By providing memory cells using OS transistors on a single crystal silicon substrate on which peripheral circuits are formed, the chip area can be reduced. In addition, since the off-current of OS transistors is very small, stored data can be retained for a long time. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Japanese Patent Application Publication No. 9-246936 [Patent Document 2] JP 2002-328643 A [Patent Document 3] JP 2012-256820 A Summary of the Invention [Problem to be solved by the invention]

[0013] Patent Documents 1 and 2 disclose a circuit that employs dual rails and bootstrap, and is a logic circuit constructed using unipolar transistors, but like a CMOS circuit, has the characteristic that no through current flows from a high power supply potential to a low power supply potential (also called no steady-state current flows) once a high or low level is determined, and that can represent a high level using a high power supply potential and a low level using a low power supply potential.

[0014] Here, in the bootstrap, it is preferable that the voltage Vgs of the gate of the transistor with respect to the source of the transistor is sufficiently secured in a transistor having a capacitance between the source and the gate. If the voltage Vgs of the gate of the transistor with respect to the source of the transistor is not sufficiently secured, there are cases where the high level does not rise to the high power supply potential or the low level does not fall to the low power supply potential.

[0015] In Patent Documents 1 and 2, the source of the transistor is electrically connected to the output terminal, and a capacitance is provided between the source and gate of the transistor. For example, when a capacitive load is connected to the output terminal, the potential of the output terminal may not rise to the high power supply potential when at a high level, or may not fall to the low power supply potential when at a low level.

[0016] An object of one embodiment of the present invention is to provide a logic circuit including unipolar transistors, in which no steady current flows and the potential of the output terminal rises to a high power supply potential when the output is at a high level and the potential of the output terminal falls to a low power supply potential when the output is at a low level.Another object of one embodiment of the present invention is to provide a semiconductor device including unipolar transistors, in which no steady current flows and the potential of the output terminal rises to a high power supply potential when the output is at a high level and the potential of the output terminal falls to a low power supply potential when the output is at a low level.

[0017] It is not necessary for one embodiment of the present invention to solve all of the above problems, but it is sufficient if it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description of the specification, claims, drawings, etc., and it is possible to extract other problems from the description of the specification, claims, drawings, etc. [Means for solving the problem]

[0018] One embodiment of the present invention is a semiconductor device including first to eighth transistors, first and second capacitance elements, first and second wirings, first and second input terminals, and first and second output terminals. One of the source or drain of the first transistor is electrically connected to the first wiring, the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one terminal of the first capacitance element, and the first output terminal, and the other of the source or drain of the second transistor is electrically connected to the second wiring. A gate of the first transistor is electrically connected to a gate of a fourth transistor, one of the source or drain of the eighth transistor, one of the source or drain of the seventh transistor, one terminal of the second capacitance element, and a gate of a sixth transistor, and a gate of the second transistor is electrically connected to the other terminal of the first capacitance element, one of the source or drain of the fourth transistor, one of the source or drain of the third transistor, the gate of the eighth transistor, and the gate of the fifth transistor. The other of the source or drain of the fourth transistor is electrically connected to the first wiring, the other of the source or drain of the third transistor is electrically connected to the second wiring, the gate of the third transistor is electrically connected to the second input terminal, the other of the source or drain of the eighth transistor is electrically connected to the first wiring, the other of the source or drain of the seventh transistor is electrically connected to the second wiring, and the gate of the seventh transistor is electrically connected to the first input terminal. One of the source or drain of the fifth transistor is electrically connected to the first wiring, the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor, the other terminal of the second capacitance element, and the second output terminal, and the other of the source or drain of the sixth transistor is electrically connected to the second wiring.

[0019] In the above embodiment, the first to eighth transistors are n-channel transistors.

[0020] In the above embodiment, the first to eighth transistors each include a metal oxide in a channel formation region.

[0021] Another embodiment of the present invention is a semiconductor device including first to sixth transistors, first and second capacitance elements, first and second wirings, first and second input terminals, and first and second output terminals, wherein one of a source or a drain of the first transistor is electrically connected to a first wiring, the other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, a gate of the fourth transistor, one terminal of the first capacitance element, and the first output terminal, and the other of the source or the drain of the second transistor is electrically connected to the second wiring. The gate of the first transistor is electrically connected to one of the source or drain of the fourth transistor, one of the source or drain of the fifth transistor, one terminal of the second capacitance element, and the second output terminal, the gate of the second transistor is electrically connected to one of the source or drain of the third transistor and the other terminal of the first capacitance element, the gate of the third transistor is electrically connected to the second wiring, and the other of the source or drain of the third transistor is electrically connected to the second input terminal. The other of the source or drain of the fourth transistor is electrically connected to the first wiring, the other of the source or drain of the fifth transistor is electrically connected to the second wiring, the gate of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor and the other terminal of the second capacitance element, the gate of the sixth transistor is electrically connected to the second wiring, and the other of the source or drain of the sixth transistor is electrically connected to the first input terminal.

[0022] In the above embodiment, the first to sixth transistors are n-channel transistors.

[0023] In the above embodiment, the first to sixth transistors each include a metal oxide in a channel formation region.

[0024] One embodiment of the present invention is a semiconductor device including first to tenth transistors, first and second capacitance elements, first and second wirings, first to fourth input terminals, and first and second output terminals, wherein one of a source or a drain of the first transistor is electrically connected to a first wiring, the other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of a second transistor, one terminal of the first capacitance element, and the first output terminal, and the other of the source or the drain of the second transistor is electrically connected to the second wiring. The gate of the first transistor is electrically connected to the gate of the fifth transistor, one of the source or drain of the tenth transistor, one of the source or drain of the ninth transistor, one terminal of the second capacitance element, and the gate of the seventh transistor, the gate of the second transistor is electrically connected to the other terminal of the first capacitance element, one of the source or drain of the fourth transistor, one of the source or drain of the third transistor, one of the source or drain of the fifth transistor, the gate of the tenth transistor, and the gate of the sixth transistor. The other of the source or drain of the fifth transistor is electrically connected to the first wiring, the other of the source or drain of the fourth transistor is electrically connected to the second wiring, the other of the source or drain of the third transistor is electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the fourth input terminal, and the gate of the third transistor is electrically connected to the second input terminal. The other of the source or drain of the tenth transistor is electrically connected to a first wiring, the other of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the eighth transistor, the other of the source or drain of the eighth transistor is electrically connected to a second wiring, the gate of the ninth transistor is electrically connected to the third input terminal, and the gate of the eighth transistor is electrically connected to the first input terminal.One of the source or drain of the sixth transistor is electrically connected to the first wiring, the other of the source or drain of the sixth transistor is electrically connected to one of the source or drain of the seventh transistor, the other terminal of the second capacitive element, and the second output terminal, and the other of the source or drain of the seventh transistor is electrically connected to the second wiring.

[0025] In the above embodiment, the first to tenth transistors are n-channel transistors.

[0026] In the above embodiment, the first to tenth transistors each include a metal oxide in a channel formation region.

[0027] One embodiment of the present invention is a semiconductor device including first to tenth transistors, first and second capacitance elements, first and second wirings, first to fourth input terminals, and first and second output terminals, wherein one of a source or a drain of the first transistor is electrically connected to a first wiring, the other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of a second transistor, one terminal of the first capacitance element, and the first output terminal, and the other of the source or the drain of the second transistor is electrically connected to the second wiring. The gate of the first transistor is electrically connected to the gate of the fifth transistor, one of the source or drain of the tenth transistor, one of the source or drain of the eighth transistor, one of the source or drain of the ninth transistor, one terminal of the second capacitance element, and the gate of the seventh transistor, the gate of the second transistor is electrically connected to the other terminal of the first capacitance element, one of the source or drain of the fourth transistor, one of the source or drain of the fifth transistor, the gate of the tenth transistor, and the gate of the sixth transistor. The other of the source or drain of the fifth transistor is electrically connected to the first wiring, the other of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the third transistor, the other of the source or drain of the third transistor is electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the fourth input terminal, and the gate of the third transistor is electrically connected to the second input terminal. The other of the source or drain of the tenth transistor is electrically connected to a first wiring, the other of the source or drain of the eighth transistor is electrically connected to a second wiring, the other of the source or drain of the ninth transistor is electrically connected to the second wiring, the gate of the eighth transistor is electrically connected to the first input terminal, and the gate of the ninth transistor is electrically connected to the third input terminal.One of the source or drain of the sixth transistor is electrically connected to the first wiring, the other of the source or drain of the sixth transistor is electrically connected to one of the source or drain of the seventh transistor, the other terminal of the second capacitive element, and the second output terminal, and the other of the source or drain of the seventh transistor is electrically connected to the second wiring.

[0028] In the above embodiment, the first to tenth transistors are n-channel transistors.

[0029] In the above embodiment, the first to tenth transistors each include a metal oxide in a channel formation region.

[0030] One embodiment of the present invention is a semiconductor device including first to eighth transistors, first and second capacitance elements, first and second wirings, first and second input terminals, and first and second output terminals. One of the source or drain of the first transistor is electrically connected to the first wiring, the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one terminal of the first capacitance element, and the first output terminal, and the other of the source or drain of the second transistor is electrically connected to the second wiring. A gate of the first transistor is electrically connected to a gate of a fourth transistor, one of the source or drain of the eighth transistor, one of the source or drain of the seventh transistor, one terminal of the second capacitance element, and a gate of a sixth transistor, and a gate of the second transistor is electrically connected to the other terminal of the first capacitance element, one of the source or drain of the fourth transistor, one of the source or drain of the third transistor, the gate of the eighth transistor, and the gate of the fifth transistor. The other of the source or drain of the fourth transistor is electrically connected to the first wiring, the other of the source or drain of the third transistor is electrically connected to the second wiring, the gate of the third transistor is electrically connected to the second input terminal, the other of the source or drain of the eighth transistor is electrically connected to the first wiring, the other of the source or drain of the seventh transistor is electrically connected to the second wiring, and the gate of the seventh transistor is electrically connected to the first input terminal. One of the source or drain of the fifth transistor is electrically connected to the first wiring, the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor, the other terminal of the second capacitance element, and the second output terminal, and the other of the source or drain of the sixth transistor is electrically connected to the second wiring. A first potential is supplied to the first wiring, a second potential is supplied to the second wiring, the second potential is higher than the first potential, a first signal is input to the first input terminal, and a second signal is input to the second input terminal, the second signal being a signal with the logic of the first signal inverted.

[0031] In the above embodiment, the first to eighth transistors are n-channel transistors.

[0032] In the above embodiment, the first to eighth transistors each include a metal oxide in a channel formation region.

[0033] Another embodiment of the present invention is a semiconductor device including first to sixth transistors, first and second capacitance elements, first and second wirings, first and second input terminals, and first and second output terminals, wherein one of a source or a drain of the first transistor is electrically connected to a first wiring, the other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, a gate of the fourth transistor, one terminal of the first capacitance element, and the first output terminal, and the other of the source or the drain of the second transistor is electrically connected to the second wiring. The gate of the first transistor is electrically connected to one of the source or drain of the fourth transistor, one of the source or drain of the fifth transistor, one terminal of the second capacitance element, and the second output terminal, the gate of the second transistor is electrically connected to one of the source or drain of the third transistor and the other terminal of the first capacitance element, the gate of the third transistor is electrically connected to the second wiring, and the other of the source or drain of the third transistor is electrically connected to the second input terminal. The other of the source or drain of the fourth transistor is electrically connected to the first wiring, the other of the source or drain of the fifth transistor is electrically connected to the second wiring, the gate of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor and the other terminal of the second capacitance element, the gate of the sixth transistor is electrically connected to the second wiring, and the other of the source or drain of the sixth transistor is electrically connected to the first input terminal. A first potential is supplied to the first wiring, a second potential is supplied to the second wiring, the second potential is higher than the first potential, a first signal is input to the first input terminal, and a second signal is input to the second input terminal, the second signal being a signal with the logic of the first signal inverted.

[0034] In the above embodiment, the first to sixth transistors are n-channel transistors.

[0035] In the above embodiment, the first to sixth transistors each include a metal oxide in a channel formation region.

[0036] One embodiment of the present invention is a semiconductor device including first to tenth transistors, first and second capacitance elements, first and second wirings, first to fourth input terminals, and first and second output terminals, wherein one of a source or a drain of the first transistor is electrically connected to a first wiring, the other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of a second transistor, one terminal of the first capacitance element, and the first output terminal, and the other of the source or the drain of the second transistor is electrically connected to the second wiring. The gate of the first transistor is electrically connected to the gate of the fifth transistor, one of the source or drain of the tenth transistor, one of the source or drain of the ninth transistor, one terminal of the second capacitance element, and the gate of the seventh transistor, the gate of the second transistor is electrically connected to the other terminal of the first capacitance element, one of the source or drain of the fourth transistor, one of the source or drain of the third transistor, one of the source or drain of the fifth transistor, the gate of the tenth transistor, and the gate of the sixth transistor. The other of the source or drain of the fifth transistor is electrically connected to the first wiring, the other of the source or drain of the fourth transistor is electrically connected to the second wiring, the other of the source or drain of the third transistor is electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the fourth input terminal, and the gate of the third transistor is electrically connected to the second input terminal. The other of the source or drain of the tenth transistor is electrically connected to a first wiring, the other of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the eighth transistor, the other of the source or drain of the eighth transistor is electrically connected to a second wiring, the gate of the ninth transistor is electrically connected to the third input terminal, and the gate of the eighth transistor is electrically connected to the first input terminal.One of the source or drain of the sixth transistor is electrically connected to the first wiring, the other of the source or drain of the sixth transistor is electrically connected to one of the source or drain of the seventh transistor, the other terminal of the second capacitance element, and the second output terminal, and the other of the source or drain of the seventh transistor is electrically connected to the second wiring. A first potential is supplied to the first wiring, a second potential is supplied to the second wiring, the second potential is higher than the first potential, a first signal is input to the first input terminal, a second signal is input to the second input terminal, a third signal is input to the third input terminal, and a fourth signal is input to the fourth input terminal, the second signal is a signal obtained by inverting the logic of the first signal, and the fourth signal is a signal obtained by inverting the logic of the third signal.

[0037] In the above embodiment, the first to tenth transistors are n-channel transistors.

[0038] In the above embodiment, the first to tenth transistors each include a metal oxide in a channel formation region.

[0039] One embodiment of the present invention is a semiconductor device including first to tenth transistors, first and second capacitance elements, first and second wirings, first to fourth input terminals, and first and second output terminals, wherein one of a source or a drain of the first transistor is electrically connected to a first wiring, the other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of a second transistor, one terminal of the first capacitance element, and the first output terminal, and the other of the source or the drain of the second transistor is electrically connected to the second wiring. The gate of the first transistor is electrically connected to the gate of the fifth transistor, one of the source or drain of the tenth transistor, one of the source or drain of the eighth transistor, one of the source or drain of the ninth transistor, one terminal of the second capacitance element, and the gate of the seventh transistor, the gate of the second transistor is electrically connected to the other terminal of the first capacitance element, one of the source or drain of the fourth transistor, one of the source or drain of the fifth transistor, the gate of the tenth transistor, and the gate of the sixth transistor. The other of the source or drain of the fifth transistor is electrically connected to the first wiring, the other of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the third transistor, the other of the source or drain of the third transistor is electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the fourth input terminal, and the gate of the third transistor is electrically connected to the second input terminal. The other of the source or drain of the tenth transistor is electrically connected to a first wiring, the other of the source or drain of the eighth transistor is electrically connected to a second wiring, the other of the source or drain of the ninth transistor is electrically connected to the second wiring, the gate of the eighth transistor is electrically connected to the first input terminal, and the gate of the ninth transistor is electrically connected to the third input terminal.One of the source or drain of the sixth transistor is electrically connected to the first wiring, the other of the source or drain of the sixth transistor is electrically connected to one of the source or drain of the seventh transistor, the other terminal of the second capacitance element, and the second output terminal, and the other of the source or drain of the seventh transistor is electrically connected to the second wiring. A first potential is supplied to the first wiring, a second potential is supplied to the second wiring, the second potential is higher than the first potential, a first signal is input to the first input terminal, a second signal is input to the second input terminal, a third signal is input to the third input terminal, and a fourth signal is input to the fourth input terminal, the second signal is a signal obtained by inverting the logic of the first signal, and the fourth signal is a signal obtained by inverting the logic of the third signal.

[0040] In the above embodiment, the first to tenth transistors are n-channel transistors.

[0041] In the above embodiment, the first to tenth transistors each include a metal oxide in a channel formation region. Effect of the Invention

[0042] According to one embodiment of the present invention, it is possible to provide a logic circuit including unipolar transistors, in which no steady-state current flows, and when the output is at a high level, the potential of the output terminal rises to a high power supply potential, and when the output is at a low level, the potential of the output terminal falls to a low power supply potential.Alternatively, according to one embodiment of the present invention, it is possible to provide a semiconductor device including unipolar transistors, in which no steady-state current flows, and when the output is at a high level, the potential of the output terminal rises to a high power supply potential, and when the output is at a low level, the potential of the output terminal falls to a low power supply potential.

[0043] Note that the description of these effects does not preclude the existence of other effects. Also, one embodiment of the present invention does not necessarily have to have all of these effects. Effects other than these will become apparent from the description in the specification, claims, drawings, etc., and it is possible to extract effects other than these from the description in the specification, claims, drawings, etc. [Brief description of the drawings]

[0044] [Figure 1] FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device. [Diagram 2] FIG. 2 is a timing chart. [Diagram 3] FIG. 3 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 4] FIG. 4 is a timing chart. [Diagram 5] 5A and 5B are diagrams showing circuit diagram symbols of transistors, and Fig. 5C and Fig. 5D are circuit diagrams showing configuration examples of a semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a timing chart. [Figure 9] FIG. 9 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 10] 10A, 10B, and 10C are cross-sectional views showing examples of the structure of a transistor. [Figure 11] 11A is a top view illustrating an example of a transistor structure, and FIG 11B and FIG 11C are cross-sectional views illustrating an example of a transistor structure. [Figure 12] 12A is a top view illustrating an example of a transistor structure, and FIGS. 12B and 12C are cross-sectional views illustrating an example of a transistor structure. [Figure 13] 13A is a top view illustrating an example of a transistor structure, and FIGS. 13B and 13C are cross-sectional views illustrating an example of a transistor structure. [Figure 14] 14A is a top view illustrating an example of a transistor structure, and FIGS. 14B and 14C are cross-sectional views illustrating an example of a transistor structure. [Figure 15] 15A is a top view illustrating an example of a transistor structure, and FIGS. 15B and 15C are cross-sectional views illustrating an example of a transistor structure. [Figure 16] 16A is a top view illustrating an example of a transistor structure, and FIGS. 16B and 16C are cross-sectional views illustrating an example of a transistor structure. [Figure 17] 17A and 17B are cross-sectional views showing examples of the structure of a transistor. [Figure 18] FIG. 18 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 19] 19A and 19B are cross-sectional views showing examples of the structure of a transistor. [Figure 20] Fig. 20A is a diagram explaining the classification of IGZO crystal structures, Fig. 20B is a diagram explaining the XRD spectrum of quartz glass, Fig. 20C is a diagram explaining the XRD spectrum of crystalline IGZO, and Fig. 20D is a diagram explaining the ultrafine electron beam diffraction pattern of crystalline IGZO. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different forms, and that the forms and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0046] In addition, the following embodiments may be combined as appropriate. In addition, when one embodiment includes multiple configuration examples, the configuration examples may be combined as appropriate.

[0047] In addition, in the drawings, etc., the size, layer thickness, area, etc. may be exaggerated for clarity. Therefore, the scale is not necessarily limited. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings.

[0048] In addition, in the drawings, the same symbols may be used for the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time, and repeated explanations may be omitted.

[0049] In addition, in this specification and the like, the term "film" and the term "layer" can be interchanged. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer."

[0050] In addition, in this specification and the like, terms indicating an arrangement such as "above" or "below" do not limit the positional relationship of components to "directly above" or "directly below." For example, the expression "a gate electrode on a gate insulating layer" does not exclude other components between the gate insulating layer and the gate electrode.

[0051] In addition, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and do not limit the numbers.

[0052] In addition, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying reference numeral such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL is described as wiring GL[2].

[0053] In addition, in this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transmission and reception of electrical signals between the connection objects. For example, "something having some electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitive elements, and other elements having various functions. Even when it is expressed as "electrically connected", there may be cases where there is no physical connection in the actual circuit and only wiring is extended.

[0054] In addition, in this specification and the like, the terms "electrode" and "wiring" do not limit the functionality of these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa.

[0055] In addition, in this specification, a "terminal" in an electric circuit refers to a portion where a current or potential is input (or output) or a signal is received (or transmitted). Therefore, a part of a wiring or an electrode may function as a terminal.

[0056] Generally, a "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., a "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., a "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator.

[0057] In this specification and the like, the term "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, the ground potential). Therefore, the terms "voltage" and "potential difference" can be used interchangeably.

[0058] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel-forming region is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel-forming region. In this specification, a channel-forming region refers to a region through which a current mainly flows.

[0059] In addition, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain may be used interchangeably in this specification and the like.

[0060] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage Vgs of the gate relative to the source is lower than the threshold voltage Vth in an n-channel transistor, and a state in which the voltage Vgs of the gate relative to the source is higher than the threshold voltage Vth in a p-channel transistor. In other words, the off-state current of an n-channel transistor may be referred to as the drain current when the voltage Vgs of the gate relative to the source is lower than the threshold voltage Vth.

[0061] In the above description of off-state current, the drain may be read as the source. In other words, the off-state current may refer to the source current when a transistor is in an off state. The off-state current may also be referred to as leakage current, which has the same meaning as the off-state current. In this specification and the like, the off-state current may refer to a current that flows between the source and drain when a transistor is in an off state.

[0062] In this specification and the like, the on-state current may refer to a current that flows between a source and a drain when a transistor is in an on state (also referred to as a conductive state).

[0063] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like.

[0064] For example, when a metal oxide is used in a channel formation region of a transistor, the metal oxide may be called an oxide semiconductor. In other words, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be called a metal oxide semiconductor. In other words, a transistor having a metal oxide in a channel formation region can be called an "oxide semiconductor transistor" or an "OS transistor". Similarly, the above-mentioned "transistor using an oxide semiconductor" is also a transistor having a metal oxide in a channel formation region.

[0065] In this specification and the like, a metal oxide having nitrogen may also be called a metal oxide. A metal oxide having nitrogen may also be called a metal oxynitride. Details of metal oxides will be described later.

[0066] (Embodiment 1) In this embodiment, a configuration example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention is a logic circuit including unipolar transistors, in which a high level is represented by a high power supply potential and a low level is represented by a low power supply potential.

[0067] In addition, although an example of a semiconductor device using an n-channel transistor is shown in the specification, a p-channel transistor can also be used. A change from an n-channel transistor to a p-channel transistor can be easily understood by those skilled in the art, and therefore a description thereof will be omitted.

[0068] <Configuration Example 1 of Semiconductor Device> 1 is a circuit diagram showing a configuration example of a semiconductor device 10. The semiconductor device 10 is a semiconductor device according to one embodiment of the present invention and includes transistors 11 to 18 and capacitors C11 and C12. The transistors 11 to 18 are n-channel transistors.

[0069] The semiconductor device 10 has a wiring VSS_IN to which a low power supply potential VSS is supplied, a wiring VDD_IN to which a high power supply potential VDD is supplied, an input terminal SI_IN to which a signal SI is input, an input terminal SIB_IN to which a signal SIB is input, an output terminal SO_OUT to which a signal SO is output, and an output terminal SOB_OUT to which a signal SOB is output.

[0070] Here, the high power supply potential VDD is a potential higher than the low power supply potential VSS, and the low power supply potential VSS may be a reference potential in the semiconductor device 10. Moreover, the signals SI and SIB are digital signals, and the potential representing the high level of the signals SI and SIB can be the high power supply potential VDD, and the potential representing the low level can be the low power supply potential VSS. Moreover, the signal SIB is a signal obtained by inverting the logic of the signal SI.

[0071] In the semiconductor device 10, one of the source and drain of the transistor 11 is electrically connected to the wiring VSS_IN, the other of the source and drain of the transistor 11 is electrically connected to one of the source and drain of the transistor 12, one terminal of the capacitor C11, and the output terminal SO_OUT, and the other of the source and drain of the transistor 12 is electrically connected to the wiring VDD_IN.

[0072] The gate of the transistor 11 is electrically connected to the gate of the transistor 14, one of the source or drain of the transistor 18, one of the source or drain of the transistor 17, one terminal of the capacitor C12, and the gate of the transistor 16. The gate of the transistor 12 is electrically connected to the other terminal of the capacitor C11, one of the source or drain of the transistor 14, one of the source or drain of the transistor 13, the gate of the transistor 18, and the gate of the transistor 15.

[0073] The other of the source and the drain of the transistor 14 is electrically connected to the wiring VSS_IN, the other of the source and the drain of the transistor 13 is electrically connected to the wiring VDD_IN, and the gate of the transistor 13 is electrically connected to the input terminal SIB_IN. The other of the source and the drain of the transistor 18 is electrically connected to the wiring VSS_IN, the other of the source and the drain of the transistor 17 is electrically connected to the wiring VDD_IN, and the gate of the transistor 17 is electrically connected to the input terminal SI_IN.

[0074] One of the source or drain of transistor 15 is electrically connected to the wiring VSS_IN, the other of the source or drain of transistor 15 is electrically connected to one of the source or drain of transistor 16, the other terminal of the capacitor C12, and the output terminal SOB_OUT, and the other of the source or drain of transistor 16 is electrically connected to the wiring VDD_IN.

[0075] Here, a connection portion between the gate of transistor 11, the gate of transistor 14, one of the source or drain of transistor 18, one of the source or drain of transistor 17, one terminal of the capacitor C12, and the gate of transistor 16 is referred to as a node N12. A connection portion between the gate of transistor 12, the other terminal of the capacitor C11, one of the source or drain of transistor 14, one of the source or drain of transistor 13, the gate of transistor 18, and the gate of transistor 15 is referred to as a node N11.

[0076] <Operation Example 1 of Semiconductor Device> 2 is a timing chart showing an operation example of the semiconductor device 10. In FIG. 2, the potentials of the signal SI, the signal SIB, the node N11, the node N12, the signal SO, and the signal SOB are shown for periods D11 to D14. Note that the threshold voltages of the transistors 11 to 18 are set to a threshold voltage Vth.

[0077] Period D11 is a period during which signal SI is at a high level and signal SIB is at a low level. Note that, for period D11, a static state is considered as an initial state. Since signal SI is at a high level, transistor 17 is in a conductive state and node N12 is at a high level. However, the potential of node N12 during this period is lower than the high power supply potential VDD, and is approximately a value obtained by subtracting a threshold voltage Vth from the high power supply potential VDD. Furthermore, since signal SIB is at a low level, transistor 13 is in a non-conductive state.

[0078] Since the node N12 is at a high level, the transistors 14, 11, and 16 are in a conductive state, the node N11 is at a low level, and the transistors 18, 15, and 12 are in a non-conductive state.

[0079] The signal SO is at a low level because the transistor 12 is off and the transistor 11 is on. The signal SOB is at a high level because the transistor 16 is on and the transistor 15 is off. However, the potential of the signal SOB during this period is lower than the high power supply potential VDD, similar to that of the node N12.

[0080] Period D12 is the period when signal SI changes from high level to low level and signal SIB changes from low level to high level (the period when a signal changes from high level to low level is also called the falling period, and the period when a signal changes from low level to high level is also called the rising period), and the period when signal SI is at a low level and signal SIB is at a high level.

[0081] In period D12, transistor 17 changes from a conductive state to a non-conductive state, and transistor 13 changes from a non-conductive state to a conductive state. When transistor 13 changes to a conductive state, node N11 becomes high level. On the other hand, even if transistor 17 changes to a non-conductive state, node N12 does not immediately become low level. After node N11 becomes high level, transistor 18 changes to a conductive state, and node N12 becomes low level.

[0082] When the node N11 goes high, the transistors 18, 15, and 12 are turned on, and when the node N12 goes low, the transistors 14, 11, and 16 are turned off.

[0083] Since the transistor 12 is conductive and the transistor 11 is non-conductive, the signal SO is at high level, and since the transistor 16 is non-conductive and the transistor 15 is conductive, the signal SOB is at low level.

[0084] Here, the time from when the node N11 goes high until when the node N12 goes low is defined as the delay time DT12. Even when the node N11 goes high and the transistor 12 is in a conductive state, the transistor 11 remains in a conductive state until the node N12 goes low. Therefore, the signal SO goes high with a delay from the timing when the node N11 goes high.

[0085] Since the signal SO goes high with a delay from the timing when the node N11 goes high, a potential difference occurs between the output terminal SO_OUT and the node N11. If the potential difference is a potential difference DV12, the potential difference DV12 is also applied between one terminal of the capacitance element C11 and the other terminal of the capacitance element C11. When the signal SO changes from a low level to a high level, the potential of the node N11 rises due to the capacitive coupling by the capacitance element C11, and the potential of the node N11 can be made higher than the high power supply potential VDD.

[0086] When the potential of the node N11 becomes higher than the high power supply potential VDD, the potential of the signal SO can be set to the high power supply potential VDD. The potential of the node N11 that becomes higher than the high power supply potential VDD can be maintained even if the period during which the signal SI is at a low level (the period during which the signal SIB is at a high level) is long by using transistors with low off-state current, which will be described later, for the transistors 13 and 14.

[0087] Period D13 is a period during which signal SI changes from low level to high level and signal SIB changes from high level to low level, and a period during which signal SI is at high level and signal SIB is at low level.

[0088] During period D13, transistor 17 changes from a non-conductive state to a conductive state, and transistor 13 changes from a conductive state to a non-conductive state. When transistor 17 changes to a conductive state, node N12 becomes high level. On the other hand, even if transistor 13 changes to a non-conductive state, node N11 does not immediately become low level. After node N12 becomes high level, transistor 14 changes to a conductive state, and node N11 becomes low level.

[0089] When the node N12 goes high, the transistors 14, 11, and 16 are turned on, and when the node N11 goes low, the transistors 18, 15, and 12 are turned off.

[0090] The signal SO is at a low level because the transistor 12 is non-conductive and the transistor 11 is conductive, and the signal SOB is at a high level because the transistor 16 is conductive and the transistor 15 is non-conductive.

[0091] Here, the time from when node N12 goes high until when node N11 goes low is defined as delay time DT13. Even when node N12 goes high and transistor 16 goes conductive, transistor 15 remains conductive until node N11 goes low. Therefore, signal SOB goes high with a delay from when node N12 goes high.

[0092] Since the signal SOB goes high with a delay from the timing when the node N12 goes high, a potential difference occurs between the output terminal SOB_OUT and the node N12. If the potential difference is a potential difference DV13, the potential difference DV13 is also applied between one terminal of the capacitance element C12 and the other terminal of the capacitance element C12. When the signal SOB changes from a low level to a high level, the potential of the node N12 rises due to the capacitive coupling by the capacitance element C12, and the potential of the node N12 can be made higher than the high power supply potential VDD.

[0093] When the potential of the node N12 becomes higher than the high power supply potential VDD, the potential of the signal SOB can be set to the high power supply potential VDD. The potential of the node N12 that becomes higher than the high power supply potential VDD can be maintained even if the period during which the signal SI is at a high level (the period during which the signal SIB is at a low level) is long by using transistors with low off-state current, which will be described later, for the transistors 17 and 18.

[0094] The period D14 is a period during which the signal SI changes from a high level to a low level, the signal SIB changes from a low level to a high level, and the signal SI is at a low level and the signal SIB is at a high level. Note that the period D14 is similar to the period D12, and therefore a description thereof will be omitted.

[0095] As described above, the semiconductor device 10 is a logic circuit configured using n-channel transistors, and by ensuring a potential difference DV12 between the output terminal SO_OUT and the node N11 by the delay time DT12, the potential of the node N11 can be made higher than the high power supply potential VDD more reliably than the examples disclosed in Patent Document 1 or Patent Document 2. Alternatively, by ensuring a potential difference DV13 between the output terminal SOB_OUT and the node N12 by the delay time DT13, the potential of the node N12 can be made higher than the high power supply potential VDD more reliably than the examples disclosed in Patent Document 1 or Patent Document 2.

[0096] When the signal SO output from the output terminal SO_OUT is at a high level, the potential of the node N11 is made higher than the high power supply potential VDD, thereby increasing the potential to the high power supply potential VDD. When the signal SOB output from the output terminal SOB_OUT is at a high level, the potential of the node N12 is made higher than the high power supply potential VDD, thereby increasing the potential to the high power supply potential VDD. When the signals SO and SOB are at a low level, they drop to the low power supply potential VSS, and the semiconductor device 10 has a feature that no through current flows from the high power supply potential VDD to the low power supply potential VSS after the high or low level of the signals SO and SOB is determined.

[0097] <Configuration Example 2 of Semiconductor Device> 3 is a circuit diagram showing a configuration example of a semiconductor device 20. The semiconductor device 20 is a semiconductor device according to one embodiment of the present invention and has a different configuration example from the semiconductor device 10. The semiconductor device 20 includes transistors 21 to 26 and a capacitor C21 and a capacitor C22. The transistors 21 to 26 are n-channel transistors.

[0098] The semiconductor device 20, like the semiconductor device 10, has a wiring VSS_IN to which a low power supply potential VSS is supplied, a wiring VDD_IN to which a high power supply potential VDD is supplied, an input terminal SI_IN to which a signal SI is input, an input terminal SIB_IN to which a signal SIB is input, an output terminal SO_OUT to which a signal SO is output, and an output terminal SOB_OUT to which a signal SOB is output, etc. Note that the explanation of the potentials and signals will be omitted to avoid repetition.

[0099] In the semiconductor device 20, one of the source and drain of the transistor 21 is electrically connected to the wiring VSS_IN, the other of the source and drain of the transistor 21 is electrically connected to one of the source and drain of the transistor 22, the gate of the transistor 24, one terminal of the capacitor C21, and the output terminal SO_OUT, and the other of the source and drain of the transistor 22 is electrically connected to the wiring VDD_IN.

[0100] A gate of the transistor 21 is electrically connected to one of the source or drain of the transistor 24, one of the source or drain of the transistor 25, one terminal of the capacitor C22, and the output terminal SOB_OUT, and a gate of the transistor 22 is electrically connected to one of the source or drain of the transistor 23 and the other terminal of the capacitor C21. In addition, the gate of the transistor 23 is electrically connected to a wiring VDD_IN, and the other of the source or drain of the transistor 23 is electrically connected to an input terminal SIB_IN.

[0101] The other of the source and the drain of the transistor 24 is electrically connected to the wiring VSS_IN, the other of the source and the drain of the transistor 25 is electrically connected to the wiring VDD_IN, and the gate of the transistor 25 is electrically connected to one of the source and the drain of the transistor 26 and the other terminal of the capacitor C22. In addition, the gate of the transistor 26 is electrically connected to the wiring VDD_IN, and the other of the source and the drain of the transistor 26 is electrically connected to the input terminal SI_IN.

[0102] Here, the connection between the gate of transistor 22, one of the source or drain of transistor 23, and the other terminal of the capacitance element C21 is referred to as node N21, and the connection between the gate of transistor 25, one of the source or drain of transistor 26, and the other terminal of the capacitance element C22 is referred to as node N22.

[0103] <Operation Example 2 of Semiconductor Device> 4 is a timing chart showing an operation example of the semiconductor device 20. In FIG. 4, the potentials of the signal SI, the signal SIB, the node N21, the node N22, the signal SO, and the signal SOB are shown divided into periods D21 to D24. Note that the threshold voltages of the transistors 21 to 26 are set to a threshold voltage Vth.

[0104] The period D21 is a period during which the signal SI is at a high level and the signal SIB is at a low level. Note that the period D21 is considered to be in a static state as an initial state. The transistor 26 is in a conductive state, and the potential of the node N22 is at a high level, the same as the signal SI. The transistor 23 is in a conductive state, and the potential of the node N21 is at a low level, the same as the signal SIB. However, the potential of the node N22 during this period is lower than the high power supply potential VDD, and is approximately a value obtained by subtracting the threshold voltage Vth from the high power supply potential VDD.

[0105] Since the node N22 is at a high level, the transistor 25 is in a conductive state, and the signal SOB is at a high level. However, the potential of the signal SOB during this period is lower than the high power supply potential VDD, similar to the node N22. Also, the transistor 21 is in a conductive state.

[0106] Since the node N21 is at a low level, the transistor 22 is not conductive. Furthermore, since the transistor 21 is conductive, the signal SO is at a low level. Furthermore, the transistor 24 is not conductive.

[0107] Period D22 is a period during which signal SI changes from high level to low level and signal SIB changes from low level to high level, and a period during which signal SI is at low level and signal SIB is at high level.

[0108] In period D22, node N22 changes from high to low, transistor 25 changes from conductive to non-conductive, and node N21 changes from low to high, transistor 22 changes from non-conductive to conductive.

[0109] When transistor 22 changes to a conductive state, signal SO goes to high level. On the other hand, even if transistor 25 changes to a non-conductive state, signal SOB does not immediately go to low level. After signal SO goes to high level, transistor 24 changes to a conductive state, and signal SOB goes to low level. Also, when signal SOB goes to low level, transistor 21 goes to a non-conductive state.

[0110] Here, even if the signal SO becomes high level, the transistor 21 is in a conductive state until the signal SOB becomes low level. Therefore, the potential of the signal SO is lower than the high power supply potential VDD, and after the transistor 21 becomes non-conductive, the potential of the signal SO rises again.

[0111] On the other hand, after node N21 changes from low level to high level, signal SO becomes high level, and after signal SOB changes to low level, the potential of signal SO rises again, so that a potential difference DV22 (not shown) occurs between the output terminal SO_OUT that outputs signal SO and node N21.

[0112] Since the potential difference DV22 is also applied between one terminal of the capacitive element C21 and the other terminal of the capacitive element C21, when the signal SO changes from a low level to a high level, the capacitive coupling of the capacitive element C21 can make the potential of the node N21 higher than the high power supply potential VDD.

[0113] When the potential of the node N21 becomes higher than the high power supply potential VDD, the potential of the signal SO can be set to the high power supply potential VDD. In addition, the potential of the node N21 that becomes higher than the high power supply potential VDD can be maintained even if the period during which the signal SI is at a low level (the period during which the signal SIB is at a high level) is long by using a transistor with a small off-state current, which will be described later, as the transistor 23.

[0114] Period D23 is a period during which signal SI changes from low level to high level and signal SIB changes from high level to low level, and a period during which signal SI is at high level and signal SIB is at low level.

[0115] In a period D23, the node N21 changes from a high level to a low level, the transistor 22 changes from a conductive state to a non-conductive state, and the node N22 changes from a low level to a high level, and the transistor 25 changes from a non-conductive state to a conductive state.

[0116] When transistor 25 changes to a conductive state, signal SOB goes to high level. On the other hand, even if transistor 22 changes to a non-conductive state, signal SO does not immediately go to low level. After signal SOB goes to high level, transistor 21 changes to a conductive state, and signal SO goes to low level. Also, when signal SO goes to low level, transistor 24 goes to a non-conductive state.

[0117] Here, even if the signal SOB becomes high level, the transistor 24 is in a conductive state until the signal SO becomes low level. Therefore, the potential of the signal SOB is lower than the high power supply potential VDD, and after the transistor 24 becomes non-conductive, the potential of the signal SOB rises again.

[0118] On the other hand, after node N22 changes from low level to high level, signal SOB becomes high level, and after signal SO changes to low level, the potential of signal SOB rises again, so that a potential difference DV23 (not shown) is generated between the output terminal SOB_OUT that outputs signal SOB and node N22.

[0119] Since the potential difference DV23 is also applied between one terminal of the capacitive element C22 and the other terminal of the capacitive element C22, when the signal SOB changes from a low level to a high level, the capacitive coupling of the capacitive element C22 can make the potential of the node N22 higher than the high power supply potential VDD.

[0120] When the potential of the node N22 becomes higher than the high power supply potential VDD, the potential of the signal SOB can be set to the high power supply potential VDD. In addition, the potential of the node N22 that becomes higher than the high power supply potential VDD can be maintained even if the period during which the signal SI is at a high level (the period during which the signal SIB is at a low level) is long by using a transistor with a small off-state current, which will be described later, as the transistor 26.

[0121] The period D24 is a period during which the signal SI changes from a high level to a low level, the signal SIB changes from a low level to a high level, and the signal SI is at a low level and the signal SIB is at a high level. Note that the period D24 is similar to the period D22, and therefore a description thereof will be omitted.

[0122] As described above, the semiconductor device 20 is a logic circuit configured using n-channel transistors, and by generating a potential difference DV22 between the output terminal SO_OUT and the node N21, the potential of the node N21 can be made higher than the high power supply potential VDD more reliably than the examples disclosed in Patent Document 1 or Patent Document 2. Alternatively, by generating a potential difference DV23 between the output terminal SOB_OUT and the node N22, the potential of the node N22 can be made higher than the high power supply potential VDD more reliably than the examples disclosed in Patent Document 1 or Patent Document 2.

[0123] When the signal SO output from the output terminal SO_OUT is at a high level, the potential of the node N21 is made higher than the high power supply potential VDD, thereby increasing the potential to the high power supply potential VDD. When the signal SOB output from the output terminal SOB_OUT is at a high level, the potential of the node N22 is made higher than the high power supply potential VDD, thereby increasing the potential to the high power supply potential VDD. When the signals SO and SOB are at a low level, they decrease to the low power supply potential VSS, and the semiconductor device 20 has a feature that no through current flows from the high power supply potential VDD to the low power supply potential VSS after the high or low level of the signals SO and SOB is determined.

[0124] <Transistors that constitute semiconductor devices> The transistors 11 to 18 included in the semiconductor device 10 and the transistors 21 to 26 included in the semiconductor device 20 can be transistors having a metal oxide in a channel formation region (OS transistors).

[0125] The OS transistor has characteristics such as a very small off-current, a high voltage can be applied between the source and drain, and a thin film transistor that can be stacked. Here, the off-current refers to the drain current when the transistor is in an off state. Since the band gap of the oxide semiconductor is 2.5 eV or more, preferably 3.0 eV or more, the OS transistor has a small leakage current due to thermal excitation and a very small off-current. For example, the off-current of the OS transistor per 1 μm of channel width can be 100 zA / μm or less, 10 zA / μm or less, 1 zA / μm or less, or 10 yA / μm or less.

[0126] In particular, it is preferable to use transistors with small off-state current for the transistors 13, 14, 17, 18, 23, and 26. As a result, even if the period during which the signal SI is at a low level (the period during which the signal SIB is at a high level) is long in the period D12 or the period D22, the potential of the node N11 or the node N21 that has risen beyond the high power supply potential VDD can be held for a long time. Even if the period during which the signal SI is at a high level (the period during which the signal SIB is at a low level) is long in the period D13 or the period D23, the potential of the node N12 or the node N22 that has risen beyond the high power supply potential VDD can be held for a long time.

[0127] In addition, the OS transistor has a feature that its off-state current does not easily increase even in a high-temperature environment and that its on-state current / off-state current ratio is large even in a high-temperature environment. By configuring the semiconductor device 10 or 20 using an OS transistor, the reliability of the semiconductor device can be improved.

[0128] The metal oxide used in the channel formation region of the OS transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). A typical example of such an oxide semiconductor is In-M-Zn oxide (wherein element M is, for example, Al, Ga, Y, or Sn). By reducing impurities such as moisture and hydrogen that serve as electron donors (donors) and also reducing oxygen vacancies, the oxide semiconductor can be made to be i-type (intrinsic) or substantially i-type. Such an oxide semiconductor can be called a highly purified oxide semiconductor. Details of the OS transistor will be described in Embodiments 3 and 4.

[0129] In addition, since the OS transistor is a thin film transistor, it can be provided in a stacked structure. For example, the OS transistor can be provided on a circuit configured using Si transistors formed on a single crystal silicon substrate. As a result, the chip area of ​​the semiconductor device 10 or the semiconductor device 20 can be reduced.

[0130] Alternatively, transistors other than OS transistors may be used as the transistors 11 to 18 included in the semiconductor device 10 and the transistors 21 to 26 included in the semiconductor device 20. For example, a transistor including a semiconductor with a wide band gap in a channel formation region may be used. A wide band gap semiconductor may refer to a semiconductor with a band gap of 2.2 eV or more, and examples of such a semiconductor include silicon carbide, gallium nitride, and diamond.

[0131] Further, the transistors 11 to 18 included in the semiconductor device 10 and the transistors 21 to 26 included in the semiconductor device 20 may each be a transistor having a back gate.

[0132] As an example of a transistor with a backgate, Fig. 5A shows a schematic symbol of a transistor 31. The transistor 31 has four terminals called a gate (also called a front gate), a drain, a source, and a backgate, which are represented in Fig. 5A as G (gate), D (drain), S (source), and BG (backgate), respectively.

[0133] As an example of the use of the transistor 31, the back gate may be electrically connected to the gate, the back gate may be electrically connected to the source, a predetermined potential may be applied to the back gate, or the back gate may be in an electrically floating state (also referred to as floating). For example, by electrically connecting the back gate to the gate, the on-state current of the transistor 31 can be increased. In addition, by applying a predetermined potential to the back gate, the threshold voltage of the transistor 31 can be changed. An example of a cross-sectional structure of a transistor having a back gate will be described in Embodiment 3.

[0134] Further, the transistors 11 to 18 included in the semiconductor device 10 and the transistors 21 to 26 included in the semiconductor device 20 may each be a transistor having a plurality of gates (also referred to as a multi-gate).

[0135] As an example of a transistor having multiple gates, Fig. 5B shows a schematic symbol of a transistor 32 having two gates (also called double gate). The transistor 32 has four terminals (gate 1, gate 2, drain, and source). In Fig. 5B, these are represented as G1 (gate 1), G2 (gate 2), D (drain), and S (source), respectively.

[0136] As an example of the use of the transistor 32, the gate 1 and the gate 2 may be electrically connected to each other, or a predetermined potential may be applied to the gate 1 or the gate 2. For example, by electrically connecting the gate 1 and the gate 2, the off-state current of the transistor 32 may be reduced in some cases. Furthermore, by applying a predetermined potential to the gate 1 or the gate 2, the transistor 32 may be a transistor with high withstand voltage in some cases.

[0137] For example, an example in which a transistor 31 having a backgate is used as the transistor 11 and the transistor 15 constituting the semiconductor device 10 is shown in FIG. 5C (in FIG. 5C, they are shown as transistors 31_1 and 31_2, respectively). In FIG. 5C, the backgate of the transistor 31 is electrically connected to the gate of the transistor 31.

[0138] For example, an example in which a transistor 32 having two gates is used as the transistor 11 and the transistor 15 constituting the semiconductor device 10 is shown in Fig. 5D (in Fig. 5D, they are shown as transistors 32_1 and 32_2, respectively). In Fig. 5D, a gate 1 of the transistor 32 is electrically connected to a gate 2 of the transistor 32.

[0139] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0140] (Embodiment 2) In this embodiment, an example of configuring a general-purpose logic circuit will be described by applying the semiconductor device 10 described in the above embodiment. The semiconductor device 10 described in the above embodiment can be used as a NOT circuit that inverts logic, or a buffer circuit that does not invert logic.

[0141] The semiconductor device 10 receives the signal SI and the signal SIB, and outputs the signal SO and the signal SOB. Since the signal SIB is a signal with the logic of the signal SI inverted, and the signal SOB is a signal with the logic of the signal SO inverted, the output terminals of the semiconductor device 10 can be electrically connected to the input terminals of another semiconductor device 10.

[0142] <NAND circuit> FIG. 6 is a circuit diagram showing a configuration example of the semiconductor device 40. The semiconductor device 40 is a semiconductor device applying the semiconductor device 10 and has a function as a NAND circuit. The semiconductor device 40 includes transistors 41 to 50, a capacitor element C41, and a capacitor element C42. The transistors 41 to 50 are n-channel type transistors.

[0143] The semiconductor device 40 has a wiring VSS_IN to which a low power supply potential VSS is supplied, a wiring VDD_IN to which a high power supply potential VDD is supplied, an input terminal SI1_IN to which a signal SI1 is input, an input terminal SI2_IN to which a signal SI2 is input, an input terminal SI1B_IN to which a signal SI1B is input, an input terminal SI2B_IN to which a signal SI2B is input, an output terminal SO1_OUT for outputting a signal SO1, and an output terminal SO1B_OUT for outputting a signal SO1B.

[0144] Here, the high power supply potential VDD is a potential higher than the low power supply potential VSS, and the low power supply potential VSS may be a reference potential in the semiconductor device 40. Also, the signals SI1, SI2, SI1B, and SI2B are digital signals, and the potential representing the high level of the signals SI1, SI2, SI1B, and SI2B can be the high power supply potential VDD, and the potential representing the low level can be the low power supply potential VSS. Also, the signal SI1B is a signal with the logic of the signal SI1 inverted, and the signal SI2B is a signal with the logic of the signal SI2 inverted.

[0145] In the semiconductor device 40, one of the source and drain of the transistor 41 is electrically connected to the wiring VSS_IN, the other of the source and drain of the transistor 41 is electrically connected to one of the source and drain of the transistor 42, one terminal of the capacitor C41, and the output terminal SO1_OUT, and the other of the source and drain of the transistor 42 is electrically connected to the wiring VDD_IN.

[0146] The gate of the transistor 41 is electrically connected to the gate of the transistor 45, one of the source or drain of the transistor 50, one of the source or drain of the transistor 49, one terminal of the capacitor C42, and the gate of the transistor 47. The gate of the transistor 42 is electrically connected to the other terminal of the capacitor C41, one of the source or drain of the transistor 44, one of the source or drain of the transistor 43, one of the source or drain of the transistor 45, the gate of the transistor 50, and the gate of the transistor 46.

[0147] The other of the source and drain of transistor 45 is electrically connected to wiring VSS_IN, the other of the source and drain of transistor 44 is electrically connected to wiring VDD_IN, the other of the source and drain of transistor 43 is electrically connected to wiring VDD_IN, the gate of transistor 44 is electrically connected to input terminal SI2B_IN, and the gate of transistor 43 is electrically connected to input terminal SI1B_IN.

[0148] The other of the source and drain of transistor 50 is electrically connected to wiring VSS_IN, the other of the source and drain of transistor 49 is electrically connected to one of the source and drain of transistor 48, the other of the source and drain of transistor 48 is electrically connected to wiring VDD_IN, the gate of transistor 49 is electrically connected to input terminal SI2_IN, and the gate of transistor 48 is electrically connected to input terminal SI1_IN.

[0149] One of the source or drain of transistor 46 is electrically connected to wiring VSS_IN, and the other of the source or drain of transistor 46 is electrically connected to one of the source or drain of transistor 47, the other terminal of capacitor element C42, and output terminal SO1B_OUT. The other of the source or drain of transistor 47 is electrically connected to wiring VDD_IN.

[0150] Here, the connection part of the gate of transistor 41, the gate of transistor 45, one of the source or drain of transistor 50, one of the source or drain of transistor 49, one terminal of capacitor element C42, and the gate of transistor 47 is referred to as node N42. Also, the connection part of the gate of transistor 42, the other terminal of capacitor element C41, one of the source or drain of transistor 45, one of the source or drain of transistor 44, one of the source or drain of transistor 43, the gate of transistor 50, and the gate of transistor 46 is referred to as node N41. The operation example of semiconductor device 40 will be described later.

[0151] <NOR circuit> FIG. 7 is a circuit diagram showing a configuration example of semiconductor device 60. Semiconductor device 60 is a semiconductor device applying semiconductor device 10 and has a function as a NOR circuit. Semiconductor device 60 includes transistors 61 to 70, capacitor element C61, and capacitor element C62. Transistors 61 to 70 are n-channel type transistors.

[0152] Similar to the semiconductor device 40, the semiconductor device 60 has a wiring VSS_IN to which a low power supply potential VSS is supplied, a wiring VDD_IN to which a high power supply potential VDD is supplied, an input terminal SI1_IN to which a signal SI1 is input, an input terminal SI2_IN to which a signal SI2 is input, an input terminal SI1B_IN to which a signal SI1B is input, an input terminal SI2B_IN to which a signal SI2B is input, an output terminal SO2_OUT to which a signal SO2 is output, and an output terminal SO2B_OUT to which a signal SO2B is output, etc. Note that the explanation of the potentials and signals will be omitted to avoid repetition.

[0153] In the semiconductor device 60, one of the source and drain of the transistor 61 is electrically connected to the wiring VSS_IN, the other of the source and drain of the transistor 61 is electrically connected to one of the source and drain of the transistor 62, one terminal of the capacitor C61, and the output terminal SO2_OUT, and the other of the source and drain of the transistor 62 is electrically connected to the wiring VDD_IN.

[0154] The gate of the transistor 61 is electrically connected to the gate of the transistor 65, one of the source or drain of the transistor 70, one of the source or drain of the transistor 68, one of the source or drain of the transistor 69, one terminal of the capacitor C62, and the gate of the transistor 67. The gate of the transistor 62 is electrically connected to the other terminal of the capacitor C61, one of the source or drain of the transistor 64, one of the source or drain of the transistor 65, the gate of the transistor 70, and the gate of the transistor 66.

[0155] The other of the source and drain of transistor 65 is electrically connected to wiring VSS_IN, the other of the source and drain of transistor 64 is electrically connected to one of the source and drain of transistor 63, the other of the source and drain of transistor 63 is electrically connected to wiring VDD_IN, the gate of transistor 64 is electrically connected to input terminal SI2B_IN, and the gate of transistor 63 is electrically connected to input terminal SI1B_IN.

[0156] The other of the source or drain of transistor 70 is electrically connected to wiring VSS_IN, the other of the source or drain of transistor 68 is electrically connected to wiring VDD_IN, the other of the source or drain of transistor 69 is electrically connected to wiring VDD_IN, the gate of transistor 68 is electrically connected to input terminal SI1_IN, and the gate of transistor 69 is electrically connected to input terminal SI2_IN.

[0157] One of the source or drain of the transistor 66 is electrically connected to the wiring VSS_IN, the other of the source or drain of the transistor 66 is electrically connected to one of the source or drain of the transistor 67, the other terminal of the capacitor C62, and the output terminal SO2B_OUT, and the other of the source or drain of the transistor 67 is electrically connected to the wiring VDD_IN.

[0158] Here, a connection portion between the gate of transistor 61 and the gate of transistor 65, one of the source or drain of transistor 70, one of the source or drain of transistor 68, one of the source or drain of transistor 69, one terminal of capacitor C62, and the gate of transistor 67 is referred to as a node N62. A connection portion between the gate of transistor 62 and the other terminal of capacitor C61, one of the source or drain of transistor 64, one of the source or drain of transistor 65, the gate of transistor 70, and the gate of transistor 66 is referred to as a node N61.

[0159] <Example of operation of semiconductor device> Fig. 8 is a timing chart showing an example of the operation of the semiconductor device 40 and the semiconductor device 60. Fig. 8 shows the potentials of the signals SI1, SI2, SO1, SO1B, SO2, and SO2B divided into periods D41 to D45.

[0160] [Period D41] The period D41 is a period during which the signals SI1 and SI2 change from high level to low level and are at low level. Note that the signal SI1B is a signal obtained by inverting the logic of the signal SI1, and the signal SI2B is a signal obtained by inverting the logic of the signal SI2, so a description thereof will be omitted (not shown).

[0161] In the semiconductor device 40 during the period D41, the transistors 48 and 49 change from the conductive state to the non-conductive state, and the transistors 43 and 44 change from the non-conductive state to the conductive state. When the transistors 43 and 44 change to the conductive state, the node N41 becomes high level. On the other hand, even if the transistors 48 and 49 change to the non-conductive state, the node N42 does not immediately become low level. After the node N41 becomes high level, the transistor 50 changes to the conductive state, and the node N42 becomes low level.

[0162] When node N41 goes high, transistor 50, transistor 46, and transistor 42 are turned on. When node N42 goes low, transistor 45, transistor 41, and transistor 47 are turned off. Since transistor 42 is turned on and transistor 41 is turned off, signal SO1 goes high. Since transistor 47 is turned off and transistor 46 is turned on, signal SO1B goes low.

[0163] Here, even if the node N41 goes high and the transistor 42 goes conductive, the transistor 41 remains conductive until the node N42 goes low, so the signal SO1 goes high with a delay from the timing when the node N41 goes high. Therefore, a potential difference is generated between the output terminal SO1_OUT and the node N41, and the potential difference is also applied between one terminal of the capacitance element C41 and the other terminal of the capacitance element C41.

[0164] When a potential difference is applied between one terminal of the capacitance element C41 and the other terminal of the capacitance element C41, when the signal SO1 changes from low level to high level, the potential of the node N41 rises due to capacitive coupling by the capacitance element C41, and the potential of the node N41 can be made higher than the high power supply potential VDD. When the potential of the node N41 becomes higher than the high power supply potential VDD, the potential of the signal SO1 can be made the high power supply potential VDD. In addition, by using the transistors 43, 44, and 45 with the above-mentioned small off-currents, the potential of the node N41 that has become higher than the high power supply potential VDD can be maintained even if the period during which the signal SO1 is at a high level (the period during which the signal SO1B is at a low level) is long.

[0165] In the semiconductor device 60 during period D41, the transistors 68 and 69 change from a conductive state to a non-conductive state, and the transistors 63 and 64 change from a non-conductive state to a conductive state. When the transistors 63 and 64 change to a conductive state, the node N61 becomes high level. On the other hand, even if the transistors 68 and 69 change to a non-conductive state, the node N62 does not immediately become low level. After the node N61 becomes high level, the transistor 70 changes to a conductive state, and the node N62 becomes low level.

[0166] When node N61 goes high, transistor 70, transistor 66, and transistor 62 are turned on. When node N62 goes low, transistor 65, transistor 61, and transistor 67 are turned off. Since transistor 62 is turned on and transistor 61 is turned off, signal SO2 goes high. Since transistor 67 is turned off and transistor 66 is turned on, signal SO2B goes low.

[0167] Here, even if the node N61 goes high and the transistor 62 goes conductive, the transistor 61 remains conductive until the node N62 goes low, so the signal SO2 goes high with a delay from the timing when the node N61 goes high. Therefore, a potential difference occurs between the output terminal SO2_OUT and the node N61, and the potential difference is also applied between one terminal of the capacitance element C61 and the other terminal of the capacitance element C61.

[0168] When a potential difference is applied between one terminal of the capacitance element C61 and the other terminal of the capacitance element C61, when the signal SO2 changes from low level to high level, the potential of the node N61 rises due to capacitive coupling by the capacitance element C61, and the potential of the node N61 can be made higher than the high power supply potential VDD. When the potential of the node N61 becomes higher than the high power supply potential VDD, the potential of the signal SO2 can be made the high power supply potential VDD. In addition, by using the transistors 63, 64, and 65 with the above-mentioned small off-currents, the potential of the node N61 that has become higher than the high power supply potential VDD can be maintained even if the period during which the signal SO2 is at a high level (the period during which the signal SO2B is at a low level) is long.

[0169] [Period D42] The period D42 is a period during which the signal SI1 changes from a low level to a high level, and a period during which the signal SI1 is at a high level and the signal SI2 is at a low level.

[0170] In the semiconductor device 40 during the period D42, the transistor 48 changes from a non-conductive state to a conductive state, and the transistor 43 changes from a conductive state to a non-conductive state. The transistor 49 is in a non-conductive state, and the transistor 44 does not change from a conductive state. Therefore, the node N41 remains at a high level, and the node N42 remains at a low level.

[0171] Since node N41 is at a high level, transistor 50, transistor 46, and transistor 42 are in a conductive state. Also, since node N42 is at a low level, transistor 45, transistor 41, and transistor 47 are in a non-conductive state. Since transistor 42 is in a conductive state and transistor 41 is in a non-conductive state, signal SO1 remains at a high level. Also, since transistor 47 is in a non-conductive state and transistor 46 is in a conductive state, signal SO1B remains at a low level. That is, during period D42, semiconductor device 40 maintains the state of period D41.

[0172] In the semiconductor device 60 during period D42, the transistor 69 remains in the non-conductive state and the transistor 64 remains in the conductive state, but the transistor 68 changes from the non-conductive state to the conductive state and the transistor 63 changes from the conductive state to the non-conductive state. When the transistor 68 changes to the conductive state, the node N62 becomes high level. On the other hand, even if the transistor 63 changes to the non-conductive state, the node N61 does not immediately become low level. After the node N62 becomes high level, the transistor 65 changes to the conductive state and the node N61 becomes low level.

[0173] When node N61 goes low, transistor 70, transistor 66, and transistor 62 go into a non-conductive state. When node N62 goes high, transistor 65, transistor 61, and transistor 67 go into a conductive state. Since transistor 62 is in a non-conductive state and transistor 61 is in a conductive state, signal SO2 goes low. Since transistor 67 is in a conductive state and transistor 66 is in a non-conductive state, signal SO2B goes high.

[0174] Here, even if node N62 goes high and transistor 67 goes conductive, transistor 66 remains conductive until node N61 goes low, so signal SO2B goes high with a delay from when node N62 goes high. Therefore, a potential difference occurs between output terminal SO2B_OUT and node N62, and this potential difference is also applied between one terminal of capacitance element C62 and the other terminal of capacitance element C62.

[0175] When a potential difference is applied between one terminal of the capacitance element C62 and the other terminal of the capacitance element C62, when the signal SO2B changes from low level to high level, the potential of the node N62 rises due to capacitive coupling by the capacitance element C62, and the potential of the node N62 can be made higher than the high power supply potential VDD. When the potential of the node N62 becomes higher than the high power supply potential VDD, the potential of the signal SO2B can be made the high power supply potential VDD. In addition, by using the transistors 68, 69, and 70 with the above-mentioned low off-currents, the potential of the node N62 that has become higher than the high power supply potential VDD can be maintained even if the period during which the signal SO2B is at a high level (the period during which the signal SO2 is at a low level) is long.

[0176] [Period D43] The period D43 is a period during which the signal SI1 changes from high level to low level and the signal SI2 changes from low level to high level, and a period during which the signal SI1 is at low level and the signal SI2 is at high level.

[0177] In the semiconductor device 40 during the period D43, the transistors 48 and 44 change from the conductive state to the non-conductive state, and the transistors 49 and 43 change from the non-conductive state to the conductive state. Therefore, the node N41 remains at the high level, and the node N42 remains at the low level.

[0178] Since node N41 is at a high level, transistor 50, transistor 46, and transistor 42 are in a conductive state. Also, since node N42 is at a low level, transistor 45, transistor 41, and transistor 47 are in a non-conductive state. Since transistor 42 is in a conductive state and transistor 41 is in a non-conductive state, signal SO1 remains at a high level. Also, since transistor 47 is in a non-conductive state and transistor 46 is in a conductive state, signal SO1B remains at a low level. That is, in period D43, semiconductor device 40 maintains the state of period D42.

[0179] In the semiconductor device 60 during the period D43, the transistors 68 and 64 change from the conductive state to the non-conductive state, and the transistors 69 and 63 change from the non-conductive state to the conductive state. Therefore, the node N61 remains at the low level, and the node N62 remains at the high level.

[0180] Since node N61 is at a low level, transistor 70, transistor 66, and transistor 62 are in a non-conductive state. Also, since node N62 is at a high level, transistor 65, transistor 61, and transistor 67 are in a conductive state. Since transistor 62 is in a non-conductive state and transistor 61 is in a conductive state, signal SO2 remains at a low level. Also, since transistor 67 is in a conductive state and transistor 66 is in a non-conductive state, signal SO2B remains at a high level. That is, the semiconductor device 60 in period D43 maintains the state of period D42.

[0181] [Period D44] The period D44 is a period during which the signal SI1 changes from a low level to a high level, and a period during which the signals SI1 and SI2 are at a high level.

[0182] In the semiconductor device 40 during period D44, the transistor 49 remains in the conductive state and the transistor 44 remains in the non-conductive state, but the transistor 48 changes from the non-conductive state to the conductive state and the transistor 43 changes from the conductive state to the non-conductive state. When the transistor 48 changes to the conductive state, the node N42 becomes high level. On the other hand, even if the transistor 43 changes to the non-conductive state, the node N41 does not immediately become low level. After the node N42 becomes high level, the transistor 45 changes to the conductive state and the node N41 becomes low level.

[0183] When node N41 goes low, transistor 50, transistor 46, and transistor 42 go into a non-conductive state. When node N42 goes high, transistor 45, transistor 41, and transistor 47 go into a conductive state. Since transistor 42 is in a non-conductive state and transistor 41 is in a conductive state, signal SO1 goes low. Since transistor 47 is in a conductive state and transistor 46 is in a non-conductive state, signal SO1B goes high.

[0184] Here, even if node N42 goes high and transistor 47 goes conductive, transistor 46 remains conductive until node N41 goes low, so signal SO1B goes high with a delay from when node N42 goes high. Therefore, a potential difference occurs between output terminal SO1B_OUT and node N42, and the potential difference is also applied between one terminal of capacitance element C42 and the other terminal of capacitance element C42.

[0185] When a potential difference is applied between one terminal of the capacitance element C42 and the other terminal of the capacitance element C42, and the signal SO1B changes from low level to high level, the potential of the node N42 rises due to capacitive coupling by the capacitance element C42, and the potential of the node N42 can be made higher than the high power supply potential VDD. When the potential of the node N42 becomes higher than the high power supply potential VDD, the potential of the signal SO1B can be made the high power supply potential VDD. In addition, by using the transistors 48, 49, and 50 with the above-mentioned low off-currents, the potential of the node N42 that has become higher than the high power supply potential VDD can be maintained even if the period during which the signal SO1B is at a high level (the period during which the signal SO1 is at a low level) is long.

[0186] In the semiconductor device 60 during the period D44, the transistor 68 changes from a non-conductive state to a conductive state, and the transistor 63 changes from a conductive state to a non-conductive state. The transistor 64 remains in a non-conductive state, and the transistor 69 remains in a conductive state. Therefore, the node N61 remains at a low level, and the node N62 remains at a high level.

[0187] Since node N61 is at a low level, transistor 70, transistor 66, and transistor 62 are in a non-conductive state. Also, since node N62 is at a high level, transistor 65, transistor 61, and transistor 67 are in a conductive state. Since transistor 62 is in a non-conductive state and transistor 61 is in a conductive state, signal SO2 remains at a low level. Also, since transistor 67 is in a conductive state and transistor 66 is in a non-conductive state, signal SO2B remains at a high level. That is, the semiconductor device 60 in period D44 maintains the state of period D43.

[0188] [Period D45] The period D45 is a period during which the signals SI1 and SI2 change from a high level to a low level, and a period during which the signals SI1 and SI2 are at a low level. Note that the period D45 is similar to the period D41, and therefore a description thereof will be omitted.

[0189] As described above, signals SI1, SI2, SI1B, and SI2B are input to the semiconductor device 40, and the semiconductor device 40 outputs signals SO1 and SO1B. That is, the semiconductor device 40 functions as a NAND circuit. Moreover, signals SI1, SI2, SI1B, and SI2B are input to the semiconductor device 60, and the semiconductor device 60 outputs signals SO2 and SO2B. That is, the semiconductor device 60 functions as a NOR circuit.

[0190] Since the signal SO1B is a signal with the logic of the signal SO1 inverted, and the signal SO2B is a signal with the logic of the signal SO2 inverted, the semiconductor device 10 having a function as a NOT circuit or a buffer circuit, the semiconductor device 40 having a function as a NAND circuit, and the semiconductor device 60 having a function as a NOR circuit can be electrically connected to each other. In other words, a general-purpose logic circuit can be configured by using the semiconductor device 10, the semiconductor device 40, and the semiconductor device 60.

[0191] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0192] (Embodiment 3) In this embodiment, a configuration example of an OS transistor that can be used for the transistor constituting the semiconductor device 10, the transistor constituting the semiconductor device 20, the transistor constituting the semiconductor device 40, and the transistor constituting the semiconductor device 60, which are described in the above embodiments, will be described. Note that the OS transistor is a thin film transistor and can be provided in a stacked state. Therefore, in this embodiment, a configuration example of a semiconductor device in which an OS transistor is provided above a Si transistor formed on a single crystal silicon substrate will be described.

[0193] <Example of semiconductor device configuration> 9 includes a transistor 300, a transistor 500, and a capacitor 600. Fig. 10A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 10B is a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 10C is a cross-sectional view of the transistor 300 in the channel width direction.

[0194] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). The transistor 500 has features that a high voltage can be applied between the source and drain, that the off-current is not likely to increase even in a high-temperature environment, and that the ratio of the on-current to the off-current is large even in a high-temperature environment. Therefore, by using the transistor 500 in the semiconductor device 10, the semiconductor device 20, the semiconductor device 40, and the semiconductor device 60 in the above embodiments, the semiconductor device can be made to have high reliability.

[0195] 9, the semiconductor device described in this embodiment includes a transistor 300, a transistor 500, and a capacitor 600. The transistor 500 is provided above the transistor 300, and the capacitor 600 is provided above the transistor 300 and the transistor 500.

[0196] The transistor 300 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, and a low resistance region 314a and a low resistance region 314b functioning as a source region or a drain region.

[0197] 10C, the upper surface and the side surface in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this manner, the effective channel width is increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-characteristics of the transistor 300.

[0198] The transistor 300 may be either a p-channel type or an n-channel type.

[0199] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low resistance region 314a which becomes the source region or the drain region, and the low resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0200] Low resistance region 314a and low resistance region 314b contain, in addition to the semiconductor material applied to semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0201] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, such as silicon, containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0202] Since the work function is determined by the material of the conductor, the Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum laminated on the conductor, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0203] Note that the transistor 300 illustrated in FIG. 9 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0204] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300.

[0205] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0206] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 300 provided thereunder. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0207] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or the transistor 300 to a region where the transistor 500 is provided.

[0208] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0209] The amount of desorption of hydrogen can be analyzed by, for example, thermal desorption spectroscopy (TDS) or the like. For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0210] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0211] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wiring. A plurality of conductors that function as plugs or wiring may be collectively given the same reference numeral. In this specification and the like, the wiring and the plug connected to the wiring may be integral. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0212] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form it from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0213] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 9, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0214] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0215] Note that, for example, tantalum nitride or the like may be used as the conductor having a barrier property against hydrogen. By stacking tantalum nitride and tungsten having high conductivity, it is possible to suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0216] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 9, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0217] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0218] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 9, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0219] Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0220] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 9, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. The conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0221] Note that, for example, the insulator 380 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0222] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device of this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0223] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen or hydrogen.

[0224] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0225] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0226] As a film having a barrier property against hydrogen, for example, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0227] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0228] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced. For example, the insulator 512 and the insulator 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0229] A conductor 518, a conductor constituting the transistor 500 (conductor 503 (see FIG. 10A)), and the like are embedded in the insulators 510, 512, 514, and 516. Note that the conductor 518 functions as a plug or wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0230] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0231] Above the insulator 516 is a transistor 500 .

[0232] As shown in FIGS. 10A and 10B , a transistor 500 includes an insulator 514 and a conductor 503 disposed so as to be embedded in an insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, and conductors 542a and 542b disposed apart from each other on the oxide 530b. and conductor 542b, an insulator 580 disposed on conductor 542a and conductor 542b and having an opening formed overlapping conductor 542a and conductor 542b, a conductor 560 disposed in the opening, an oxide 530b, conductor 542a, conductor 542b, and insulator 580, and an insulator 550 disposed between conductor 560, and an oxide 530c disposed between oxide 530b, conductor 542a, conductor 542b, and insulator 580, and insulator 550.

[0233] 10A and 10B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. It is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 550.

[0234] In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530. The conductor 542a and the conductor 542b may be collectively referred to as the conductor 542.

[0235] In the transistor 500, a three-layer structure of oxide 530a, oxide 530b, and oxide 530c is shown in the region where a channel is formed and in the vicinity thereof, but the present invention is not limited thereto. For example, a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a stacked structure of four or more layers may be provided. In addition, in the transistor 500, the conductor 560 is shown as having a two-layer stacked structure, but the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. In addition, the transistor 500 shown in FIG. 9, FIG. 10A, and FIG. 10B is an example, and the present invention is not limited to the structure, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

[0236] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

[0237] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This makes it possible to improve the switching speed of the transistor 500 and provide high frequency characteristics.

[0238] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the Vth of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the Vth of the transistor 500 can be made higher than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V, compared to not applying a negative potential.

[0239] The conductor 503 is disposed so as to overlap the oxide 530 and the conductor 560. In this manner, when a potential is applied to the conductor 560 and the conductor 503, an electric field generated from the conductor 560 and an electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0240] In addition, in this specification, the S-channel structure has a feature that the side and periphery of the oxide 530 in contact with the conductor 542a and the conductor 542b functioning as the source electrode and the drain electrode are I-type like the channel formation region. In addition, the side and periphery of the oxide 530 in contact with the conductor 542a and the conductor 542b are in contact with the insulator 544, so they can be I-type like the channel formation region. In this specification, the I-type can be treated as the same as the high purity intrinsic described later. In addition, the S-channel structure disclosed in this specification is different from the fin type structure and the planar type structure. By adopting the S-channel structure, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, a transistor that is less likely to cause the short channel effect.

[0241] Moreover, the conductor 503 has a configuration similar to that of the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inside.

[0242] The insulators 520, 522, 524, and 550 function as gate insulating films.

[0243] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0244] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide material from which oxygen is released by heating is an oxide material from which the amount of oxygen released, converted into oxygen atoms, is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0245] When the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0246] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, so that oxygen contained in the oxide 530 does not diffuse toward the insulator 520. Furthermore, reaction of the conductor 503 with the insulator 524 or oxygen contained in the oxide 530 can be suppressed.

[0247] The insulator 522 is preferably a single layer or a multilayer of an insulator containing, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0248] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing the diffusion of impurities and oxygen (the oxygen is unlikely to permeate through them). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0249] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0250] In addition, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining a high-k material insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable laminated structure with a high dielectric constant.

[0251] The insulator 520, the insulator 522, and the insulator 524 may have a layered structure of two or more layers. In that case, the layers are not limited to being made of the same material, and may be made of different materials.

[0252] In the transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used for the oxide 530. Alternatively, In-Ga oxide or In-Zn oxide may be used for the oxide 530.

[0253] In addition, it is preferable to use a metal oxide with a low carrier density for the transistor 500. In order to reduce the carrier density of the metal oxide, the impurity concentration in the metal oxide may be reduced to reduce the defect state density. In this specification and the like, a low impurity concentration and a low defect state density are referred to as high purity intrinsic or substantially high purity intrinsic. Note that examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0254] In particular, hydrogen contained in metal oxide reacts with oxygen that bonds to metal atoms to form water, which may cause oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region in the metal oxide, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that bonds to metal atoms to generate electrons that serve as carriers. Therefore, transistors using metal oxides that contain a large amount of hydrogen tend to have normally-on characteristics.

[0255] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for a metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in a metal oxide, the carrier density may be used instead of the donor concentration. Therefore, in this specification, the carrier density assuming a state in which no electric field is applied may be used as a parameter of the metal oxide, instead of the donor concentration. In other words, the "carrier density" described in this specification may be rephrased as the "donor concentration".

[0256] Therefore, when a metal oxide is used for the oxide 530, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0257] In addition, when a metal oxide is used for the oxide 530, the carrier density of the metal oxide in the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3The lower limit of the carrier density of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0258] Furthermore, when a metal oxide is used for the oxide 530, contact between the conductor 542 (conductor 542a and conductor 542b) and the oxide 530 may cause oxygen in the oxide 530 to diffuse into the conductor 542, resulting in the oxidation of the conductor 542. The oxidation of the conductor 542 is likely to result in a decrease in the conductivity of the conductor 542. The diffusion of oxygen in the oxide 530 into the conductor 542 can be rephrased as the conductor 542 absorbing the oxygen in the oxide 530.

[0259] Furthermore, oxygen in the oxide 530 may diffuse into the conductor 542 (conductor 542a and conductor 542b), forming a foreign layer between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. The foreign layer contains more oxygen than the conductor 542, and is therefore presumed to have insulating properties. In this case, the three-layer structure of the conductor 542, the foreign layer, and the oxide 530b can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0260] In addition, the above-mentioned different layer is not limited to being formed between the conductor 542 and the oxide 530b. For example, the different layer may be formed between the conductor 542 and the oxide 530c, between the conductor 542 and the oxide 530b, and between the conductor 542 and the oxide 530c.

[0261] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0262] In addition, the semiconductor material that can be used for the oxide 530 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as the oxide 530. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material, a two-dimensional material, or the like) that functions as a semiconductor is preferably used as the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor as the semiconductor material.

[0263] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0264] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0265] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 530. Specific examples of transition metal chalcogenides that can be used as the oxide 530 include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0266] The oxide 530 has the oxide 530a below the oxide 530b, so that the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b can be suppressed. Also, the oxide 530 has the oxide 530c on the oxide 530b, so that the diffusion of impurities from structures formed above the oxide 530c to the oxide 530b can be suppressed.

[0267] The oxide 530 preferably has a laminated structure of a plurality of oxide layers having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a. In addition, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0268] In addition, the energy of the conduction band minimum of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b, or in other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0269] Here, the energy level of the conduction band minimum changes gradually at the junction of the oxide 530a, the oxide 530b, and the oxide 530c. In other words, it can be said that the energy level of the conduction band minimum at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c.

[0270] Specifically, the oxides 530a and 530b, and the oxides 530b and 530c have a common element other than oxygen (as a main component), so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxides 530a and 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0271] At this time, the main carrier path is the oxide 530b. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0272] Conductors 542 (conductors 542a and 542b) functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductor 542, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are difficult to oxidize or materials that maintain their conductivity even when they absorb oxygen.

[0273] 10A, a region 543 (regions 543a and 543b) may be formed as a low-resistance region at the interface between the oxide 530 and the conductor 542 and in its vicinity. In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0274] By providing the conductor 542 so as to be in contact with the oxide 530, the oxygen concentration in the region 543 may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542 and a component of the oxide 530 may be formed in the region 543. In such a case, the carrier density in the region 543 increases, and the region 543 becomes a low-resistance region.

[0275] The insulator 544 is provided to cover the conductor 542 and suppresses oxidation of the conductor 542. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0276] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0277] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later process. Note that, if the conductor 542 is a material having oxidation resistance or the conductivity does not decrease significantly even when oxygen is absorbed, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.

[0278] The insulator 550 functions as a gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top and side surfaces) of the oxide 530c. The insulator 550 is preferably formed using an insulator that releases oxygen when heated. For example, in a TDS analysis, the amount of released oxygen converted into oxygen atoms is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less.

[0279] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0280] By providing an insulator that releases oxygen when heated as the insulator 550 in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0281] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0282] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 10A and 10B, it may have a single-layer structure or a laminated structure of three or more layers.

[0283] Conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is preferably used. Conductor 560a has a function of suppressing the diffusion of oxygen, so that it is possible to suppress the oxidation of conductor 560b due to oxygen contained in insulator 550, which leads to a decrease in conductivity. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0284] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b also functions as wiring, so it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0285] The insulator 580 is provided on the conductor 542 via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having voids are preferable because an excess oxygen region can be easily formed in a later step.

[0286] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, which releases oxygen when heated, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0287] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b, so that conductor 560 is formed so as to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0288] In miniaturizing a semiconductor device, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for that purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0289] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0290] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0291] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as a barrier film against impurities such as hydrogen as well as an oxygen source.

[0292] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0293] Conductor 540a and conductor 540b are arranged in openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductor 540a and conductor 540b are provided facing each other with conductor 560 interposed therebetween. Conductor 540a and conductor 540b have the same configuration as conductor 546 and conductor 548, which will be described later.

[0294] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably made of a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0295] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0296] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0297] In addition, conductors 546, 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0298] The conductor 546 and the conductor 548 function as a plug or a wiring connected to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0299] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0300] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0301] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned element (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide can also be used.

[0302] 9, the conductor 612 and the conductor 610 are shown as having a single-layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0303] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When the conductor 620 is formed simultaneously with other structures such as a conductor, a low resistance metal material such as Cu (copper) or Al (aluminum) may be used.

[0304] An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape underneath.

[0305] By using this structure, in a semiconductor device including a transistor having an oxide semiconductor, a change in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, miniaturization or high integration of a semiconductor device including a transistor having an oxide semiconductor can be achieved.

[0306] <Example of transistor structure> Note that the transistor 500 of the semiconductor device described in this embodiment is not limited to the above structure. Hereinafter, examples of a structure that can be used for the transistor 500 will be described.

[0307] <Transistor structure example 1> A structural example of a transistor 510A will be described with reference to Figures 11A, 11B, and 11C. Figure 11A is a top view of the transistor 510A. Figure 11B is a cross-sectional view of a portion indicated by dashed line L1-L2 in Figure 11A. Figure 11C is a cross-sectional view of a portion indicated by dashed line W1-W2 in Figure 11A. Note that in the top view of Figure 11A, some elements are omitted for clarity.

[0308] 11A, 11B, and 11C show a transistor 510A, and insulators 511, 512, 514, 516, 580, 582, and 584 which function as interlayer films. Also shown are a conductor 546 (conductor 546a and conductor 546b) which is electrically connected to the transistor 510A and functions as a contact plug, and a conductor 503 which functions as a wiring.

[0309] Transistor 510A has a conductor 560 (conductor 560a and conductor 560b) that functions as a first gate electrode, a conductor 505 (conductor 505a and conductor 505b) that functions as a second gate electrode, an insulator 550 that functions as a first gate insulating film, insulators 521, 522, and 524 that function as a second gate insulating film, an oxide 530 (oxide 530a, oxide 530b, and oxide 530c) having a region where a channel is formed, a conductor 542a that functions as one of a source or a drain, a conductor 542b that functions as the other of the source or a drain, and an insulator 574.

[0310] 11A, 11B, and 11C, the oxide 530c, the insulator 550, and the conductor 560 are disposed in an opening in the insulator 580 with the insulator 574 interposed therebetween. The oxide 530c, the insulator 550, and the conductor 560 are disposed between the conductor 542a and the conductor 542b.

[0311] The insulators 511 and 512 function as interlayer films.

[0312] As the interlayer film, a single layer or a laminated layer of an insulator such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulators.

[0313] For example, the insulator 511 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, the insulator 511 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (through which the above impurities are unlikely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (through which the above oxygen is unlikely to permeate). Furthermore, for example, aluminum oxide or silicon nitride may be used as the insulator 511. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side through the insulator 511.

[0314] For example, the insulator 512 preferably has a lower dielectric constant than the insulator 511. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0315] The conductor 503 is formed so as to be embedded in the insulator 512. Here, the height of the top surface of the conductor 503 and the height of the top surface of the insulator 512 can be made approximately the same. Note that although the conductor 503 is shown as being a single layer, the present invention is not limited to this. For example, the conductor 503 may be a multilayer film structure having two or more layers. Note that the conductor 503 is preferably made of a highly conductive material containing tungsten, copper, or aluminum as a main component.

[0316] In the transistor 510A, the conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 505 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 510A can be controlled by changing the potential applied to the conductor 505 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 505, the threshold voltage of the transistor 510A can be made higher than 0 V, thereby reducing the off-current. Therefore, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller when a negative potential is applied to the conductor 505 than when a negative potential is not applied.

[0317] Furthermore, for example, by overlapping the conductor 505 and the conductor 560, when a potential is applied to the conductor 560 and the conductor 505, the electric field generated from the conductor 560 and the electric field generated from the conductor 505 can be connected and can cover the channel formation region formed in the oxide 530.

[0318] That is, the channel formation region can be electrically surrounded by the electric field of the conductor 560 functioning as the first gate electrode and the electric field of the conductor 505 functioning as the second gate electrode. That is, like the transistor 500 described above, this has a surrounded channel (S-channel) structure.

[0319] The insulator 514 and the insulator 516 function as an interlayer film, similar to the insulator 511 or the insulator 512. For example, the insulator 514 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 510A from the substrate side. With this structure, impurities such as hydrogen and water can be suppressed from diffusing from the substrate side to the transistor 510A side through the insulator 514. For example, the insulator 516 preferably has a lower dielectric constant than the insulator 514. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0320] The conductor 505 functioning as the second gate has a conductor 505a formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 505b formed further inside. Here, the height of the top surfaces of the conductor 505a and the conductor 505b can be made approximately the same as the height of the top surface of the insulator 516. Note that although the transistor 510A has a structure in which the conductor 505a and the conductor 505b are stacked, the present invention is not limited to this. For example, the conductor 505 may have a single layer structure or a stacked structure of three or more layers.

[0321] Here, the conductor 505a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (through which the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (through which the above oxygen is difficult to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the above impurities and oxygen.

[0322] For example, the conductor 505a has a function of suppressing the diffusion of oxygen, so that the conductor 505b can be prevented from being oxidized and causing a decrease in electrical conductivity.

[0323] In addition, when the conductor 505 also functions as a wiring, it is preferable that the conductor 505b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. In that case, the conductor 503 is not necessarily provided. Although the conductor 505b is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material.

[0324] The insulators 521, 522, and 524 function as a second gate insulating film.

[0325] The insulator 522 preferably has a barrier property. When the insulator 522 has a barrier property, it functions as a layer that prevents impurities such as hydrogen from entering the transistor 510A from the periphery of the transistor 510A.

[0326] The insulator 522 is preferably a single layer or a multilayer insulator containing, for example, aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0327] In addition, it is preferable that the insulator 521 is thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining a high-k material insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 521 having a thermally stable laminated structure with a high relative dielectric constant.

[0328] 11B and 11C show a three-layered structure as the second gate insulating film, but it may have a two-layered or less, or four-layered or more. In that case, it is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0329] The oxide 530 having a region functioning as a channel formation region includes an oxide 530a, an oxide 530b on the oxide 530a, and an oxide 530c on the oxide 530b. By providing the oxide 530a under the oxide 530b, it is possible to suppress the diffusion of impurities from a structure formed below the oxide 530a to the oxide 530b. By providing the oxide 530c on the oxide 530b, it is possible to suppress the diffusion of impurities from a structure formed above the oxide 530c to the oxide 530b. An oxide semiconductor, which is one of the above-mentioned metal oxides, can be used as the oxide 530.

[0330] Note that the oxide 530c is preferably provided in an opening in the insulator 580 via the insulator 574. When the insulator 574 has a barrier property, diffusion of impurities from the insulator 580 to the oxide 530 can be suppressed.

[0331] One of the conductors 542 (conductor 542a and conductor 542b) functions as a source electrode, and the other functions as a drain electrode.

[0332] The conductor 542a and the conductor 542b can be made of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing these as a main component. In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.

[0333] 11B shows a single-layer structure for conductor 542a and conductor 542b, but a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be laminated. A titanium film and an aluminum film may be laminated. A two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0334] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated with an aluminum film or copper film on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated with an aluminum film or copper film on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0335] A barrier layer may be provided over the conductor 542. The barrier layer is preferably formed using a substance having a barrier property against oxygen or hydrogen. With this structure, oxidation of the conductor 542 can be suppressed when the insulator 574 is formed.

[0336] For example, a metal oxide can be used for the barrier layer. In particular, it is preferable to use an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide. Silicon nitride formed by a CVD method may also be used.

[0337] The inclusion of the barrier layer can broaden the range of material choices for the conductor 542. For example, a material that has low oxidation resistance but high conductivity, such as tungsten or aluminum, can be used for the conductor 542. In addition, for example, a conductor that is easy to form or process can be used.

[0338] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably provided in an opening provided in the insulator 580 with the oxide 530c and the insulator 574 interposed therebetween.

[0339] As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. In that case, the insulator 550 may have a laminated structure, as with the second gate insulating film. By making the insulator functioning as the gate insulating film a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0340] The conductor 560 functioning as the first gate electrode has a conductor 560a and a conductor 560b on the conductor 560a. As with the conductor 505a, the conductor 560a is preferably made of a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, the conductor 560a is preferably made of a conductive material having a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like).

[0341] The conductor 560a has a function of suppressing the diffusion of oxygen, which widens the range of material choices for the conductor 560b. In other words, the inclusion of the conductor 560a suppresses oxidation of the conductor 560b, thereby preventing a decrease in electrical conductivity.

[0342] As the conductive material having the function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, an oxide semiconductor that can be used as the oxide 530 can be used as the conductor 560a. In this case, the electric resistance value of the conductor 560a can be reduced by forming the conductor 560b by a sputtering method, thereby making the conductor 560a a conductor. This can be called an OC (Oxide Conductor) electrode.

[0343] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0344] An insulator 574 is disposed between the insulator 580 and the transistor 510A. The insulator 574 may be an insulating material that has a function of suppressing diffusion of impurities such as water or hydrogen, and oxygen. For example, aluminum oxide or hafnium oxide may be preferably used. In addition, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0345] The insulator 574 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 574 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0346] Insulator 580, insulator 582, and insulator 584 function as interlayer films.

[0347] Like the insulator 514, the insulator 582 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 510A from the outside.

[0348] Similarly to the insulator 516, the insulators 580 and 584 preferably have a lower dielectric constant than the insulator 582. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0349] Additionally, transistor 510A may be electrically connected to other structures through plugs or wiring, such as conductor 546 embedded in insulator 580, insulator 582, and insulator 584.

[0350] As the material of the conductor 546, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a single layer or a stacked layer, similar to the conductor 505. For example, it is preferable to use a high-melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Alternatively, it is preferable to form the conductor 546 from a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0351] For example, by using a layered structure of tantalum nitride, a conductor having barrier properties against hydrogen and oxygen, and tungsten, which has high conductivity, as the conductor 546, it is possible to suppress the diffusion of impurities from the outside while maintaining the conductivity as a wiring.

[0352] With the above structure, a semiconductor device including a transistor having an oxide semiconductor and high on-state current can be provided. Alternatively, a semiconductor device including a transistor having an oxide semiconductor and low off-state current can be provided. Alternatively, a semiconductor device in which fluctuation in electrical characteristics is suppressed, which has stable electrical characteristics and improved reliability can be provided.

[0353] <Transistor structure example 2> A structural example of a transistor 510B will be described with reference to Figures 12A, 12B, and 12C. Figure 12A is a top view of the transistor 510B. Figure 12B is a cross-sectional view of a portion indicated by dashed dotted line L1-L2 in Figure 12A. Figure 12C is a cross-sectional view of a portion indicated by dashed dotted line W1-W2 in Figure 12A. Note that in the top view of Figure 12A, some elements are omitted for clarity.

[0354] The transistor 510B is a modified example of the transistor 510A. Therefore, in order to avoid repetition of the description, the following description will mainly focus on the differences from the transistor 510A.

[0355] The transistor 510B has a region in which the conductor 542 (the conductor 542a and the conductor 542b) overlaps with the oxide 530c, the insulator 550, and the conductor 560. With this structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.

[0356] The conductor 560 functioning as the first gate electrode has a conductor 560a and a conductor 560b on the conductor 560a. As with the conductor 505a, the conductor 560a is preferably made of a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, the conductor 560a is preferably made of a conductive material having a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like).

[0357] The conductor 560a has a function of suppressing the diffusion of oxygen, and thus the width of the conductor 560b can be increased. In other words, the presence of the conductor 560a suppresses oxidation of the conductor 560b, and prevents a decrease in electrical conductivity.

[0358] It is preferable to provide an insulator 574 so as to cover the top surface and side surface of the conductor 560, the side surface of the insulator 550, and the side surface of the oxide 530c. Note that the insulator 574 may be made of an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may also be used.

[0359] Providing the insulator 574 can suppress oxidation of the conductor 560. Furthermore, providing the insulator 574 can suppress diffusion of impurities such as water and hydrogen contained in the insulator 580 to the transistor 510B.

[0360] Furthermore, an insulator 576 (insulator 576a and insulator 576b) having barrier properties may be disposed between the conductor 546 and the insulator 580. Providing the insulator 576 can prevent oxygen in the insulator 580 from reacting with the conductor 546 and oxidizing the conductor 546.

[0361] Furthermore, by providing the insulator 576 having a barrier property, the range of materials that can be selected for the conductor used for the plug or wiring can be expanded. For example, by using a metal material that has a property of absorbing oxygen and has high conductivity for the conductor 546, a semiconductor device with low power consumption can be provided. Specifically, a material that has low oxidation resistance but high conductivity, such as tungsten or aluminum, can be used. Also, for example, a conductor that is easy to form or process can be used.

[0362] <Transistor structure example 3> A structural example of a transistor 510C will be described with reference to Figures 13A, 13B, and 13C. Figure 13A is a top view of the transistor 510C. Figure 13B is a cross-sectional view of a portion indicated by dashed line L1-L2 in Figure 13A. Figure 13C is a cross-sectional view of a portion indicated by dashed line W1-W2 in Figure 13A. Note that in the top view of Figure 13A, some elements are omitted for clarity.

[0363] The transistor 510C is a modified example of the transistor 510A. Therefore, in order to avoid repetition of the description, the following description will mainly focus on the differences from the transistor 510A.

[0364] In the transistor 510C shown in FIGS. 13A, 13B, and 13C, a conductor 547a is disposed between the conductor 542a and the oxide 530b, and a conductor 547b is disposed between the conductor 542b and the oxide 530b. Here, the conductor 542a (conductor 542b) extends beyond the upper surface of the conductor 547a (conductor 547b) and the side surface on the conductor 560 side, and has a region in contact with the upper surface of the oxide 530b. Here, the conductor 547 may be any conductor that can be used for the conductor 542. Furthermore, the thickness of the conductor 547 is preferably at least thicker than that of the conductor 542.

[0365] 13A, 13B, and 13C has the above-described structure, and therefore the conductor 542 can be closer to the conductor 560 than in the transistor 510A. Alternatively, the ends of the conductor 542a and the conductor 542b can overlap with the conductor 560. This can shorten the effective channel length of the transistor 510C, and improve the on-state current and frequency characteristics.

[0366] The conductor 547a (conductor 547b) is preferably provided so as to overlap the conductor 542a (conductor 542b). With this configuration, the conductor 547a (conductor 547b) functions as a stopper in etching to form an opening in which the conductor 546a (conductor 546b) is to be embedded, thereby preventing the oxide 530b from being overetched.

[0367] 13A, 13B, and 13C may have a structure in which an insulator 545 is disposed on and in contact with an insulator 544. The insulator 544 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen or excess oxygen from entering the transistor 510C from the insulator 580 side. The insulator 545 can be any insulator that can be used for the insulator 544. The insulator 544 may be a nitride insulator such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon nitride oxide.

[0368] 11A, 11B, and 11C, the transistor 510C shown in FIG. 13A, 13B, and 13C may have a single-layer structure of the conductor 505. In this case, an insulating film to be the insulator 516 may be formed on the patterned conductor 505, and the upper part of the insulating film may be removed by a CMP method or the like until the upper surface of the conductor 505 is exposed. Here, it is preferable to improve the flatness of the upper surface of the conductor 505. For example, the average surface roughness (Ra) of the upper surface of the conductor 505 may be 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. This improves the flatness of the insulating layer formed on the conductor 505, and improves the crystallinity of the oxide 530b and the oxide 530c.

[0369] <Transistor structure example 4> A structural example of a transistor 510D will be described with reference to Figures 14A, 14B, and 14C. Figure 14A is a top view of the transistor 510D. Figure 14B is a cross-sectional view of a portion indicated by dashed line L1-L2 in Figure 14A. Figure 14C is a cross-sectional view of a portion indicated by dashed line W1-W2 in Figure 14A. Note that in the top view of Figure 14A, some elements are omitted for clarity.

[0370] The transistor 510D is a variation of the transistor described above, and therefore, in order to avoid repetition of the description, the differences from the transistor described above will be mainly described.

[0371] 14A to 14C, the conductor 503 is not provided, and the conductor 505 having a function as the second gate also functions as a wiring. An insulator 550 is provided over the oxide 530c, and a metal oxide 552 is provided over the insulator 550. A conductor 560 is provided over the metal oxide 552, and an insulator 570 is provided over the conductor 560. An insulator 571 is provided over the insulator 570.

[0372] The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 552, which suppresses oxygen diffusion, between the insulator 550 and the conductor 560, the diffusion of oxygen to the conductor 560 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 by oxygen can be suppressed.

[0373] Note that the metal oxide 552 may function as a part of the first gate. For example, an oxide semiconductor that can be used as the oxide 530 can be used as the metal oxide 552. In that case, by forming the conductor 560 by a sputtering method, the electric resistance value of the metal oxide 552 can be reduced to form a conductive layer. This can be called an OC (Oxide Conductor) electrode.

[0374] Furthermore, the metal oxide 552 may function as a part of the gate insulating film. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 550, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant for the metal oxide 552. By using such a stacked structure, a stacked structure that is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as a gate insulating film.

[0375] Although the metal oxide 552 in the transistor 510D is shown as a single layer, it may have a stacked structure of two or more layers. For example, a metal oxide functioning as part of a gate electrode and a metal oxide functioning as part of a gate insulating film may be stacked.

[0376] When the metal oxide 552 functions as a gate electrode, the on-state current of the transistor 510D can be improved without weakening the influence of the electric field from the conductor 560. Alternatively, when the metal oxide 552 functions as a gate insulating film, the physical thickness of the insulator 550 and the metal oxide 552 can maintain a distance between the conductor 560 and the oxide 530, thereby suppressing leakage current between the conductor 560 and the oxide 530. Therefore, by providing a stacked structure of the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the oxide 530 and the electric field strength applied from the conductor 560 to the oxide 530 can be easily and appropriately adjusted.

[0377] Specifically, an oxide semiconductor that can be used for the oxide 530 can be reduced in resistance to be used as the metal oxide 552. Alternatively, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

[0378] In particular, it is preferable to use an insulating layer containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later process. Note that the metal oxide 552 is not an essential component. It may be appropriately designed depending on the desired transistor characteristics.

[0379] The insulator 570 may be made of an insulating material that has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. This can suppress the conductor 560 from being oxidized by oxygen from above the insulator 570. In addition, impurities such as water or hydrogen from above the insulator 570 can be suppressed from being mixed into the oxide 530 through the conductor 560 and the insulator 550.

[0380] The insulator 571 functions as a hard mask. By providing the insulator 571, when the conductor 560 is processed, the side surface of the conductor 560 can be approximately vertical, specifically, the angle between the side surface of the conductor 560 and the substrate surface can be set to 75 degrees or more and 100 degrees or less, preferably 80 degrees or more and 95 degrees or less.

[0381] Note that the insulator 571 may also function as a barrier layer by using an insulating material that has a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 570 is not necessarily provided.

[0382] Using insulator 571 as a hard mask, portions of insulator 570, conductor 560, metal oxide 552, insulator 550, and oxide 530c can be selectively removed to roughly align their sides and expose a portion of the surface of oxide 530b.

[0383] Transistor 510D also has regions 531a and 531b on a portion of the exposed oxide 530b surface, with either region 531a or region 531b functioning as a source region and the other functioning as a drain region.

[0384] The formation of the regions 531a and 531b can be achieved by introducing an impurity element such as phosphorus or boron into the exposed surface of the oxide 530b by, for example, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, etc. In this embodiment and the like, the term "impurity element" refers to an element other than the main component element.

[0385] In addition, a metal film can be formed after exposing a portion of the surface of oxide 530b, and then heat-treated to diffuse elements contained in the metal film into oxide 530b, thereby forming regions 531a and 531b.

[0386] The region of the oxide 530b into which the impurity element has been introduced has a reduced electrical resistivity, and therefore the region 531a and the region 531b are sometimes referred to as "impurity region" or "low resistance region."

[0387] By using the insulator 571 and / or the conductor 560 as a mask, the regions 531a and 531b can be formed in a self-aligned manner. Therefore, the regions 531a and / or 531b do not overlap with the conductor 560, and parasitic capacitance can be reduced. In addition, an offset region is not formed between the channel formation region and the source / drain region (region 531a or region 531b). By forming the regions 531a and 531b in a self-aligned manner, it is possible to realize an increase in on-current, a reduction in threshold voltage, an improvement in operating frequency, and the like.

[0388] In order to further reduce the off-state current, an offset region may be provided between the channel formation region and the source / drain region. The offset region is a region having high electrical resistivity, into which the above-described impurity element is not introduced. The offset region can be formed by introducing the above-described impurity element after the formation of the insulator 575. In this case, the insulator 575 also functions as a mask, similar to the insulator 571. Therefore, the impurity element is not introduced into the region of the oxide 530b that overlaps with the insulator 575, and the electrical resistivity of the region can be kept high.

[0389] The transistor 510D also has an insulator 575 on the side surfaces of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the oxide 530c. The insulator 575 is preferably an insulator with a low dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin is preferable. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having voids is used for the insulator 575, it is preferable because an excess oxygen region can be easily formed in the insulator 575 in a later step. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. The insulator 575 also preferably has a function of diffusing oxygen.

[0390] The transistor 510D further includes an insulator 575 and an insulator 574 over the oxide 530. The insulator 574 is preferably formed by a sputtering method. By using a sputtering method, an insulator containing few impurities such as water or hydrogen can be formed. For example, aluminum oxide is preferably used as the insulator 574.

[0391] Note that an oxide film formed by a sputtering method may extract hydrogen from a structure to be deposited. Therefore, the insulator 574 absorbs hydrogen and water from the oxide 530 and the insulator 575, thereby reducing the hydrogen concentrations in the oxide 530 and the insulator 575.

[0392] <Transistor structure example 5> A structural example of a transistor 510E will be described with reference to Figures 15A, 15B, and 15C. Figure 15A is a top view of the transistor 510E. Figure 15B is a cross-sectional view of a portion indicated by dashed line L1-L2 in Figure 15A. Figure 15C is a cross-sectional view of a portion indicated by dashed line W1-W2 in Figure 15A. Note that in the top view of Figure 15A, some elements are omitted for clarity.

[0393] The transistor 510E is a variation of the transistor described above, and therefore, in order to avoid repetition of description, the following description will focus mainly on the differences from the transistor described above.

[0394] 15A to 15C, the conductor 542 is not provided, and the exposed oxide 530b has a region 531a and a region 531b on a part of the surface. One of the region 531a and the region 531b functions as a source region, and the other functions as a drain region. An insulator 573 is provided between the oxide 530b and the insulator 574.

[0395] 15B, a region 531 (region 531a and region 531b) is a region in which the following elements are added to an oxide 530b: The region 531 can be formed by using, for example, a dummy gate.

[0396] Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask to add an element that reduces the resistance of the oxide 530b. That is, the element is added to a region where the oxide 530 does not overlap with the dummy gate, forming a region 531. The element can be added by an ion implantation method in which an ionized source gas is added after being mass-separated, an ion doping method in which an ionized source gas is added without being mass-separated, a plasma immersion ion implantation method, or the like.

[0397] Representative elements that reduce the resistance of the oxide 530 include boron and phosphorus. Hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, and the like may also be used. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. The concentration of the element may be measured using SIMS or the like.

[0398] In particular, boron and phosphorus are preferable because, for example, equipment in a low-temperature polysilicon production line can be used, and existing facilities can be repurposed, thereby reducing capital investment.

[0399] Subsequently, an insulating film to be the insulator 573 and an insulating film to be the insulator 574 may be formed over the oxide 530b and the dummy gate. By stacking the insulating film to be the insulator 573 and the insulating film to be the insulator 574, a region in which the region 531 overlaps with the oxide 530c and the insulator 550 can be provided.

[0400] Specifically, an insulating film to be the insulator 580 is provided on an insulating film to be the insulator 574, and then a CMP process is performed on the insulating film to be the insulator 580 to remove a part of the insulating film to be the insulator 580 and expose the dummy gate. Then, when removing the dummy gate, a part of the insulator 573 in contact with the dummy gate may also be removed. Therefore, the insulator 574 and the insulator 573 are exposed on the side of the opening provided in the insulator 580, and a part of the region 531 provided in the oxide 530b is exposed on the bottom of the opening. Next, an oxide film to be the oxide 530c, an insulating film to be the insulator 550, and a conductive film to be the conductor 560 are sequentially formed in the opening, and then the oxide film to be the oxide 530c, the insulating film to be the insulator 550, and a conductive film to be the conductor 560 are removed by CMP or the like until the insulator 580 is exposed, thereby forming the transistor shown in FIG. 15A to FIG. 15C.

[0401] Note that the insulators 573 and 574 are not essential components and may be appropriately designed depending on desired transistor characteristics.

[0402] The transistors shown in FIGS. 15A to 15C can use existing devices and further, since the conductor 542 is not provided, costs can be reduced.

[0403] <Transistor structure example 6> A structural example of a transistor 510F will be described with reference to Figures 16A, 16B, and 16C. Figure 16A is a top view of the transistor 510F. Figure 16B is a cross-sectional view of a portion indicated by a dashed line L1-L2 in Figure 16A. Figure 16C is a cross-sectional view of a portion indicated by a dashed line W1-W2 in Figure 16A. Note that in the top view of Figure 16A, some elements are omitted for clarity.

[0404] The transistor 510F is a modified example of the transistor 510A. Therefore, in order to avoid repetition of the description, the following description will focus mainly on the differences from the above transistor.

[0405] In transistor 510A, a portion of insulator 574 is provided in an opening provided in insulator 580 and is provided so as to cover the side surface of conductor 560. On the other hand, in transistor 510F, an opening is formed by removing a portion of insulator 580 and insulator 574.

[0406] Furthermore, an insulator 576 (insulator 576a and insulator 576b) having barrier properties may be disposed between the conductor 546 and the insulator 580. Providing the insulator 576 can prevent oxygen in the insulator 580 from reacting with the conductor 546 and oxidizing the conductor 546.

[0407] In addition, when an oxide semiconductor is used as the oxide 530, it is preferable to have a stacked structure of a plurality of oxide layers having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a. In addition, the oxide 530c can be a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0408] The oxide 530a, the oxide 530b, and the oxide 530c are preferably crystalline, and in particular, CAAC-OS is preferably used. Crystalline oxides such as CAAC-OS have few impurities and defects (oxygen vacancies, etc.), and have a dense structure with high crystallinity. This can suppress the source electrode or the drain electrode from extracting oxygen from the oxide 530b. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 530b can be reduced, and the transistor 510F is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0409] One or both of the oxide 530a and the oxide 530c may be omitted. The oxide 530 may be a single layer of the oxide 530b. When the oxide 530 is a stack of the oxides 530a, 530b, and 530c, it is preferable that the energy of the conduction band minimum of the oxide 530a and the oxide 530c is higher than the energy of the conduction band minimum of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a and the oxide 530c is smaller than the electron affinity of the oxide 530b. In this case, it is preferable that the oxide 530c is made of a metal oxide that can be used for the oxide 530a. Specifically, it is preferable that the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530c is larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for oxide 530c, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. In addition, in the metal oxide used for oxide 530b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 530c.

[0410] Here, the energy level of the conduction band minimum changes gradually at the junction of the oxide 530a, the oxide 530b, and the oxide 530c. In other words, it can be said that the energy level of the conduction band minimum at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c.

[0411] Specifically, the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element other than oxygen (as a main component), so that a mixed layer with a low defect level density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and the oxide 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like. The oxide 530c may also have a laminated structure. For example, a laminated structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a laminated structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide can be used. In other words, a laminated structure of an In-Ga-Zn oxide and an oxide not containing In may be used as the oxide 530c.

[0412] Specifically, the oxide 530a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. The oxide 530b may be a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or 3:1:2. The oxide 530c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0413] At this time, the main path of the carriers is the oxide 530b. By configuring the oxide 530a and the oxide 530c as described above, the defect level density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of the interface scattering on the carrier conduction is reduced, and the transistor 510F can obtain a high on-current and high frequency characteristics. When the oxide 530c has a stacked structure, in addition to the effect of reducing the defect level density at the interface between the oxide 530b and the oxide 530c, it is expected that the constituent elements of the oxide 530c can be suppressed from diffusing to the insulator 550 side. More specifically, the oxide 530c has a stacked structure, and an oxide not containing In is positioned above the stacked structure, so that In that may diffuse to the insulator 550 side can be suppressed. Since the insulator 550 functions as a gate insulator, if In diffuses, the transistor characteristics become poor. Therefore, by forming the oxide 530c into a layered structure, a highly reliable semiconductor device can be provided.

[0414] The oxide 530 is preferably a metal oxide that functions as an oxide semiconductor. For example, a metal oxide that serves as a channel formation region of the oxide 530 has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap in this manner, the off-state current of the transistor can be reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0415] <Transistor structure example 7> A structural example of a transistor 510G will be described with reference to Figures 17A and 17B. The transistor 510G is a variation of the transistor 500. Therefore, to avoid repetition of the description, differences from the above transistor will be mainly described. Note that the structure illustrated in Figures 17A and 17B can also be applied to other transistors included in a semiconductor device of one embodiment of the present invention, such as the transistor 300.

[0416] 17A is a cross-sectional view of the transistor 510G in the channel length direction, and FIG. 17B is a cross-sectional view of the transistor 510G in the channel width direction. The transistor 510G shown in FIGS. 17A and 17B differs from the transistor 500 shown in FIGS. 10A and 10B in that the transistor 510G includes an insulator 402 and an insulator 404. The transistor 510G also differs from the transistor 500 shown in FIGS. 10A and 10B in that an insulator 551 is provided in contact with a side surface of the conductor 540a and an insulator 551 is provided in contact with a side surface of the conductor 540b. The transistor 510G also differs from the transistor 500 shown in FIGS. 10A and 10B in that the transistor 510G does not include an insulator 520.

[0417] 17A and 17B, the insulator 402 is provided over the insulator 512. Furthermore, the insulator 404 is provided over the insulator 574 and the insulator 402.

[0418] 17A and 17B, the insulator 514, the insulator 516, the insulator 522, the insulator 524, the insulator 544, the insulator 580, and the insulator 574 are patterned, and the insulator 404 covers them. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 402. As a result, the oxide 530 and the like are isolated from the outside by the insulator 404 and the insulator 402.

[0419] The insulators 402 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules) or water molecules. For example, the insulators 402 and 404 are preferably made of silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration of the characteristics of the transistor 510G. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0420] The insulator 551 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 551 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 551 is preferably made of an insulator having a high hydrogen barrier property, such as silicon nitride, aluminum oxide, or silicon nitride oxide. In particular, silicon nitride is a material having a high hydrogen barrier property, and is therefore suitable for use as the insulator 551. By using a material having a high hydrogen barrier property as the insulator 551, impurities such as water or hydrogen can be suppressed from diffusing from the insulator 580 or the like to the oxide 530 through the conductor 540a and the conductor 540b. Furthermore, oxygen contained in the insulator 580 can be suppressed from being absorbed by the conductor 540a and the conductor 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0421] 18 is a cross-sectional view illustrating a configuration example of a semiconductor device in which the transistor 500 and the transistor 300 have the configurations illustrated in FIGS. 17A and 17B. An insulator 551 is provided on a side surface of a conductor 546.

[0422] 19A and 19B are modified examples of the transistor shown in FIG. 17A and FIG. 17B. FIG. 19A is a cross-sectional view of the transistor in the channel length direction, and FIG. 19B is a cross-sectional view of the transistor in the channel width direction. The transistor shown in FIG. 19A and FIG. 19B is different from the transistor shown in FIG. 17A and FIG. 17B in that the oxide 530c has a two-layer structure of an oxide 530c1 and an oxide 530c2.

[0423] The oxide 530c1 is in contact with the top surface of the insulator 524, the side surface of the oxide 530a, the top surface and side surface of the oxide 530b, the side surfaces of the conductors 542a and 542b, the side surface of the insulator 544, and the side surface of the insulator 580. The oxide 530c2 is in contact with the insulator 550.

[0424] The oxide 530c1 may be, for example, an In-Zn oxide. The oxide 530c2 may be the same material as that used for the oxide 530c when the oxide 530c has a single-layer structure. For example, the oxide 530c2 may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5.

[0425] By forming the oxide 530c in a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be, for example, a power MOS transistor. The oxide 530c of the transistor shown in FIG. 10A and FIG. 10B can also have a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0426] The transistors shown in FIGS. 19A and 19B may be applied to, for example, transistor 500, transistor 300, or both.

[0427] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0428] (Embodiment 4) In this embodiment, a cloud-aligned composite oxide semiconductor (CAC-OS) and a c-axis aligned crystalline oxide semiconductor (CAAC-OS), which are metal oxides that can be used for the OS transistor described in the above embodiment, will be described.

[0429] <Metal oxide composition> CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor as a whole. When CAC-OS or CAC-metal oxide is used in an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) as carriers, and the insulating function is a function of not flowing electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0430] Moreover, the CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected in a cloud shape with a blurred periphery.

[0431] In addition, in the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may each be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0432] In addition, the CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In this configuration, when carriers are caused to flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily on the component having the wide gap, and carriers also flow in the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force in the on state of the transistor, that is, a large on-current and a high field effect mobility can be obtained.

[0433] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0434] <Metal oxide structure> Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0435] In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of the crystal structure of oxide semiconductors will be described with reference to Fig. 20A. Fig. 20A is a diagram for explaining the classification of the crystal structure of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0436] As shown in FIG. 20A, IGZO is broadly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes c-axis aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). Crystalline excludes single crystal, poly crystal, and completely amorphous. Crystal includes single crystal and poly crystal.

[0437] The structure in the bold frame shown in Fig. 20A is an intermediate state between Amorphous and Crystal, and belongs to a new boundary region (New crystalline phase). This structure is in the boundary region between Amorphous and Crystal. In other words, this structure can be said to be a structure that is completely different from Amorphous, which is energetically unstable, or Crystal.

[0438] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) image. Here, XRD spectra of quartz glass and IGZO (also called crystalline IGZO) having a crystal structure classified as Crystalline are shown in Fig. 20B and Fig. 20C. Fig. 20B shows the XRD spectrum of quartz glass, and Fig. 20C shows the XRD spectrum of crystalline IGZO. The composition of the crystalline IGZO shown in Fig. 20C is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the crystalline IGZO shown in Fig. 20C is 500 nm.

[0439] As shown by the arrow in FIG. 20B, the shape of the peak in the XRD spectrum (indicated as "Intensity" in FIG. 20B and FIG. 20C) of silica glass is almost symmetrical. On the other hand, as shown by the arrow in FIG. 20C, the shape of the peak in the XRD spectrum of crystalline IGZO is asymmetrical. The asymmetric shape of the peak in the XRD spectrum clearly indicates the presence of crystals. In other words, if the shape of the peak in the XRD spectrum is not symmetrical, it cannot be said to be amorphous. Note that FIG. 20C clearly indicates the crystal phase (IGZO crystal phase) at or near 2θ=31°. It is presumed that the reason why the shape of the peak in the XRD spectrum is asymmetrical is due to the crystal phase (microcrystals).

[0440] Specifically, the XRD spectrum of crystalline IGZO shown in FIG. 20C has a peak at or near 2θ=34°. Microcrystals have a peak at or near 2θ=31°. When an oxide semiconductor film is evaluated using an X-ray diffraction image, the width of the spectrum on the low-angle side is wider than the peak at or near 2θ=34°, as shown in FIG. 20C. This suggests that the oxide semiconductor film contains microcrystals having a peak at or near 2θ=31°.

[0441] The crystal structure of the film can be evaluated from the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). Figure 20D shows the diffraction pattern of an IGZO film formed at room temperature on the substrate. The IGZO film shown in Figure 20D was formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. In the nanobeam electron diffraction method, electron diffraction was performed with a probe diameter of 1 nm.

[0442] As shown in Figure 20D, a spot-like pattern, not a halo, is observed in the diffraction pattern of the IGZO film deposited at room temperature. Therefore, it is presumed that the IGZO film deposited at room temperature is in an intermediate state, neither crystalline nor amorphous, and it cannot be concluded that it is in an amorphous state.

[0443] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a portion where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0444] Nanocrystals are basically hexagonal, but may be non-regular hexagonal. In addition, the lattice arrangement may be pentagonal or heptagonal due to the distortion. In CAAC-OS, no clear grain boundary can be confirmed even in the vicinity of the distortion. In other words, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms in the ab-plane direction is not dense and the bond distance between atoms changes due to the substitution of metal elements.

[0445] A crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor or a decrease in field-effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0446] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M can be substituted for each other, and when element M in an (M, Zn) layer is substituted for indium, it can also be represented as an (In, M, Zn) layer. When indium in an In layer is substituted for element M, it can also be represented as an (In, M) layer.

[0447] The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since no clear crystal grain boundaries can be identified in the CAAC-OS, it can be said that a decrease in electron mobility due to the crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0448] The nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0449] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0450] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0451] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0452] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0453] In addition, it is preferable to use an oxide semiconductor with low carrier density for the transistor. In order to reduce the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly pure intrinsic semiconductor or a substantially highly pure intrinsic semiconductor.

[0454] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0455] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0456] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0457] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0458] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as 2×10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0459] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor. Specifically, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is reduced to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0460] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier density increases, and the oxide semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen for a channel formation region is likely to have normally-on characteristics. Therefore, it is preferable that nitrogen be reduced as much as possible in the oxide semiconductor. For example, the nitrogen concentration in the oxide semiconductor is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0461] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0462] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0463] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification. [Explanation of symbols]

[0464] C11: capacitive element, C12: capacitive element, C21: capacitive element, C22: capacitive element, C41: capacitive element, C42: capacitive element, C61: capacitive element, C62: capacitive element, DV12: potential difference, DV13: potential difference, DV22: potential difference, DV23: potential difference, N11: node, N12: node, N21: node, N22: node, N41: node, N42: node, N61: node, N62: node, SI1: signal, SI1_IN: input terminal, SI1B: signal, SI1B_IN: input terminal, SI2: signal, SI2_IN: input terminal, SI2B: signal, SI2B_IN: input terminal, SO1: signal, SO1_OUT: output terminal, SO1B: signal, SO1B_OUT: output terminal, SO2: signal, SO2_OUT: output terminal, SO2B: signal, SO2B_OUT: output terminal, 10: semiconductor device, 11: transistor, 12: transistor, 13: transistor, 14: transistor, 15: transistor, 16: transistor, 17: transistor, 18: transistor, 20: semiconductor device, 21: transistor, 22: transistor, 23: transistor, 24: transistor, 25: transistor, 26: transistor, 31: transistor transistor, 31_1: transistor, 31_2: transistor, 32: transistor, 32_1: transistor, 32_2: transistor, 40: semiconductor device, 41: transistor, 42: transistor, 43: transistor, 44: transistor, 45: transistor, 46: transistor, 47: transistor, 48: transistor, 49: transistor, 50: transistor, 60: semiconductor device, 61: transistor, 62: transistor, 63: transistor, 64: transistor, 65: transistor, 66: transistor, 67: transistor , 68: transistor, 69: transistor, 70: transistor, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: insulator, 374: insulator, 376: conductor, 380: insulator,382: insulator, 384: insulator, 386: conductor, 402: insulator, 404: insulator, 500: transistor, 503: conductor, 503a: conductor, 503b: conductor, 505: conductor, 505a: conductor, 505b: conductor, 510: insulator, 510A: transistor, 510B: transistor, 510C: transistor, 510D: transistor, 510E: transistor, 51 0F: transistor, 510G: transistor, 511: insulator, 512: insulator, 514: insulator, 516: insulator, 518: conductor, 520: insulator, 521: insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 530c: oxide, 530c1: oxide, 530c2: oxide, 531: region, 531a: region, 531b: region, 54 0a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543: region, 543a: region, 543b: region, 544: insulator, 545: insulator, 546: conductor, 546a: conductor, 546b: conductor, 547: conductor, 547a: conductor, 547b: conductor, 548: conductor, 550: insulator, 551: insulator, 552: metal oxide, 560: conductor , 560a: conductor, 560b: conductor, 570: insulator, 571: insulator, 573: insulator, 574: insulator, 575: insulator, 576: insulator, 576a: insulator, 576b: insulator, 580: insulator, 581: insulator, 582: insulator, 584: insulator, 586: insulator, 600: capacitance element, 610: conductor, 612: conductor, 620: conductor, 630: insulator, 650: insulator,

Claims

1. first to sixth transistors; a first capacitance element and a second capacitance element; A first wiring and a second wiring; a first input terminal and a second input terminal; a first output terminal and a second output terminal; one of a source and a drain of the first transistor is always electrically connected to the first wiring, the other of the source and the drain of the first transistor is always electrically connected to the first output terminal; one of the source and the drain of the second transistor is always electrically connected to the first output terminal; the other of the source and the drain of the second transistor is always electrically connected to the second wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the third transistor is always electrically connected to the second input terminal; a gate of the third transistor is always electrically connected to the second wiring; one of a source and a drain of the fourth transistor is always electrically connected to the first wiring, the other of the source and the drain of the fourth transistor is always electrically connected to the second output terminal; one of the source and the drain of the fifth transistor is always electrically connected to the second output terminal; the other of the source and the drain of the fifth transistor is always electrically connected to the second wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the first input terminal; the gate of the sixth transistor is always electrically connected to the second wiring; a first electrode of the first capacitance element is always electrically connected to the first output terminal; a second electrode of the first capacitance element is always electrically connected to a gate of the second transistor; a first electrode of the second capacitance element is always electrically connected to the second output terminal; a second electrode of the second capacitance element is always electrically connected to a gate of the second transistor; Semiconductor device.

2. first to sixth transistors; a first capacitance element and a second capacitance element; A first wiring and a second wiring; a first input terminal and a second input terminal; a first output terminal and a second output terminal; one of a source and a drain of the first transistor is always electrically connected to the first wiring, the other of the source and the drain of the first transistor is always electrically connected to the first output terminal; one of the source and the drain of the second transistor is always electrically connected to the first output terminal; the other of the source and the drain of the second transistor is always electrically connected to the second wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the third transistor is always electrically connected to the second input terminal; a gate of the third transistor is always electrically connected to the second wiring; one of a source and a drain of the fourth transistor is always electrically connected to the first wiring, the other of the source and the drain of the fourth transistor is always electrically connected to the second output terminal; one of the source and the drain of the fifth transistor is always electrically connected to the second output terminal; the other of the source and the drain of the fifth transistor is always electrically connected to the second wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the first input terminal; the gate of the sixth transistor is always electrically connected to the second wiring; a first electrode of the first capacitance element is always electrically connected to the first output terminal; a second electrode of the first capacitance element is always electrically connected to a gate of the second transistor; a first electrode of the second capacitance element is always electrically connected to the second output terminal; a second electrode of the second capacitance element is always electrically connected to a gate of the second transistor; A first potential is supplied to the first wiring, A second potential is supplied to the second wiring, the second potential is higher than the first potential, A first digital signal is input to the first input terminal, a second digital signal is input to the second input terminal; the second signal is a signal obtained by inverting the logic of the first signal; Semiconductor device.

3. In claim 1 or 2, the first transistor to the sixth transistor are n-channel transistors; Semiconductor device.

4. In claim 1 or 2, the first transistor to the sixth transistor each have a metal oxide in a channel formation region; Semiconductor device.

5. In claim 4, The metal oxide is an oxide semiconductor containing at least one of indium and zinc. Semiconductor device.

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