Semiconductor device

Abstract

To provide a highly-reliable semiconductor device using an oxide semiconductor.SOLUTION: There is provided a semiconductor device that includes an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer, where the oxide semiconductor layer includes a first region having crystal of size of 10 nm or less, and a second region overlapping the insulating layer with the first region interposed therebetween and having a crystal portion in which a c axis is aligned in a direction parallel to a normal vector of a surface of the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed herein relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter In particular, the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, and a drive circuit thereof. For example, the present invention relates to a semiconductor device having an oxide semiconductor. The present invention relates to a semiconductor device, a display device, or a light-emitting device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to all devices, including electro-optical devices, semiconductor circuits, display devices, light-emitting devices, and electronic equipment. It is a body device. [Background technology]

[0003] The technology of constructing transistors using semiconductor films formed on substrates with insulating surfaces is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (also known simply as display devices). The term "transistor" is used in a wide range of electronic devices, including semiconductors. Silicon-based semiconductor materials are widely known as semiconductor films, but other materials with semiconductor properties are also available. Metal oxides (oxide semiconductors) that exhibit this property have been attracting attention.

[0004] For example, amorphous oxides containing In, Zn, Ga, Sn, etc. are used as oxide semiconductors. A technique for fabricating a transistor is disclosed in Patent Document 1.

[0005] Although it is relatively easy to obtain transistor characteristics using an oxide semiconductor, However, since the oxide semiconductor film is easily amorphous and has unstable physical properties, it is difficult to ensure reliability. do.

[0006] On the other hand, a transistor using a crystalline oxide semiconductor film is different from a transistor using an amorphous oxide semiconductor film. It has been reported that it has superior electrical properties and reliability compared to transistors (Non-Patent (See Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2006-165529 A [Non-patent literature]

[0008] [Non-Patent Document 1] Shunpei Yamazaki, Jun Koyama, Yoshitaka Yamamoto and Kenji Okamoto, “Research, Development, and Application of Crystalline Oxide Semiconductor” SID 2012 DIGEST pp183-186 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a highly reliable semiconductor device that includes an oxide semiconductor. It shall be one of the following.

[0010] Another object of one embodiment of the present invention is to provide a transistor or the like with low off-state current. Another embodiment of the present invention provides a normally-off transistor or the like. Another object of one embodiment of the present invention is to provide a semiconductor device that can suppress fluctuation or deterioration of a threshold voltage. Another object of the present invention is to provide a transistor or the like having a small number of transistors. Another object of the present invention is to provide a semiconductor device or the like with low power consumption. Another object of the present invention is to provide a display device or the like that is easy on the eyes. Another object of the present invention is to provide a semiconductor device or the like using a transparent semiconductor layer. An object of the present invention is to provide a novel semiconductor device and the like.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the disclosed invention is a semiconductor device including an oxide semiconductor layer and an insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region having crystals with a size of 10 nm or less, and The c-axis of the oxide semiconductor layer is aligned parallel to the normal vector of the surface of the oxide semiconductor layer. and a second region having a crystal portion. The semiconductor device has the following configuration.

[0013] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, and an oxide semiconductor a gate electrode layer overlapping the oxide semiconductor layer; and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. and a first electrode layer, the oxide semiconductor layer having a first region having crystals of 10 nm or less in size. The first region overlaps with the insulating layer with the first region sandwiched therebetween, and the c-axis is a normal vector of the surface of the oxide semiconductor layer. and a second region having crystal parts aligned in a direction parallel to the first region.

[0014] In the above, the first region and the second region have oxide semiconductors having different compositions. Good too.

[0015] In another embodiment of the present invention, a first insulating layer, an oxide semiconductor layer over the first insulating layer, and an oxide semiconductor layer a second insulating layer over the oxide semiconductor layer; a gate electrode layer overlying the oxide semiconductor layer; a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer; The layer includes a first region having crystals of 10 nm or less in size and a first insulating layer sandwiching the first region. A crystal part overlapping with the edge layer and having its c-axis aligned parallel to the normal vector of the surface of the oxide semiconductor layer. a second region having a size of 10 nm or less, the second region being located between the second region and the second insulating layer; and a third region having a zinc crystal.

[0016] In the above, the first region and the second region have oxide semiconductors having different compositions. The second region and the third region may have oxide semiconductors having different compositions. Good too.

[0017] In the semiconductor device described above, the third region has a beam diameter of the electron beam of 1 nmφ or more and 10 nmφ or less. By focusing the electron microbeam diffraction, multiple spots distributed in a circular pattern were observed. A limited-field transmission electron microscope with an electron beam diameter of 300 nm or more In electron diffraction, a halo pattern can sometimes be observed.

[0018] In the semiconductor device, the first region is configured to have an electron beam diameter of 1 nmφ or more and 10 By using ultrafine electron diffraction focused to less than nmφ, multiple spots distributed circumferentially were observed. The electron beam diameter was 300 nm or more. In limited-area electron diffraction, a halo pattern can sometimes be observed.

[0019] In the above semiconductor device, the film density of the second region is higher than the film density of the first region. It is preferable that

[0020] In the above semiconductor device, a channel is preferably formed in the second region. Effect of the Invention

[0021] According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a schematic diagram illustrating an example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic diagram showing a state of sputtering particles peeling off from a sputtering target. [Diagram 3] FIG. 2 is a diagram for explaining a discharge state during sputtering using an AC power source. [Figure 4] FIG. 2 is a schematic diagram showing how sputtered particles reach a deposition surface when a substrate is heated. [Diagram 5] FIG. 2 is a schematic diagram showing how sputtered particles reach a deposition surface during deposition at room temperature. [Figure 6] 1A to 1C are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 7] FIG. 2 is a flow diagram showing an example of a method for producing a sputtering target. [Figure 8]1A and 1B are schematic diagrams illustrating an example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention, and diagrams illustrating its band structure. [Figure 9] 1A to 1C illustrate examples of the structure of a transistor according to an embodiment. [Figure 10] 1A to 1C illustrate an example of a method for manufacturing a transistor according to an embodiment. [Figure 11] 1A to 1C illustrate examples of the structure of a transistor according to an embodiment. [Figure 12] FIG. 1 is a circuit diagram of a semiconductor device of one embodiment of the present invention. [Figure 13] 1A and 1B are a circuit diagram and a conceptual diagram of a semiconductor device of one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a structure of a display panel according to an embodiment. [Figure 15] 1A to 1C are block diagrams illustrating electronic devices according to an embodiment. [Figure 16] 1A to 1C are diagrams illustrating external views of electronic devices according to an embodiment. [Figure 17] 1A and 1B show a cross-sectional TEM image and a microelectron beam diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 18] 1A and 1B show a planar TEM image and a selected area electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 19] Schematic diagram of electron diffraction intensity distribution. [Figure 20] FIG. 2 is a diagram showing an electron microbeam diffraction pattern of a quartz glass substrate. [Figure 21] 1 shows a microelectron beam diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 22] FIG. 2 shows a cross-sectional TEM image of a nanocrystalline oxide semiconductor layer. [Figure 23] FIG. 13 shows the results of X-ray diffraction analysis of a nanocrystalline oxide semiconductor layer. [Figure 24] 1A and 1B show crystal structures of oxide semiconductor layers used in calculation. [Diagram 25] Calculation results showing the effect of hydrogen addition on the crystal state. [Figure 26] Calculation results using radial distribution function. [Figure 27]13A to 13C are diagrams showing electron microbeam diffraction patterns of an oxide semiconductor layer using an electron microbeam; [Figure 28] 13A and 13B show the results of CPM measurement of an oxide semiconductor layer. [Figure 29] 13A and 13B show the results of CPM measurement of an oxide semiconductor layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and those skilled in the art will recognize that the present invention can be modified in various ways. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that is done.

[0024] In each figure described in this specification, the size, thickness, or area of ​​each component is not clearly indicated. The figures may be exaggerated for illustrative purposes and are not necessarily limited to scale.

[0025] In this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of steps or the order of layers. It does not indicate a specific name as a matter for the purpose of

[0026] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle between 80° and 100°. Therefore, cases between 85° and 95° are also included.

[0027] In this specification and the like, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0028] (Embodiment 1) In this embodiment, with respect to an oxide semiconductor layer included in a semiconductor device of one embodiment of the present invention, The following description will be given with reference to FIG.

[0029] <Stacked structure of oxide semiconductor layers> FIG. 1A is a schematic diagram illustrating an example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, an oxide semiconductor layer 104 is provided on and in contact with an insulating layer 102. Yes.

[0030] The oxide semiconductor layer 104 includes a first region 104a and an insulating layer 104b sandwiching the first region 104a. 02 and a second region 104b overlapping therewith.

[0031] In the oxide semiconductor layer 104, the first region 104a and the second region 104b are bonded together. The regions have different crystallinity from each other. More specifically, the second The region 104b has higher crystallinity than the first region 104a.

[0032] Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS (CA xis Aligned Crystalline Oxide Semiconductor tor), oxide semiconductors containing polycrystals (hereafter, polycrystalline oxide semiconductors), microcrystals (nanocrystals Examples of such oxide semiconductors include oxide semiconductors containing nanocrystalline oxide semiconductors (hereinafter referred to as nanocrystalline oxide semiconductors).

[0033] In the oxide semiconductor layer 104 of this embodiment, the first region 104a has a thickness of, for example, 1 nm. Contains crystals with a size of 10 nm or less (nano crystals (nc)) It is preferable to do so.

[0034] Nanocrystalline oxide semiconductor films are denser and more dense than amorphous oxide semiconductor films. Therefore, the first region 104a of the oxide semiconductor layer 104 containing nanocrystals is an amorphous oxide. This is a region where the defect state density is reduced as compared to the nitride semiconductor film.

[0035] Note that in this specification, an amorphous oxide semiconductor film is a film in which atomic arrangement is irregular. The oxide semiconductor film does not have a crystal component even in a microscopic region. A typical example is an oxide semiconductor film whose entire structure is completely amorphous.

[0036] In the second region 104b, the c-axis is a normal vector of the surface on which the oxide semiconductor layer 104 is formed or a vector of the surface of the oxide semiconductor layer 104. It is preferable that the crystal portions are aligned in a direction parallel to the normal vector of the surface. An example of the oxide semiconductor film is a CAAC-OS film.

[0037] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with one side less than 100 nm. The crystal parts contained in the OS film are in the form of cubes with one side less than 10 nm, 5 nm, or 3 nm. In addition, the CAAC-OS membrane was observed under a transmission electron microscope (TEM). Observed using a Transmission Electron Microscope Then, clear boundaries between crystals, that is, grain boundaries, were confirmed. Therefore, the CAAC-OS film is susceptible to the decrease in electron mobility caused by grain boundaries. It can be said that it is unlikely to occur.

[0038] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) it can be confirmed that the metal atoms are arranged in layers in the crystal parts. Each layer of metal atoms is formed on the surface on which the CAAC-OS film is to be formed (the surface on which the film is to be formed) or on the unevenness of the upper surface. The shape of the CAAC-OS film reflects this, and the CAAC-OS films are aligned parallel to the surface on which the film is formed or the upper surface.

[0039] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms are aligned in a triangular or hexagonal pattern in the crystals, However, there is no regularity in the arrangement of metal atoms between different crystal parts. .

[0040] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0041] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. From this, it is considered that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0042] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane is returned to the equivalent of the (110) plane. In contrast, in the case of the CAAC-OS film, 2θ is set at 56 Even when φ is fixed at around 100° and scanned, no clear peak appears.

[0043] From the above, it is concluded that the orientation of the a-axis and b-axis is irregular between different crystal regions in the CAAC-OS film. However, the c-axis is oriented parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is in a plane parallel to the ab plane of the crystal.

[0044] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0045] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area adjacent to the surface may have a higher crystallinity than the area adjacent to the surface on which the CAAC When impurities are added to the -OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may form.

[0046] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a peak at 2θ of around 31°. It is preferable that the compound has a peak at 2θ of about 36°.

[0047] The CAAC-OS film is denser and has a higher film density than nanocrystalline oxide semiconductor films. Therefore, the second region 104b of the oxide semiconductor layer 104 containing the CAAC-OS is composed of nanocrystals. This region has a further reduced defect state density as compared to the first region 104a including the crystals.

[0048] The oxide semiconductor layer 104 described in this embodiment is an oxide semiconductor layer with a reduced density of defect states. A first region 104a including a nanocrystal and a defect level further than that of the nanocrystal oxide semiconductor. a second region 104b including a CAAC-OS which is an oxide semiconductor having a reduced density; do.

[0049] In a semiconductor device using an oxide semiconductor layer, in order to improve reliability, It is necessary to reduce defect levels in the oxide semiconductor layer and its interface. The negative shift in threshold voltage of a transistor using a conductor layer is due to the This is believed to be due to defect levels caused by oxygen vacancies in the oxide semiconductor layer and its interface. can be done.

[0050] Therefore, as shown in this embodiment, an oxide semiconductor layer 1 including a region where defect levels are reduced is provided. By using 04 in a transistor, the transistor can be irradiated with visible light or ultraviolet light. Fluctuations in electrical characteristics can be reduced, thereby improving the reliability of the transistor. It can be done.

[0051] In addition, when the oxide semiconductor layer 104 is used for a transistor, the defect level is further reduced. The second region 104b including the AAC-OS is applied to the main current path (channel) of the transistor. In addition, the second region 104b is preferably used as the main current path of the transistor. When the insulating layer 102 functions as a first region 104b, the first region 104b is formed at the interface between the insulating layer 102 and the second region 104b. By including a, the formation of defect levels at the interface between the channel and the insulating layer 102 is suppressed. It also has the effect of

[0052] In addition, in the oxide semiconductor layer 104, the second region 104b functions as a main path for current. Even if the first region 104a is not connected to the first region 104b, a certain amount of current may still flow through the first region 104a. The oxide semiconductor layer 104 shown in FIG. 1 has a low density of defect states even in the first region 104a. Since the first region 104a includes the reduced nanocrystalline oxide semiconductor, In comparison with the other cases, the reliability can be improved.

[0053] Note that the stacked structure included in the semiconductor device of one embodiment of the present invention is not limited to the structure shown in FIG. For example, as shown in FIG. 1B, This may also be configured.

[0054] In FIG. 1B, the oxide semiconductor layer 114 located under the insulating layer 106 is The first region 114a containing nanocrystals is disposed on the second region 114b containing OS. In other words, in FIG. 1B, as in FIG. 1A, the first region 114a and the first region The insulating layer 106 has a second region 114b overlapping the insulating layer 106 with the region 114a sandwiched therebetween.

[0055] Alternatively, as shown in FIG. 1C, the oxide semiconductor layer 124 over the insulating layer 102 and the oxide semiconductor In the structure having the insulating layer 106 on the conductor layer 124, the oxide semiconductor layer 124 is A first region 124a including a silicon crystal and a second region 124b overlapping the insulating layer 102 with the first region 124a sandwiched therebetween. , a second region 124b including CAAC-OS, and a second region 124b and an insulating layer 106 and a third region 124c located therebetween and including nanocrystals.

[0056] The oxide semiconductor layer 114 illustrated in FIG. 1B and the oxide semiconductor layer 124 illustrated in FIG. Similar to FIG. 1(A), the nanocrystal-containing region and the CAAC-OS-containing region are Therefore, such an oxide semiconductor layer is used as a transistor. By applying this to transistors, the fluctuation in electrical characteristics is reduced, resulting in highly reliable transistors. This can be done.

[0057] In addition, similar to FIG. 1(A), the stacked structure shown in FIG. 1(B) contains CAAC-OS. A first region 114a containing nanocrystals is provided between a second region 114b containing nanocrystals and the insulating layer 106. In addition, in the stacked structure shown in FIG. 1(C), the second domain containing CAAC-OS A first region 124a including nanocrystals is provided between the first region 124b and the insulating layer 102, and A third region including nanocrystals is formed between the second region including AC-OS and the insulating layer 106. With this structure, the oxide semiconductor layer 114 is provided. In the case where the second region 114b functions as a channel in the transistor, It is possible to prevent the insulating layer 106 in contact with the semiconductor layer 114 from directly contacting the channel. In the transistor including the oxide semiconductor layer 124, the second region 124b When the insulating layer 102 or This can prevent the insulating layer 106 from coming into direct contact with the channel. Therefore, the formation of defect levels at the interface of the channel can be prevented. The reliability can be improved.

[0058] Note that the oxide semiconductor layers 104, 114, and 124 illustrated in FIG. 1 may each include a single crystal region. Alternatively, it may contain amorphous regions.

[0059] For example, in FIG. 1A, the oxide semiconductor layer 104 has an amorphous portion on the second region 104b. In FIG. 1B, the oxide semiconductor layer 114 may include a second The layer below the region 114b may include an amorphous region.

[0060] In addition, the first region 104a and the second region 104b included in the oxide semiconductor layer 104 shown in FIG. The region 104b may include regions of different crystallinity in a single layer film, or may be a region of different crystallinity. A structure in which different films are laminated may be used. Unless otherwise specified, the term "region" may be read as "layer." For example, an oxide semiconductor The layer 104 is a first oxide semiconductor layer including nanocrystals and a second oxide semiconductor layer including CAAC-OS. It may also have a laminated structure with a compound semiconductor layer.

[0061] The oxide semiconductor layer 104 is a first oxide semiconductor layer including nanocrystals and a CAAC-O In the case of a stacked structure with a second oxide semiconductor layer containing S, the first oxide semiconductor layer and the second oxide semiconductor layer The metal elements constituting the oxide semiconductor layer may be the same or different. In addition, when the same metal element is contained, the composition may be the same or different. The same applies to the oxide semiconductor layer 114 and the oxide semiconductor layer 124.

[0062] The oxide semiconductor layer described in this embodiment has a CAAC-OS functioning as a main current path. The oxide semiconductor has a region including nanocrystals at an interface between the region including nanocrystals and the insulating layer. The reliability of a transistor including the layer can be improved.

[0063] Note that the oxide semiconductor layer described in this embodiment is used as, for example, an active layer of a transistor. However, the embodiment of the present invention is not limited to this. The oxide semiconductor layer can be configured as a part of various elements. The oxide semiconductor layer shown in the embodiment can be formed as a part of a resistor. A protection circuit can be formed using the element. The oxide semiconductor layer can also be formed as a part of an electrode of a capacitor. The capacitor can be configured as a storage capacitor in the pixel, or as a capacitive element in the driver circuit. The oxide semiconductor layer described in this embodiment can be formed as a transistor. When the semiconductor device is configured as a capacitance element or a resistance element, the oxide semiconductor contained in these elements In this case, the number of process steps can be reduced, which is preferable. Note that the oxide semiconductor layer described in this embodiment can be used as a capacitor or a resistor. In this case, it is possible to introduce hydrogen or the like into the film in order to reduce the resistance value. For this reason, when a film containing hydrogen, such as a silicon nitride film, is in contact with the oxide semiconductor layer described in this embodiment, In this manner, the resistance value of the oxide semiconductor layer described in this embodiment can also be reduced.

[0064] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0065] (Embodiment 2) In this embodiment, with respect to formation of a crystal portion included in the oxide semiconductor layer described in Embodiment 1, The film formation model will be described with reference to FIGS. 2 to 6. It should be noted that the present invention is not limited to the following models. .

[0066] <Crystal part film formation model> FIG. 2A shows a sputtering target 1000 for forming an oxide semiconductor layer. This is a schematic diagram showing how ions 1001 collide and sputtering particles 1002 peel off. In FIG. 2, the sputtering particle 1002 is a hexagonal columnar shape, and the hexagonal faces are ab When the sputtering particle is triangular prism-shaped and the triangular face is a -b plane is parallel to the plane. In this case, the direction perpendicular to the hexagonal plane is The direction is the c-axis direction (see FIG. 2(B)). The same applies to the case of a triangular prism. The grains 1002 are parallel to the ab plane, although this varies depending on the type of oxide semiconductor used. The diameter of the surface (equivalent circle diameter) is 1 nm to 30 nm, or 1 nm to 10 nm. The ions 1001 are oxygen cations. In place of the argon cation, other rare earth ions may be used. Positive ions of the gas may also be used.

[0067] By using oxygen cations as ion 1001, plasma damage during film formation is reduced. Therefore, the ions 1001 can be incident on the surface of the sputtering target 1000. When the target 1000 is struck against the surface of the sputtering target, the crystallinity of the target 1000 decreases. can suppress the amorphization.

[0068] The detached sputtered particles 1002 are preferably positively charged. The timing at which the sputtering particles 1002 are positively charged is not particularly important. The sputtering particles 1002 may become positively charged due to exposure to the plasma; or When the ion 1001 collides with the ion, it may become positively charged. The positive ions 1001 are charged to the side, top or bottom of the sputtered particles 1002. It may become positively charged by binding to a surface.

[0069] The sputtered particles 1002 have a positive charge at the corners of the polygonal faces. By having positive charges at the corners of the tubular surface, the positive charges repel each other and the tubular shape is maintained. It can be held.

[0070] In order for the corners of the polygonal faces of the sputtering particle 1002 to have a positive charge, It is preferable to use a direct current (DC) power source. Note that a radio frequency (RF) power source or an alternating current (AC) power source is also not applicable. However, the RF power supply is not suitable for sputtering, which can deposit films on large-area substrates. In addition, DC power is preferable to AC power for the following reasons: This is considered desirable.

[0071] When an AC power source is used, adjacent targets alternate between cathode and anode potentials. In the period A shown in FIG. 3(A), the target 1 is a cathode as shown in FIG. The target 2 functions as an anode. In this case, target 1 acts as the anode and target 2 acts as the cathode, as shown in FIG. 3(B2). The total duration of period A and period B is 20 to 50 μs. Periods A and B are repeated at regular intervals.

[0072] When the sputtered particles 1002 are positively charged, they repel each other, It can maintain its flat shape. However, when using an AC power source, the electric field momentarily Since there is a time when the charge is not applied, the charge on the sputtering particle 1002 disappears. As a result, the structure of the sputtered particles may be destroyed (see Figure 3(C)). It can be seen that using a DC power supply is preferable to using an AC power supply.

[0073] <CAAC-OS film formation> The manner in which sputtered particles are deposited on a film-forming surface will be described below with reference to FIG. FIG. 4 shows the case where the film was formed while the substrate was heated.

[0074] As shown in FIG. 4, when the substrate is heated, the sputtering particles 1002 are deposited on the deposition surface 1003. In the process, other sputtered particles 1002 move to an area where they are not deposited, resulting in migration. By joining the particles, they bond with the particles already in the pile and accumulate. The sputtering particles 1002 are laid out so that the flat surface faces upward. The c-axis of the quartz grains 1002 is aligned in a direction perpendicular to the deposition surface 1003. The oxide film obtained by deposition is uniform in thickness and has a uniform crystal orientation. This becomes an oxide semiconductor layer.

[0075] The CAAC-OS obtained by this mechanism has an amorphous surface, an amorphous insulating surface, and an amorphous Even the surface of a porous oxide film has high crystallinity.

[0076] <<Deposition of nanocrystalline oxide semiconductor film>> Figure 5 shows how sputtered particles accumulate on the deposition surface when deposition is performed without heating the substrate. Indicates a child.

[0077] From FIG. 5, when the substrate is not heated (for example, the substrate temperature is room temperature plus or minus 50°C, (When the temperature is room temperature plus or minus 10°C), the sputtering particles 1002 are 03. Therefore, the sputtering particles 1002 are already falling on the other sputtering particles. The deposition is disordered, including the area where the granular particles 1002 are deposited. The oxide semiconductor layer thus grown will not have a uniform thickness and will have a different crystal orientation. The obtained oxide semiconductor layer has the crystallinity of the flat sputtered particles 1002. Since the crystal structure is maintained to a certain degree, the oxide semiconductor layer has crystal parts.

[0078] As described above, the sputtering particles 1002 are, for example, perpendicular to a plane parallel to the ab plane. The diameter is about 1 nm to 30 nm, or 1 nm to 10 nm, and the film is formed. The crystal portion contained in the compound semiconductor layer may be smaller than the sputtering particle 1002. For example, nanocrystalline oxide semiconductors having crystal parts of 10 nm or less, or 5 nm or less. There may be layers.

[0079] A nanocrystalline oxide semiconductor layer is equivalent to a film having a disordered atomic arrangement from a macroscopic perspective. Therefore, it has a wide measurement range (for example, a beam diameter larger than the sputtering particle 1002). Analysis by X-ray diffraction (XRD) can determine the orientation. In addition, the peaks shown in the graph may not be detected. In the diffraction pattern produced by an electron beam with a beam diameter, a halo pattern may be observed. In this case, for example, the diameter of the electron beam is set to be sufficiently smaller than the sputtering particles 1002. The electron microbeam diffraction pattern obtained by measuring the nanocrystalline oxide semiconductor layer as a small diameter You can observe spots (bright points) here.

[0080] It is preferable that the film-forming surface 1003 has an insulating surface. By having the above structure, a positive charge is generated from the sputtering particles 1002 deposited on the film-forming surface 1003. However, the deposition rate of the sputtering particles 1002 is slower than the rate at which the positive charge dissipates. In the case where the loss of the film is slower than the loss of the film, the film-forming surface 1003 may be conductive. Surface 1003 is preferably an amorphous surface, an amorphous insulating surface.

[0081] Figure 6(A) shows the crystal structure of In-Ga-Zn oxide when viewed parallel to the ab plane of the crystal. The crystal structure after ion collision during sputtering is shown in Figure 6(B).

[0082] For example, the crystals contained in the In-Ga-Zn oxide are composed of gallium atoms or and a layer having zinc atoms and oxygen atoms, and a layer having gallium atoms or / and zinc atoms and The cleavage occurs between the layer with oxygen atoms at the top and the layer with negative charges at the bottom. This is because the oxygen atoms that are adjacent to each other are close to each other. Thus, the cleavage plane is parallel to the ab plane. It becomes.

[0083] That is, ions are deposited on the surface of a sputtering target containing In-Ga-Zn oxide crystal grains. When a neutron hits the In-Ga-Zn oxide, the crystals are split into two planes parallel to the ab plane of the crystal. A plate-like sputtered grain cleaved along the ab plane and having upper and lower surfaces parallel to the ab plane. peels off.

[0084] In addition, the In-Ga-Zn oxide crystal shown in Figure 6 has the following structure when viewed from a direction perpendicular to the ab plane: Since metal atoms are arranged in equilateral triangles or equilateral hexagons, the aforementioned flat crystal grains have internal angles of 12 It tends to become a hexagonal prism with regular hexagonal faces at 0°.

[0085] <How to make a sputtering target>

[0086] A method for producing the above-mentioned sputtering target will be described with reference to FIG.

[0087] In FIG. 7(A), oxide powder containing multiple metal elements is used as a sputtering target. First, in step S101, the oxide powder is weighed.

[0088] Here, as the oxide powder containing multiple metal elements, an oxide powder containing In, M and Zn is used. The preparation of In-M-Zn oxide powder will be described below. The raw material is InO X Oxide powder, MO Y Oxide powder and ZnO Z Prepare oxide powder Note that X, Y, and Z are any positive numbers. For example, X is 1.5, Y is 1.5, and Z is Of course, the above oxide powder is just an example, and it is possible to select an appropriate powder to obtain a desired composition. The oxide powder can be selected appropriately. M is Ga, Sn, Hf, Al, La, Ce, P R, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu. In this embodiment, an example using three types of oxide powder is shown, but the present invention is not limited to this. For example, This embodiment may be applied to the case where four or more kinds of oxide powders are used, or one or This may also be applied to the case where two types of oxide powder are used.

[0089] Next, InO X Oxide powder, MO Y Oxide powder and ZnO Z The oxide powder is mixed with a given mole Mix in numerical ratios.

[0090] The predetermined molar ratio is, for example, InO X Oxide powder, MO Y Oxide powder and Zn O Z The oxide powders are 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 1 :1:2, 3:1:4 or 3:1:2. By using such molar ratios, This makes it easier to obtain a sputtering target containing a polycrystalline oxide with high crystallinity.

[0091] Next, in step S102, InO X Oxide powder, MO Y Oxidation Powder and ZnO Z The oxide powder is subjected to the first firing to obtain In-M-Zn oxide. obtain.

[0092] The first firing is performed in an inert atmosphere, an oxidizing atmosphere, or a reduced pressure atmosphere at a temperature of 40 The temperature is from 0°C to 1700°C, preferably from 900°C to 1500°C. The time is, for example, from 3 minutes to 24 hours, preferably from 30 minutes to 17 hours, and more preferably The first baking may be performed for 30 minutes or more and 5 hours or less. This suppresses unnecessary reactions other than the intended reaction, and the impurity concentration in the In-M-Zn oxide powder is Therefore, it is possible to improve the crystallinity of the In-M-Zn oxide powder. can.

[0093] The first baking may be performed multiple times by changing the temperature and / or atmosphere. The In-M-Zn oxide powder was held at a first temperature in the first atmosphere, and then heated in a second atmosphere. The second temperature may be maintained. Specifically, the first atmosphere may be an inert atmosphere or a reduced pressure atmosphere. It is preferable that the second atmosphere is an oxidizing atmosphere. In order to reduce the impurities contained in the In-M-Zn oxide powder, This is because oxygen deficiency may occur. Therefore, the In-M obtained in the second atmosphere It is preferable to reduce oxygen vacancies in the In-Zn oxide. By reducing the concentration and reducing the oxygen vacancies, the crystallinity of the In-M-Zn oxide powder was improved. can be increased.

[0094] Next, in step S103, the In-M-Zn oxide is pulverized to obtain an In-M-Zn oxide. A powder is obtained.

[0095] The In-M-Zn oxide has many surface structures parallel to the ab plane. The In-M-Zn oxide powder is a plate-like crystal with upper and lower surfaces parallel to the ab plane. In-M-Zn oxide crystals are hexagonal or trigonal (rhombohedral) crystals. Since the aforementioned flat crystal grains are often roughly hexagonal with an internal angle of 120°, They are often shaped like hexagonal prisms with square faces.

[0096] Next, the particle size of the obtained In-M-Zn oxide powder is confirmed in step S104. The average particle size of the In-M-Zn oxide powder is 3 μm or less, preferably 2.5 μm or less, and It is preferable to confirm that the particle size is 2 μm or less. Using a diameter filter, the particle size is 3 μm or less, preferably 2.5 μm or less, and more preferably Alternatively, only In-M-Zn oxide powder having a particle size of 2 μm or less may be selected. The oxide powder has a particle size of 3 μm or less, preferably 2.5 μm or less, and more preferably 2 μm or less. By selecting the following, the average particle size of the In-M-Zn oxide powder is ensured to be 3 μm or less. The thickness is preferably 2.5 μm or less, and more preferably 2 μm or less.

[0097] In step S104, if the average particle size of the In-M-Zn oxide powder exceeds a predetermined value, Returning to S103, the In-M-Zn oxide powder is pulverized again.

[0098] In this manner, the average particle size is 3 μm or less, preferably 2.5 μm or less, and more preferably In-M-Zn oxide powder having an average particle size of 3 μm or less can be obtained. μm or less, preferably 2.5 μm or less, and more preferably 2 μm or less. By obtaining n-oxide powder, the crystal grains contained in the sputtering target to be prepared later can be The particle size can be reduced.

[0099] Next, in FIG. 7(B), the In-M-Zn oxide obtained by the flow chart shown in FIG. 7(A) is The material powder is used to prepare a sputtering target.

[0100] In step S111, the In-M-Zn oxide powder is spread in a mold and molded. This means that the In-M-Zn oxide is spread evenly on the mold. The powder is introduced and molded by applying vibration from the outside. The n-oxide powder is introduced and formed into a uniform thickness using a roller or the like. In S111, In-M-Zn oxide powder was mixed with water, a dispersant, and a binder to form a slurry. In this case, the slurry is poured into a mold and then suctioned from the bottom of the mold. After that, the molded body after suction is dried. Air drying is preferable because it is less likely to cause cracks in the molded body. Heat treatment at temperatures below 00℃ removes residual moisture that could not be removed by natural drying. Remove.

[0101] In-M-Zn oxide containing many plate-like grains with upper and lower surfaces parallel to the ab plane By spreading the powder in a mold and molding it, the crystal grains are arranged with the ab plane and parallel to it facing upwards. Therefore, by spreading and molding the obtained In-M-Zn oxide powder, a- The ratio of the surface structure of the plane parallel to the b plane can be increased. It may be made of oxide and have a rectangular or round top surface.

[0102] Next, in step S112, the In-M-Zn oxide powder is subjected to a second firing. In step S113, the In-M-Zn oxide powder subjected to the second firing is subjected to a first pressurization treatment. The second firing is carried out under the same conditions and conditions as the first firing to obtain plate-shaped In-M-Zn oxide. The second baking step can be performed in the following manner to enhance the crystallinity of the In-M-Zn oxide. It is possible.

[0103] The first pressure treatment is sufficient if it can compress and compact the In-M-Zn oxide powder. For example, this can be done by using a weight of the same type as the mold. Or, compressed air, etc. Alternatively, the first pressure treatment may be carried out using various known techniques. The first pressure treatment may be carried out simultaneously with the second baking.

[0104] A planarization process may be performed after the first pressure treatment. The planarization process may be performed by chemical mechanical polishing (CMP). Chemical Mechanical Polishing (CMP) treatment can be used. good.

[0105] The plate-like In-M-Zn oxide thus obtained is a polycrystalline oxide with high crystallinity.

[0106] Next, in step S114, the thickness of the obtained plate-shaped In-M-Zn oxide is confirmed. If the thickness of the In-M-Zn oxide is thinner than the desired thickness, the process returns to step S111. Spread In-M-Zn oxide powder on Zn oxide and mold it. When the oxide has the desired thickness, the plate-shaped In-M-Zn oxide is sputtered. The following is a case where the plate-shaped In-M-Zn oxide is thinner than the desired thickness. This article explains:

[0107] Next, in step S112, a plate-shaped In-M-Zn oxide and a plate-shaped In-M-Zn oxide are The In-M-Zn oxide powder is then subjected to a third firing. The plate-shaped In-M-Zn oxide calcined as described in 3 and the I-type oxide on the plate-shaped In-M-Zn oxide were The second pressure treatment was performed on the nM-Zn oxide powder, and the In-M-Zn oxide powder was The plate-like In-M-Zn oxide with increased thickness was obtained. The material is obtained by crystal growth using plate-shaped In-M-Zn oxide as a seed crystal, so the crystalline This results in a highly polycrystalline oxide.

[0108] The third baking may be performed under the same conditions and by the same method as the second baking. The treatment may be carried out under the same conditions and by the same method as the first pressure treatment. This may be done simultaneously with the firing.

[0109] Again, in step S114, the thickness of the obtained plate-shaped In-M-Zn oxide is confirmed.

[0110] Through the above process, the crystal orientation is improved and the plate-shaped In-M-Zn oxide is gradually thickened. It is possible.

[0111] By repeating this process of thickening the plate-shaped In-M-Zn oxide n times (n is a natural number), The desired thickness (t) is, for example, 2 mm or more and 20 mm or less, preferably 3 mm or more and 20 mm or less. A plate-like In-M-Zn oxide can be obtained. The plate-like In-M-Zn oxide can be used to Used as a sputtering target.

[0112] After that, a planarization process may be performed.

[0113] The resulting sputtering target may be subjected to a fourth firing. The fourth firing may be performed under the same conditions and by the same method as the first firing. Furthermore, it is possible to obtain a sputtering target containing a highly crystalline polycrystalline oxide. .

[0114] In this manner, a polycrystalline oxide having a cleavage plane parallel to the ab plane and a plurality of crystal grains was obtained. The present invention provides a sputtering target having a small average grain size of a plurality of crystal grains. can.

[0115] The sputtering target thus produced can be made highly dense. The high density of the sputtering target allows the density of the deposited film to be high. Specifically, the relative density of the sputtering target is 90% or more, 95% or more, or 9 It can be 9% or more.

[0116] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0117] (Embodiment 3) In this embodiment, another example of a stacked structure included in a semiconductor device of one embodiment of the present invention will be described. 8. Specifically, in this embodiment, the oxide semiconductor The conductive layer includes a first oxide semiconductor layer including nanocrystals and a second oxide semiconductor layer including CAAC-OS. The case where an oxide semiconductor layer and a third oxide semiconductor layer including nanocrystals are stacked will be described as an example. vinegar.

[0118] FIG. 8A is a cross-sectional view of an oxide semiconductor layer located between insulating layers. FIG. 8(A) is a diagram showing the band structure in X1-Y1.

[0119] In the stacked structure of this embodiment, an oxide semiconductor layer 404 is provided between an insulating layer 402 and an insulating layer 410. The oxide semiconductor layer 404 includes a first oxide semiconductor layer 404a, a second oxide semiconductor layer The insulating layer 404 includes a layer 404b and a third oxide semiconductor layer 404c.

[0120] The second oxide semiconductor layer 404b included in the oxide semiconductor layer 404 is made of CAAC-OS The second oxide semiconductor layer 404b is an oxide semiconductor layer containing the first oxide The oxide semiconductor layer 404a and the third oxide semiconductor layer 404c have a higher electron affinity. For example, the second oxide semiconductor layer 404b is made of a first oxide semiconductor 0.07 eV to 1.3 eV lower than the oxide semiconductor layer 404a and the third oxide semiconductor layer 404c , preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 An oxide semiconductor layer having a large electron affinity of 0.1 eV or less is used.

[0121] The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band. The energy of the conduction band minimum of the first oxide semiconductor layer 404a is Ec1, and the energy of the conduction band minimum of the second oxide semiconductor layer 404b is Ec2. The energy of the conduction band minimum of the semiconductor layer 404b is Ec2, and the energy of the conduction band minimum of the third oxide semiconductor layer 404c is Ec3. The energy of the conduction band minimum is denoted as Ec3. The energy of the upper end of the electronic band is Ev1, and the energy of the upper end of the valence band of the second oxide semiconductor layer 404b is The energy of the upper end of the valence band of the third oxide semiconductor layer 404c is denoted as Ev2 and Ev3. Write.

[0122] In addition, the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404b included in the oxide semiconductor layer 404 At least one of the semiconductor layers 404c is an oxide semiconductor layer containing nanocrystals. In this embodiment, the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c An oxide semiconductor layer containing nanocrystals is used for both.

[0123] The first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c are formed of a second oxide The oxide semiconductor layer 404b has an energy gap larger than the energy gap Eg2. For example, the energy gap E g1 and the energy gap Eg3 of the third oxide semiconductor layer 404c are 2.7 eV or more. 4.9 eV or less, preferably 3 eV to 4.7 eV, and more preferably 3.2 eV or less The energy gap E g2 is smaller than Eg1 and Eg3, and is preferably, for example, 2.5 eV or more and 4.2 eV or less. Preferably, the value is 2.8 eV or more and 3.8 eV or less, and more preferably, 3 eV or more and 3.5 eV or less. do.

[0124] In such a structure, when an electric field is applied to the gate electrode layer, The second oxide semiconductor layer 404b, which has the smallest energy at the bottom of the conduction band, is the main path of the current. That is, the first oxide semiconductor layer 404b is formed between the second oxide semiconductor layer 404b and the insulating layer 402. A second oxide semiconductor layer 404a is formed between the second oxide semiconductor layer 404b and the insulating layer 410. The third oxide semiconductor layer 404c is formed, so that the channel of the transistor A structure in which the gate insulating layer is not in contact with the gate insulating layer can be used.

[0125] The second oxide semiconductor layer 404b is a semiconductor layer including the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404b. The oxide semiconductor layer has a higher film density and a lower defect state density than the oxide semiconductor layer 404c. When a channel is formed in the second oxide semiconductor layer 404b, This suppresses fluctuations in the electrical characteristics of transistors, resulting in highly reliable transistors. It can be said that:

[0126] In addition, the second oxide semiconductor layer 404b is formed using an oxide semiconductor layer with low carrier density. For example, the second oxide semiconductor layer 404b has a carrier density of 1×10 17 pieces / cm 3 below , preferably 1 x 10 15 pieces / cm 3 Less than 1×10, more preferably 13 pieces / cm 3 Below or less, more preferably 1×10 11 pieces / cm 3 The following oxide semiconductor layer is used.

[0127] The second oxide semiconductor layer 404b is an oxide semiconductor layer containing at least indium. When the second oxide semiconductor layer 404b contains at least indium, the carrier mobility (electron In addition to indium, element M (aluminum, It is preferred that the metal oxide contains at least one of gallium, yttrium, zirconium or tin.

[0128] The first oxide semiconductor layer 404a contains at least one element constituting the second oxide semiconductor layer 404b. The second oxide semiconductor layer 404 is an oxide semiconductor layer including two or more kinds of oxide semiconductors. The first oxide semiconductor layer 404a is formed of one or more elements constituting b. Therefore, at the interface between the second oxide semiconductor layer 404b and the first oxide semiconductor layer 404a, Therefore, the movement of carriers is not hindered at the interface. This increases the field effect mobility of the transistor.

[0129] The first oxide semiconductor layer 404a is made of, for example, aluminum, titanium, silicon, or gallium. , germanium, yttrium, zirconium, tin, lanthanum, cerium or hafnium The oxide semiconductor layer may contain sium at a higher atomic ratio than indium. The first oxide semiconductor layer 404a preferably contains the above elements at a concentration 1.5 times or more higher than that of indium. Preferably, the oxide semiconductor layer has an atomic ratio that is at least two times, more preferably at least three times higher. The above-mentioned elements may have a function of increasing the energy gap of the oxide semiconductor layer. In addition, since the oxide semiconductor layer contains the above-mentioned elements at a high atomic ratio, In some cases, the element has the function of reducing the electron affinity of the semiconductor layer. Since it bonds more strongly to oxygen than uranium, it suppresses the occurrence of oxygen vacancies in the oxide semiconductor layer. In addition, the above-described elements have a function of shielding impurities from the oxide semiconductor layer or a function of preventing the impurities from entering the oxide semiconductor layer. The first oxide semiconductor layer 404a may have a function of reducing the diffusion coefficient of a pure material. The oxide semiconductor layer 404b contains the above-mentioned elements in a higher atomic ratio than the second oxide semiconductor layer 404b. It is.

[0130] The third oxide semiconductor layer 404c contains at least one of the elements constituting the second oxide semiconductor layer 404b. The second oxide semiconductor layer 404 is an oxide semiconductor layer including two or more kinds of oxide semiconductors. The third oxide semiconductor layer 404c is formed of one or more elements constituting b. Therefore, at the interface between the second oxide semiconductor layer 404b and the third oxide semiconductor layer 404c, Therefore, the movement of carriers is not hindered at the interface. This increases the field effect mobility of the transistor.

[0131] The third oxide semiconductor layer 404c is formed of, for example, aluminum, titanium, silicon, or gallium. , germanium, yttrium, zirconium, tin, lanthanum, cerium or hafnium The oxide semiconductor layer may contain sium at a higher atomic ratio than indium. The third oxide semiconductor layer 404c preferably contains the above elements at a concentration 1.5 times or more higher than that of indium. Preferably, the oxide semiconductor layer has an atomic ratio that is at least two times, more preferably at least three times higher. Note that the third oxide semiconductor layer 404c contains the above-mentioned elements. The oxide semiconductor layer has a higher atomic ratio than that of b.

[0132] Note that the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c have different physical properties. Alternatively, an oxide semiconductor layer having the same physical properties may be used. good.

[0133] When the first oxide semiconductor layer 404a is an In-M-Zn oxide, Zn and oxygen are The atomic ratio of In and M, excluding In, is preferably less than 50 atomic % and M is preferably less than 50 atomic %. % or more, more preferably In is less than 25 atomic %, and M is 75 atomic % or more. The second oxide semiconductor layer 404b is an In-M-Zn oxide. In this case, the atomic ratio of In and M excluding Zn and oxygen is preferably 25 atomic % In. or more, M is less than 75 atomic %, and more preferably In is 34 atomic % or more; In addition, the third oxide semiconductor layer 404c is In-M- When the oxide is Zn, the atomic ratio of In and M excluding Zn and oxygen is preferably 5:1 or less. 0 atomic %, M is 50 atomic % or more, and more preferably In is 25 atomic % or more. omic% or less, and M is 75 atomic% or more.

[0134] Note that the thickness of the first oxide semiconductor layer 404a is greater than or equal to 5 nm and less than or equal to 100 nm, preferably The thickness of the second oxide semiconductor layer 404b is 5 nm or more and 50 nm or less. More preferably, the thickness is 5 nm or less, and more preferably, the thickness is 200 nm or less, more ...200 nm or less, and more preferably, the The thickness of the third oxide semiconductor layer 404c is 5 nm or more and 10 nm or less. 0 nm or less, preferably 5 nm or more and 50 nm or less.

[0135] The first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c are Since the oxide semiconductor layer 404b is an oxide semiconductor layer containing one or more metal elements, The semiconductor layer 404 can be said to be a stack of oxides having the same main component. The oxide stack is a continuous junction (here, specifically, A U-shaped well structure is formed in which the energy of the conduction band edge changes continuously between layers. This is because the interface between the layers is fabricated in such a way that defect levels such as trap centers and recombination centers are created. When impurities that form junctions are present, the continuity of the energy bands is lost and the interface is cracked. This is because the carriers disappear due to trapping or recombination.

[0136] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. (sputtering equipment) to continuously stack each layer without exposing them to the air Each chamber in the sputtering equipment must be free of impurities for oxide semiconductors. In order to remove as much water as possible, a vacuum pump of the adsorption type like a cryopump is used. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to set the temperature to about 10 Pa. Alternatively, a turbomolecular pump and cold trap can be combined to vent the gas from the exhaust system to the chamber. It is preferable to prevent gas from flowing back into the tank.

[0137] In addition, hydrogen and oxygen vacancies that cause defect states in the oxide semiconductor layer are reduced, and oxidation is prevented. In order to obtain a highly pure intrinsic semiconductor layer, it is not enough to evacuate the chamber to a high vacuum. In addition, the sputtering gas must be highly purified. The gas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using gas that has been highly purified up to 1000 times, moisture and other substances can be absorbed into the oxide semiconductor. It can be prevented as much as possible.

[0138] The first oxide semiconductor layer 404 is provided above or below the second oxide semiconductor layer 404b. The a and the third oxide semiconductor layers 404c function as barrier layers. The influence of defect states formed at the interface between the oxide semiconductor layer 404 and the insulating layer in contact with the oxide semiconductor layer 404 is The second oxide semiconductor layer 404b serves as a main carrier path for the diode. It is possible to suppress the spread of

[0139] For example, oxygen vacancies in an oxide semiconductor layer are This manifests itself as a localized level that exists at a deep energy position. When ions are trapped in the oxide semiconductor layer, the reliability of the transistor decreases. In the oxide semiconductor layer 404, the second The oxide semiconductor layer 404b is formed by dissolving the oxide semiconductor layer 404a in a liquid crystal display. By providing the second oxide semiconductor layer 404b above and below, the second oxide semiconductor layer 40 The oxygen vacancy in 4b can be reduced.

[0140] In addition, the second oxide semiconductor layer 404b may be an insulating layer having a different constituent element (e.g., silicon oxide). When the semiconductor layer contacts a silicon film (an insulating underlayer), an interface state is formed at the interface between the two layers. In this case, a second transistor with a different threshold voltage may be formed. However, this can cause the apparent threshold voltage of the transistor to fluctuate. However, in the oxide semiconductor layer 404, the metal element constituting the second oxide semiconductor layer 404b Since the first oxide semiconductor layer 404a contains one or more elements, Therefore, an interface state is unlikely to be formed at the interface between the oxide semiconductor layer 404a and the second oxide semiconductor layer 404b. By providing the first oxide semiconductor layer 404a, the threshold voltage of the transistor can be reduced. This can reduce the variation in electrical characteristics.

[0141] In addition, the gate insulating layer (here, assumed to be the insulating layer 410) and the second oxide semiconductor layer 40 When a channel is formed at the interface with 4b, interface scattering occurs at the interface, and the transistor However, in the oxide semiconductor layer 404, the second oxide The third oxide semiconductor layer 404b contains one or more metal elements. Since the second oxide semiconductor layer 404b and the third oxide semiconductor layer 404c are formed, At the interface, carrier scattering is unlikely to occur, which increases the field effect mobility of the transistor. This can be done.

[0142] The first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c are made of oxide semiconductors. The constituent elements of the insulating layer in contact with the oxide semiconductor layer 404 are mixed into the second oxide semiconductor layer 404b, resulting in insufficient insulation. It also functions as a barrier layer for suppressing the formation of levels due to impurities.

[0143] For example, the insulating layers 402 and 410 in contact with the oxide semiconductor layer 404 may be made of an insulating material containing silicon. When an edge layer is used, the silicon in the insulating layer or the carbon that may be mixed into the insulating layer may be the first The oxide semiconductor layer 404a or the third oxide semiconductor layer 404c is formed to a depth of about several nm from the interface. When impurities such as silicon and carbon enter the oxide semiconductor layer, they can be mixed into the oxide semiconductor layer. In some cases, the impurity level acts as a donor and generates electrons, making the material n-type.

[0144] However, the thicknesses of the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c However, if the thickness is more than a few nm, impurities such as silicon and carbon may be mixed into the second oxide semiconductor layer. Since the impurity level does not reach 404b, the influence of the impurity level is reduced.

[0145] Here, the concentration of silicon in the oxide semiconductor layer is 3×10 18 / cm 3 The following is preferred: 3×10 17 / cm 3 The concentration of carbon in the oxide semiconductor layer is 3 ×10 18 / cm 3 Less than or equal to 3×10 17 / cm 3 In particular, the second oxidation In order to prevent silicon or carbon, which are group 14 elements, from being mixed into the compound semiconductor layer 404b in a large amount, The first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c form a carrier path. It is preferable that the second oxide semiconductor layer 404b be sandwiched or surrounded by the insulating film. The concentrations of silicon and carbon in the second oxide semiconductor layer 404b are higher than those in the first oxide semiconductor layer 404b. The concentrations of silicon and carbon contained in the conductor layer 404a and the third oxide semiconductor layer 404c are It is preferable that the temperature is lower than that of the conventional method.

[0146] The impurity concentration in the oxide semiconductor layer was measured using secondary ion mass spectrometry (SIMS). It can be measured by y Ion Mass Spectrometry.

[0147] In addition, when hydrogen or moisture is included in the oxide semiconductor layer as an impurity, it creates donors and becomes n-type. Therefore, hydrogen or moisture can be prevented from entering above the oxide semiconductor layer 404 from the outside. Providing a protective insulating layer (such as a silicon nitride layer) is useful in realizing a well structure. do.

[0148] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0149] (Embodiment 4) In this embodiment, the transistor including the oxide semiconductor layer described in Embodiment 1 or 3 is An example of the configuration of the transistor will be described with reference to the drawings.

[0150] <Example of transistor configuration> FIG. 9A is a schematic cross-sectional view of a transistor 300. The transistor 300 is a bottom gate type transistor.

[0151] The transistor 300 includes a gate electrode layer 302 provided on a substrate 301 and a An insulating layer 303 is provided on the gate electrode layer 302, and a gate electrode layer 304 is provided on the insulating layer 303. 02, and an oxide semiconductor layer 314 provided on the top surface of the oxide semiconductor layer 314. The source electrode layer 305a and the drain electrode layer 305b are in contact with each other. 3. An insulating layer covering the oxide semiconductor layer 314, the source electrode layer 305a, and the drain electrode layer 305b. An edge layer 306 and an insulating layer 307 on the insulating layer 306 are provided.

[0152] The oxide semiconductor layer 314 included in the transistor 300 is a semiconductor layer including an oxide semiconductor layer 314a and an oxide The oxide semiconductor layer 314a and the oxide semiconductor layer 314b are stacked together. Since the boundaries of the conductor layer 314b may be unclear, these are not shown in the drawings such as FIG. The boundaries are shown with dashed lines.

[0153] The oxide semiconductor layer 314a and the oxide semiconductor layer 314b are both oxide semiconductors having crystallinity. In the present embodiment, the oxide semiconductor layer 314a is an oxide semiconductor layer having a crystallinity different from that of the oxide semiconductor layer 314a. The oxide semiconductor layer 314b has a higher film density and a lower density of defect states than the oxide semiconductor layer 314b. The oxide semiconductor layer 314a is preferably a CAAC-OS film. The semiconductor layer 314b is a nanocrystalline oxide semiconductor layer. In the transistor 300, the oxide semiconductor layer 314 is the same as that shown in FIG. The insulating layer 306 in the transistor 300 corresponds to the oxide semiconductor layer 114. This corresponds to the insulating layer 106 shown in FIG.

[0154] The oxide semiconductor layer 314a is typically made of In-Ga oxide, In-Zn oxide, In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) When the oxide semiconductor layer 314a is an In-M-Zn oxide, Zn and oxygen are The atomic ratio of the excluding In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. atomic %, more preferably, In is 34 atomic % or more and M is 66 atomic % or more. For example, the oxide semiconductor layer 314a has an energy gap of A material having a potential of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more is used. .

[0155] In this embodiment, the oxide semiconductor layer 314b is formed of the oxide semiconductor layer 314a. For example, an oxide semiconductor layer containing one or more metal elements is used. (metals such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or Hf) In other words, the oxide semiconductor layer has a higher atomic ratio of M than the oxide semiconductor layer 314a. The amount of element M is 1.5 times or more, preferably 2 times or more, more preferably 1.5 times or more, more preferably 2 times or more, more preferably 1.5 times or more, more preferably 2 times or more, more preferably 1.5 times or more, more preferably 2 times or more, more preferably 2.5 ... It is preferable to use an oxide semiconductor containing M at an atomic ratio three times or more higher. It binds more strongly to oxygen than indium, so it has the function of suppressing the occurrence of oxygen deficiency. Therefore, oxygen vacancies are less likely to occur in the oxide semiconductor layer 314b than in the oxide semiconductor layer 314a. The insulating layer may be an oxide semiconductor layer.

[0156] The oxide semiconductor layer 314b is formed of In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf) and is more conductive than the oxide semiconductor layer 314a. It is preferable to use an oxide semiconductor whose conduction band minimum energy is close to the vacuum level. For example, the energy of the bottom of the conduction band of the oxide semiconductor layer 314b and the energy of the bottom of the conduction band of the oxide semiconductor layer 314a are The difference in energy from the bottom of the conduction band is 0.05 eV or more, 0.07 eV or more, or 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or It is preferable to set it to 0.4 eV or less.

[0157] For example, when the oxide semiconductor layer 314b is an In-M-Zn oxide, the components other than Zn and oxygen are The atomic ratio of In and M is preferably less than 50 atomic % for In and less than 50 atomic % for M. omic% or more, more preferably, In is less than 25 atomic% and M is 75 atomic% or more. ic% or more.

[0158] For example, the oxide semiconductor layer 314a may have a composition of In:Ga:Zn=1:1:1 or 3:1:2. In the oxide semiconductor layer 31, an In-Ga-Zn oxide having an atomic ratio of 100 to 1500 can be used. 4b: In:Ga:Zn=1:3:2, 1:6:4, or 1:9:6 atomic ratio In-Ga-Zn oxide can be used. The atomic ratio of the compound semiconductor layer 314b is plus or minus the above atomic ratio as an error. Includes a 20% fluctuation in speed.

[0159] In addition, the semiconductor characteristics and electrical characteristics (field effect The appropriate composition should be used depending on the required properties (mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the oxide semiconductor layer 314a and the oxide semiconductor layer 31 4b Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, It is preferable to make the density etc. appropriate.

[0160] Note that in the above description, the oxide semiconductor layer 314 has a structure in which two oxide semiconductor layers are stacked. Although this is illustrated as an example, a structure in which three or more oxide semiconductor layers are stacked may be used.

[0161] "Substrate 301" There is no particular restriction on the material of the substrate 301, but it should be at least strong enough to withstand the subsequent heat treatment. Use heat-resistant materials. For example, glass substrate, ceramic substrate, quartz substrate, safa A ceramic substrate, a YSZ (yttria stabilized zirconia) substrate, etc. may be used as the substrate 301. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a silicon It is also possible to use a compound semiconductor substrate such as congermanium, an SOI substrate, or the like. Moreover, a substrate having a semiconductor element formed thereon may be used as the substrate 301. .

[0162] In addition, a flexible substrate such as plastic is used as the substrate 301, and the substrate is directly formed on the flexible substrate. Alternatively, the transistor 300 may be formed between the substrate 301 and the transistor 300. A peeling layer may be provided on the upper layer of the transistor. After that, it can be separated from the substrate 301 and used for transfer to another substrate. Therefore, the transistor 300 can be mounted on a substrate having low heat resistance or a flexible substrate.

[0163] <Gate electrode layer 302> The gate electrode layer 302 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or tantalum. or an alloy containing the above-mentioned metals or It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. The gate electrode layer 302 may be made of one or more of the following metals: It may be a single layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon A single-layer structure of the film, a two-layer structure of a titanium film laminated on an aluminum film, a titanium nitride film laminated on a titanium nitride film A two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, A two-layer structure in which a tungsten film is laminated on a tungsten film or a tungsten nitride film, a titanium film and A three-layer structure is formed in which an aluminum film is laminated on the titanium film, and a titanium film is further formed on the aluminum film. In addition, aluminum, titanium, tantalum, tungsten, molybdenum, chromium, etc. an alloy film combining one or more metals selected from chromium, neodymium, and scandium; Alternatively, a nitride film of these may be used.

[0164] The gate electrode layer 302 may be formed of indium tin oxide or indium containing tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide, etc. A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0165] In addition, an In-Ga-Zn-based oxynitride semiconductor is provided between the gate electrode layer 302 and the insulating layer 303. film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride semiconductor film Semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN These films have a surface area of ​​5 eV or more, preferably 5.5 eV or more. Since the work function is larger than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor used can be shifted to the positive side, resulting in a so-called normally-on For example, an In-Ga-Zn-based oxynitride semiconductor film can be used as a switching element with a high switching characteristic. In the case of using the oxide semiconductor layer 314, the nitrogen concentration is at least 7 atomic %. The above-mentioned In-Ga-Zn-based oxynitride semiconductor film is used.

[0166] Insulating layer 303 The insulating layer 303 functions as a gate insulating film. The edge layer 303 is preferably an amorphous film.

[0167] The insulating layer 303 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Copper, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide The above may be used, and the layer may be a laminate or a single layer.

[0168] The insulating layer 303 is made of hafnium silicate (HfSiOx ), nitrogen added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide By using this, the gate leakage of the transistor can be reduced.

[0169] Source Electrode Layer 305a and Drain Electrode Layer 305b The source electrode layer 305a and the drain electrode layer 305b are formed using a conductive material such as aluminum. Titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum The alloy mainly composed of tungsten or tungsten is used in a single layer structure. For example, a single layer of aluminum film containing silicon can be used. A two-layer structure in which a titanium film is laminated on an aluminum film, and a titanium film is laminated on a tungsten film A two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film. A titanium film or a titanium nitride film is laminated on the titanium film or the titanium nitride film by an aluminum film. A three-layer structure in which an aluminum or copper film is laminated and a titanium or titanium nitride film is formed on top of it. Structure, molybdenum film or molybdenum nitride film, and the molybdenum film or molybdenum nitride film An aluminum film or a copper film is laminated on the film, and a molybdenum film or a nitrogen film is further laminated on the aluminum film or a copper film. In addition, there are three-layer structures in which indium oxide, tin oxide or molybdenum oxide are formed. A transparent conductive material containing zinc may also be used.

[0170] In addition, at least the oxide semiconductor layer of the source electrode layer 305a and the drain electrode layer 305b The oxide semiconductor layer 314 is in contact with the oxide semiconductor layer 314, and oxygen is taken from the oxide semiconductor layer 314 to cause oxygen vacancies. It is preferable to use a material that can reduce oxygen vacancies in the oxide semiconductor layer 314. The carrier concentration in the affected region increases, the region becomes n-type, and the n-type region (n + layer). Thus, the regions can act as source and drain regions. As an example of a material capable of removing oxygen from the compound semiconductor layer 314 and causing oxygen vacancies, , tungsten, titanium, etc.

[0171] In addition, depending on the material and thickness of the oxide semiconductor layer 314, The entire region overlapping with the source electrode layer 305a and the drain electrode layer 305b is a source region. It can also be the drain region.

[0172] The source and drain regions are formed in the oxide semiconductor layer 314, so that the source The contact resistance between the electrode layer 305a and the oxide semiconductor layer 314 and between the drain electrode layer 305b and the oxide semiconductor layer 314 is reduced. Therefore, the electrical characteristics of the transistor, such as the field effect mobility and the threshold voltage, can be improved. The material can be made to have good properties.

[0173] Insulating layers 306 and 307 The insulating layer 306 is made of an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. It is preferable that the oxide insulating film contains more oxygen than the oxygen required for the stoichiometric composition. When heated, some oxygen is released. The oxide insulating film, including the On-line Spectroscopy analysis showed that the amount of oxygen released, calculated as oxygen atoms, was 1. 0×10 18 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 The oxide insulating film is as described above.

[0174] The insulating layer 306 may be an insulating layer containing silicon oxide, silicon oxynitride, or the like. Cut.

[0175] The insulating layer 306 is formed to cover the oxide semiconductor layer 31 when the insulating layer 307 is formed later. It also functions as a damage mitigation membrane for 4.

[0176] Alternatively, an oxide film through which oxygen passes may be provided between the insulating layer 306 and the oxide semiconductor layer 314. good.

[0177] As the oxide film that transmits oxygen, an insulating layer containing silicon oxide, silicon oxynitride, or the like is used. In this specification, the silicon oxynitride film has a composition of A silicon nitride oxide film is a film that contains more oxygen than nitrogen. The composition of the silicon nitride oxide film is as follows: This refers to a film that contains more nitrogen than oxygen.

[0178] The insulating layer 307 can be made of an insulating film having a blocking effect against oxygen, hydrogen, water, etc. By providing the insulating layer 307 over the insulating layer 306, oxygen from the oxide semiconductor layer 314 can be prevented. Therefore, the diffusion of hydrogen, water, and the like to the outside and the intrusion of hydrogen, water, and the like into the oxide semiconductor layer 314 from the outside can be prevented. Examples of insulating films that have a blocking effect against oxygen, hydrogen, water, etc. include silicon nitride, Silicon oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride Yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride There is an insulating layer containing

[0179] Note that a channel protective film may be provided over a channel formation region of the oxide semiconductor layer 314. The channel protective film may be provided between the source electrode layer 305a and the oxide semiconductor layer 314 or between the It is also provided between the drain electrode layer 305b and the oxide semiconductor layer 314. When a protective film is provided, the transistor becomes a channel protective type. The protective film may be, for example, a silicon oxide film or a silicon oxynitride film. When forming a silicon oxide film or a silicon oxynitride film, the source gas is silicon. It is preferable to use a deposition gas containing silicon and an oxidizing gas. Representative examples include silane, disilane, trisilane, and fluorinated silane. Examples include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0180] <Modifications of Transistor 300> An example of the configuration of a transistor that is partially different from the transistor 300 will be described below.

[0181] Variation 1 FIG. 9B is a schematic cross-sectional view of a transistor 310. The transistor 310 is an oxide It differs from the transistor 300 in that the configuration of the semiconductor layers is different.

[0182] In the transistor 310, the oxide semiconductor layer 304 is an oxide semiconductor layer 304a. The oxide semiconductor layer 304a includes an oxide semiconductor layer 304b including nanocrystals. In addition, the oxide semiconductor layer 304b has a film density higher than that of the oxide semiconductor layer 304a. The oxide semiconductor layer 3 is preferably an oxide semiconductor layer having a high conductivity and a low density of defect states. 04b, CAAC-OS is applied. That is, the transistor 31 of this embodiment is In the embodiment 0, the oxide semiconductor layer 304 is the oxide semiconductor layer In the transistor 310, the insulating layer 303 corresponds to the conductor layer 104. 1 corresponds to the insulating layer 102 shown in FIG.

[0183] Note that the components of the transistor 310 other than the oxide semiconductor layer 304 are the same as those of the transistor 300 can be taken into consideration.

[0184] Variation 2 FIG. 9C is a schematic cross-sectional view of a transistor 320. The transistor 320 is an oxide The transistor 300 differs from the transistor 310 in the configuration of the semiconductor layer. do.

[0185] The oxide semiconductor layer 324 of the transistor 320 includes an oxide semiconductor layer 324a and an oxide The semiconductor layer 324b and the oxide semiconductor layer 324c are laminated in this order.

[0186] The oxide semiconductor layer 324a and the oxide semiconductor layer 324b are stacked over the insulating layer 303. The oxide semiconductor layer 324c is formed on the top surface of the oxide semiconductor layer 324b and on the source The drain electrode layer 305a and the drain electrode layer 305b are provided in contact with each other.

[0187] The oxide semiconductor layer 324a and the oxide semiconductor layer 324c are oxide semiconductor layers containing nanocrystals. In addition, the oxide semiconductor layer 324b can be formed by the following method. and an oxide semiconductor layer having a higher film density and a lower density of defect states than the oxide semiconductor layer 324c. Preferably, CAAC-OS is used for the oxide semiconductor layer 324b.

[0188] <Example of transistor manufacturing method> Next, an example of a method for manufacturing the transistor 300 illustrated in FIG. 9A will be described.

[0189] First, as shown in FIG. 10A, a gate electrode layer 302 is formed on a substrate 301. An insulating layer 303 is formed on the electrode layer 302 .

[0190] Here, a glass substrate is used as the substrate 301 .

[0191] <<Formation of gate electrode layer>> The method for forming the gate electrode layer 302 will be described below. First, a sputtering method, a CVD method, A conductive film is formed by a deposition method or the like, and a photolithography is performed on the conductive film using a first photomask. A resist mask is formed by a photolithography process. Next, a portion of the conductive film is The portion is etched to form a gate electrode layer 302. After that, the resist mask is removed. do.

[0192] The gate electrode layer 302 may be formed by electrolytic plating, printing, inkjet printing, or the like instead of the above-mentioned method. It may be formed by a jet method or the like.

[0193] <<Formation of gate insulating layer>> The insulating layer 303 that functions as a gate insulating layer is formed by a sputtering method, a CVD method, a deposition method, or the like. Form.

[0194] The insulating layer 303 is a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. In the case of forming the silicon-containing film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen oxides.

[0195] In addition, when forming a silicon nitride film as the insulating layer 303, a two-stage formation method is used. First, a mixture of silane, nitrogen, and ammonia is used as a raw material gas. A first silicon nitride film with few defects is formed by the plasma CVD method using the same material. The fuel gas was changed to a mixture of silane and nitrogen, and the hydrogen concentration was low and hydrogen was not blown. A second silicon nitride film capable of being coated is formed. As the insulating layer 303, a silicon nitride film having few defects and a hydrogen blocking property is used. can be formed.

[0196] In addition, when a gallium oxide film is formed as the insulating layer 303, MOCVD (Metal O Formed using the organic chemical vapor deposition (OCVD) method It is possible.

[0197] <<Formation of oxide semiconductor layer>> Next, as shown in FIG. 10B, an oxide semiconductor layer 304 is formed over the insulating layer 303.

[0198] The oxide semiconductor layer 314 can be formed by the method described in Embodiment 2. In the embodiment, first, an oxide semiconductor including CAAC-OS is formed on the substrate 301 while the substrate 301 is heated. A conductor layer 314a is formed, and then the substrate temperature is set to room temperature to form an oxide semiconductor layer 314b. Then, a photolithography process is performed on the oxide semiconductor layer 314b using a photomask. Next, a resist mask is formed by the process of forming an island-shaped oxide semiconductor using the resist mask. A dielectric layer 314 is formed, and then the resist mask is removed.

[0199] When the oxide semiconductor layer 314a is formed, the substrate 301 is heated to a temperature of 150° C. The substrate temperature may be set to 200° C. or higher and 450° C. or lower, and preferably, the substrate temperature is set to 200° C. or higher and 350° C. or lower. Note that forming an oxide semiconductor layer while the substrate 301 is kept at high temperature is an oxide semiconductor layer. This is effective in reducing the concentration of impurities that may be contained in the oxide semiconductor layer.

[0200] After the oxide semiconductor layer 314 is formed, excess hydrogen (including water and a hydroxyl group) contained in the film is removed. It is preferable to perform a heat treatment to remove (dehydrate or dehydrogenate) the above-mentioned. The temperature of the heat treatment is The temperature is 300°C to 700°C, or lower than the distortion point of the substrate. This heat treatment can be carried out under atmospheric conditions. Some hydrogen can be removed.

[0201] Note that the heat treatment for dehydration or dehydrogenation can be performed after the formation of the oxide semiconductor layer. The dehydration or dehydrogenation may be carried out at any time during the process of preparing the photocatalyst. The heat treatment for this purpose may be carried out multiple times or may be combined with other heat treatments.

[0202] In heat treatment, nitrogen or rare gases such as helium, neon, argon, water, hydrogen, etc. It is preferable that the nitrogen, helium, or neon introduced into the heat treatment device is not included. The purity of rare gas such as argon should be 6N (99.9999%) or more, preferably 7N (99. 99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to do so.

[0203] After the oxide semiconductor layer 314 is heated by the heat treatment, the heating temperature is maintained or the heating temperature is increased. While slowly cooling from the beginning, high purity oxygen gas, high purity dinitrogen monoxide gas, or ultra-dry air was added to the same furnace. The dew point was measured using a CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter. In this case, the moisture content is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, more preferably Preferably, air of 10 ppb or less may be introduced. It is preferable that the oxygen gas or the like introduced into the heat treatment device does not contain water, hydrogen, etc. The purity of the dinitrogen monoxide gas is 6N or more, preferably 7N or more (i.e., oxygen gas or dinitrogen monoxide gas). It is preferable to keep the impurity concentration in the nitrogen gas at 1 ppm or less, preferably 0.1 ppm or less. It is preferable that the action of oxygen gas or nitrous oxide gas is used to remove impurities caused by dehydration or dehydrogenation treatment. The main component material of the oxide semiconductor that was reduced at the same time by the process of removing the pure material. By supplying oxygen, the oxide semiconductor layer is highly purified and made to be i-type (intrinsic). can be done.

[0204] In order to obtain a high-purity intrinsic oxide semiconductor, it is necessary to not only evacuate the chamber to a high vacuum, but also to In addition, the sputtering gas must be highly purified. The gas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using gas that has been highly purified up to 1000 times, moisture and other substances can be absorbed into the oxide semiconductor. It can be prevented as much as possible.

[0205] In addition, oxygen, which is a main component material of an oxide semiconductor, can be removed by the dehydration or dehydrogenation treatment. Since there is a risk that the amount of The compound semiconductor layer is doped with oxygen (at least one of oxygen radicals, oxygen atoms, and oxygen ions). ) may be introduced to supply oxygen into the film.

[0206] Oxygen is introduced into the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. By this, the oxide semiconductor layer can be highly purified and made to be i-type (intrinsic). A transistor having a purified i-type (intrinsic) oxide semiconductor has low fluctuation in electrical characteristics. It is controlled and electrically stable.

[0207] <<Formation of Source Electrode Layer and Drain Electrode Layer>> Next, as shown in FIG. 10C, the source electrode layer 305a and the drain electrode layer 305b are Form.

[0208] A method for forming the source electrode layer 305a and the drain electrode layer 305b will be described below. A conductive film is formed by a sputtering method, a CVD method, a vapor deposition method, or the like. Next, a third A resist mask is formed by a photolithography process using a photomask. The conductive film is partly etched using the resist mask to form the source electrode layer 305a and the The rain electrode layer 305b is formed, and then the resist mask is removed.

[0209] Note that as shown in FIG. 10C, when the conductive film is etched, the top of the oxide semiconductor layer 304 is In some cases, a portion of the surface may be etched and thinned.

[0210] <<Formation of insulating layer>> Next, as shown in FIG. 10D, the oxide semiconductor layer 304, the source electrode layer 305a, and the drain electrode layer 305b are An insulating layer 306 is formed on the rain electrode layer 305b, and then an insulating layer 30 is formed on the insulating layer 306. Form 7.

[0211] When a silicon oxide film or a silicon oxynitride film is formed as the insulating layer 306, the source gas As the gas, a deposition gas containing silicon and an oxidizing gas are preferably used. Representative examples of deposition gases containing silane include silane, disilane, trisilane, and fluorosilane. The oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0212] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180° C. or higher. The temperature is kept at 260° C. or less, more preferably at 200° C. or more and 240° C. or less, and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is adjusted to 100 Pa or more and 250 Pa or less, more preferably 1 00 Pa to 200 Pa, and 0.17 W / cm2 to the electrode installed in the treatment chamber 2 End 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 More than 0.35W / cm 2 Below Silicon oxide film or silicon oxynitride film is formed by supplying high frequency power under the following conditions. do.

[0213] As a film formation condition, high frequency power with the above power density is supplied in a processing chamber with the above pressure. In the plasma, the decomposition efficiency of the source gas increases, oxygen radicals increase, and the source gas is oxidized. As a result, the oxygen content in the oxide insulating film becomes higher than the stoichiometric ratio. However, when the substrate temperature is above this level, the bond between silicon and oxygen is weak, and the A portion of the oxygen is released. As a result, the mixture contains more oxygen than the stoichiometric composition. In this case, an oxide insulating film from which part of oxygen is released by heating can be formed.

[0214] In addition, in the case where an oxide insulating film is provided between the oxide semiconductor layer 304 and the insulating layer 306, In the step of forming the layer 306 , the oxide insulating film serves as a protective film for the oxide semiconductor layer 304 . As a result, damage to the oxide semiconductor layer 304 is reduced, and high-frequency power density is reduced. A force may be used to form the insulating layer 306 .

[0215] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180° C. or higher. The temperature is kept at 400° C. or less, more preferably 200° C. to 370° C., and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is adjusted to 20 Pa or more and 250 Pa or less, more preferably 10 The pressure is between 0 Pa and 250 Pa, and high-frequency power is supplied to the electrode installed in the processing chamber. As a result, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film. In addition, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the oxide insulation can be improved. When the insulating layer is formed, damage to the oxide semiconductor layer 304 can be reduced.

[0216] As the source gas for the oxide insulating film, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen oxides.

[0217] The insulating layer 307 can be formed by a sputtering method, a CVD method, or the like.

[0218] When a silicon nitride film or a silicon nitride oxide film is formed as the insulating layer 307, the raw material gas The gas used may be a deposition gas containing silicon, an oxidizing gas, or a gas containing nitrogen. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and fluorinated silane. Nitrogen, etc. Nitrogen-containing gases include nitrogen and ammonia.

[0219] Through the above steps, the transistor 300 can be formed.

[0220] <Other examples of transistor configurations> A top-gate transistor to which the oxide semiconductor layer of one embodiment of the present invention can be applied will be described below. A configuration example of the data recorder will be described below.

[0221] In the following, components having the same configuration or function as those described above will be referred to as the same. Each component will be given the same reference symbol, and duplicated explanations will be omitted.

[0222] Example of configuration FIG. 11A is a schematic cross-sectional view of a top-gate transistor 360.

[0223] The transistor 360 is an oxide semiconductor provided on a substrate 301 on which an insulating layer 351 is provided. The oxide semiconductor layer 364 and the source electrode layer 305a and the drain electrode layer 305b are in contact with the upper surface of the oxide semiconductor layer 364. The electrode layer 305b, the oxide semiconductor layer 364, the source electrode layer 305a, and the drain electrode layer 3 05b, and a portion over the insulating layer 303 overlapping with the oxide semiconductor layer 364. The insulating layer 303 and the gate electrode layer 302 are formed in such a manner that the insulating layer 303 and the gate electrode layer An insulating layer 352 is provided over 302 .

[0224] The oxide semiconductor layer of one embodiment of the present invention is applied to the oxide semiconductor layer 364 of the transistor 360. It is possible.

[0225] For example, the oxide semiconductor layer 364 includes an oxide semiconductor layer 364a and an oxide semiconductor layer 364b. Here, the oxide semiconductor layer 364a and the oxide semiconductor layer 364c are The layer 364c is an oxide semiconductor layer including nanocrystals. The oxide semiconductor layer 364b has a higher film density and a lower defect density than the oxide semiconductor layer 364a and the oxide semiconductor layer 364c. An oxide semiconductor layer with a low density of states is preferably used as the oxide semiconductor layer 364b. , and apply CAAC-OS.

[0226] The insulating layer 351 has a function of suppressing diffusion of impurities from the substrate 301 to the oxide semiconductor layer 364. For example, the insulating layer 307 may have the same structure as the insulating layer 307. 351 need not be provided if it is not necessary.

[0227] The insulating layer 352 has a blocking effect against oxygen, hydrogen, water, etc., similar to the insulating layer 307. Note that the insulating layer 307 may not be provided if it is not necessary. stomach.

[0228] <<Variation>> An example of the configuration of a transistor that is partially different from the transistor 360 will be described below.

[0229] FIG. 11B is a schematic cross-sectional view of a transistor 370. The transistor 370 is a source The transistor 360 differs from the transistor 360 in that the configurations of the source electrode layer and the drain electrode layer are different. More specifically, in the transistor 370, the source electrode layer 31 is formed on the source electrode layer 305a. 6a is formed, and a drain electrode layer 316b is formed on the drain electrode layer 305b. The points are different.

[0230] As described above, the source electrode layer 305a and the drain electrode layer 305b are formed of an oxide semiconductor. By using a material that can generate oxygen vacancies in the oxide semiconductor layer, Oxygen vacancies occur in the areas near the contact with the source electrode layer 305a and the drain electrode layer 305b. The region becomes n-type and acts as a source region or drain region of a transistor. It is possible.

[0231] However, when forming a transistor with an extremely short channel length, the occurrence of oxygen vacancies is The n-type region caused by the growth may extend in the direction of the transistor channel length. In this case, the electrical characteristics of the transistor include the variation of the threshold voltage and the difference between the source and drain regions. The on-state region becomes conductive, and the on-state and off-state cannot be controlled. Therefore, when forming a transistor with an extremely short channel length, the source electrode layer and the drain electrode layer It is not preferable to use a conductive material that easily bonds with oxygen for the silicon electrode layer.

[0232] Therefore, the source electrode layer 305a and the drain electrode layer 305b shown as L1 in FIG. The distance between the first and second electrodes 5b is 0.8 μm or more, preferably 1.0 μm or more. L1 is 0.8 μm. If it is smaller, the effect of oxygen vacancies occurring in the channel formation region cannot be eliminated. The electrical characteristics of the transistor may be degraded. From the end of the source electrode layer 305a to the end of the drain electrode layer 305b, which are in contact with each other and face each other In Figure 11(B), the n-type region is shown by a dotted line. Illustrated.

[0233] Therefore, in the transistor 370, a conductive material that is not easily bonded to oxygen is used to form a source electrode layer. A source electrode layer 316a is formed in contact with the oxide semiconductor layer 305a and the oxide semiconductor layer 364. The drain electrode layer 305b and the oxide semiconductor layer 364 are connected to each other using a conductive material that is not easily bonded to the oxide semiconductor layer 364. This forms the drain electrode layer 316b.

[0234] The source electrode layer 316a is formed by insulating the end of the source electrode layer 305a which is in contact with the oxide semiconductor layer 364. The drain electrode layer 316b extends in the direction of L1 beyond the oxide semiconductor layer 364. It extends in the direction L1 beyond the end of the drain electrode layer 305b.

[0235] The above-mentioned extended portion of the source electrode layer 316a and the above-mentioned extended portion of the drain electrode layer 316b are oxidized. In addition, the oxide semiconductor layer 364 is in contact with the oxide semiconductor layer 364c. In the transistor 370 shown in FIG. 1, the oxide semiconductor of the extension of the source electrode layer 316a is The oxide semiconductor of the above-mentioned extending portion of the drain electrode layer 316b is The distance from the tip of the electrode to the tip of the electrode 364 is the channel length, and is shown in FIG. 11(B) as L2. show.

[0236] The oxygen that is used to form the source electrode layer 316a and the drain electrode layer 316b is unlikely to bond with the oxygen. The conductive material may be, for example, a conductive nitride such as tantalum nitride or titanium nitride, or ruthenium. It is preferable to use niobium or the like. In addition, the conductive material that is difficult to bond with oxygen has a low oxygen diffusion rate. The thickness of the conductive material is preferably 5 nm to 500 nm. , more preferably 10 nm or more and 300 nm or less, and further preferably 10 nm or more and 100 nm or less. m or less.

[0237] The conductive material that is difficult to bond with oxygen is used as the source electrode layer 316a and the drain electrode layer 316b. By using the oxide semiconductor layer 364, oxygen vacancies are formed in a channel formation region of the oxide semiconductor layer 364. It is possible to suppress the formation of n-type in the channel formation region. Therefore, even a transistor with an extremely short channel length can have good electrical characteristics. That is, it is possible to set L2 to a value smaller than L1. For example, Even if 2 is 30 nm or less, good transistor electrical characteristics can be obtained. When the single crystal region included in the oxide semiconductor layer 364 has a width of 30 nm or more, In the cross section in the channel length direction, the entire region of the channel formation region is a single-crystal oxide semiconductor layer. Possible.

[0238] Incidentally, conductive nitrides such as tantalum nitride and titanium nitride may absorb hydrogen. Therefore, by providing a conductive nitride in contact with the oxide semiconductor layer 364, the oxide semiconductor layer 3 The hydrogen concentration in 64 can be reduced.

[0239] When forming a transistor with an extremely short channel length, fine lithography such as electron beam exposure is used. A resist mask is formed using a method suitable for line processing, and etching is performed. The source electrode layer 316a and the drain electrode layer 316b may be formed by the above-mentioned method. If a positive resist is used as the resist mask, the exposed area can be minimized. By using this method, the channel length can be increased to 3 It is possible to fabricate transistors with a thickness of 0 nm or less.

[0240] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. can be done.

[0241] (Embodiment 5) As an example of a semiconductor device according to one embodiment of the present invention, a circuit diagram of a NOR circuit which is a logic circuit is shown in FIG. An example is shown in Figure 12(A) and Figure 12(B) is a circuit diagram of a NAND type circuit.

[0242] In the NOR circuit shown in FIG. 12(A), a p-channel transistor is The transistors 801 and 802 have a channel formation region formed of a semiconductor material other than an oxide semiconductor (for example, a silicon The transistor is an n-channel transistor, and the transistor 8 is an n-channel transistor. The transistors 803 and 804 include an oxide semiconductor and have a structure similar to that of the transistor described in Embodiment 4. A transistor that performs this function is used.

[0243] Transistors made of semiconductor materials such as silicon can operate at high speeds. A transistor using a semiconductor is capable of holding charge for a long period of time due to its characteristics.

[0244] In order to miniaturize the logic circuit, n-channel transistors 803 and 8 04 is stacked on p-channel transistors 801 and 802. For example, it is preferable to form the transistors 801 and 802 using a single crystal silicon substrate. Transistors 803 and 804 are formed on the transistors 801 and 802 via an insulating layer. It is possible to achieve this.

[0245] In the NAND circuit shown in FIG. 12B, the transistors are p-channel transistors. The transistors 811 and 814 have channel formation regions formed of a semiconductor material other than an oxide semiconductor (e.g., The transistor is an n-channel transistor, and the transistor is made of silicon. The transistors 812 and 813 each include an oxide semiconductor layer and have the same structure as the transistor described in Embodiment 4. A transistor having a different structure is used.

[0246] In the NAND circuit shown in FIG. The potential of the second gate electrode of the transistor 360 is controlled by a transistor having a similar configuration to the transistor 360. For example, by setting the input terminal to GND, the threshold voltage of the transistors 812 and 813 becomes more positive. Furthermore, the transistor can be a normally-off transistor.

[0247] In addition, in order to miniaturize the logic circuit, an n-channel NOR circuit is used, similar to the NOR circuit shown in FIG. The transistors 812 and 813 are p-channel transistors. It is preferably stacked on certain transistors 811 and 812 .

[0248] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using transistors with extremely low power consumption, power consumption can be sufficiently reduced.

[0249] In addition, stacking semiconductor elements using different semiconductor materials allows for miniaturization and high integration. A semiconductor device having stable and high electrical characteristics and a method for manufacturing the semiconductor device A method can be provided.

[0250] In addition, by applying the structure of a transistor including an oxide semiconductor layer according to one embodiment of the present invention, This makes it possible to provide NOR and NAND circuits that are highly reliable and exhibit stable characteristics. Cut.

[0251] In this embodiment, a NOR circuit using the transistor described in Embodiment 3 and an NOR Although an example of an AND circuit is shown, the present invention is not limited to this. The transistors shown in the embodiment 3 may be used. It is also possible to form AND circuits, OR circuits, etc.

[0252] Alternatively, the transistor described in this embodiment or another embodiment may be combined with a display element. For example, a display device having a display element and a display element can be formed by combining the above elements. Display devices, light emitting devices, and light emitting devices having light emitting devices are available in various forms. A display element, a display device, a light-emitting element, or a display device having various elements can be used. An example of a light-emitting device is an EL (electroluminescence) element (organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs (color LEDs, blue LEDs, etc.), transistors (transistors that emit light according to the current), Emission element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GL V), plasma display (PDP), digital micromirror device (DMD), Piezoelectric ceramic displays, carbon nanotubes, etc., are made by electromagnetic interactions. Some have display media that change contrast, brightness, reflectance, transmittance, etc. An example of a display device using electron-emitting devices is an EL display. An example of such a display device is a field emission display (FED) or SED. Type Flat Panel Display (SED: Surface-conduction Elect Examples of display devices using liquid crystal elements include Examples include LCDs (transmissive LCDs, semi-transmissive LCDs, reflective LCDs, etc.) LCD displays include projection LCDs, direct-view LCDs, and projection LCDs. An example of a display device using electronic ink or electrophoretic elements is electronic paper. do.

[0253] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0254] (Embodiment 6) In this embodiment mode, the transistor described in Embodiment 3 is used, and the transistor is used in a case where power is not supplied. However, it is possible to retain memory contents and there is no limit to the number of times it can be written to. An example of the above will be described with reference to the drawings.

[0255] FIG. 13A is a circuit diagram showing the semiconductor device of the present embodiment.

[0256] The transistor 260 in FIG. 13A is made of a semiconductor material other than an oxide semiconductor (for example, This allows the use of transistors using silicon (e.g., silicon nitride), making high-speed operation easy. The transistor 262 includes an oxide semiconductor layer according to one embodiment of the present invention, and is the same as the transistor 262 described in Embodiment 4. A transistor having a structure similar to that of a transistor can be applied, and its characteristics allow for long-term This allows the charge to be retained for a long time.

[0257] It should be noted that the above transistors are all n-channel transistors. However, the transistor used in the semiconductor device described in this embodiment is a p-channel transistor. A transistor may also be used.

[0258] In FIG. 13A, the first wiring (1st Line) and the source of the transistor 260 The electrode layer is electrically connected to the second wiring (2nd Line) and the transistor 260 The drain electrode layer is electrically connected to the third wiring (3rd Line ) is electrically connected to one of the source electrode layer and the drain electrode layer of the transistor 262. The fourth line and the gate electrode layer of the transistor 262 are electrically connected to each other. The gate electrode layer of the transistor 260 and the gate electrode layer of the transistor 26 The other of the source electrode layer and the drain electrode layer of the second capacitor 264 is electrically connected to one of the electrodes of the capacitor 264. The fifth wiring and the other electrode of the capacitor 264 are electrically connected. Connected.

[0259] In the semiconductor device shown in FIG. 13A, the potential of the gate electrode layer of the transistor 260 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0260] The writing and holding of data will be described. First, the potential of the fourth wiring is set to The transistor 262 is turned on by applying a potential to the transistor 262. The potential of the third wiring is applied to the gate electrode layer of the transistor 260 and the capacitor 264. That is, a predetermined charge is applied to the gate electrode layer of the transistor 260. (Write). Here, the charges that give two different potential levels (hereafter, low-level charges) Then, the fourth wiring The potential of the transistor 262 is set to a potential at which the transistor 262 is turned off. By setting the transistor 260 in the ON state, the charge applied to the gate electrode layer of the transistor 260 is held. (retain).

[0261] Since the off-state current of the transistor 262 is extremely low, the gate electrode layer of the transistor 260 The charge is retained for a long period of time.

[0262] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 260 Depending on the amount of charge held in the electrode layer, the second wiring has a different potential. If the transistor 260 is an n-channel type, a high level is applied to the gate electrode layer of the transistor 260. The apparent threshold voltage V for a given charge th_H The gate of transistor 260 The apparent threshold voltage V when a low-level charge is applied to the gate electrode layer th_L twist Here, the apparent threshold voltage is the voltage at which the transistor 260 is turned "on". The term "potential of the fifth wiring" refers to the potential of the fifth wiring required to achieve the "state". The potential of V th_H and V th_L By setting the potential V0 at the intermediate potential between the transistor 26 0 gate electrode layer. For example, in writing, When a level charge is applied, the potential of the fifth wire is V0 (>V th_H ) If a low level charge is applied, the transistor 260 is in the "on state." The potential of the fifth wire is V0( <V th_L ), transistor 260 remains in the "ON" state. Therefore, by observing the potential of the second wiring, the stored information can be read out.

[0263] When memory cells are arranged in an array, only the information in a desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 260 is in the "off state" regardless of th_H Alternatively, the potential of the fifth wiring may be lower than that of the fifth wiring. The potential at which the transistor 260 is in the "on" state, i.e., V th_L Higher potential should be applied to the fifth wire.

[0264] FIG. 13B shows an example of a structure of a different memory device. FIG. 13C is a conceptual diagram showing an example of a semiconductor device. The semiconductor device shown in FIG. 13(B) will be described first, followed by the semiconductor device shown in FIG. 13(C). The location will be explained below.

[0265] In the semiconductor device shown in FIG. 13B, the bit line BL and the source voltage of the transistor 262 The gate or drain electrode of the transistor 262 is electrically connected to the word line WL. The source electrode layer is electrically connected to the source electrode or drain electrode of the transistor 262. The first terminal of the capacitance element 254 is electrically connected.

[0266] The transistor 262 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 262 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) can be maintained for an extremely long period of time. It is possible to have it.

[0267] Next, data is written and stored in the semiconductor device (memory cell 250) shown in FIG. The case where the above is performed will be explained.

[0268] First, the potential of the word line WL is set to a potential at which the transistor 262 is turned on. The transistor 262 is turned on. This causes the potential of the bit line BL to change to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal of the transistor 2 By setting the potential at which the transistor 262 is turned off, the capacitance The potential of the first terminal of the quantum element 254 is held (held).

[0269] Since the off-state current of the transistor 262 is extremely low, the potential of the first terminal of the capacitor 254 ( Alternatively, the charge stored in the capacitor 254 can be held for a long period of time.

[0270] Next, the reading of information will be described. When the transistor 262 is turned on, The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in the potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0271] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 250 is In this case, the potential of the first terminal of the capacitance element 254 is assumed to be in two states, V1 and V0 (V1>V0). Then, the potential of the bit line BL when the potential V1 is held is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is held (=(CB × VB0+C×V0) / (CB+C)).

[0272] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0273] As described above, in the semiconductor device illustrated in FIG. 13B, the off-state current of the transistor 262 is extremely low. Since the capacitance is low, the charge stored in the capacitance element 254 can be held for a long time. In other words, refresh operations are not required or the frequency of refresh operations can be reduced. Since it is possible to extremely reduce the power consumption, Even if there is no power supply, the memory contents can be retained for a long period of time. do.

[0274] Next, the semiconductor device shown in FIG.

[0275] The semiconductor device shown in FIG. 13C has a memory cell shown in FIG. 13B in an upper portion thereof as a memory circuit. A memory cell array 251 having a plurality of memory cells 250 (memory cell array 251a and memory cell The memory cell array 251b has a peripheral circuit necessary for operating the memory cell array 251. The peripheral circuit 253 is electrically connected to the memory cell array 251. This is being continued.

[0276] By using the configuration shown in FIG. 13C, the peripheral circuit 253 is connected to the memory cell array 251. (Memory cell array 251a and memory cell array 251b) Therefore, the semiconductor device can be made smaller.

[0277] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 262. It is more preferable to use silicon, germanium, silicon germanium, etc. Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can be used. Alternatively, organic semiconductor materials may be used. The transistor can operate at a sufficiently high speed. It is possible to realize various circuits (logic circuits, driver circuits, etc.) that require high speed operation. be.

[0278] In the semiconductor device shown in FIG. 13C, two memory cell arrays 251 (memory cell In the illustrated embodiment, a stacked memory cell array 251a and a stacked memory cell array 251b are used. The number of memory cell arrays to be stacked is not limited to this. It may be configured as follows.

[0279] The transistor 262 includes an oxide semiconductor layer of one embodiment of the present invention in a channel formation region. By using transistors that can store data, it is possible to retain the data for a long period of time. In other words, no refresh operation is required, or the frequency of refresh operations is extremely low. Since it is possible to fabricate a semiconductor memory device with a smaller number of memory cells than ever before, power consumption can be reduced sufficiently. can be done.

[0280] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0281] (Embodiment 7) In this embodiment, a structure of a display panel according to one embodiment of the present invention will be described with reference to FIG. explain.

[0282] FIG. 14A is a top view of a display panel according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 14C is a circuit diagram for explaining a display panel according to one embodiment of the present invention. A circuit diagram for explaining a pixel circuit that can be used when an organic EL element is used as a substrate. It is.

[0283] The transistor disposed in the pixel portion can be formed according to the third embodiment. Since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be made of type transistors on the same substrate as the transistors in the pixel section. In this manner, the transistor described in Embodiment 3 is used in the pixel portion and the driver circuit. This makes it possible to provide a highly reliable display device.

[0284] An example of a block diagram of an active matrix display device is shown in FIG. On a substrate 500, a pixel section 501, a first scanning line driving circuit 502, a second scanning line driving circuit The pixel portion 501 includes a signal line driver circuit 503 and a signal line driver circuit 504. A first scanning line driving circuit 502 extends from the first scanning line driving circuit 504. The scanning line driving circuit 503 is arranged to extend from the scanning line driving circuit 503. In the display area, pixels each having a display element are arranged in a matrix. The substrate 500 is a connection board for FPC (Flexible Printed Circuit) etc. It is connected to a timing control circuit (also called a controller or control IC) via .

[0285] In FIG. 14A, a first scanning line driver circuit 502, a second scanning line driver circuit 503, a signal line The driver circuit 504 is formed on the same substrate 500 as the pixel portion 501. Since the number of components such as the drive circuits to be mounted is reduced, the cost can be reduced. 00When an external driving circuit is provided, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driving circuit is provided on the same substrate 500, the number of connections between the wirings can be reduced. Therefore, it is possible to improve reliability or yield.

[0286] <Liquid crystal panel> An example of the circuit configuration of a pixel is shown in FIG. 14(B). 4 shows a pixel circuit that can be applied to the pixel.

[0287] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of a multi-domain pixel to be The signals applied to the electrode layers can be controlled independently.

[0288] The gate wiring 512 of the transistor 516 and the gate wiring 513 of the transistor 517 are , are separated so that different gate signals can be applied. On the other hand, The functioning source or drain electrode layer 514 is a transistor 516 and a transistor The transistors 516 and 517 are used in common. The transistors described in Section 3 can be used appropriately. This makes it possible to realize a highly reliable liquid crystal display. A display panel can be provided.

[0289] A first pixel electrode layer electrically connected to the transistor 516 and a second pixel electrode layer electrically connected to the transistor 517 The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The shape of the electrode layer is separated by slits. The first pixel electrode layer spreads in a V-shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0290] The gate electrode layer of the transistor 516 is connected to the gate wiring 512, and the gate electrode layer of the transistor 517 is connected to the gate wiring 512. The gate electrode layer of the gate electrode 512 is connected to the gate wiring 513. 13, different gate signals are applied to transistors 516 and 517. By varying the orientation of the liquid crystal, the alignment of the liquid crystal can be controlled.

[0291] In addition, the capacitance wiring 510, the gate insulating layer functioning as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0292] The multi-domain structure includes a first liquid crystal element 518 and a second liquid crystal element 519 in one pixel. The first liquid crystal element 518 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 519 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. do.

[0293] Note that the pixel circuit shown in FIG. 14B is not limited to this. The pixels are now equipped with new switches, resistors, capacitors, transistors, sensors, logic circuits, etc. Any of the above may be added.

[0294] <Organic EL panel> Another example of the circuit configuration of a pixel is shown in FIG. 14(C). 4 shows the pixel structure of the display panel.

[0295] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, which When the excited state of the electron returns to the ground state, light is emitted. The element is called a current-excited light-emitting element.

[0296] FIG. 14C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can apply digital time gray scale driving.

[0297] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, He explains.

[0298] The pixel 520 includes a switching transistor 521, a driving transistor 522, and a light-emitting element The switching transistor 521 has a gate electrode 524 and a capacitance element 523. The first electrode layer is connected to the scanning line 526, and the second electrode (one of the source electrode layer and the drain electrode layer) is connected to the scanning line 526. ) is connected to a signal line 525, and the second electrode (the other of the source electrode layer and the drain electrode layer) is The driving transistor 522 is connected to the gate electrode layer of the driving transistor 522. The gate electrode layer is connected to a power supply line 527 via a capacitance element 523, and the first electrode is connected to the power supply line 527. 27, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 524. The second electrode of the light emitting element 524 corresponds to a common electrode 528. The common electrode 528 is formed on the same substrate. The common potential line is electrically connected to the common potential line formed in the

[0299] The switching transistor 521 and the driving transistor 522 are the same as those described in the third embodiment. This allows the use of transistors that illuminate the display, making it possible to achieve highly reliable organic EL displays. A panel can be provided.

[0300] The potential of the second electrode (common electrode 528) of the light emitting element 524 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential set on the power supply line 527, for example, GND The low power supply potential can be set to 0 V or the like. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 524, a current flows through the light emitting element 524, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and must be at least the forward threshold. Includes low-value voltages.

[0301] The capacitance element 523 can be omitted by substituting the gate capacitance of the driving transistor 522. The gate capacitance of the driving transistor 522 can be omitted. A capacitance may be formed between the first electrode layer and the second electrode layer.

[0302] Next, a signal input to the driving transistor 522 will be described. In this case, the driving transistor 522 is either fully on or fully off. A video signal such as the above is input to the driving transistor 522. In order to operate the drive transistor 522 in a linear region, a voltage higher than the voltage of the power supply line 527 is applied to the drive transistor 522. A signal line 525 is connected to the gate electrode layer of the transistor 522. A voltage equal to or greater than the threshold voltage Vth of the input transistor 522 is applied.

[0303] When analog gradation driving is performed, the gate electrode layer of the driving transistor 522 is connected to the light emitting element 52 A voltage equal to or greater than the sum of the forward voltage of the transistor 4 and the threshold voltage Vth of the driving transistor 522 is applied. In addition, a video signal is input so that the driving transistor 522 operates in the saturation region. A current flows through the light emitting element 524. In addition, the driving transistor 522 is operated in a saturation region. In order to achieve this, the potential of the power supply line 527 is set higher than the gate potential of the driving transistor 522. By converting the video signal into an analog signal, a current corresponding to the video signal is passed through the light emitting element 524. , analog gray scale driving can be performed.

[0304] Note that the configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. (C) A switch, a resistive element, a capacitive element, a sensor, a transistor or a logic Circuits etc. may be added.

[0305] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0306] (Embodiment 8) In this embodiment, a semiconductor device and an electronic device including an oxide semiconductor layer according to one embodiment of the present invention will be described. The configuration will be described with reference to FIG. 15 and FIG.

[0307] FIG. 15 is a block diagram of an electronic device including a semiconductor device to which an oxide semiconductor layer of one embodiment of the present invention is applied. This is a block diagram.

[0308] FIG. 16 illustrates the appearance of an electronic device including a semiconductor device to which an oxide semiconductor layer of one embodiment of the present invention is applied. FIG.

[0309] The electronic device shown in FIG. 15 includes an RF circuit 901, an analog baseband circuit 902, a digital A baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, flash memory 910, display controller 911, memory circuit 91 2. Display 913, touch sensor 919, audio circuit 917, keyboard 918, etc. It is composed of:

[0310] The application processor 906 includes a CPU 907, a DSP 908, and an interface ( The memory circuit 912 is composed of an SRAM or a DRAM. It is possible.

[0311] By applying the transistor described in Embodiment 3 to the memory circuit 912, It is possible to provide a highly reliable electronic device capable of writing and reading information.

[0312] In addition, the transistor described in the third embodiment may be included in the CPU 907 or the DSP 908. By applying this to registers, etc., it is possible to write and read information with high reliability. It is possible to provide high-quality electronic equipment.

[0313] Note that in the case where the off-leak current of the transistor described in Embodiment 3 is extremely low, A memory circuit 912 capable of retaining stored contents for a long period of time and having sufficiently reduced power consumption is provided. In addition, during the power gating period, the state before the power gating can be reviewed. A CPU 907 or a DSP 908 can be provided that can store the do.

[0314] The display 913 includes a display unit 914, a source driver 915, and a gate driver 91 It is composed of 6.

[0315] The display unit 914 has a plurality of pixels arranged in a matrix. Each pixel includes a pixel circuit. The pixel circuit is electrically connected to a gate driver 916 .

[0316] The transistor described in Embodiment 3 is used as appropriate for the pixel circuit or the gate driver 916. This makes it possible to provide a highly reliable display.

[0317] Examples of electronic devices include television sets (also known as televisions or television receivers). (hereinafter referred to as "computer monitors"), digital cameras, digital video cameras, and other cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0318] FIG. 16A shows a portable information terminal, which includes a main body 1101, a housing 1102, a display unit 110, and a The display unit 1103b is a touch panel. The screen can be operated by touching keyboard buttons 1104 displayed on the display unit 1103b. Of course, the display unit 1103a can be configured as a touch panel. The transistor described in Embodiment 3 may be used as a switching element in a liquid crystal panel or By fabricating an organic light-emitting panel and applying it to the display units 1103a and 1103b, reliability is improved. It can be a highly portable information terminal.

[0319] The portable information terminal shown in FIG. 16(A) displays various information (still images, videos, text images, etc. ), calendar, date or time display function, The ability to manipulate or edit the information displayed, and to process it using various software (programs) In addition, the rear and side of the housing can have external connection terminals ( It may also be configured to include an earphone jack, a USB terminal, a recording medium insertion portion, etc.

[0320] The portable information terminal shown in FIG. 16(A) can also be configured to transmit and receive information wirelessly. You can wirelessly purchase and download the desired book data from the electronic book server. It is also possible to configure it in this way.

[0321] FIG. 16B shows a portable music player. The main body 1021 has a display unit 1023 and an earphone. A fixing part 1022 for mounting, a speaker, an operation button 1024, and an external memory slot The transistor shown in the third embodiment is used as a switching element. By manufacturing a liquid crystal panel or an organic light-emitting panel as the display unit 1023, This makes it possible to provide a more reliable portable music player.

[0322] Furthermore, the portable music player shown in FIG. 16(B) has an antenna, a microphone function, and a wireless function. In addition, by linking it with a mobile phone, you can enjoy wireless hands-free driving while driving a passenger car. Conversation by telephone is also possible.

[0323] FIG. 16C shows a mobile phone, which is composed of two housings, a housing 1030 and a housing 1031. The housing 1031 includes a display panel 1032, a speaker 1033, a microphone, and a 1034, pointing device 1036, camera lens 1037, external connection terminal The housing 1030 also includes a solar cell for charging the mobile phone. The housing 10 is also provided with an antenna. The transistor described in the third embodiment is built in the display panel 1032. By applying this to the above, a highly reliable mobile phone can be achieved.

[0324] The display panel 1032 is equipped with a touch panel, and an image is displayed on the display panel 1032 as shown in FIG. The operation keys 1035 are indicated by dotted lines. It also implements a boost circuit to boost the input voltage to the voltage required for each circuit.

[0325] For example, the power transistor used in a power supply circuit such as a boost circuit is also described in the third embodiment. The thickness of the oxide semiconductor layer of the transistor is set to 2 μm to 50 μm. It is possible.

[0326] The display direction of the display panel 1032 changes appropriately depending on the usage mode. Since it has a camera lens 1037 on the same surface as 1032, video telephony is possible. The speaker 1033 and the microphone 1034 are not limited to voice calls, but can also be used for video calls, Recording and playback are possible. Furthermore, the housing 1030 and the housing 1031 can be slid to each other. As shown in 16(C), the device can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0327] The external connection terminal 1038 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. A recording medium can be inserted into the memory slot 1041 to accommodate the storage and transfer of larger amounts of data. do.

[0328] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0329] FIG. 16D shows an example of a television device. The television device 1050 includes: A display unit 1053 is built into the housing 1051. The display unit 1053 displays images. In addition, the CPU is built into the stand 1055 that supports the housing 1051. The transistor described in the third embodiment is applied to the display unit 1053 and the CPU. This makes it possible to provide a highly reliable television device 1050.

[0330] The television device 1050 can be operated using an operation switch provided on the housing 1051 or a separate remote control. The remote control can also be operated by the remote control. A display unit for displaying the output information may be provided.

[0331] The television device 1050 is configured to include a receiver, a modem, and the like. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0332] The television device 1050 also includes an external connection terminal 1054 and a storage medium playback / recording unit 10 52, an external memory slot. An external connection terminal 1054 is provided for connecting a USB cable, etc. It can be connected to various cables, enabling data communication with a personal computer, etc. In the storage medium playback / recording unit 1052, a disk-shaped recording medium is inserted and recorded on the recording medium. It is possible to read data stored in the external memory and write data to the recording medium. Displays images and videos stored in the external memory 1056 inserted in the slot. It is also possible to display it on the display unit 1053.

[0333] In addition, when the off-leak current of the transistor described in the third embodiment is extremely low, By applying transistors to external memory 1056 and CPU, power consumption is sufficiently low. This can result in a television apparatus 1050 with reduced reliability. EXAMPLES

[0334] In this example, the nanocrystals contained in the oxide semiconductor layer according to one embodiment of the present invention were The following description will be given using an electron diffraction pattern of a crystalline oxide semiconductor film.

[0335] The nanocrystalline oxide semiconductor film was analyzed by electron diffraction (ultrafine electron diffraction) with a beam diameter of 10 nmφ or less. In the electron beam diffraction pattern using the diffractometer, a halo pattern indicating an amorphous state was observed, which was also Unlike the regular spots that indicate a crystalline state oriented on the same plane, the spots have no directionality. 1 is an oxide semiconductor film in which pots are observed.

[0336] Figure 17(A) shows a cross-sectional TEM (Transmission El) image of a nanocrystalline oxide semiconductor film. The transmission electron microscopy images are shown in Fig. 17. B) shows the electron diffraction pattern measured by using a microelectron diffraction microscope at point 1 in FIG. 17(A). The turn is shown in FIG. 17(C) by measuring the turn at point 2 in FIG. 17(A) using ultrafine electron diffraction. The electron diffraction pattern measured at point 3 in FIG. 17(A) is shown in FIG. Electron beam diffraction patterns measured using sagittal beam diffraction are shown.

[0337] FIG. 17 shows an example of a nanocrystalline oxide semiconductor film, in which an In-Ga-Zn oxide film is formed on a quartz substrate. A sample was prepared by depositing a film of 50 nm on a glass substrate. The deposition conditions for the thin film were an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. Using this, under an oxygen atmosphere (flow rate 45sccm), pressure 0.4Pa, direct current (DC) power supply 0. The power was set to 5 kW and the substrate temperature was room temperature. The nanocrystalline oxide semiconductor film was then heated to 100 nm. The specimen is sliced ​​to a width of 40 nm or less (for example, 40 nm plus or minus 10 nm) and a cross-sectional TEM image is taken. Electron diffraction patterns were obtained by microelectron diffraction.

[0338] In Figure 17(A), a transmission electron microscope (Hitachi High-Technologies Corporation, H-9000NAR Nanocrystalline oxide semiconductor photographed at an accelerating voltage of 300 kV and a magnification of 2 million times. 17(B) to 17(D) are cross-sectional TEM images of the membrane. (Hitachi High-Technologies Corporation "HF-2000") was used, and the accelerating voltage was 200 kV. The electron diffraction pattern was obtained by ultrafine electron diffraction with a diameter of about 1 nmφ. The measurement range of ultrafine electron diffraction with a beam diameter of approximately 1 nmφ is 5 nmφ or more. It is less than 0 nmφ.

[0339] As shown in FIG. 17B, the nanocrystalline oxide semiconductor film was analyzed by electron beam diffraction using ultrafine electron beam diffraction. In the diffraction pattern, multiple spots (bright spots) arranged in a circular pattern are observed. Then, in the nanocrystalline oxide semiconductor film, multiple spots distributed in a circumferential (concentric) shape were observed. Alternatively, multiple spots distributed circumferentially form multiple concentric circles. It can also be said that.

[0340] In addition, FIG. 17(D) shows the vicinity of the interface with the quartz glass substrate, and FIG. In the center of the film thickness direction in FIG. 17(C), multiple circumferentially distributed In FIG. 17(C), the radius to the first circumference (main spot The interplanar spacing (distance from the surface) was 3.88 / nm to 4.93 / nm. .203nm to 0.257nm.

[0341] From the ultrafine electron beam diffraction pattern in FIG. 17, it is clear that the nanocrystalline oxide semiconductor film has irregular plane orientation. It can also be seen that the film contains a mixture of crystal parts of different sizes.

[0342] Next, FIG. 18(A) shows a planar TEM image of the nanocrystalline oxide semiconductor film. B) shows the electron diffraction pattern of the circled area in FIG. 18(A) measured by selected area electron diffraction. The sagittal diffraction pattern is shown.

[0343] FIG. 18 shows an example of a nanocrystalline oxide semiconductor film, in which an In-Ga-Zn oxide film is formed on a quartz substrate. A sample was prepared by depositing a film of 30 nm on a glass substrate. The deposition conditions for the thin film were an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. Using this, under an oxygen atmosphere (flow rate 45sccm), pressure 0.4Pa, direct current (DC) power supply 0. The power was 5 kW and the substrate temperature was room temperature. Then, the sample was cut into thin slices, and the flatness of the nanocrystalline oxide semiconductor film was measured. Area TEM images and electron diffraction patterns were obtained by electron beam diffraction.

[0344] In Fig. 18(A), a transmission electron microscope (Hitachi High-Technologies Corporation "H-9000NAR Nanocrystalline oxide semiconductor photographed using a 300kV accelerating voltage and 500,000x magnification. FIG. 18(B) is a planar TEM photograph of the film. This is an electron beam diffraction pattern obtained by X-ray diffraction. The measurement range is 300 nmφ or more.

[0345] As shown in FIG. 18(B), in the case of the nanocrystalline oxide semiconductor film, the measurement range is larger than that of the ultrafine electron beam diffraction. In the electron diffraction pattern using the selected area electron diffraction with a wide range, The observed multiple spots are absent and a halo pattern is observed.

[0346] Next, FIG. 19 shows a conceptual diagram of the distribution of diffraction intensity in the electron beam diffraction patterns of FIG. 17 and FIG. FIG. 19(A) shows the electron microbeam diffraction patterns shown in FIG. 17(B) to FIG. 17(D). FIG. 19(B) is a conceptual diagram of the distribution of diffraction intensity in the diffracted light shown in FIG. A schematic diagram of the distribution of diffraction intensity in a selected area electron beam diffraction pattern. ) is a schematic diagram of the distribution of diffraction intensities in the electron diffraction pattern of a single crystal structure or a polycrystalline structure. It is.

[0347] In FIG. 19, the vertical axis is the electron beam diffraction intensity (arbitrary unit) which shows the distribution of spots, etc., and the horizontal axis is Indicates the distance from the main spot.

[0348] In the single crystal structure or polycrystalline structure shown in FIG. 19(C), the interplanar surfaces of the crystal parts are oriented. Peaks are seen at specific distances from the main spot depending on the spacing (d value).

[0349] On the other hand, as shown in FIG. 17, the electron diffraction pattern of the nanocrystalline oxide semiconductor film The circumferential area formed by the multiple spots has a relatively large width. , FIG. 19(A) shows a discrete distribution. Also, in the ultrafine electron beam diffraction pattern, concentric circles It can be seen that there are areas of high brightness between the luminous regions, although they are not clearly defined spots.

[0350] In addition, as shown in FIG. 19(B), a selected area electron diffraction pattern of the nanocrystalline oxide semiconductor film was obtained. The electron diffraction intensity distribution in the figure shows a continuous intensity distribution. The electron beam diffraction intensity distribution shown in A) can be approximated by the results of observing the intensity over a wide area. It can be considered that the pots overlap and connect to each other, resulting in a continuous intensity distribution.

[0351] As shown in FIGS. 19A to 19C, the nanocrystalline oxide semiconductor film has an irregular plane orientation. The film has a plurality of crystal parts of different sizes, and the crystal parts are The particles are so fine that no spots are observed in the selected area electron diffraction pattern. This suggests that...

[0352] In Figure 17, where multiple spots were observed, the nanocrystalline oxide semiconductor film was 50 nm or less. The electron beam diameter is focused to 1 nmφ, so the measurement range is The range is 5 nm to 10 nm. is estimated to be 50 nm or less, for example, 10 nm or less, or 5 nm or less. can be.

[0353] FIG. 20 shows a micro-electron diffraction pattern of a quartz glass substrate. The measurement conditions were the same as those for the electron beam diffraction patterns shown in FIGS. 17(B) to 17(D).

[0354] As shown in FIG. 20, the quartz glass substrate having an amorphous structure does not have a specific spot. A halo pattern with continuously changing brightness is observed from the main spot. In the case of a film having an amorphous structure, even if electron beam diffraction is performed on a very small area, A plurality of circularly distributed spots observed in a crystalline oxide semiconductor film are not observed. Therefore, the multiple spots distributed in a circular shape observed in Figs. 17(B) to 17(D) It is confirmed that this is unique to nanocrystalline oxide semiconductor films.

[0355] FIG. 21 shows the electric field generated by converging the beam diameter to about 1 nmφ at point 2 shown in FIG. 17(A). The electron diffraction pattern was measured after irradiation with a sagittal beam for 1 minute.

[0356] The electron beam diffraction pattern shown in FIG. 21 is similar to the electron beam diffraction pattern shown in FIG. Multiple spots distributed in a circular pattern were observed, and no significant differences were found between the two measurement results. This is because the crystals confirmed in the electron diffraction pattern of FIG. 17(C) are oxide semiconductors. This means that the material has been present since the formation of the membrane, and was formed by irradiating it with a focused electron beam. This means that no crystal parts are formed.

[0357] Next, FIG. 22 shows a partially enlarged view of the cross-sectional TEM image shown in FIG. 17(A). FIG. 22(A) shows 17(A) near point 1 (surface of nanocrystalline oxide semiconductor film) at a magnification of 8 million times. The cross-sectional TEM image was observed. Also, Fig. 22(B) shows the vicinity of point 2 in Fig. 17(A) ( Cross-sectional TEM image of the center of the nanocrystalline oxide semiconductor film in the thickness direction, observed at 8 million times magnification. It is.

[0358] The cross-sectional TEM image shown in FIG. 22 does not clearly show the crystal structure of the nanocrystalline oxide semiconductor film. Cannot be confirmed.

[0359] In addition, the nanocrystalline acid of the present embodiment was formed on the quartz glass substrate used in the observations of FIGS. The sample on which the semiconductor film was formed was analyzed by X-ray diffraction (XRD). n) was used for the analysis. Figure 23 shows the XRD spectrum using the out-of-plane method. The measurement results are shown below.

[0360] In FIG. 23, the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the diffraction angle 2θ (deg. The XRD spectrum was measured using a Bruker AXS X-ray diffractometer. -8 ADVANCE was used.

[0361] As shown in FIG. 23, a peak due to quartz is observed in the vicinity of 2θ=20 to 23°. However, no peaks due to crystal parts contained in the nanocrystalline oxide semiconductor film can be confirmed.

[0362] From the results of FIG. 22 and FIG. 23, it is clear that the crystal parts contained in the nanocrystalline oxide semiconductor film are extremely fine. This suggests that it is a crystalline part.

[0363] As described above, the nanocrystalline oxide semiconductor film of this embodiment has a wide measurement range of X-ray diffraction ( Analysis by XRD (X-ray diffraction) detects peaks indicating orientation The electron diffraction pattern obtained by the selected area electron diffraction with a wide measurement range is Therefore, the nanocrystalline oxide semiconductor film of this example has a large Visually, it can be said to be equivalent to a film with a disordered atomic arrangement. Nanocrystals with sufficiently small diameters (e.g., 10 nmφ or less) can be obtained by ultrafine electron beam diffraction. By measuring the oxide semiconductor film, the electron microbeam diffraction pattern obtained shows spots (bright spots). ) can be observed. Therefore, the nanocrystalline oxide semiconductor film of this example has no misalignment of the plane orientation. Regular ultrafine crystal parts (for example, grain size is 10 nm or less, or 5 nm or less, or 3 nm or less) It can be assumed that the film is formed by the aggregation of nanoparticles (the crystal part below). The nanocrystalline region is included in the entire region of the nanocrystalline oxide semiconductor film in the thickness direction. EXAMPLES

[0364] In this example, the influence of impurities in an oxide semiconductor layer on the crystallinity of the oxide semiconductor layer was measured. I calculated it.

[0365] In this embodiment, hydrogen is assumed as an impurity contained in the oxide semiconductor layer. The correlation between the amount of hydrogen added to the conductor layer and the order of the oxide semiconductor layer to which the hydrogen has been added was examined. This was investigated using first-principles calculations.

[0366] The oxide semiconductor layer is In-Ga-Zn with an atomic ratio of In:Ga:Zn=1:1:1. First, the structure of 28 atoms shown in Figure 24 was optimized, and then the a-axis and The b axis is doubled to create a lattice containing 112 atoms. A structure with hydrogen (H) added to the molecule and a structure without hydrogen (H) added to a lattice containing 112 atoms The temperature was changed for each, the motion of each atom was calculated, and the structure with and without the addition of hydrogen was calculated. We investigated the differences.

[0367] In this embodiment, the hydrogenated structure has an atomic ratio of In:Ga:Zn=1:1:1. In the lattice of In-Ga-Zn oxide containing 112 atoms, four hydrogen atoms (hydrogen concentration 3.45a tom%) or 8 hydrogen atoms (hydrogen concentration 6.67 atom%) were added. The added hydrogen is placed within the lattice of a perfect crystal.

[0368] Molecular dynamics simulations were performed on three structures: no hydrogen added, four hydrogen atoms added, and eight hydrogen atoms added. We performed calculations to investigate the change in bonding strength and structural disorder in the In-Ga-Zn oxide due to hydrogen addition. To investigate this, we performed an analysis using the radial distribution function. The calculation conditions are shown in Table 1. The calculation was performed ”VASP(Vienna Ab-initio Simulation Packag) e)” was used.

[0369] [Table 1]

[0370] The calculation results are shown in Figure 25. Figure 25(A) shows the crystal structure of the In-Ga-Zn oxide in the initial state. FIG. 25(B) shows the structure of the In-Ga-Zn oxide without hydrogen addition at a temperature of 2 The crystal structure after 5 psec at 500K. Figure 25(C) shows the crystal structure of the 4-hydrogen-atom-added ZnO. In the In-Ga-Zn oxide with hydrogen concentration of 3.45 atom%, the temperature was increased to 25 00K after 5 psec. And Figure 25(D) shows the crystal structure of hydrogen atoms. In the In-Ga-Zn oxide with 8 doped particles (hydrogen concentration 6.67 atom%), the temperature This is the crystal structure after 5 psec when the temperature is set to 2500K.

[0371] As shown in Figure 25, the hydrogen-added structure has a crystal structure that is smaller than that of the non-hydrogen-added structure. This is because the bonds in the In-Ga-Zn oxide are disordered by hydrogenation. This suggests that it is weakening.

[0372] In order to quantitatively evaluate the effect of hydrogen addition on the bond strength in In-Ga-Zn oxide, For the structure from psec to 5psec, the elements In, Ga, Zn, and O other than hydrogen The radial distribution function was calculated for only the nuclei, and the results are shown in Figure 26.

[0373] As shown by the arrow in FIG. 26, the more hydrogen added, the lower the first peak becomes, and It can be seen that the valley between the first and second peaks is shallower. The radial distribution function g( r) represents the probability density that another atom exists at a distance r from a certain atom. As the correlation between atoms decreases, g(r) approaches 1. Therefore, as shown in Figure 2, The results of 6 show that the addition of hydrogen weakens the bonds in the In-Ga-Zn oxide, causing the structure to collapse. This indicates that the structure is easily disorganized (disorderly).

[0374] As described above, when the impurity (here, hydrogen) concentration in the oxide semiconductor layer becomes high, the oxide semiconductor It was confirmed that the order of the layers was disturbed and the crystallinity was reduced. The layer can be described as a film that contains a large amount of impurities (here, hydrogen). EXAMPLES

[0375] In this example, oxide semiconductor layers having different crystal states were measured and compared using various methods. The results will be explained.

[0376] First, the method for preparing the measurement samples used in the present embodiment will be described below.

[0377] <Measurement sample A> The CAAC-OS layer was applied to the measurement sample A. The measurement sample A had an In-Ga-Zn oxide layer. The target is a mixture of In:Ga:Zn (atomic ratio: 1:1:1) and the deposition gas is The gas pressure was set at 0.4 Pa and the flow rate was 30 sccm for argon gas and 15 sccm for oxygen gas. Sputtering was performed under the conditions of a substrate temperature of 400°C and a DC power of 0.5 kW. An oxide semiconductor layer was formed by a method. Note that a glass substrate was used as the substrate. After heating in a nitrogen atmosphere at 0°C for 1 hour, the material was heated in an oxygen atmosphere at 450°C for 1 hour to form an oxide. A process for desorbing hydrogen contained in the semiconductor layer and a process for supplying oxygen to the oxide semiconductor layer are performed. In this manner, a measurement sample A including an oxide semiconductor layer which is a CAAC-OS layer was obtained.

[0378] Regarding the measurement sample A, X-ray reflectometry (XRR) was used. The film density was measured using a sintered sintering machine, and the film density was 6.3 g / cm. 3 It was. That is, the CAAC-OS film has a high film density.

[0379] <Measurement sample B1, measurement sample B2> A nanocrystalline oxide semiconductor layer was applied to the measurement samples B1 and B2. The substrate is a tantalum-gallium-zinc oxide (In:Ga:Zn=1:1:1 [atomic ratio]) A target was used, and the deposition gases were argon gas at 30 sccm and oxygen gas at 15 sccm. The conditions were: pressure 0.4 Pa, substrate temperature room temperature, and DC power 0.5 kW. The oxide semiconductor layer was formed by a sputtering method using a glass substrate. As a result of the above, the measurement sample B including the oxide semiconductor layer, which is a nanocrystalline oxide semiconductor layer, I got 1.

[0380] Measurement sample B2 was prepared by subjecting an oxide semiconductor layer prepared in the same manner as measurement sample B1 to nitrogen heating at 450° C. After heating for 1 hour in a nitrogen atmosphere, the oxide semiconductor was heated for 1 hour in an oxygen atmosphere at 450°C. A process for desorbing hydrogen from the conductor layer and a process for supplying oxygen to the oxide semiconductor layer are performed. In this way, measurement sample B2 was obtained.

[0381] In addition, the film density of measurement samples B1 and B2 was measured using X-ray reflectivity. The film density of the measurement sample B1 was 5.9 g / cm3 The film density of the measurement sample B2 is 6.1 g / cm 3 It was.

[0382] Therefore, it was confirmed that the film density of the oxide semiconductor film can be increased by the heat treatment. Ta.

[0383] <Measurement sample C> The measurement sample C is a nanocrystalline oxide semiconductor layer, and is thinner than the measurement samples B1 and B2. As described in Example 2, an oxide semiconductor layer containing a large amount of hydrogen was used. Addition of hydrogen to the oxide semiconductor layer disrupts the order of the oxide semiconductor layer, resulting in a decrease in crystallinity. , Measurement sample C is a nanocrystal with even lower crystallinity than Measurement sample B1 and Measurement sample B2. It can be said to be an oxide semiconductor layer.

[0384] Measurement sample C is In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]) The target was a mixture of argon gas and hydrogen gas (Ar:H2 = The gas pressure was set to 2.0 Pa and the substrate temperature was set to room temperature. The oxide semiconductor layer was deposited by sputtering under the condition of applying a DC power of 200 W. In this way, measurement sample C was obtained.

[0385] The film density of the measurement sample C was measured using the X-ray reflectance method. Density: 5.0g / cm 3 It was confirmed that the film density decreased by adding hydrogen. It was.

[0386] The obtained electron microbeam diffraction patterns of the measurement samples A, B1, and C are shown in FIG. FIG. 27(A) is a micro-electron beam diffraction pattern of the measurement sample A, and FIG. 27(B) is FIG. 27(C) is the electron microbeam diffraction pattern of the measurement sample B1, and FIG. 27(D) is the electron microbeam diffraction pattern of the measurement sample C. In the electron microbeam diffraction pattern shown in FIG. The beam diameter was converged to 1 nmφ for observation.

[0387] As shown in Figure 27, the spots in the measurement sample A, which is a high-density CAAC-OS layer, are due to crystallinity. On the other hand, in the case of measurement sample C, which is a low-density nanocrystalline oxide semiconductor layer, The electron beam spot appears as a halo pattern, but some of the particles are nanocrystals. In addition, in the measurement sample B1, which is a medium-density nanocrystalline oxide semiconductor layer, The pot-shaped pattern is now more clearly visible.

[0388] This indicates that the higher the density of the film, the higher the crystallinity. It was shown that the lower the value, the higher the crystallinity of the film obtained.

[0389] In addition, the localized levels (defect levels) of the obtained measurement samples A, B1, and B2 are Here, the oxide semiconductor layer was subjected to CPM (Constant Photocurrent Measurement). The results of the evaluation using the ent method will be explained below.

[0390] In the CPM measurement, a voltage is applied between a pair of electrodes placed in contact with the oxide semiconductor layer. The amount of light irradiated onto the sample surface between the terminals is adjusted so that the current value is constant, and the desired wavelength range is obtained. The absorption coefficient was derived from the amount of irradiated light.

[0391] The absorption coefficient due to the band tail was removed from the absorption coefficient obtained by CPM measurement of the measurement sample A. The absorption coefficient, i.e., the absorption coefficient due to defects, is shown in Figure 28. The absorption coefficient obtained by measuring the band tail absorption coefficient is subtracted from the absorption coefficient due to defects. The resulting absorption coefficient is shown in FIG. 29(A). The absorption coefficient obtained by subtracting the absorption coefficient due to the band tail from the absorption coefficient, i.e., the absorption coefficient due to defects The numbers are shown in FIG.

[0392] 28 and 29, the horizontal axis represents the absorption coefficient, and the vertical axis represents the light energy. 28 and 29, the lower end of the conduction band of the oxide semiconductor layer is set to 0 eV, and the The upper end of the band is set to 3.15 eV. In addition, in Figs. 28 and 29, the curves represent the absorption coefficient and the photoelectron This is a curve showing the relationship between energy and corresponds to the defect level.

[0393] In the curve shown in FIG. 28, the absorption coefficient due to the defect level is 5.86×10 -4 cm -1 in That is, the CAAC-OS film has an absorption coefficient due to defect levels of 1×10 -3 / cm , preferably 1 x 10 -4 / cm, which means that the film has a low defect level density.

[0394] From FIG. 29(A), the absorption coefficient due to the defect level of the measurement sample B1 is 5.28×10 -1 cm -1 From FIG. 29(B), the absorption coefficient due to the defect level of the measurement sample B2 is 1.75 ×10 -2 cm -1 Therefore, the defects in the oxide semiconductor layer were eliminated by the heat treatment. can be reduced.

[0395] Based on the results obtained above, the crystal state of oxide semiconductors (referred to as OS) was classified as follows: A comparison with silicon (denoted as Si) is shown in Table 2.

[0396] [Table 2]

[0397] As shown in Table 2, the crystalline state of the oxide semiconductor can be, for example, an amorphous oxide semiconductor (aO S, a-OS:H), microcrystalline oxide semiconductors (nc-OS, μc-OS), polycrystalline oxide semiconductors Conductor (polycrystalline OS), continuous crystalline oxide semiconductor (CAAC-OS), single crystal oxide semiconductor ( The crystal state of silicon can be classified into the following types: As such, amorphous silicon (a-Si and a-Si:H), microcrystalline silicon (nc-Si, μ c-Si), polycrystalline silicon (polycrystalline Si), continuous crystal silicon (CG (Continu Examples include single grain silicon, and single crystal silicon (single crystal Si).

[0398] For oxide semiconductors in each crystal state, the electron beam was focused to a beam diameter of 10 nmφ or less. When electron diffraction (ultrafine electron diffraction) is performed using In amorphous oxide semiconductors, a halo pattern (halo In the case of a microcrystalline oxide semiconductor, spots are observed. In the case of polycrystalline oxide semiconductor, spots and / or ring patterns are observed. In the case of a continuous crystal oxide semiconductor, spots are observed. In the case of a single crystal oxide semiconductor, , a spot is observed.

[0399] In addition, from the ultrafine electron diffraction pattern, the crystal part of the microcrystalline oxide semiconductor is nanometer (n The diameter of the polycrystalline oxide semiconductor is in the range of 100 to 200 μm. It can be seen that there are grain boundaries between the crystal parts, and the boundaries are discontinuous. It can be seen that no boundaries are observed between the crystalline portions of the conductor, and the crystalline portions are continuously connected.

[0400] The density of an oxide semiconductor in each crystalline state will be described. The density of an amorphous oxide semiconductor is The density of a microcrystalline oxide semiconductor is low. The density of a continuous crystalline oxide semiconductor is medium. That is, the density of the continuous crystal oxide semiconductor is higher than that of the microcrystalline oxide semiconductor. The density of the semiconductor is higher than that of an amorphous oxide semiconductor.

[0401] In addition, the defect density (DOS) in the oxide semiconductor in each crystal state is The characteristics of the amorphous oxide semiconductor are explained below. Oxide semiconductors have a slightly higher DOS. Continuous crystal oxide semiconductors have a lower DOS. Single crystal oxide Semiconductors have an extremely low DOS. That is, single crystal oxide semiconductors have a lower DOS than continuous crystal oxide semiconductors. The OS is low, and the DOS of continuous crystalline oxide semiconductors is lower than that of microcrystalline oxide semiconductors. The DOS of amorphous semiconductors is lower than that of amorphous oxide semiconductors.

[0402] In the oxide semiconductor layer according to one embodiment of the present invention, a continuous crystal oxide semiconductor having a low DOS is used as the main current source. The interface between the insulating layer and the channel is made of DO rather than amorphous. Therefore, a transistor including the oxide semiconductor layer This makes it possible to make the capacitor a highly reliable transistor. [Explanation of symbols]

[0403] 102 Insulating layer 104 Oxide semiconductor layer 104a area 104b area 106 Insulating Layer 114 Oxide semiconductor layer 114a area 114b area 124 Oxide semiconductor layer 124a area 124b area 124c area 250 memory cells 251 Memory Cell Array 251a Memory Cell Array 251b Memory Cell Array 253 Peripheral Circuits 254 Capacitive element 260 Transistors 262 Transistor 264 Capacitive element 300 Transistors 301 Substrate 302 Gate electrode layer 303 Insulating layer 304 Oxide semiconductor layer 304a Oxide semiconductor layer 304b Oxide semiconductor layer 305a Source electrode layer 305b Drain electrode layer 306 Insulating layer 307 Insulating layer 310 Transistor 314 Oxide semiconductor layer 314a Oxide semiconductor layer 314b Oxide semiconductor layer 316a Source electrode layer 316b Drain electrode layer 320 Transistor 324 Oxide semiconductor layer 324a Oxide semiconductor layer 324b Oxide semiconductor layer 324c Oxide semiconductor layer 351 Insulating layer 352 Insulating layer 360 Transistor 364 Oxide Semiconductor Layer 364a Oxide semiconductor layer 364b Oxide semiconductor layer 364c Oxide semiconductor layer 370 Transistors 402 Insulating layer 404 Oxide semiconductor layer 404a Oxide semiconductor layer 404b Oxide semiconductor layer 404c Oxide semiconductor layer 410 Insulating layer 500 boards 501 Pixel section 502 Scanning line driver circuit 503 Scanning line driver circuit 504 Signal line driver circuit 510 Capacitance wiring 512 Gate wiring 513 Gate wiring 514 Drain electrode layer 516 Transistor 517 Transistor 518 Liquid crystal element 519 Liquid crystal element 520 pixels 521 Switching Transistors 522 Driving Transistor 523 Capacitive element 524 Light emitting element 525 Signal Line 526 scan lines 527 Power line 528 Common electrode 801 Transistors 802 Transistor 803 Transistor 804 Transistor 811 Transistor 812 Transistor 813 Transistor 814 Transistor 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Voice Circuit 918 Keyboard 919 Touch Sensor 1000 Sputtering Targets 1001 ION 1002 Sputtering particles 1003 Film-forming surface 1021 Main unit 1022 Fixed part 1023 Display section 1024 operation buttons 1025 external memory slot 1030 Case 1031 Case 1032 Display Panel 1033 Speaker 1034 Microphone 1035 Operation Key 1036 Pointing Device 1037 Camera Lenses 1038 External connection terminal 1040 Solar Cell 1041 External memory slot 1050 Television Equipment 1051 Case 1052 Storage media playback and recording unit 1053 Display section 1054 External connection terminal 1055 Stand 1056 External Memory 1101 Main unit 1102 Case 1103a Display section 1103b Display section 1104 Keyboard Buttons

Claims

1. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer overlying the first conductive layer; a first oxide semiconductor layer having a region in contact with an upper surface of the first insulating layer; a second oxide semiconductor layer having a region in contact with an upper surface of the first oxide semiconductor layer; a second conductive layer which is located over the second oxide semiconductor layer and functions as one of a source electrode and a drain electrode of the transistor; a third conductive layer which is located over the second oxide semiconductor layer and functions as the other of the source electrode and the drain electrode of the transistor; a second insulating layer located on the second conductive layer and on the third conductive layer; the first insulating layer comprises silicon oxide; the second oxide semiconductor layer has a crystal part having a c-axis orientation, the second oxide semiconductor layer has higher crystallinity than the first oxide semiconductor layer; a hydrogen concentration in the second oxide semiconductor layer is lower than a hydrogen concentration in the first oxide semiconductor layer.

2. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer overlying the first conductive layer; a first oxide semiconductor layer having a region in contact with an upper surface of the first insulating layer; a second oxide semiconductor layer having a region in contact with an upper surface of the first oxide semiconductor layer; a second conductive layer which is located over the second oxide semiconductor layer and functions as one of a source electrode and a drain electrode of the transistor; a third conductive layer which is located over the second oxide semiconductor layer and functions as the other of the source electrode and the drain electrode of the transistor; a second insulating layer located on the second conductive layer and on the third conductive layer; the first insulating layer comprises silicon oxide; the second oxide semiconductor layer has a crystal part having a c-axis orientation, the second oxide semiconductor layer has higher crystallinity than the first oxide semiconductor layer; a concentration of silicon in the second oxide semiconductor layer is lower than a concentration of silicon in the first oxide semiconductor layer.

3. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer overlying the first conductive layer; a first oxide semiconductor layer having a region in contact with an upper surface of the first insulating layer; a second oxide semiconductor layer having a region in contact with an upper surface of the first oxide semiconductor layer; a second conductive layer which is located over the second oxide semiconductor layer and functions as one of a source electrode and a drain electrode of the transistor; a third conductive layer which is located over the second oxide semiconductor layer and functions as the other of the source electrode and the drain electrode of the transistor; a second insulating layer located on the second conductive layer and on the third conductive layer; the first insulating layer comprises silicon oxide; the second oxide semiconductor layer has a crystal part having a c-axis orientation, the second oxide semiconductor layer has higher crystallinity than the first oxide semiconductor layer; a hydrogen concentration in the second oxide semiconductor layer is lower than a hydrogen concentration in the first oxide semiconductor layer; a concentration of silicon in the second oxide semiconductor layer is lower than a concentration of silicon in the first oxide semiconductor layer.

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