Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device with an improved reliability and a method for manufacturing the semiconductor device.SOLUTION: The semiconductor device includes: a semiconductor substrate 1; a semiconductor substrate 2 formed above the semiconductor substrate 1, the semiconductor substrate 2 being smaller than the semiconductor substrate 1 when seen from the above; a layer 12 formed between the semiconductor substrate 1 and the semiconductor substrate 2, the layer 12 having a conductive pad 121; a layer 22 formed between the layer 12 and the semiconductor substrate 2, the layer 22 having a conductive pad 221 joined to the conductive pad 121; and an insulation body 3 for covering the side surface of the semiconductor substrate 1 and the side surface of the semiconductor substrate 2.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In recent years, semiconductor devices such as semiconductor memory devices that can be formed by bonding a first semiconductor substrate having a memory cell array to a second semiconductor substrate having peripheral circuits have become known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-146527 A [Patent Document 2] JP 2014-78764 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to improve the reliability of a semiconductor device. [Means for solving the problem]

[0005] The semiconductor device of the embodiment comprises a first substrate, a second substrate disposed above the first substrate and having a smaller area than the first substrate when viewed from above, a first layer disposed between the first substrate and the second substrate and having a first conductive pad, a second layer disposed between the first layer and the second substrate and having a second conductive pad joined to the first conductive pad, and an insulator covering each of the side surfaces of the first substrate and the side surfaces of the second substrate. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic top view illustrating an example of the structure of a semiconductor chip. [Diagram 2] 1 is a schematic cross-sectional view showing a structural example of a semiconductor chip. [Diagram 3] 1 is a schematic cross-sectional view showing a structural example of a semiconductor chip. [Figure 4] 1 is a schematic cross-sectional view showing a structural example of a semiconductor chip. [Diagram 5] 1 is a schematic XZ cross-sectional view for explaining a structural example of a memory pillar MP. FIG. [Figure 6] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 7] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 8] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 9] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 10] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 11] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 12] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 13] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 14] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 15] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 16] 1A to 1C are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip. [Figure 17] 13 is a schematic diagram for explaining the difference between a case where a groove D is formed and a case where a groove D is not formed. FIG. [Figure 18] 13 is a schematic diagram for explaining the difference between a case where a groove D is formed and a case where a groove D is not formed. FIG. [Figure 19] FIG. 2 is a schematic diagram showing an example of the structure of a semiconductor package. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. The relationship between the thickness and planar dimensions of each component, the thickness ratio of each component, etc. shown in the drawings may differ from the actual product. In addition, in the embodiments, substantially the same components are given the same reference numerals and the description will be omitted as appropriate.

[0008] (Example of semiconductor chip structure) As an example of the semiconductor device of the embodiment, an example of a semiconductor chip will be described. FIG. 1 is a top view schematic diagram showing a structural example of the semiconductor chip. FIG. 2 is a cross-sectional schematic diagram showing a structural example of the semiconductor chip, showing an example of a cross section of the line segment A1-B1 of the semiconductor chip 100 of FIG. 1. FIG. 3 is a cross-sectional schematic diagram showing a structural example of the semiconductor chip, showing an example of a cross section of the line segment A2-B2 of the semiconductor chip 100 of FIG. 1. FIG. 1, FIG. 2, and FIG. 3 show an X-axis, a Y-axis, and a Z-axis. The X-axis, the Y-axis, and the Z-axis intersect perpendicularly with each other. The Z-axis is along the thickness direction of the semiconductor chip 100. FIG. 1 shows an XY plane including the X-axis and the Y-axis. FIG. 2 shows an XZ cross section including the X-axis and the Z-axis. FIG. 3 shows a YZ cross section including the Y-axis and the Z-axis. Note that the above structural example is just an example, and the structural example of the semiconductor chip of the embodiment is not limited to this structural example.

[0009] The semiconductor chip 100 includes a semiconductor substrate 1, a semiconductor substrate 2, an insulator 3, an insulating layer 4, and a conductor 5. An example of the semiconductor chip 100 includes a memory chip. As the memory chip, a non-volatile memory chip or a volatile memory chip can be used. As the non-volatile memory chip, a NAND memory chip, a phase change memory chip, a resistive change memory chip, a ferroelectric memory chip, a magnetic memory chip, or the like can be used. As the volatile memory chip, a dynamic random access memory (DRAM) chip, or the like can be used.

[0010] The semiconductor substrate 1 includes a substrate 11 and a layer 12. The semiconductor substrate 1 includes, for example, a semiconductor chip having a peripheral circuit. The semiconductor substrate 1 includes a side surface 1a, a side surface 1b, a side surface 1c, and a side surface 1d. The side surface 1a extends in a direction intersecting the Z-axis direction (for example, the Y-axis direction). The side surface 1b is provided on the opposite side of the semiconductor substrate 1 to the side surface 1a, and extends in a direction intersecting the Z-axis direction (for example, the Y-axis direction). The side surface 1c extends in a direction intersecting the side surface 1a (for example, the X-axis direction). The side surface 1d is provided on the opposite side of the semiconductor substrate 1 to the side surface 1c, and extends in a direction intersecting the side surface 1a (for example, the X-axis direction).

[0011] The side surface 1a includes the side surface 11a of the substrate 11 and the side surface 12a of the layer 12. The side surface 1b includes the side surface 11b of the substrate 11 and the side surface 12b of the layer 12. The side surface 1c includes the side surface 11c of the substrate 11 and the side surface 12c of the layer 12. The side surface 1d includes the side surface 11d of the substrate 11 and the side surface 12d of the layer 12. The side surfaces 12a, 12b, 12c, and 12d extend, for example, flush with the side surfaces 11a, 11b, 11c, and 11d, respectively.

[0012] Examples of substrate 11 include semiconductor wafers, such as silicon substrates.

[0013] The layer 12 is provided on the surface of the substrate 11. The layer 12 is disposed between the substrate 11 and the semiconductor substrate 2. The layer 12 includes a peripheral circuit 120 and a conductive pad 121.

[0014] The semiconductor substrate 2 is provided on a part of the semiconductor substrate 1. In the XY plane, when viewed from above, the plane area of ​​the semiconductor substrate 2 is smaller than that of the semiconductor substrate 1. That is, when viewed from the Z direction, the plane area of ​​the semiconductor substrate 2 is smaller than that of the semiconductor substrate 1. The semiconductor substrate 2 has a substrate 21 and a layer 22. The semiconductor substrate 2 includes, for example, a semiconductor chip having a memory cell array. The semiconductor substrate 2 includes a side surface 2a, a side surface 2b, a side surface 2c, and a side surface 2d. The side surface 2a extends in a direction intersecting the Z axis direction (for example, the Y axis direction). The side surface 2b is provided on the opposite side of the side surface 2a of the semiconductor substrate 1 and extends in a direction intersecting the Z axis direction (for example, the Y axis direction). The side surface 2c extends in a direction intersecting the side surface 2a (for example, the X axis direction). The side surface 2d is provided on the opposite side of the side surface 2c of the semiconductor substrate 1 and extends in a direction intersecting the side surface 2a (for example, the X axis direction). The number of semiconductor substrates 2 and the number of memory cell arrays are not limited to the numbers shown in FIGS.

[0015] The side surface 2a includes a side surface 21a of the substrate 21 and a side surface 22a of the layer 22. The side surface 2b includes a side surface 21b of the substrate 21 and a side surface 22b of the layer 22. The side surface 2c includes a side surface 21c of the substrate 21 and a side surface 22c of the layer 22. The side surface 2d includes a side surface 21d of the substrate 21 and a side surface 22d of the layer 22. The side surfaces 22a, 22b, 22c, and 22d extend, for example, flush with the side surfaces 21a, 21b, 21c, and 21d, respectively.

[0016] The substrate 21 is provided above the substrate 11. Examples of the substrate 21 include a semiconductor wafer such as a silicon substrate.

[0017] The layer 22 is provided on the surface of the substrate 21. The layer 22 is disposed between the substrate 21 and the layer 12. The layer 22 includes a memory cell array 220 and a conductive pad 221.

[0018] A structural example of the semiconductor substrate 1 and the semiconductor substrate 2 will be further described with reference to Fig. 4. Fig. 4 is a schematic cross-sectional view showing a structural example of the semiconductor chip 100. Fig. 4 shows a specific example of a part of the XZ cross section shown in Fig. 2. Fig. 4 omits the illustration of a part of the memory cell array 220 and indicates it with a dotted line.

[0019] The peripheral circuit 120 includes a transistor TR provided on the substrate 11, a conductive layer 122, a multi-layer wiring 123, and an interlayer insulating film .

[0020] The transistor TR is an N-channel field effect transistor or a P-channel field effect transistor. Although Figures 1 to 4 illustrate a plurality of transistors TR, the number of transistors TR is not limited to the number of transistors TR shown in Figures 1 to 4. The plurality of transistors TR may include an N-channel field effect transistor and a P-channel field effect transistor.

[0021] The plurality of transistors TR form, for example, a CMOS circuit of the peripheral circuit 120. The plurality of transistors TR may be electrically isolated from each other by an element isolator such as shallow trench isolation (STI).

[0022] The conductive pads 121 are exposed on the surface of the layer 12. The conductive pads 121 are electrically connected to the peripheral circuit 120 via multi-layer wiring 123 in the layer 12. The conductive pads 121 can be formed using a metal material such as copper. Although FIGS. 1 to 4 show a plurality of conductive pads 121, the number of conductive pads 121 is not limited to the number shown in FIGS. 1 to 4.

[0023] The conductive layer 122 includes a contact plug. The multilayer wiring 123 is electrically connected to any one of the gate, source, or drain of the transistor TR via the conductive layer 122. The conductive layer 122 and the multilayer wiring 123 include a metal material.

[0024] The interlayer insulating film 124 covers the transistor TR, the conductive layer 122, and the multilayer wiring 123. An example of the interlayer insulating film 124 is a silicon oxide film.

[0025] The memory cell array 220 is provided between the substrate 21 and a conductive pad 221. The memory cell array 220 has a conductive layer 222, a stacked body 223, a memory pillar MP, a multilayer wiring 224, and an interlayer insulating film 225.

[0026] The conductive layer 222 is disposed between the substrate 21 and the stacked body 223. The conductive layer 222 forms, for example, a source line of a memory chip. The conductive layer 222 includes, for example, a metal material. The conductive layer 222 is not necessarily provided.

[0027] The laminate 223 has a plurality of insulating layers and a plurality of conductive layers, and the plurality of insulating layers and the plurality of conductive layers are alternately laminated in the Z-axis direction.

[0028] As shown in Fig. 4, the memory pillar MP extends penetrating through the stack 223 in the Z-axis direction. The memory pillar MP is electrically connected to, for example, the conductive layer 222. Although Fig. 4 illustrates a plurality of memory pillars MP, the number of memory pillars MP is not limited to the number of memory pillars MP illustrated in Fig. 4. Note that, in Fig. 4, the memory cell array 220 overlaps the peripheral circuit 120 in the Z-axis direction, but this is not limited thereto, and the memory cell array 220 does not have to overlap the peripheral circuit 120.

[0029] Fig. 5 is a schematic cross-sectional view for explaining a structural example of a memory pillar MP. Fig. 5 shows a specific example of a part of the XZ cross section shown in Fig. 4. Fig. 5 shows an insulating layer 231, a conductive layer 232, a memory layer 233, a semiconductor layer 234, and a core insulator 235. The memory pillar MP has the memory layer 233, the semiconductor layer 234, and the core insulator 235.

[0030] The insulating layer 231 and the conductive layer 232 form a stack 223. The conductive layers 232 form word lines of the memory chip. The insulating layer 231 includes, for example, silicon oxide. The conductive layer 232 includes a metal material.

[0031] The memory layer 233 includes a block insulating film 233a, a charge storage film 233b, and a tunnel insulating film 233c. The block insulating film 233a and the tunnel insulating film 233c include, for example, silicon oxide. The charge storage film 233b includes, for example, silicon nitride.

[0032] The semiconductor layer 234 penetrates the stacked body 223 along the Z-axis direction. The semiconductor layer 234 is electrically connected to the conductive layer 222. The outer periphery of the semiconductor layer 234 is surrounded and covered by the memory layer 233. The semiconductor layer 234 includes, for example, polycrystalline silicon.

[0033] The core insulator 235 is provided inside the semiconductor layer 234. The core insulator 235 extends along the semiconductor layer 234. The core insulator 235 includes, for example, silicon oxide.

[0034] The intersections of the memory pillars MP and the conductive layers 232 function as memory transistors. The memory transistors form memory cells of the memory cell array.

[0035] The multi-layer wiring 224 includes a bit line of the memory chip. The bit line is connected to one of the memory pillars MP via a plug. The multi-layer wiring 224 includes a metal material.

[0036] The conductive pads 221 are exposed on the surface of the layer 22. The conductive pads 221 are connected to the memory cell array 220 via multi-layer wiring 224. The conductive pads 221 can be formed using a metal material such as copper. Although FIGS. 1 to 4 show a plurality of conductive pads 221, the number of the plurality of conductive pads 221 is not limited to the number shown in FIGS. 1 to 4.

[0037] The conductive pad 221 is bonded to the conductive pad 121. This allows, for example, the memory cell array 220 and the peripheral circuit 120 to be electrically connected to each other.

[0038] The interlayer insulating film 225 covers the surface on the memory pillar MP side of the substrate 21. The interlayer insulating film 225 covers the conductive layer 222, the stacked body 223, the memory pillar MP, and the multilayer wiring 224, and also flattens the surface facing the interlayer insulating film 124. An example of the interlayer insulating film 225 is a silicon oxide film.

[0039] As shown in FIG. 1 to FIG. 3, the insulator 3 contacts each of the side surfaces 11a to 11d, the side surfaces 12a to 12d, the side surfaces 21a to 21d, and the side surfaces 22a to 22d. The insulator 3 covers each of the side surfaces 11a to 11d, the side surfaces 12a to 12d, the side surfaces 21a to 21d, and the side surfaces 22a to 22d. The insulator 3 may cover one of the side surfaces 11a to 11d. The insulator 3 may cover each of the entire side surfaces. The insulator 3 includes, for example, a molding resin such as an epoxy-based thermosetting resin represented by an epoxy molding compound (EMC), an underfill resin, or a polyimide resin. The insulator 3 may further include a silicon oxide filler such as silicon oxide.

[0040] The insulating layer 4 is provided on the insulator 3 and on the semiconductor substrate 2. The insulating layer 4 covers the surface of the substrate 21 opposite to the memory pillar MP. The insulating layer 4 is in contact with, for example, the surface of the insulator 3 and the surface of the substrate 21. The insulating layer 4 includes, for example, a polyimide resin. For convenience, the insulating layer 4 is not shown in FIG. 1.

[0041] The conductor 5 is provided on the insulating layer 4. The conductor 5 functions as a pad for inputting and outputting a signal or voltage to and from the outside. Although FIG. 1 shows a plurality of conductors 5, the number of the conductors 5 is not limited to the number shown in FIG. 1. As shown in FIG. 4, one of the plurality of conductors 5 is electrically connected to the memory cell array 220 through the substrate 21 and the insulating layer 4. Another of the plurality of conductors 5 may be electrically connected to one source region or drain region of the transistor TR via a contact plug (not shown). The conductor 5 can be formed using a metal material such as copper, for example.

[0042] As described above, the semiconductor chip 100 has a structure in which the insulator 3 covers the side surface of the semiconductor substrate 1. This makes it possible to suppress, for example, warping of the semiconductor chip 100. As a result, the reliability of the semiconductor chip 100 can be improved.

[0043] (Example of Manufacturing Method of Semiconductor Chip 100) 6 to 16 are schematic diagrams for explaining an example of a method for manufacturing a semiconductor chip 100. Here, an example of a method for manufacturing a plurality of semiconductor chips 100 in the same process will be explained below. Figs. 6 to 11 and Figs. 13 to 16 show a part of an XZ cross section of a semiconductor substrate 1. Fig. 12 shows a part of an XY plane of a semiconductor substrate 1.

[0044] As shown in Fig. 6, a groove D is formed in the semiconductor substrate 1. The semiconductor substrate 1 can be manufactured, for example, by preparing a substrate 11 and forming a layer 12 on the substrate 11 using a known method. The layer 12 has a plurality of peripheral circuits 120, and each peripheral circuit 120 is provided for each semiconductor chip 100 to be manufactured. The groove D can be formed, for example, by blade dicing, laser grooving, plasma dicing, or etching.

[0045] The grooves D are provided, for example, in a lattice pattern along the surface of the semiconductor substrate 1. The depth of the grooves D (the length in the Z-axis direction from the surface of the semiconductor substrate 1 to the inner bottom surface of the grooves D) is, for example, 20 mm or more and ⅓ or less of the thickness of the substrate 11 before processing (the length in the Z-axis direction of the substrate 11). By adjusting the depth of the grooves D to the above range, for example, warping of the substrate 11 after the semiconductor chip 100 is manufactured can be suppressed. Therefore, the reliability of the semiconductor chip 100 can be improved.

[0046] Next, as shown in FIG. 7, the semiconductor substrate 2 is bonded to the semiconductor substrate 1. For example, a plurality of semiconductor substrates 2 can be bonded by closely contacting the semiconductor substrate 1 with the layer 22 facing the layer 12. The semiconductor substrate 2 can be manufactured, for example, by preparing a substrate 21 and forming the layer 22 on the substrate 21 using a known method. Each semiconductor substrate 2 is bonded for each semiconductor chip 100 to be manufactured. In this specification, bonding refers to bringing the semiconductor substrate 1 and the semiconductor substrate 2 into close contact with each other before heat treatment. The semiconductor substrate 2 is bonded, for example, to a region surrounded by the groove D on the surface of the semiconductor substrate 1.

[0047] Thereafter, the semiconductor substrate 1 and the semiconductor substrate 2 are bonded. In this specification, bonding means that the semiconductor substrate 1 and the semiconductor substrate 2 are firmly fixed. The semiconductor substrate 1 and the semiconductor substrate 2 are bonded, for example, by heat treatment. The conductive pad 121 and the conductive pad 221 are directly bonded, for example, by element diffusion between metals, van der Waals force, recrystallization due to volume expansion or melting, or the like. Furthermore, the semiconductor substrate 1 and the semiconductor substrate 2 can be bonded by direct bonding by element diffusion between the interlayer insulating film 124 and the interlayer insulating film 225, van der Waals force, chemical reaction such as dehydration condensation or polymerization, or bonding between a metal and an insulating layer. These bonding methods are also called hybrid bonding. Note that the interface (bonding surface) between the semiconductor substrate 1 and the semiconductor substrate 2 may not be clearly observed after heat treatment.

[0048] By laminating and bonding the semiconductor substrate 2 to the semiconductor substrate 1 after the formation of the groove D, for example, damage to the semiconductor substrate 2 due to the formation of the groove D can be suppressed. Without being limited thereto, as shown in FIG. 8, the semiconductor substrate 2 may be laminated and bonded to the semiconductor substrate 1 before the formation of the groove D, and then, for example, the groove D may be formed in a region surrounding the semiconductor substrate 2 on the surface of the semiconductor substrate 1. By laminating and bonding the semiconductor substrate 2 to the semiconductor substrate 1 before the formation of the groove D, for example, it is possible to suppress dust generated by the formation of the groove D from remaining between the semiconductor substrate 1 and the semiconductor substrate 2. Dust, for example, causes a decrease in reliability of the semiconductor chip 100.

[0049] 9, the insulator 3 is formed. The insulator 3 is formed so as to fill the groove D and cover the semiconductor substrate 2. Thus, the insulator 3 contacts the inner bottom surface and the inner side surface of the groove D. The insulator 3 can be formed, for example, by a molding method such as a transfer molding method, a compression molding method, or an injection molding method using a material applicable to the insulator 3.

[0050] 10, the insulator 3 is partially removed in the thickness direction (Z-axis direction) to expose the surface of the substrate 21 opposite to the layer 22. The insulator 3 can be partially removed by, for example, chemical mechanical polishing (CMP). Alternatively, the substrate 21 may be completely removed to expose the layer 22. In this case, the CMP is stopped after the layer 22 is exposed, thereby allowing the substrate 21 to be completely removed.

[0051] Next, as shown in FIG. 11, an insulating layer 4 and a conductor 5 are formed. For example, the insulating layer 4 is formed by forming an opening that penetrates the substrate 21 to reach the layer 22, and then covering the semiconductor substrate 2 and the insulator 3. The insulating layer 4 can be formed by, for example, chemical vapor deposition (CVD) or a coating method. The conductor 5 is formed by, for example, forming a conductive film in the opening. The conductive film can be formed by, for example, sputtering. If the substrate 21 is completely removed, the insulating layer 4 and the conductor 5 are formed directly on the layer 22.

[0052] Fig. 12 shows a part of the XY plane of the semiconductor substrate 1 and the semiconductor substrate 2 after the formation of the conductor 5. For convenience, the insulator 3 and the insulating layer 4 are omitted from Fig. 12. As shown in Fig. 12, the semiconductor substrate 2, the conductor 5, etc. are formed in each region surrounded by the groove D of the semiconductor substrate 1.

[0053] 13, tape 6 is attached to the surface of insulating layer 4 opposite to semiconductor substrate 2 and the surface of conductor 5 opposite to semiconductor substrate 2. Tape 6 is, for example, a backgrinding tape.

[0054] 14, the semiconductor substrate 1 is partially removed in the thickness direction (Z-axis direction) from the surface opposite to the semiconductor substrate 2 by backgrinding, thereby exposing a part of the region filled in the groove D of the insulator 3 from the semiconductor substrate 1. At this time, by exposing a part of the insulator 3 from the surface of the semiconductor substrate 1 opposite to the semiconductor substrate 2, warping of the semiconductor substrate 1 can be suppressed. This improves the reliability of the semiconductor chip 100. After backgrinding, the tape 6 is removed from the insulating layer 4 and the conductor 5.

[0055] 15, the surface of the semiconductor substrate 1 opposite to the semiconductor substrate 2 is attached to a dicing tape 8 with an adhesive layer 7 sandwiched therebetween. Examples of the adhesive layer 7 include a die attach film. The periphery of the dicing tape 8 is fixed to a wafer ring 9. The semiconductor substrate 1 is attached to the dicing tape 8 so as to overlap the hollow portion of the wafer ring 9.

[0056] 16, the semiconductor substrate 1 and the insulator 3 are divided along the grooves D. The semiconductor substrate 1 and the insulator 3 can be divided by using, for example, blade dicing, laser dicing, or a water jet. Blade dicing is particularly preferable because it is easy to process the semiconductor substrate 1 and the insulator 3. The semiconductor substrate 1 and the insulator 3 are divided (singled) into individual semiconductor chips 100.

[0057] When the semiconductor substrate 1 and the insulator 3 are divided along the groove D by blade dicing, it is preferable that the width of the groove D (the length of the groove D in the X-axis direction or the Y-axis direction) is greater than the thickness of the dicing blade. This allows the semiconductor substrate 1 to be divided along the insulator 3 without the dicing blade coming into contact with the semiconductor substrate 1.

[0058] Thereafter, each semiconductor chip 100 is detached from the adhesive layer 7 and the dicing tape 8. Through the above steps, the semiconductor chip 100 can be manufactured.

[0059] Here, a difference between the case where the groove D is formed and the case where the groove D is not formed will be described in the example of the manufacturing method of the semiconductor chip 100. Figures 17 and 18 are schematic diagrams for explaining the difference between the case where the groove D is formed and the case where the groove D is not formed. Figures 17 and 18 show the state where the semiconductor substrate 1 is divided by blade dicing, and show the XZ cross sections of the semiconductor substrate 1 and the semiconductor substrate 2.

[0060] When the groove D is not formed in the semiconductor substrate 1, as shown in FIG. 17, the dicing blade 10 passes through the interface between the semiconductor substrate 1 and the insulator 3, and the semiconductor substrate 1 is divided while the dicing blade 10 contacts both the semiconductor substrate 1 and the insulator 3. This may cause defects such as chipping, which is a crack or chipping on the cut surface, or peeling of the insulator 3 at the interface between the layer 12 and the insulator 3. The above defects are likely to occur, for example, when two different hard layers such as the semiconductor substrate 1 and the insulator 3 are cut at the same time. In addition, since the above defects occur inside the semiconductor chip 100, it is difficult to find them by inspecting the semiconductor chip 100 after cutting.

[0061] In contrast, in the manufacturing method of the semiconductor chip 100 of the embodiment, a groove D is formed in the semiconductor substrate 1 and the groove D is filled with the insulator 3, so that the semiconductor substrate 1 can be divided while cutting only the insulator 3 without the dicing blade 10 coming into contact with the semiconductor substrate 1, as shown in FIG. 18. This makes it possible to suppress defects such as chipping and peeling of the insulator 3. This improves the reliability of the semiconductor chip 100. Although the case of blade dicing has been described in FIG. 17 and FIG. 18, the same applies to cases where the semiconductor substrate 1 is divided by other methods.

[0062] (Example of semiconductor package structure) As another example of the semiconductor device according to the embodiment, an example of a semiconductor package having a semiconductor chip 100 will be described. Fig. 19 is a schematic diagram showing an example of the structure of the semiconductor package. Fig. 19 shows an XZ cross section.

[0063] The semiconductor package 300 includes a wiring substrate 301 , a chip stack 302 , and a sealing insulator 303 .

[0064] The wiring board 301 has a conductive pad 311 provided on a surface 301a, an external connection terminal 312 provided on the surface of the conductive pad 311, a conductive pad 313 provided on a surface 301b opposite to the surface 301a, and internal wiring 314 electrically connecting the conductive pad 311 and the conductive pad 313. Examples of the wiring board 301 include a printed wiring board (PWB) and the like. Fig. 19 illustrates a plurality of conductive pads 311, a plurality of external connection terminals 312, a plurality of conductive pads 313, and a plurality of internal wiring 314, but the number of each is not limited to the number shown in Fig. 19.

[0065] The external connection terminals 312 can be formed using, for example, gold, copper, solder, or the like. The external connection terminals 312 may be formed using, for example, tin-silver or tin-silver-copper lead-free solder. The external connection terminals 312 may also be formed using a laminate of multiple metal materials. Note that FIG. 19 illustrates the external connection terminals 312 formed using conductive balls.

[0066] Conductive pad 313 is connected to external connection terminal 312 via internal wiring 314 of wiring board 301 and conductive pad 311. Conductive pad 311 and conductive pad 313 contain a metal element such as copper, gold, palladium, or nickel. For example, conductive pad 311 and conductive pad 313 may be formed by forming a plating film containing the above material by electrolytic plating or electroless plating.

[0067] Chip stack 302 is provided above surface 301b of wiring substrate 301. Chip stack 302 has semiconductor chip 100, adhesive layer 321, and bonding wire 322. Fig. 19 illustrates chip stack 302 having a plurality of semiconductor chips 100, but the number of semiconductor chips 100 is not limited to the number shown in Fig. 19. Other descriptions of semiconductor chip 100 can be appropriately cited from the descriptions of the above embodiments.

[0068] Each of the multiple semiconductor chips 100 is stacked in order on the upper surface 301b of the wiring substrate 301 via an adhesive layer 321. An example of the adhesive layer 321 includes a die attach film. Fig. 19 shows three semiconductor chips 100 stacked on top of each other on the surface 301b. In other words, the multiple semiconductor chips 100 stacked on top of each other partially overlap each other.

[0069] The conductors 5 of each of the semiconductor chips 100 are connected to the conductive pads 313 via corresponding bonding wires 322. The bonding wires 322 contain a metal element such as gold, silver, copper, or palladium. The semiconductor chips 100 are bonded to each other via, for example, an adhesive layer 321. The bottom semiconductor chip 100 may be bonded to the surface 301b or a spacer via, for example, the adhesive layer 321.

[0070] The sealing insulator 303 is provided to cover the chip stack 302 and seals the chip stack 302. The sealing insulator 303 contains an inorganic filler such as silicon oxide (SiO2) and a resin such as an epoxy-based thermosetting resin, and is formed by a molding method such as a transfer molding method, a compression molding method, or an injection molding method using a sealing resin in which an inorganic filler is mixed with an organic resin or the like.

[0071] The semiconductor package 300 may have a conductive shield on the surface of the sealing insulator 303. The conductive shield covers, for example, at least a part of the side surface of the wiring board 301 and the sealing insulator 303. The conductive shield can be formed by, for example, forming a film by sputtering or the like. In order to prevent leakage of unnecessary electromagnetic waves radiated from the semiconductor chip 100 in the sealing insulator 303 and the internal wiring of the wiring board 301, the conductive shield is preferably formed of a metal layer having a low electrical resistivity, and for example, a metal layer made of copper, SUS, nickel, or the like is applied. The thickness of the conductive shield is preferably set based on the electrical resistivity. Note that the conductive shield may be connected to the wiring connected to the external connection terminal 312 such as a ground terminal by exposing a part of the via in the wiring board 301 and bringing it into contact with the conductive shield.

[0072] As described above, the semiconductor package of the embodiment has semiconductor chip 100 that is suppressed from defects such as warping, chipping, and peeling of insulator 3. This can improve the reliability of the semiconductor package.

[0073] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0074] 1...semiconductor substrate, 1a...side, 1b...side, 1c...side, 1d...side, 2...semiconductor substrate, 2a...side, 2b...side, 2c...side, 2d...side, 3...insulator, 4...insulating layer, 5...conductor, 6...tape, 7...adhesive layer, 8...dicing tape, 9...wafer ring, 10...dicing blade, 11...substrate, 11a...side, 11b...side, 11c...side, 11d...side, 12...layer, 12a...side, 12b...side, 12c...side, 12d...side, 21...substrate, 21a...side, 21b...side, 21c...side, 21d Side, 22...layer, 22a...side, 22b...side, 22c...side, 22d...side, 100...semiconductor chip, 120...peripheral circuit, 121...conductive pad, 122...conductive layer, 123...multilayer wiring, 124...interlayer insulating film, 220...memory cell array, 221...conductive pad, 222...conductive layer, 223...laminated body, 224...multilayer wiring, 225...interlayer insulating film, 231...insulating layer, 232...conductive layer, 233...memory layer, 233a...block insulating film , 233b...charge storage film, 233c...tunnel insulating film, 234...semiconductor layer, 235...core insulator, 300...semiconductor package, 301...wiring board, 301a...surface, 301b...surface, 302...chip stack, 303...sealing insulator, 311...conductive pad, 312...external connection terminal, 313...conductive pad, 314...internal wiring, 321...adhesive layer, 322...bonding wire, D...groove, MP...memory pillar, TR...transistor.

Claims

1. A first substrate; a second substrate provided above the first substrate and having an area smaller than that of the first substrate when viewed from above; a first layer disposed between the first substrate and the second substrate and having a first conductive pad; a second layer disposed between the first layer and the second substrate and having a second conductive pad bonded to the first conductive pad; an insulator covering each of a side surface of the first substrate and a side surface of the second substrate; A semiconductor device comprising:

2. the first substrate has a first side, a second side, a third side, and a fourth side; the insulator covers each of the first side surface, the second side surface, the third side surface, and the fourth side surface; The semiconductor device according to claim 1 .

3. A wiring board; a semiconductor chip provided on the wiring substrate; Equipped with The semiconductor chip has the first substrate, the first layer, the second substrate, the second layer, and the insulator. The semiconductor device according to claim 1 .

4. The insulator includes a molding resin, an underfill resin, or a polyimide resin. The semiconductor device according to claim 1 .

5. The insulator includes silicon oxide. The semiconductor device according to claim 1 or 4.

6. A first semiconductor substrate includes a first substrate and a first layer including a first conductive pad provided on the first substrate, and a trench is formed on a surface of the first semiconductor substrate, the trench penetrating the first layer and extending into the first substrate; a second layer having a second substrate and a second conductive pad provided on the second substrate, the second semiconductor substrate having an area smaller than that of the first semiconductor substrate when viewed from above being attached to a surface of the first semiconductor substrate, and the first conductive pad and the second conductive pad are bonded to each other; forming an insulator that fills the groove and covers the second semiconductor substrate; dividing the first semiconductor substrate by dividing the insulator along the groove; A method for manufacturing a semiconductor device.

7. The method of claim 6 , wherein the trench is formed in a surface of the first semiconductor substrate to surround the second semiconductor substrate.

8. The method of claim 6 , wherein the grooves are formed prior to laminating the second semiconductor substrate to a surface of the first semiconductor substrate.

9. The method of claim 6 , wherein the groove is formed after laminating the second semiconductor substrate to a surface of the first semiconductor substrate.

10. The method of claim 6 , wherein forming the grooves is performed using blade dicing, laser grooving, plasma dicing, or etching.

11. The method of claim 6 , wherein the dividing of the first semiconductor substrate and the insulator is performed using blade dicing, laser dicing, or a water jet.

Images