Semiconductor device and method for manufacturing the same

Abstract

To suppress intrusion of water into between a semiconductor module and a cooling unit.SOLUTION: A semiconductor device 100 includes: a semiconductor module 10 including a semiconductor chip 12; a cooling unit 20 for cooling the semiconductor module 10; a thermal conduction layer 30 interposed between the semiconductor module 10 and the cooling unit 20; and a protective film 40 for covering a boundary between the semiconductor module 10 and the thermal conduction layer 30 and a boundary between the cooling unit 20 and the thermal conduction layer 30. A water absorption rate of the protective film 40 becomes lower than a water absorption rate of the thermal conduction layer 30.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] For example, semiconductor devices using power semiconductor chips such as IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have been proposed (for example, Patent Documents 1 to 3). For example, Patent Document 1 discloses a power semiconductor device in which a module section and a cooling section are joined via a resin insulating member. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7154422 [Patent Document 2] Patent No. 7134360 [Patent Document 3] JP 2020-098882 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the configuration of Patent Document 1, there is a possibility that moisture may penetrate through the boundary between the resin insulating member and the module section or the cooling section. The penetration of moisture may cause problems such as a decrease in adhesive strength between the module section and the cooling section, or a decrease in the dielectric strength of the resin insulating member. In consideration of the above circumstances, one aspect of the present disclosure aims to suppress the penetration of moisture between the semiconductor module and the cooling section. [Means for solving the problem]

[0005] In order to solve the above problems, a semiconductor device according to one embodiment of the present disclosure comprises a semiconductor module including a semiconductor chip, a cooling section for cooling the semiconductor module, a thermally conductive layer interposed between the semiconductor module and the cooling section, and a protective film covering the boundary between the semiconductor module and the thermally conductive layer and the boundary between the cooling section and the thermally conductive layer, wherein the water absorption rate of the protective film is lower than that of the thermally conductive layer.

[0006] A semiconductor device according to another aspect of the present disclosure comprises a semiconductor module including a semiconductor chip, a cooling section for cooling the semiconductor module, a thermally conductive layer interposed between the semiconductor module and the cooling section, and a protective film covering the boundary between the semiconductor module and the thermally conductive layer and the boundary between the cooling section and the thermally conductive layer, wherein the thickness of the protective film is less than the distance between the semiconductor module and the cooling section.

[0007] A manufacturing method for a semiconductor device according to one aspect of the present disclosure includes a bonding process for bonding a semiconductor module including a semiconductor chip and a cooling section for cooling the semiconductor module with a thermally conductive layer interposed between the semiconductor module and the cooling section, and a protection process, which is performed after the bonding process, for forming a protective film that covers the boundary between the semiconductor module and the thermally conductive layer and the boundary between the cooling section and the thermally conductive layer. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is an enlarged cross-sectional view of the vicinity of the outer periphery of the semiconductor module (region α in FIG. 1). [Diagram 3] 1A to 1C are explanatory diagrams of a process for manufacturing a semiconductor device. [Figure 4] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Diagram 5] 10A to 10C are explanatory diagrams of a process for manufacturing a semiconductor device according to a second embodiment. [Figure 6]13 is an enlarged cross-sectional view of the vicinity of the outer periphery of a semiconductor module in a semiconductor device according to a third embodiment. FIG. [Figure 7] FIG. 11 is a cross-sectional view of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments for carrying out the present disclosure will be described with reference to the drawings. Note that in each drawing, the dimensions and scale of each element may differ from those of the actual product. The embodiment described below is an exemplary embodiment assumed when carrying out the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiment exemplified below.

[0010] A: First embodiment 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment of the present disclosure. The semiconductor device 100 according to the first embodiment is a power semiconductor device constituting a power conversion device such as an inverter circuit. As illustrated in FIG. 1, the semiconductor device 100 includes a semiconductor module 10, a cooling unit 20, a thermally conductive layer 30, and a protective film 40.

[0011] In the following description, the Z axis is assumed. One direction along the Z axis is denoted as the Z1 direction, and the opposite direction to the Z1 direction is denoted as the Z2 direction. Viewing any element of the semiconductor device 100 along the complementary transverse direction of the Z axis (Z1 direction or Z2 direction) is hereinafter referred to as "planar view."

[0012] In actual use, the semiconductor device 100 may be installed in any direction, but for convenience in the following description, the Z1 direction is assumed to be downward and the Z2 direction is assumed to be upward. Therefore, the surface of any element of the semiconductor device 100 facing the Z1 direction may be referred to as the "lower surface," and the surface of the element facing the Z2 direction may be referred to as the "upper surface."

[0013] The semiconductor module 10 is a power module including a mounting substrate 11, a semiconductor chip 12, a plurality of connection terminals 13, and a sealing body 14. The semiconductor chip 12 and the plurality of connection terminals 13 are mounted on the mounting substrate 11, and the semiconductor chip 12 is sealed by the sealing body 14. Note that, although the following description focuses on one semiconductor chip 12, a plurality of semiconductor chips 12 may be mounted on the mounting substrate 11.

[0014] The mounting substrate 11 is an insulating substrate such as a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, an IMS (Insulated Metal Substrate), etc. Specifically, the mounting substrate 11 is formed by laminating an insulating substrate 111, a metal layer 112, and a conductive pattern 113.

[0015] The insulating substrate 111 is a rectangular plate-like member made of an insulating material. The insulating substrate 111 is made of a resin material, such as an epoxy resin to which a ceramic filler is added. The insulating substrate 111 may be made of a ceramic material, such as aluminum oxide, zirconium oxide, aluminum nitride, or silicon nitride.

[0016] The metal layer 112 is a rectangular plate-like member disposed on the lower surface of the insulating substrate 111. The metal layer 112 is formed of a metal material having high thermal conductivity. Any material may be used for the metal layer 112, and examples of the material include copper alone, a copper alloy, and aluminum.

[0017] The conductive patterns 113 are conductive films formed on the upper surface of the insulating substrate 111. Each conductive pattern 113 is made of a low-resistance conductive material. The material of each conductive pattern 113 is arbitrary, and examples thereof include copper, a copper alloy, and aluminum.

[0018] The semiconductor chip 12 is a power semiconductor element mounted on the mounting substrate 11. Specifically, the semiconductor chip 12 is joined to the conductive pattern 113 by a joining material 151 such as solder or a sintered material. The semiconductor chip 12 functions as a switching element capable of switching between conducting and blocking a current. The semiconductor chip 12 of the first embodiment is, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0019] The semiconductor chip 12 includes a first electrode 121, a second electrode 122, and a control electrode (not shown). The first electrode 121 and the second electrode 122 are main electrodes to which a current to be controlled is input or output. The first electrode 121 is a collector electrode that constitutes the lower surface of the semiconductor chip 12, and is electrically connected to the conductive pattern 113. The second electrode 122 is an emitter electrode that constitutes the upper surface of the semiconductor chip 12. The control electrode is a gate electrode to which a control voltage for controlling the on / off of the semiconductor chip 12 is applied, and constitutes the upper surface of the semiconductor chip 12 together with the second electrode 122.

[0020] Each of the multiple connection terminals 13 is a conductor electrically connected to the semiconductor chip 12. Specifically, each connection terminal 13 is a lead frame for electrically connecting the semiconductor chip 12 to an external device (not shown). Each connection terminal 13 is formed of a conductive material such as, for example, copper alone or a copper alloy. The connection terminal 13a is bonded to the second electrode 122 of the semiconductor chip 12 via a bonding material 152. The connection terminal 13b is bonded to the conductive pattern 113 via a bonding material 153. The bonding material 152 and the bonding material 153 are conductive materials such as, for example, solder or a sintered material.

[0021] The sealing body 14 is an insulating mold that covers the semiconductor chip 12. For example, the sealing body 14 is formed of a hard resin material such as epoxy resin. The sealing body 14 of the first embodiment is a substantially rectangular parallelepiped structure including a top surface 141, a back surface 142, and a side surface 143. The top surface 141 is an upper surface facing the Z2 direction, and the back surface 142 is a lower surface facing the Z1 direction. The side surface 143 is an end surface that connects the top surface 141 and the back surface 142. Each connection terminal 13 protrudes from the side surface 143 of the sealing body 14. A portion of the tip side of each connection terminal 13 is bent in the Z2 direction.

[0022] 1 is a rectangular lower surface facing the Z1 direction of the semiconductor module 10. The first surface F1 is composed of the surface of the metal layer 112 and the back surface 142 of the sealing body 14.

[0023] 1 is a structure that cools the semiconductor module 10. For example, a heat sink that dissipates heat transmitted from the semiconductor module 10 to the surroundings is used as the cooling unit 20. Also, a heat sink with multiple fins or a water jacket with a flow path through which a coolant such as cooling water flows may be adopted as the cooling unit 20. The second surface F2 in FIG. 1 is a rectangular upper surface of the cooling unit 20 facing the Z2 direction.

[0024] The thermally conductive layer 30 is a rectangular film interposed between the semiconductor module 10 and the cooling unit 20. The thermally conductive layer 30 is formed, for example, in a thin plate, sheet or film shape, and is placed between the semiconductor module 10 and the cooling unit 20. The first face F1 of the semiconductor module 10 and the second face F2 of the cooling unit 20 face each other with the thermally conductive layer 30 in between. The thermally conductive layer 30 functions as an adhesive layer that bonds the first face F1 and the second face F2. The thickness of the thermally conductive layer 30 is an appropriate dimension, for example, not less than 10 μm and not more than 300 μm.

[0025] The thermally conductive layer 30 is formed of a material having high thermal conductivity. Specifically, the thermally conductive layer 30 is formed of a thermosetting resin such as an epoxy resin or a polyimide resin, or a thermoplastic resin such as an olefin. For example, fillers such as silver, aluminum, copper, silicon oxide (SiO2), aluminum oxide (Al2O3), boron nitride, aluminum nitride, and zinc oxide may be dispersed in the thermally conductive layer 30. The thermally conductive layer 30 is basically composed of a single layer, but may be composed of a laminate of multiple layers made of different materials.

[0026] In the above configuration, heat generated in the semiconductor chip 12 is transferred to the cooling unit 20 via the mounting substrate 11 and the thermally conductive layer 30. The thermally conductive layer 30 functions as a heat dissipation layer for transferring heat from the semiconductor module 10 to the cooling unit 20.

[0027] FIG. 2 is an enlarged cross-sectional view of the vicinity of the outer periphery E1 of the semiconductor module 10. The region α of FIG. 1 is illustrated in FIG. 2. As illustrated in FIG. 2, the outer periphery E3 of the thermally conductive layer 30 is located between the outer periphery E1 of the semiconductor module 10 and the outer periphery E2 of the cooling unit 20 in a plan view. Specifically, the outer dimensions of the thermally conductive layer 30 exceed the outer dimensions of the first face F1 of the semiconductor module 10, and the outer periphery E1 of the first face F1 is located inside the outer periphery E3 of the thermally conductive layer 30. In addition, the outer dimensions of the second face F2 of the cooling unit 20 exceed the outer dimensions of the thermally conductive layer 30, and the outer periphery E2 of the second face F2 is located outside the outer periphery E3 of the thermally conductive layer 30. The outer periphery 31 in FIG. 1 and FIG. 2 is a rectangular frame-shaped portion of the thermally conductive layer 30 located outside the outer periphery E1 of the semiconductor module 10 in a plan view.

[0028] The protective film 40 is a coating for preventing moisture from penetrating between the semiconductor module 10 and the cooling unit 20. The protective film 40 of the first embodiment covers and seals the portion where the semiconductor module 10 and the cooling unit 20 are joined. Specifically, the protective film 40 covers a boundary B1 between the semiconductor module 10 and the thermally conductive layer 30, and a boundary B2 between the cooling unit 20 and the thermally conductive layer 30.

[0029] The boundary B1 is between the semiconductor module 10 and the thermally conductive layer 30. Specifically, the boundary B1 is a portion where the side surface 143 of the semiconductor module 10 and the upper surface 32 of the thermally conductive layer 30 intersect. The boundary B2 is a boundary between the cooling unit 20 and the thermally conductive layer 30. Specifically, the boundary B2 is a portion where the second surface F2 of the cooling unit 20 and the side surface 33 of the thermally conductive layer 30 intersect.

[0030] The protective film 40 is formed from the side surface 143 of the semiconductor module 10 to the second surface F2 of the cooling unit 20 so as to cover both the boundary B1 and the boundary B2. Therefore, the protective film 40 covers the outer periphery 31 of the thermally conductive layer 30. The protective film 40 is also expressed as a coating for protecting the thermally conductive layer 30, or a coating for protecting the bond between the thermally conductive layer 30 and the semiconductor module 10 or the cooling unit 20.

[0031] The protective film 40 is made of a material that is more water-resistant and moisture-resistant than the thermally conductive layer 30. Specifically, the protective film 40 is made of a resin material such as a urethane resin, a fluororesin, or a polyimide resin. For the urethane resin, an ether-based resin that is particularly water-resistant and moisture-resistant is preferably used. The resin material of the protective film 40 may have a filler such as silicon oxide (SiO2) or aluminum oxide (Al2O3) dispersed therein.

[0032] As a result of using the above materials, the water absorption rate of the protective film 40 is lower than that of the thermally conductive layer 30. The water absorption rate is the ratio of the weight of water that an object can absorb to the weight of the object. In other words, the protective film 40 is less likely to absorb water than the thermally conductive layer 30.

[0033] 2, the thickness T of the protective film 40 is less than the distance δ between the semiconductor module 10 and the cooling unit 20 (T<δ). The thickness T of the protective film 40 is the average value of the dimensions of the protective film 40 in the direction of the Z axis. The distance δ is the distance between the first face F1 and the second face F2. The thickness of the thermally conductive layer 30 is equal to the distance δ. Therefore, the thickness T of the protective film 40 is less than the thickness of the thermally conductive layer 30.

[0034] As described above, in the first embodiment, the boundary B1 between the semiconductor module 10 and the thermally conductive layer 30 and the boundary B2 between the cooling unit 20 and the thermally conductive layer 30 are covered with the protective film 40. This makes it possible to suppress the intrusion of moisture between the semiconductor module 10 and the cooling unit 20. For example, as a result of suppressing the intrusion of moisture into the boundary B1, a decrease in the adhesive strength between the semiconductor module 10 (first surface F1) and the thermally conductive layer 30 is suppressed. Similarly, as a result of suppressing the intrusion of moisture into the boundary B2, a decrease in the adhesive strength between the cooling unit 20 (second surface F2) and the thermally conductive layer 30 is suppressed.

[0035] In addition, in the first embodiment, since the water absorption rate of the protective film 40 is lower than that of the thermally conductive layer 30, the intrusion of moisture into the thermally conductive layer 30 is suppressed compared to a configuration in which the water absorption rate of the protective film 40 exceeds that of the thermally conductive layer 30. That is, the intrusion of moisture between the semiconductor module 10 and the cooling unit 20 can be suppressed. Therefore, the deterioration of the characteristics of the thermally conductive layer 30 caused by water absorption is suppressed. For example, the deterioration of the insulation property of the thermally conductive layer 30 caused by water absorption is suppressed. Therefore, the deterioration of the dielectric strength voltage in the semiconductor device 100 can be suppressed. Furthermore, the deterioration of the heat dissipation property caused by water absorption is suppressed. Therefore, the deterioration of the heat dissipation performance in the semiconductor device 100 can be suppressed.

[0036] [Method of Manufacturing Semiconductor Device 100] 3 is an explanatory diagram of a process for manufacturing the above-described semiconductor device 100. As illustrated in FIG 3, the process for manufacturing the semiconductor device 100 includes a bonding step P1 and a protection step P2.

[0037] In the bonding process P1, the semiconductor module 10 and the cooling unit 20 are bonded together by the thermally conductive layer 30. Specifically, in the bonding process P1, one of the semiconductor module 10 and the cooling unit 20 is pressed toward the other with the thermally conductive layer 30 interposed between them. The bonding process P1 is performed in a high-temperature environment in which the thermally conductive layer 30 is heated. By the heating and pressurization described above, the semiconductor module 10 and the cooling unit 20 are bonded together via the thermally conductive layer 30.

[0038] After the joining process P1 is performed, the protection process P2 is performed. In the protection process P2, a protective film 40 is formed to cover the boundary B1 and the boundary B2. In the protection process P2, a liquid material prepared to have a low viscosity is applied and cured to form the protective film 40. Specifically, the viscosity of the liquid material before curing used in the protection process P2 is, for example, 3 Pa s or less. By applying and curing a low-viscosity liquid material as described above, a uniform protective film 40 can be formed over a wide area.

[0039] The protective film 40 in the protection step P2 is formed, for example, by spray coating, in which a liquid resin material is applied by spraying from a spray device and then cured. The protective film 40 may also be formed, for example, by dispenser coating, in which a liquid resin material is applied by spraying from a dispenser device and then cured. The protective film 40 can be formed inexpensively and easily by the coating techniques exemplified above.

[0040] B: Second embodiment A second embodiment of the present disclosure will be described. Note that, for elements having the same functions as those in the first embodiment in each of the following exemplary aspects, the same reference numerals as those in the first embodiment will be used, and detailed descriptions of each will be omitted as appropriate.

[0041] 4 is a cross-sectional view of the semiconductor device 100 according to the second embodiment. In the second embodiment, the configuration of the protective film 40 is different from that of the first embodiment. The configuration other than the protective film 40 is the same as that of the first embodiment.

[0042] 4, the protective film 40 of the second embodiment not only covers the boundary B1 and the boundary B2 as in the first embodiment, but also covers the entire sealing body 14. Specifically, the protective film 40 covers the top surface 141 of the sealing body 14 located on the opposite side to the cooling unit 20, and the side surface 143 of the sealing body 14. The protective film 40 covers the entire area of ​​the top surface 141 and the entire area of ​​the side surface 143.

[0043] The protective film 40 of the second embodiment also covers a portion of each connection terminal 13 (13a, 13b). Specifically, the protective film 40 covers a portion of each connection terminal 13 other than the tip portion 131. That is, the protective film 40 is continuous from the side surface 143 of the sealing body 14 to the surface of each connection terminal 13.

[0044] [Method of Manufacturing Semiconductor Device 100] Fig. 5 is an explanatory diagram of a protection step P2 in the process of manufacturing the semiconductor device 100 of the second embodiment. After the bonding step P1 similar to that of the first embodiment is performed, the protection step P2 of Fig. 5 is performed.

[0045] In the second embodiment, dip coating is used to form the protective film 40. In the dip coating, a liquid resin material 61 stored in a container 60 is used. The viscosity of the resin material 61 stored in the container 60 is, for example, 3 Pa·s or less.

[0046] Specifically, in the protection step P2, the semiconductor device 100' before the formation of the protective film 40 is immersed in the resin material 61 in the container 60 to apply the resin material 61. For example, the semiconductor device 100 is immersed in the resin material 61 while the tip portion 131 of each connection terminal 13 is held. Therefore, the resin material 61 does not adhere to the tip portion 131 of each connection terminal 13. The resin material 61 applied in the above steps is cured to form the protective film 40 illustrated in FIG. 4.

[0047] The second embodiment also achieves the same effects as the first embodiment. In the second embodiment, not only the boundary B1 and the boundary B2, but also the top surface 141 and the side surface 143 of the sealing body 14 that seals the semiconductor chip 12 are covered with the protective film 40. Therefore, it is possible to more effectively prevent moisture from entering between the semiconductor module 10 and the cooling unit 20. Furthermore, in the second embodiment, the protective film 40 is formed by dip coating, so that the protective film 40 can be formed inexpensively and easily, similar to the first embodiment in which the protective film 40 is formed by spray coating or dispenser coating.

[0048] C: Third embodiment 6 is an enlarged cross-sectional view of the vicinity of the outer periphery E1 of the semiconductor module 10 in the semiconductor device 100 according to the third embodiment. In the third embodiment, the configurations of the thermally conductive layer 30 and the protective film 40 are different from those of the first embodiment. The configurations other than the thermally conductive layer 30 and the protective film 40 are the same as those of the first embodiment.

[0049] In the first embodiment, the outer periphery E3 of the thermally conductive layer 30 is located outside the outer periphery E1 of the semiconductor module 10. In the third embodiment, as illustrated in Fig. 6, the outer periphery E3 of the thermally conductive layer 30 is located inside the outer periphery E1 of the semiconductor module 10. That is, the thermally conductive layer 30 of the third embodiment does not include the outer periphery 31 of the first embodiment.

[0050] 6, the boundary B1 between the semiconductor module 10 and the thermally conductive layer 30 is a portion where the first surface F1 of the semiconductor module 10 intersects with the side surface 33 of the thermally conductive layer 30. The boundary B2 between the cooling unit 20 and the thermally conductive layer 30 is a portion where the second surface F2 of the cooling unit 20 intersects with the side surface 33 of the thermally conductive layer 30, similar to the first embodiment.

[0051] The protective film 40 of the third embodiment covers the above-described boundary B1 and boundary B2. Specifically, the protective film 40 is formed across the first face F1 of the semiconductor module 10, the side face 33 of the thermally conductive layer 30, and the second face F2 of the cooling unit 20, as illustrated in Fig. 6. That is, the protective film 40 of the third embodiment enters into a recess located outside the thermally conductive layer 30 between the first face F1 and the second face F2.

[0052] The configuration in which the water absorption rate of the protective film 40 is lower than that of the thermally conductive layer 30 and the thickness T of the protective film 40 is lower than the distance δ between the semiconductor module 10 and the cooling unit 20 are the same as those in the first embodiment. The manufacturing method of the semiconductor device 100 in the third embodiment is the same as that in the first embodiment. The semiconductor device 100 of the third embodiment may be manufactured by the manufacturing method exemplified in the second embodiment. The third embodiment also achieves the same effects as the first embodiment.

[0053] In comparison with the above-described third embodiment, in the first embodiment, the outer periphery 31 of the thermally conductive layer 30 is located outside the outer periphery E1 of the semiconductor module 10, and the protective film 40 covers the outer periphery 31 of the thermally conductive layer 30. Therefore, compared with the third embodiment in which the outer periphery E3 of the thermally conductive layer 30 is located inside the outer periphery E1 of the semiconductor module 10, there is an advantage that the intrusion of moisture between the semiconductor module 10 and the cooling unit 20 can be more effectively suppressed.

[0054] D: Variation Specific modified embodiments added to each of the above-mentioned embodiments are exemplified below. Two or more embodiments selected from the following examples may be appropriately combined within a range not causing any contradiction.

[0055] (1) In each of the above-described embodiments, the protective film 40 is formed of a single layer, but the protective film 40 may be formed of a laminate of multiple layers made of different materials. In addition, in each of the above-described embodiments, the protective film 40 is formed of a resin material, but the material of the protective film 40 is not limited to the above examples. For example, the protective film 40 may be formed of an insulating inorganic material.

[0056] (2) The configuration of the semiconductor module 10 is not limited to the examples in the above-mentioned embodiments. For example, the number or arrangement of the semiconductor chips 12, the number or arrangement of the conductive patterns 113, and the number or arrangement of the connection terminals 13 may be changed as desired from the examples in the above-mentioned embodiments. The semiconductor module 10 is collectively expressed as an element including the semiconductor chip 12.

[0057] (3) In the above-described embodiments, the thickness T of the protective film 40 is smaller than the distance δ between the semiconductor module 10 and the cooling unit 20, but the relationship between the thickness T and the distance δ is not limited to the above examples. For example, a configuration in which the thickness T of the protective film 40 is equal to the distance δ (T=δ) or a configuration in which the thickness T of the protective film 40 exceeds the distance δ (T>δ) is also conceivable. Similarly, a configuration in which the thickness T of the protective film 40 is equal to the thickness of the thermal conduction layer 30 or a configuration in which the thickness T exceeds the thickness is also conceivable.

[0058] (4) In each of the above-described embodiments, the thermally conductive layer 30 formed in, for example, a thin plate, sheet or film shape is provided between the semiconductor module 10 and the cooling unit 20, but the shape of the thermally conductive layer 30 is not limited to the above examples. For example, the thermally conductive layer 30 may be formed by curing a liquid resin material applied between the semiconductor module 10 and the cooling unit 20.

[0059] (5) The method for manufacturing the protective film 40 is not limited to the methods exemplified in the above-described embodiments. For example, spin coating, in which a liquid resin material is applied over a wide area by rotating the semiconductor device 100 before the protective film 40 is formed, may be used to form the protective film 40 in the protection step P2.

[0060] (6) In the above-described embodiments, the mounting board 11 is configured by laminating the insulating board 111, the metal layer 112, and the conductive pattern 113, but the configuration of the mounting board 11 is not limited to the above examples. For example, as illustrated in FIG. 7, the mounting board 11 may be configured by only the conductive pattern 114. The surface of the conductive pattern 114 is exposed from the back surface 142 of the sealing body 14. The first face F1 in FIG. 7 is configured by the surface of the conductive pattern 114 and the back surface 142 of the sealing body 14. The mounting board 11 (conductive pattern 114) in FIG. 7 is formed of a conductive material such as copper, a copper alloy, aluminum, or an aluminum alloy.

[0061] In a configuration in which the mounting substrate 11 has no insulation as illustrated in Fig. 7, the thermally conductive layer 30 is formed of an insulating material. Specifically, the thermally conductive layer 30 in Fig. 7 is formed of a thermosetting resin such as an epoxy resin or a polyimide resin, or a thermoplastic resin such as an olefin. For example, a filler such as silicon oxide (SiO2), aluminum oxide (Al2O3), boron nitride, aluminum nitride, or zinc oxide may be dispersed in the thermally conductive layer 30. Note that the thermally conductive layer 30 is basically formed of a single layer, but may be formed of a laminate of multiple layers formed of different materials.

[0062] In addition, in FIG. 7, for the sake of convenience, one conductive pattern 114 is illustrated as the mounting substrate 11, but in a configuration in which, for example, multiple semiconductor chips 12 are mounted, the mounting substrate 11 may be composed of multiple conductive patterns 114.

[0063] (7) In the above-described embodiments, an IGBT is exemplified as the semiconductor chip 12, but the configuration and type of the semiconductor chip 12 are not limited to the above examples. For example, a reverse conducting IGBT (RC-IGBT) including an IGBT and a free wheeling diode (FWD) may be adopted as the semiconductor chip 12. Also, a MOSFET having a semiconductor layer formed of silicon (Si) or silicon carbide (SiC) may be adopted as the semiconductor chip 12. In an embodiment in which the semiconductor chip 12 is a MOSFET, the first electrode 121 is a drain electrode and the second electrode 122 is a source electrode. Furthermore, the semiconductor chip 12 is not limited to a transistor. For example, a diode such as a Schottky Barrier Diode (SBD) may be used as the semiconductor chip 12.

[0064] E: Notes From the above-described exemplary embodiments, the following configurations can be understood, for example.

[0065] A semiconductor device according to one embodiment (embodiment 1) of the present disclosure includes a semiconductor module including a semiconductor chip, a cooling unit for cooling the semiconductor module, a thermally conductive layer interposed between the semiconductor module and the cooling unit, and a protective film for covering the boundary between the semiconductor module and the thermally conductive layer and the boundary between the cooling unit and the thermally conductive layer, the water absorption rate of the protective film being lower than that of the thermally conductive layer. In the above embodiment, the boundary between the semiconductor module and the thermally conductive layer and the boundary between the cooling unit and the thermally conductive layer are covered by the protective film. Therefore, it is possible to suppress the intrusion of moisture between the semiconductor module and the cooling unit. Since the water absorption rate of the protective film is lower than that of the thermally conductive layer, the effect of suppressing the intrusion of moisture between the semiconductor module and the cooling unit is remarkable compared to a configuration in which the water absorption rate of the protective film is higher than that of the thermally conductive layer.

[0066] A semiconductor device according to another aspect (aspect 2) of the present disclosure includes a semiconductor module including a semiconductor chip, a cooling section for cooling the semiconductor module, a thermally conductive layer interposed between the semiconductor module and the cooling section, and a protective film for covering the boundary between the semiconductor module and the thermally conductive layer and the boundary between the cooling section and the thermally conductive layer, the thickness of the protective film being less than the distance between the semiconductor module and the cooling section. In the above aspect, the boundary between the semiconductor module and the thermally conductive layer and the boundary between the cooling section and the thermally conductive layer are covered by the protective film. Therefore, it is possible to suppress the intrusion of moisture between the semiconductor module and the cooling section.

[0067] In a specific example (Aspect 3) of Aspect 2, the water absorption rate of the protective film is lower than that of the thermally conductive layer. In the above aspect, since the water absorption rate of the protective film is lower than that of the thermally conductive layer, the effect of suppressing the intrusion of water between the semiconductor module and the cooling unit is remarkable compared to a configuration in which the water absorption rate of the protective film exceeds that of the thermally conductive layer.

[0068] In a specific example (Aspect 4) of any one of Aspects 1 to 3, the thermally conductive layer includes an outer peripheral portion located outside the outer peripheral edge of the semiconductor module in a planar view, and the protective film covers the outer peripheral portion. In the above aspects, the outer peripheral portion of the thermally conductive layer is located outside the outer peripheral edge of the semiconductor module, and the protective film covers the outer peripheral portion. Therefore, compared to a configuration in which the outer peripheral edge of the thermally conductive layer is located inside the outer peripheral edge of the semiconductor module, it is possible to more effectively suppress the intrusion of moisture between the semiconductor module and the cooling unit.

[0069] In a specific example (Aspect 5) of any one of Aspects 1 to 4, the semiconductor module further includes a sealing body that seals the semiconductor chip, and a connection terminal that is electrically connected to the semiconductor chip and protrudes from the sealing body, and the protective film covers the surface of the sealing body opposite the cooling unit and the side of the sealing body. In the above aspects, not only the boundaries between the semiconductor module and the cooling unit and the thermally conductive layer, but also the surface and side of the sealing body that seals the semiconductor chip are covered with the protective film. Therefore, it is possible to more effectively prevent moisture from penetrating between the semiconductor module and the cooling unit. In addition, the protective film can be formed inexpensively and easily by dipping the semiconductor module in a liquid resin material.

[0070] In a specific example (Aspect 6) of any one of Aspects 1 to 5, the protective film is made of a urethane resin, a fluororesin, or a polyimide resin. As the urethane resin, an ether-based resin that has particularly high water resistance and moisture resistance is preferable.

[0071] A manufacturing method according to one embodiment (embodiment 7) of the present disclosure includes a bonding step of bonding a semiconductor module including a semiconductor chip to a cooling unit that cools the semiconductor module with a thermally conductive layer interposed between the semiconductor module and the cooling unit, and a protection step, which is performed after the bonding step, of forming a protective film that covers the boundary between the semiconductor module and the thermally conductive layer and the boundary between the cooling unit and the thermally conductive layer. In the above embodiment, the boundary between the semiconductor module and the thermally conductive layer and the boundary between the cooling unit and the thermally conductive layer are covered with the protective film. Therefore, it is possible to suppress the intrusion of moisture between the semiconductor module and the cooling unit.

[0072] In a specific example of Aspect 7 (Aspect 8), the protective film is formed by spray coating, dip coating, dispenser coating, or spin coating in the protection step. In the above aspects, the protective film can be formed by a low-cost and simple coating technique such as spray coating, dip coating, dispenser coating, or spin coating.

[0073] Specific Example (Aspect 9) of Aspect 7 or Aspect 8: In the protecting step, the protective film is formed by applying and curing a liquid material having a viscosity of 3 Pa s or less. In the above aspects, a uniform protective film can be formed over a wide area by applying and curing a liquid material having a viscosity of 3 Pa s or less. [Explanation of symbols]

[0074] 100...semiconductor device, 10...semiconductor module, 11...mounting substrate, 111...insulating substrate, 112...metal layer, 113, 114...conductive pattern, 12...semiconductor chip, 121...first electrode, 122...second electrode, 13 (13a, 13b)...connection terminal, 14...sealing body, 141...top surface, 142...rear surface, 143...side surface, 151, 152, 153...bonding material, 20...cooling portion, 30...thermal conductive layer, 31...periphery, 32...upper surface, 33...side surface, 40...protective film, F1...first surface, F2...second surface, B1, B2...boundary.

Claims

1. a semiconductor module including a semiconductor chip; a cooling unit that cools the semiconductor module; a thermally conductive layer interposed between the semiconductor module and the cooling unit; a protective film that covers a boundary between the semiconductor module and the thermally conductive layer and a boundary between the cooling unit and the thermally conductive layer, The water absorption rate of the protective film is lower than that of the thermally conductive layer. Semiconductor device.

2. a semiconductor module including a semiconductor chip; a cooling unit that cools the semiconductor module; a thermally conductive layer interposed between the semiconductor module and the cooling unit; a protective film that covers a boundary between the semiconductor module and the thermally conductive layer and a boundary between the cooling unit and the thermally conductive layer, The thickness of the protective film is less than the distance between the semiconductor module and the cooling unit. Semiconductor device.

3. The water absorption rate of the protective film is lower than that of the thermally conductive layer. The semiconductor device according to claim 2.

4. the thermal conduction layer includes an outer periphery portion located outside an outer periphery of the semiconductor module in a plan view, The protective film covers the outer periphery.

4. The semiconductor device according to claim 1.

5. The semiconductor module includes: an encapsulant that encapsulates the semiconductor chip; a connection terminal electrically connected to the semiconductor chip and protruding from the sealing body, The protective film covers a surface of the sealing body opposite to the cooling portion and a side surface of the sealing body.

3. The semiconductor device according to claim 1.

6. The protective film is made of a urethane resin, a fluororesin, or a polyimide resin.

3. The semiconductor device according to claim 1.

7. a bonding step of bonding a semiconductor module including a semiconductor chip to a cooling unit that cools the semiconductor module by a thermally conductive layer interposed between the semiconductor module and the cooling unit; a protection step, which is performed after the bonding step, of forming a protection film that covers a boundary between the semiconductor module and the thermally conductive layer and a boundary between the cooling portion and the thermally conductive layer; A method for manufacturing a semiconductor device comprising the steps of:

8. In the protection step, the protection film is formed by spray coating, dip coating, dispenser coating, or spin coating. The method for manufacturing a semiconductor device according to claim 7.

9. In the protection step, a liquid material having a viscosity of 3 Pa·s or less is applied and cured to form the protection film. The method for manufacturing a semiconductor device according to claim 7 or 8.

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