Memory system

Abstract

To improve the ability of correcting data errors in a memory system.SOLUTION: A memory system according to an embodiment comprises a semiconductor memory including a plurality of first memory cells configured to store data in a non-volatile fashion depending respectively upon threshold voltages and a controller. The controller is configured to perform first error correction on the plurality of first memory cells based on first hard-bit data and first soft-bit data acquired by using a plurality of first soft-bit voltages and, if a first condition based on correction data as corrected by the first error correction is satisfied, determine a second shift voltage different from the first shift voltage based on a first shift voltage as a potential difference related to the plurality of first soft-bit voltages.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The embodiments relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art There is known a memory system including a memory device capable of storing data in a non-volatile manner and a controller that controls the memory device. The memory system corrects errors in data when reading the data, for example. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2018 / 0074894 [Patent Document 2] US Patent Application Publication No. 2022 / 0180957 [Patent Document 3] US Patent Application Publication No. 2018 / 0006667 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve the data error correction capability of a memory system. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a semiconductor memory including a plurality of first memory cells, each configured to non-volatilely store data according to a threshold voltage, and a controller, wherein the controller is configured to perform a first error correction for the plurality of first memory cells based on first hard bit data and first soft bit data obtained using a plurality of first soft bit voltages, and when a first condition based on corrected data corrected by the first error correction is satisfied, determine a second shift voltage different from the first shift voltage based on a first shift voltage which is a potential difference related to the plurality of first soft bit voltages. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a memory system and a host device according to an embodiment. [Diagram 2] FIG. 1 is a block diagram showing an example of the configuration of a NAND memory according to an embodiment. [Diagram 3] 2 is a circuit diagram for explaining an example of a configuration of a block included in a memory cell array of a NAND memory according to an embodiment. [Figure 4] 4 is a diagram for explaining threshold voltage distributions of memory cell transistors included in the NAND memory according to the embodiment; [Diagram 5] 2 is a diagram for explaining an example of the configuration of an ECC circuit included in the memory system according to the embodiment. [Figure 6] 2 is a block diagram for explaining an example of a configuration of data stored in an internal memory included in the memory system according to the embodiment. [Figure 7] 1 is a flowchart for explaining an overall flow of a read operation using the memory system according to the embodiment. [Figure 8] 5A and 5B are diagrams for explaining fluctuations in threshold voltage distribution of memory cell transistors included in the NAND memory according to the embodiment. [Figure 9] 1 is a diagram for explaining an example of a soft bit read in a memory system according to an embodiment; [Figure 10]11 is a flowchart for explaining a flow of a correction process based on soft bit data in the memory system according to the embodiment. [Figure 11] 1 is a diagram for explaining a log-likelihood ratio table used for error correction in the memory system according to the embodiment. [Figure 12] 1A and 1B are diagrams for explaining generation of a channel matrix executed in a memory system according to an embodiment. [Figure 13] 11 is a diagram for explaining calculation of a shift voltage of a soft bit read executed in the memory system according to the embodiment. [Figure 14] 11A and 11B are diagrams for explaining a soft bit read using a calculated shift voltage, which is performed in the memory system according to the embodiment. [Figure 15] 13 is a flowchart illustrating the flow of a correction process based on soft bit data in a memory system according to a third modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are given the same reference numerals. When elements having similar configurations are to be particularly distinguished from each other, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. Embodiment 1.1 Configuration 1.1.1 Memory System An example of the configuration of the memory system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system and a host device according to an embodiment.

[0009] The memory system 1 includes a controller 10 and a memory device 20 .

[0010] The memory system 1 is, for example, a solid state drive (SSD) or TMThe memory system 1 is a card. The memory system 1 communicates with, for example, an external host device 2. The memory system 1 stores data from the host device 2. The memory system 1 also reads data to the host device 2.

[0011] The controller 10 is configured with an integrated circuit such as a system-on-a-chip (SoC). The controller 10 receives an instruction from the host device 2. The function of each part of the controller 10 can be realized by dedicated hardware, a processor that executes a program (firmware), or a combination of these. The controller 10 controls the memory device 20 based on the received instruction. Specifically, the controller 10 writes data that is instructed to be written based on a write instruction received from the host device 2 to the memory device 20. Also, the controller 10 reads data that is instructed to be read by the host device 2 from the memory device 20 based on a read instruction received from the host device 2, and transmits the data to the host device 2.

[0012] The memory device 20 is, for example, a semiconductor memory. The memory device 20 is, for example, a NAND flash memory. Hereinafter, the memory device 20 is referred to as a NAND memory 20. The NAND memory 20 includes a plurality of memory cell transistors. The NAND memory 20 stores data in a non-volatile manner. The NAND memory 20 is connected to the controller 10 by a NAND bus.

[0013] The NAND bus transmits and receives various signals conforming to the NAND interface via individual signal lines. The various signals include, for example, IO<7:0>, / CE, CLE, ALE, / WE, / RE, and / RB. The signal / CE is a chip enable signal. The signal / CE is a signal for enabling the NAND memory 20. The signal CLE is a command latch enable signal. The signal CLE notifies the NAND memory 20 that the signal IO<7:0> transmitted to the NAND memory 20 while the signal CLE is at the “H (High)” level is a command. The signal ALE is an address latch enable signal. The signal ALE notifies the NAND memory 20 that the signal IO<7:0> transmitted to the NAND memory 20 while the signal ALE is at the “H” level is an address. The signal / WE is a write enable signal. The signal / WE instructs the NAND memory 20 to take in the signal IO<7:0>. The signal / RE is a read enable signal. The signal / RE instructs the NAND memory 20 to output the signal IO<7:0>. The signal / RB is a ready busy signal. The signal / RB indicates whether the NAND memory 20 is in a ready state (a state in which it can accept commands from the outside) or a busy state (a state in which it cannot accept commands from the outside).

[0014] The signal IO<7:0> is, for example, an 8-bit signal. The signal IO<7:0> is transmitted and received between the controller 10 and the NAND memory 20. The signal IO<7:0> includes an address, a command, and data. The command is a signal for controlling the entire NAND memory 20. The data includes read data and write data.

[0015] 1.1.2 Controller The controller 10 includes a processor (CPU: Central Processing Unit) 11, an internal memory 12, a buffer memory 13, a host I / F (host interface circuit) 14, a NAND I / F (NAND interface circuit) 15, and an ECC (Error Checking and Correcting) circuit 16.

[0016] The processor 11 controls the overall operation of the controller 10. The processor 11 issues commands to instruct the NAND memory 20 to execute various operations including a write operation, a read operation, and an erase operation, for example.

[0017] The built-in memory 12 is, for example, a semiconductor memory such as a static random access memory (SRAM). The built-in memory 12 is used as a working area for the processor 11. The built-in memory 12 holds firmware for managing the NAND memory 20, various management tables including multiple compressed data tables, and the like.

[0018] The buffer memory 13 is, for example, a semiconductor memory such as a dynamic random access memory (DRAM). The buffer memory 13 temporarily holds write data received from the host device 2, read data received by the controller 10 from the NAND memory 20, and the like. The buffer memory 13 may be provided outside the controller 10.

[0019] The host interface circuit 14 is connected to the host device 2 via a host bus. The host bus is, for example, a PCI Express (PCI Express TM (Peripheral component interconnect express)), UFS (Universal Flash Storage), SD TMInterface: SAS (Serial attached SCSI (small computer system interface)), SATA (Serial ATA (advanced technology attachment)), or NVMe (NVM EXPRESS TM (Non-volatile memory express). The host interface circuit 14 manages communication between the controller 10 and the host device 2. The host interface circuit 14 transfers, for example, commands and data received from the host device 2 to the processor 11 and buffer memory 13, respectively.

[0020] The NAND interface circuit 15 is connected to the NAND memory 20 via a NAND bus. The NAND bus is, for example, a bus conforming to Toggle NAND (Toggle DDR) and ONFI (Open NAND Flash Interface). The NAND interface circuit 15 controls communication with the NAND memory 20. The NAND interface circuit 15 transmits commands, addresses, and write data to the NAND memory 20 in response to instructions from the processor 11. The NAND interface circuit 15 also receives read data from the NAND memory 20.

[0021] The ECC circuit 16 performs error detection and error correction for data stored in the NAND memory 20. More specifically, the ECC circuit 16 generates an error correction code when writing data. The ECC circuit 16 also adds an error correction code (parity) to the written data. The ECC circuit 16 then performs error correction using the error correction code when reading data. Error correction includes hard decision decoding (hard bit correction) and soft decision decoding (soft bit correction). In the following description and drawings, the hard bit is also simply called HB, and the soft bit is also simply called SB. The success rate of error correction by soft bit correction can be higher than the success rate of error correction by hard bit correction. In hard bit correction, a hard decision decoding code such as a BCH (Bose-Chaudhuri-Hocquenghem) code or an RS (Reed-Solomon) code is used as the error correction code. In the soft bit correction, a soft decision decoding code such as a low-density parity-check (LDPC) code is used as an error correction code. In the following description, the error correction is also called the decoding.

[0022] 1.1.3 NAND memory configuration Next, a configuration example of the NAND memory 20 according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the configuration of the NAND memory according to the embodiment.

[0023] The NAND memory 20 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a register 24, a sequencer 25, a voltage generation circuit 26, a row decoder module 27, and a sense amplifier module .

[0024] The memory cell array 21 includes a plurality of blocks BLK0, BLK1, ..., and BLK(k-1) (k is an integer equal to or greater than 2). Hereinafter, each of the plurality of blocks BLK0, BLK1, ..., and BLK(k-1) will also be simply referred to as a block BLK. Each block BLK is a set of a plurality of memory cell transistors capable of storing data in a non-volatile manner, and is used, for example, as a data erase unit. In addition, the memory cell array 21 is provided with a plurality of bit lines and a plurality of word lines. One memory cell transistor is associated with, for example, one bit line and one word line.

[0025] The input / output circuit 22 transmits and receives signals IO<7:0> to and from the controller 10. The input / output circuit 22 transfers commands and addresses in the signals IO<7:0> to the register 24. The input / output circuit 22 transmits and receives write data and read data to and from the sense amplifier module 28.

[0026] The logic control circuit 23 receives the signals / CE, CLE, ALE, / WE, and / RE from the controller 10. In addition, the logic control circuit 23 transfers the signal / RB to the controller 10.

[0027] The register 24 holds a command and an address. The register 24 transfers the address to a row decoder module 27 and a sense amplifier module 28, and transfers the command to a sequencer 25.

[0028] The sequencer 25 receives a command and controls the entire NAND memory 20 in accordance with a sequence based on the received command.

[0029] The voltage generation circuit 26 generates voltages necessary for operations such as writing, reading, and erasing data based on instructions from the sequencer 25. The voltage generation circuit 26 supplies the generated voltages to the memory cell array 21, the row decoder module 27, and the sense amplifier module 28.

[0030] The row decoder module 27 receives a row address from the register 24 and selects a block BLK based on the row address. Then, a voltage is transferred from the voltage generating circuit 26 to the selected block BLK via the row decoder module 27.

[0031] When reading data, the sense amplifier module 28 senses the read data read from the memory cell transistor to the bit line, and transfers the sensed read data to the input / output circuit 22. When writing data, the sense amplifier module 28 transfers write data written via the bit line to the memory cell transistor. The sense amplifier module 28 also receives a column address in the address from the register 24, and outputs column data based on the column address.

[0032] 1.1.4 Memory cell array configuration Next, the configuration of each block BLK included in the memory cell array 21 of the NAND memory 20 according to the embodiment will be described with reference to Fig. 3. Fig. 3 is a circuit diagram for explaining an example of the configuration of a block included in the memory cell array of the NAND memory according to the embodiment.

[0033] The block BLK includes, for example, four string units SU0, SU1, SU2, and SU3. Hereinafter, each of the four string units SU0, SU1, SU2, and SU3 will also be simply referred to as a string unit SU. Each string unit SU includes a plurality of NAND strings NS. The number of string units SU is not limited.

[0034] Each of the NAND strings NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. The number of memory cell transistors MT per NAND string NS is not limited. Each memory cell transistor MT includes a stack gate including a control gate and a charge storage layer. Each memory cell transistor MT is connected in series between select transistors ST1 and ST2. In the following description, the term "connection" also includes the presence of a conductive element different from the two configurations between the two configurations.

[0035] In each block BLK, the gates of the select transistors ST1 of the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. In addition, the gates of the select transistors ST2 of all the string units SU in the block BLK are commonly connected to a select gate line SGS. The control gates of the memory cell transistors MT0 to MT7 in the same block BLK are connected to word lines WL0 to WL7, respectively. That is, the word lines WL of the same address are commonly connected to all the string units SU in the same block BLK, and the select gate line SGS is commonly connected to all the string units SU in the same block BLK. On the other hand, the select gate line SGD is connected to only one of the string units SU in the same block BLK.

[0036] Among the NAND strings NS arranged in a matrix in the memory cell array 21, the other ends of the select transistors ST1 of the NAND strings NS in the same row are connected to one of m bit lines BL0 to BL(m-1) (m is an integer of 2 or more). Hereinafter, each of the m bit lines BL0 to BL(m-1) is also simply referred to as a bit line BL. The bit line BL is commonly connected to the NAND strings NS in the same column across multiple blocks BLK.

[0037] The other end of the select transistor ST2 is connected to a source line SL. The source line SL is commonly connected to a plurality of NAND strings NS across a plurality of blocks BLK.

[0038] As described above, data erasure is performed, for example, on memory cell transistors MT in the same block BLK all at once. In contrast, data reading and writing can be performed, for example, on a plurality of memory cell transistors MT commonly connected to any one word line WL in any one string unit SU of any one block BLK all at once. Such a set of memory cell transistors MT sharing a word line WL in one string unit SU is called, for example, a cell unit CU. That is, a cell unit CU is a set of memory cell transistors MT on which a write operation or a read operation is performed all at once. A cell unit CU corresponds, for example, to a set of one or more memory areas. A write operation or a read operation for one cell unit CU is performed for one of the sets of the memory areas. Such a unit of memory area is called a page. Hereinafter, various data including the data length of one page is called page data.

[0039] 1.1.5 Threshold distribution of memory cell transistors The threshold voltage distribution of the memory cell transistors MT included in the NAND memory 20 according to the embodiment will be described with reference to FIG. 4. FIG. 4 is a diagram for explaining an example of the threshold voltage distribution of the memory cell transistors included in the NAND memory according to the embodiment. FIG. 4 shows an example of the threshold voltage distribution of the memory cell transistors MT in the NAND memory 20 according to the embodiment. The vertical axis of the threshold voltage distribution shown in FIG. 4 corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltage of the memory cell transistor MT. In FIG. 4 and the following description, the number and threshold voltage of the memory cell transistors MT are also referred to as NMTs and Vth, respectively.

[0040] 4, in the threshold voltage distribution of the memory cell transistors MT included in the NAND memory 20 according to the embodiment, for example, two states are formed depending on the threshold voltages of the multiple memory cell transistors MT. Hereinafter, the two states are referred to as the "Er" state and the "A" state in order from the lowest threshold voltage.

[0041] The "Er" state corresponds to, for example, an erased state of data. The threshold voltage of the memory cell transistor MT included in the "Er" state is, for example, less than the voltage AR(0).

[0042] The "A" state corresponds to a state in which charges are injected into the charge storage layer of the memory cell transistor MT. The threshold voltage of the memory cell transistor MT included in the "A" state is, for example, equal to or higher than the voltage AR(0).

[0043] When a voltage is applied to the control gate of the memory cell transistor MT, the memory cell transistor MT is turned on if the memory cell transistor MT has a threshold voltage less than the applied voltage, and when a voltage is applied to the control gate of the memory cell transistor MT, the memory cell transistor MT is turned off if the memory cell transistor MT has a threshold voltage equal to or greater than the applied voltage.

[0044] A different 1-bit data is assigned to the "Er" state and the "A" state. For example, "1" data is assigned to the "Er" state. For example, "0" data is assigned to the "A" state.

[0045] When such data allocation is applied, one page of data consisting of data ("1" data and "0" data) held by memory cell transistor MT is determined, for example, by a data read process using voltage AR(0). Hereinafter, the process of acquiring a judgment result of which of two assigned data is the data by one read voltage set for two adjacent states is called a hard bit read. Moreover, the one read voltage is called a hard bit voltage. Moreover, the page data acquired by a hard bit read for a certain page in block BLK is called hard bit data. Moreover, each bit of the hard bit data is called a hard bit (hard judgment value).

[0046] 1.1.6 ECC circuit The configuration of the ECC circuit 16 included in the controller 10 according to the embodiment will be described with reference to Fig. 5. Fig. 5 is a diagram for explaining an example of the configuration of the ECC circuit included in the memory system according to the embodiment.

[0047] The ECC circuit 16 includes an encoding circuit 161 , a decoding circuit 162 , a channel matrix generating circuit 163 , and a shift voltage calculating circuit 164 .

[0048] The encoding circuit 161 is a circuit that performs encoding processing. In the encoding processing, the encoding circuit 161 generates an error correction code. In the encoding processing, the encoding circuit 161 also adds the error correction code to the write data.

[0049] The decoding circuit 162 includes a hard-decision decoding circuit 162a and a soft-decision decoding circuit 162b.

[0050] The hard decision decoding circuit 162a is a circuit that performs hard bit correction. The hard decision decoding circuit 162a performs error correction using a hard decision decoding code. More specifically, the hard decision decoding circuit 162a detects an error in the read data using the hard decision decoding code for the hard bit data. When an error is detected, the hard decision decoding circuit 162a corrects the error in the read data.

[0051] The soft decision decoding circuit 162b is a circuit that performs soft bit correction. The soft decision decoding circuit 162b performs error correction using a log-likelihood ratio (LLR) table and a soft decision decoding code. The LLR table will be described later, and is a table related to the likelihood of data read from the memory cell transistor MT. In the soft bit correction, the soft decision decoding circuit 162b performs iterative calculations using the LLR table and the soft decision decoding code for the hard bit data and the soft bit data in units of ECC frames. The soft bit data is page data acquired by a soft bit read for a certain page in the block BLK. The soft bit read will be described later, and is a process of calculating soft bits by a data read process using a plurality of read voltages (soft bit voltages) set based on the hard bit voltage. The soft bit is each bit included in the soft bit data. In addition, the ECC frame is, for example, a unit of data for which soft decision decoding is performed by the soft decision decoding circuit 162b. The hard bit data and the soft bit data may include one or more ECC frames. The soft decision decoding circuit 162b corrects errors in the read data based on the result of the iterative calculation.

[0052] The channel matrix generating circuit 163 is a circuit that generates a channel matrix using hard bit data and soft bit data. The channel matrix is ​​a matrix related to the expected value of the number of memory cell transistors MT having "0" data and the expected value of the number of memory cell transistors MT having "1" data. The details of the channel matrix will be described later. The channel matrix generating circuit 163 generates a channel matrix for each ECC frame, for example.

[0053] The shift voltage calculation circuit 164 is a circuit for determining a plurality of soft bit voltages. The shift voltage calculation circuit 164 calculates, for example, a shift voltage dRu relating to a difference between a plurality of soft bit voltages. The calculated shift voltage dRu is held, for example, in the built-in memory 12. The shift voltage calculation circuit 164 updates the held shift voltage dRu, for example, every time the shift voltage dRu is calculated. The shift voltage dRu will be described later. The shift voltage calculation circuit 164 may be included in a configuration different from the ECC circuit 16 in the controller 10.

[0054] 1.1.7 Data structure stored in the built-in memory The configuration of data stored in the built-in memory 12 will be described with reference to Fig. 6. Fig. 6 is a block diagram for explaining an example of the configuration of data stored in the built-in memory included in the memory system according to the embodiment.

[0055] The built-in memory 12 includes, for example, an LLR table 121, a channel matrix 122, and a shift voltage table 123.

[0056] The LLR table 121 includes log-likelihood ratios (LLR values). The LLR value is information expressing the likelihood that a bit stored in a memory cell transistor MT is "0" and the likelihood that the bit is "1" as a logarithmic ratio. The LLR value is information regarding the likelihood of data read by a certain read voltage. The LLR value is assigned to each of a plurality of threshold voltage ranges divided in the threshold voltage distribution of the memory cell transistor MT. Note that an example of the LLR table 121 in the embodiment will be shown in the description of the operation described later.

[0057] The built-in memory 12 may include multiple LLR tables 121. Each of the multiple LLR tables is set in consideration of fluctuations in the threshold voltage of the memory cell transistor MT due to various influences. One of the multiple LLR tables to be used for soft bit correction may be selected by the ECC circuit 16.

[0058] The channel matrix 122 holds an expected value of the number of memory cell transistors MT having data "0" and an expected value of the number of memory cell transistors MT having data "1" for each of a plurality of threshold voltage ranges in the LLR table 121. Note that in the description of the operation to be described later, an example of the channel matrix 122 in the embodiment will be shown.

[0059] The shift voltage table 123 holds, for example, the calculated shift voltage dRu and the shift voltage dRdef. The shift voltage dRdef is used as an initial value when determining a plurality of soft bit voltages used in the soft bit read. The shift voltage dRdef may be, for example, a fixed value. In the following description, when the shift voltages dRu and dRdef are not distinguished from each other, each of the shift voltages dRu and dRdef is also simply referred to as the shift voltage dR.

[0060] 1.2 Operation A read operation using the memory system 1 according to the embodiment will be described below.

[0061] 1.2.1 Overall operation First, the overall flow of a read operation using the memory system 1 according to the embodiment will be described with reference to Fig. 7. Fig. 7 is a flowchart for explaining the overall flow of a read operation using the memory system according to the embodiment. Below, processing related to read data for one page in a block BLK will be described.

[0062] In S1, when the controller 10 starts a read operation, it applies a hard bit voltage to the selected word line WL. Then, a hard bit read is performed to acquire hard bit data corresponding to one page in the selected block BLK. The hard bit voltage is set to, for example, a default read voltage AR(0) or a voltage shifted from the read voltage AR(0). The read hard bit data is stored in the buffer memory 13. Then, the process proceeds to S2. Note that the hard bit read in S1 of the embodiment is called a first hard bit read. Also, the hard bit data read by the first hard bit read is called the first hard bit data.

[0063] In S2, the hard decision decoding circuit 162a performs hard bit correction for each ECC frame using, for example, the first hard bit data. Then, the process proceeds to S3.

[0064] In S3, the controller 10 determines whether the hard bit correction of all ECC frames included in the first hard bit data has been successful. If the hard bit correction of all ECC frames included in the first hard bit data has been successful (S3; Yes), the read operation ends. If the first hard bit data includes an ECC frame for which the hard bit correction has failed (S3; No), the process proceeds to S4.

[0065] A supplementary explanation of step S3: Immediately after the write operation, the threshold voltage distribution is such that the “Er” state and the “A” state are separated from each other, for example, as shown in FIG 4. With such a threshold voltage distribution, for example, a first hard bit read using the default read voltage AR(0) and hard bit correction are performed, so that the correct page data can be read.

[0066] However, as shown in Fig. 8, the memory cell transistor MT may be affected by various factors, and two adjacent states may overlap in the threshold voltage distribution. Fig. 8 is a diagram for explaining the variation in threshold voltage distribution of the memory cell transistor included in the NAND memory according to the embodiment.

[0067] In this case, the controller 10 may not be able to determine the state of a certain memory cell transistor MT at the time of writing by the first hard bit read using the read voltage AR(0). Such a bit that cannot be determined is called a fail bit. More specifically, for example, in the threshold voltage distribution shown in FIG. 8, when the first hard bit read is executed using the read voltage AR(0), as shown in the hatched area in FIG. 8, the memory cell transistors MT included in the "Er" state that have a threshold voltage equal to or higher than the read voltage AR(0) and the memory cell transistors MT included in the "A" state that have a threshold voltage lower than the read voltage AR(0) become memory cell transistors MT whose state at the time of writing cannot be determined. If the number of fail bits exceeds the number of errors that can be corrected by hard bit correction, the controller 10 fails to perform hard bit correction.

[0068] Returning to Fig. 7, if the hard bit correction fails (S3; No), in S4, the controller 10 executes, for example, threshold voltage tracking. As a result, the controller 10 calculates a read voltage (tracking voltage) ARt that reduces the number of fail bits, for example, as shown by the arrow in Fig. 8. That is, the tracking voltage is, for example, a read voltage that becomes a threshold voltage near the intersection point between the "Er" state and the "A" state.

[0069] In S5, for example, the controller 10 determines whether the shift voltage calculation circuit 164 holds the shift voltage dRu. If the shift voltage calculation circuit 164 holds the shift voltage dRu (S5; YES), the process proceeds to S7. If the shift voltage calculation circuit 164 does not hold the shift voltage dRu (S5; NO), the process proceeds to S6. The shift voltage dR will be described in detail later.

[0070] In S6, the controller 10 sets the shift voltage dR to the shift voltage dRdef that is held as the initial value, and then the process proceeds to S8.

[0071] In S7, the controller 10 sets the shift voltage dR to the held calculated shift voltage dRu, and the process then proceeds to S8.

[0072] In S8, first, the controller 10 executes a hard bit read using a tracking voltage ARt. The hard bit read using the tracking voltage ARt is called a second hard bit read. The hard bit data read by the second hard bit read is called the second hard bit data. Then, the controller 10 executes a soft bit read using a tracking voltage ARt and a plurality of soft bit voltages based on the set shift voltage dR. In this way, the controller 10 acquires the soft bit data. After that, the process proceeds to S9. The soft bit read will be described in detail later.

[0073] In S9, the controller 10 executes a correction process based on the soft bit data. The correction process based on the soft bit data includes soft bit correction. The correction process based on the soft bit data will be described later.

[0074] In this manner, the read operation using the memory system 1 according to the embodiment is completed.

[0075] 1.2.2 Soft Bit Read The soft bit read will be described with reference to Fig. 9. Fig. 9 is a diagram for explaining an example of a soft bit read in the memory system according to the embodiment.

[0076] The soft bit read includes a data read process using a plurality of soft bit voltages that are set based on the shift voltage dR, for example, with the tracking voltage ARt as a reference. The shift voltage dR includes shift voltages dR1 and dR2. In FIG. 9, the soft bit voltages are voltages ARt(-3), ARt(-2), ARt(-1), ARt(+1), ARt(+2), and ARt(+3). The voltage ARt(-3) is lower than the voltage ARt(-2) by the shift voltage dR1. The voltage ARt(-2) is lower than the voltage ARt(-1) by the shift voltage dR1. The voltage ARt(-1) is lower than the tracking voltage ARt by the shift voltage dR1. The voltage ARt(+1) is higher than the tracking voltage ARt by the shift voltage dR2. The voltage ARt(+2) is higher than the voltage ARt(+1) by the shift voltage dR2. The voltage ARt(+3) is higher than the voltage ARt(+2) by a shift voltage dR2. The shift voltages dR1 and dR2 may be different from each other or may be the same as each other.

[0077] The shift voltage dRdef in the initial state includes a shift voltage dRdef1 used as the shift voltage dR1, and a shift voltage dRdef2 used as the shift voltage dR2. The shift voltages dRdef1 and dRdef2 may be different from each other or may be the same. The calculated shift voltage dRu includes a shift voltage dRu1 used as the shift voltage dR1, and a shift voltage dRu2 used as the shift voltage dR2. The combination of multiple soft bit voltages is not limited to the above combinations.

[0078] The threshold voltages are classified into eight regions according to the soft bit voltages and tracking voltages. Hereinafter, the eight regions are designated by indexes index1 “1” to “8” in ascending order of threshold voltage. The region of index index1 “1” is a region where the threshold voltage is less than voltage ARt(−3). The region of index index1 “2” is a region where the threshold voltage is equal to or greater than voltage ARt(−3) and less than voltage ARt(−2). The region of index index1 “3” is a region where the threshold voltage is equal to or greater than voltage ARt(−2) and less than voltage ARt(−1). The region of index index1 “4” is a region where the threshold voltage is equal to or greater than voltage ARt(−1) and less than tracking voltage ARt. The region of index index1 “5” is a region where the threshold voltage is equal to or greater than tracking voltage ARt and less than voltage ARt(+1). The region of index index1 “6” is a region where the threshold voltage is equal to or greater than voltage ARt(+1) and less than voltage ARt(+2). The region of index index1 “7” is a region where the threshold voltage is equal to or greater than voltage ARt(+2) and less than voltage ARt(+3). The region of index index1 “8” is a region where the threshold voltage is equal to or greater than voltage ARt(+3).

[0079] The hard bit included in the second hard bit data acquired by the second hard bit read using the tracking voltage ARt is called the hard bit HB2. When the threshold voltage of the memory cell transistor MT is included in the area specified by the indexes index1 “1” to “4”, the hard bit HB2 is “1”. When the threshold voltage of the memory cell transistor MT is included in the area specified by the indexes index1 “5” to “8”, the hard bit HB2 is “0”.

[0080] Furthermore, the soft bit read includes a process of acquiring the result of a logical operation using data acquired by a read process using the above-mentioned multiple read voltages. The result of the logical operation acquired as page data by the soft bit read is soft bit data. The soft bit data includes first soft bit data and second soft bit data. Hereinafter, the soft bit included in the first soft bit data will be referred to as the first soft bit SB1. Also, the soft bit included in the second soft bit data will be referred to as the second soft bit SB2.

[0081] The first soft bit data is obtained by, for example, an ENOR (exclusive negative OR) operation of a plurality of data read from the memory cell transistor MT using the voltages ARt(-2) and ARt(+2), respectively. When the threshold voltage of the memory cell transistor MT is included in the range specified by the indexes index1 "1", "2", "7", and "8", the first soft bit SB1 is "1". When the threshold voltage of the memory cell transistor MT is included in the range specified by the indexes index1 "3" to "6", the first soft bit SB1 is "0".

[0082] The second soft bit data is obtained by, for example, an exclusive negative OR (ENOR) operation of a plurality of data read from the memory cell transistor MT using the voltages ARt(-3), ARt(-1), ARt(+1), and ARt(+3), respectively. When the threshold voltage of the memory cell transistor MT is included in the range specified by the indexes index1 “1”, “4”, “5”, and “8”, the second soft bit SB2 is “1”. When the threshold voltage of the memory cell transistor MT is included in the range specified by the indexes index1 “2”, “3”, “6”, and “7”, the second soft bit SB2 is “0”.

[0083] 9, among the memory cell transistors MT in the "Er" state, the memory cell transistors MT whose threshold voltage is included in the region specified by index index1 "8", and among the memory cell transistors MT in the "A" state, the memory cell transistors MT whose threshold voltage is included in the region specified by index index1 "1" are called memory cell transistors MT having a hard error state. If the number of memory cell transistors MT having a hard error state increases, the success rate of soft bit correction decreases. For this reason, it is desirable to have a small number of memory cell transistors MT having a hard error state.

[0084] 1.2.3 Correction process based on soft bit data The correction process based on the soft bit data in S9 will be described with reference to Fig. 10. Fig. 10 is a flowchart for explaining the flow of the correction process based on the soft bit data in the memory system according to the embodiment.

[0085] In S11, a variable i1 is initialized (i1=0), and the process proceeds to S12.

[0086] In S12, the soft decision decoding circuit 162b converts the combination of the hard bit HB2, the first soft bit SB1, and the second soft bit SB2 into an LLR value for the i1-th ECC frame using the LLR table 121. The soft decision decoding circuit 162b executes soft bit correction for the i1-th ECC frame using the converted LLR value and the soft decision decoding code added to the data by the ECC circuit 16. Then, the channel matrix generating circuit 163 generates the channel matrix 122. Then, the process proceeds to S13. The generation of the channel matrix 122 will be described later.

[0087] The LLR table 121 will be further explained with reference to Fig. 11. Fig. 11 is a diagram for explaining a log-likelihood ratio table used for error correction in the memory system according to the embodiment.

[0088] The LLR table holds an LLR value for each index index1, for example. That is, in the LLR table, an LLR value is held for each combination of hard bit HB2, first soft bit SB1, and second soft bit SB2. The higher the likelihood that memory cell transistor MT holds "0" data, the larger the LLR value (positive value). The higher the likelihood that memory cell transistor MT holds "1" data, the smaller the LLR value (negative value).

[0089] For example, the LLR value of the memory cell transistor MT whose threshold voltage is included in the threshold voltage range specified by the index index1 “1” is −9. When the threshold voltage of the memory cell transistor MT is included in the threshold voltage range specified by the index index1 “1”, the hard bit HB2, the first soft bit SB1, and the second soft bit SB2 read from the memory cell transistor MT are “1”, “1”, and “1”, respectively, as shown in FIG. 9. The LLR value of the memory cell transistor MT whose threshold voltage is included in the threshold voltage range specified by the index index1 “5” is +1. When the threshold voltage of the memory cell transistor MT is included in the threshold voltage range specified by the index index1 “5”, the hard bit HB2, the first soft bit SB1, and the second soft bit SB2 read from the memory cell transistor MT are “0”, “0”, and “1”, respectively, as shown in FIG. 9.

[0090] Returning to FIG. 10, the correction process based on the soft bit data will be further described.

[0091] In S13, the controller 10 judges whether the soft bit correction for the i1th ECC frame is successful. If the soft bit correction for the i1th ECC frame is successful (S13; Yes), the process proceeds to S14. If the soft bit correction for the i1th ECC frame is unsuccessful (S13; NO), the process proceeds to S15.

[0092] In S14, the controller 10 determines whether the HE condition is satisfied for the i1-th ECC frame based on the channel matrix 122. In an embodiment, the HE condition is, for example, the presence of one or more memory cell transistors MT in a hard error state having a threshold voltage lower than the voltage ARt(-3) or equal to or higher than the voltage ARt(+3). If the HE condition is satisfied for the i1-th ECC frame (S14; Yes), the process proceeds to S16. If the HE condition is not satisfied for the i1-th ECC frame (S14; NO), the process proceeds to S17.

[0093] In S15, the controller 10 executes other processes except for the soft bit correction, and executes the error correction. Then, the process proceeds to S17. In the embodiment, the process of S15 may not be executed. In this case, if the soft bit correction of the i1-th ECC frame fails (S13; NO), the process proceeds to S17.

[0094] In S16, the shift voltage calculation circuit 164 calculates the shift voltages dRu1 and dRu2 based on the generated channel matrix 122. Then, the shift voltage calculation circuit 164 updates the shift voltages dRu1 and dRu2 held by the shift voltage calculation circuit 164. The update of the shift voltages dRu1 and dRu2 will be described later. Then, the process proceeds to S17.

[0095] In S17, it is determined whether the i1-th ECC frame is the last ECC frame in the page. If the i1-th ECC frame is the last ECC frame (S17; Yes), the process ends. If the i1-th ECC frame is not the last ECC frame (S17; NO), the process proceeds to S18.

[0096] In S18, the controller 10 increments the variable i1 (i1++), and the process then proceeds to S12.

[0097] In this manner, the controller 10 repeats the processes of S11 to S18 until the i1th ECC frame becomes the last ECC frame.

[0098] In this manner, correction processing based on the soft bit data is carried out.

[0099] 1.2.4 Generating the Channel Matrix The generation of the channel matrix 122 will be described with reference to FIG. 12. FIG. 12 is a diagram for explaining the generation of the channel matrix executed in the memory system according to the embodiment. FIG. 12(A) is a table showing the channel matrix 122. FIG. 12(B) is a graph showing the number of "0" data in the channel matrix 122. FIG. 12(C) is a graph showing the number of "1" data in the channel matrix 122.

[0100] In the example of the embodiment, the size of the channel matrix 122 is 2 rows and 8 columns. The rows represent the number DLECNT of "0" data and "1" data in the data corrected by the soft bit correction. The values ​​N1[1] to N1[8] are the number of "1" data. The values ​​N0[1] to N0[8] are the number of "0" data. The columns represent the index index1.

[0101] The value N1[1] is, for example, the number of memory cell transistors MT whose bit value in the corrected data is "1" and whose threshold voltage is included in the threshold voltage range specified by index index1 "1". The value N0[1] is, for example, the number of memory cell transistors MT whose bit value in the corrected data is "0" and whose threshold voltage is included in the threshold voltage range specified by index index1 "1".

[0102] Similarly, the value N1[5] is, for example, the number of memory cell transistors MT whose bit value in the corrected data is “1” and whose threshold voltage is included in the threshold voltage range specified by the index index1 “5.” Also, the value N0[5] is, for example, the number of memory cell transistors MT whose bit value in the corrected data is “0” and whose threshold voltage is included in the threshold voltage range specified by the index index1 “5.”

[0103] 12, the value N1[8] is the number of memory cell transistors MT in a hard error state in which the bit value in the corrected data is "1". Also, the value N0[1] is the number of memory cell transistors MT in a hard error state in which the bit value in the corrected data is "0".

[0104] 1.2.5 Calculating the shift voltage The calculation of the shift voltage will be described with reference to FIG. 13. FIG. 13 is a diagram for explaining the calculation of the shift voltage of the soft bit read executed in the memory system according to the embodiment. FIG. 13(A) is a graph for explaining the calculation of the shift voltage dRu1 using the number DLECNT of “0” data. In FIG. 13(A), the horizontal axis, which is the linear axis, shows an index index2, which will be described later, and the vertical axis, which is the logarithmic axis, shows the number DLECNT. FIG. 13(B) is a graph for explaining the calculation of the shift voltage dRu2 using the number DLECNT of “1” data. In FIG. 13(B), the horizontal axis, which is the linear axis, shows an index index3, which will be described later, and the vertical axis, which is the logarithmic axis, shows the number DLECNT.

[0105] When the HE condition is satisfied, the shift voltage calculation circuit 164 updates the shift voltage dRu based on the number DLECNT in the channel matrix 122. More specifically, the HE condition includes a first HE condition and a second HE condition. The first HE condition is that a memory cell transistor MT that is in a hard error state in which the bit value in the corrected data is "0" exists (value N0[1]) ≧ 1). The second HE condition is that a memory cell transistor MT that is in a hard error state in which the bit value in the corrected data is "1" exists (value N1[8]) ≧ 1). When the first HE condition is satisfied, the shift voltage calculation circuit 164 changes the shift voltage dRu1. When the second HE condition is satisfied, the shift voltage calculation circuit 164 changes the shift voltage dRu2.

[0106] The following describes the case where the shift voltage dRu1 is changed and the case where the shift voltage dRu2 is changed.

[0107] (When changing the shift voltage dRu1) The shift voltage calculation circuit 164 performs fitting on the memory cell transistors MT whose bit values ​​in the corrected data are “0” based on the number DLECNT in the channel matrix 122.

[0108] 13A, the shift voltage calculation circuit 164 uses values ​​N0[2] to N0[7] of the channel matrix 122 to perform fitting for an index index2 corresponding to these values. That is, the shift voltage calculation circuit 164 performs fitting using data excluding values ​​N0[1] and N0[8]. In the example of the embodiment, the index index2 is an index obtained by adding 2 to the index index1 (index2=index1+2).

[0109] The fitting is performed, for example, using a function Fit0 expressed by the following formula (1) for a value N0[index2-2] where index index2 is an integer between 4 and 9 inclusive.

[0110]

number

[0111] In the above formula (1), the values ​​a and b are fitting parameters.

[0112] In the following description, the value of a function at each index is suffixed with "[index]." For example, the value of the function Fit0 at index2 is called the value Fit0[index2].

[0113] By the above fitting, the shift voltage calculation circuit 164 estimates the number DLECNT corresponding to the indexes index2 “1” to “9” as the value Fit0[index2]. In FIG 13(A), the value Fit0[index2] estimated by the fitting is indicated by “Δ”.

[0114] The shift voltage calculation circuit 164 adds the values ​​Fit0[index2] where the index index2 is 3 or less, in ascending order of index2, and determines the index index2max where the sum exceeds the value N0[1] for the first time. That is, the shift voltage calculation circuit 164 determines the maximum index index2max that satisfies the following formula (2) among the indexes index2 that are 3 or less.

[0115]

number

[0116] The shift voltage calculation circuit 164 calculates the shift voltage dRu1 based on the index index2max so that the threshold voltage of the memory cell transistor MT in the hard error state is included in the range of voltage ARt(-3) or more. Specifically, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 so that the voltage ARt(-3) is lowered by the voltage ((4-index2max)×dR1) obtained by multiplying the shift voltage dR1 used in S8 by the value obtained by subtracting the index index2max from 4. As a result, the calculated shift voltage dRu1 is the voltage ((3×dR1+(4-index2max)×dR1) / 3).

[0117] In this manner, the shift voltage dRu1 is calculated.

[0118] (When changing the shift voltage dRu2) The shift voltage calculation circuit 164 performs fitting on the memory cell transistors MT whose bit values ​​in the corrected data are “1” based on the number DLECNT in the channel matrix 122.

[0119] 13B, the shift voltage calculation circuit 164 uses the values ​​N1[2] to N1[7] of the channel matrix 122 to perform fitting for the index index3 corresponding to these values. That is, the shift voltage calculation circuit 164 performs fitting using data excluding the values ​​N1[1] and N1[8]. In the example of the embodiment, the index index3 is an index obtained by subtracting the index index1 from 11 (index3=11-index1).

[0120] The fitting is performed, for example, using a function Fit1 expressed by the following formula (3) for a value N1[11-index3] where index index3 is an integer between 4 and 9 inclusive.

[0121]

number

[0122] In the above equation (3), the values ​​c and d are fitting parameters.

[0123] By the above fitting, the shift voltage calculation circuit 164 estimates the number DLECNT corresponding to the index index3 “1” to “9” as the value Fit1[index3]. In FIG. 13B, the value Fit1[index3] estimated by the fitting is indicated by “Δ”.

[0124] The shift voltage calculation circuit 164 adds up the values ​​Fit1[index3] where index index3 is 3 or less, in ascending order of index3, and determines an index index3max where the sum exceeds the value N1[8] for the first time. That is, the shift voltage calculation circuit 164 determines the maximum index index3max that satisfies the following formula (4) among the indexes index3 that are 3 or less.

[0125]

number

[0126] The shift voltage calculation circuit 164 calculates the shift voltage dRu2 based on the index index3max so that the threshold voltage of the memory cell transistor MT in the hard error state is included in the range of voltage ARt(-3) or more. Specifically, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 so that the voltage ARt(-3) is lowered by the voltage ((4-index3max)×dR2) obtained by multiplying the shift voltage dR2 used in S8 by the value obtained by subtracting the index index3max from 4. As a result, the calculated shift voltage dRu2 is the voltage ((3×dR2+(4-index3max)×dR2) / 3).

[0127] In this manner, the shift voltage dRu2 is calculated.

[0128] As described above, by calculating the shift voltage dRu, the controller 10 is configured to use the updated shift voltage dRu when performing a soft bit read in the next or subsequent read operation, as shown in Fig. 14. Fig. 14 is a diagram for explaining a soft bit read using the calculated shift voltage, which is performed in the memory system according to the embodiment. Fig. 14 shows a case where both the shift voltages dRu1 and dRu2 are updated.

[0129] In FIG. 14, a tracking voltage ARt' is shown as a hard bit voltage of the second hard bit read in the next or subsequent read operation. Also, voltages ARt'(-3), ARt'(-2), ARt'(-1), ARt'(+1), ARt'(+2), and ARt'(+3) based on the tracking voltage ARt' and the shift voltages dRu1 and dRu2 are shown as soft bit voltages of the soft bit read in the next or subsequent read operation. The voltage ARt'(-3) is lower by the shift voltage dRu1 than the voltage ARt'(-2). The voltage ARt'(-2) is lower by the shift voltage dRu1 than the voltage ARt'(-1). The voltage ARt'(-1) is lower by the shift voltage dRu1 than the tracking voltage ARt'. The voltage ARt'(+1) is higher by the shift voltage dRu2 than the tracking voltage ARt'. The voltage ARt'(+2) is higher by the shift voltage dRu2 than the voltage ARt'(+1). The voltage ARt'(+3) is higher than the voltage ARt'(+2) by a shift voltage dRu2.

[0130] The updated shift voltages dRu1 and dRu2 are higher than the pre-update shift voltages dR1 and dR2, respectively. As a result, the voltage ARt'(-3) becomes lower than the voltage ARt(-3). Also, the voltage ARt'(+3) becomes higher than the voltage ARt(+3).

[0131] From the above, when the shift voltage dR is updated in a read operation of a certain page, after the read operation, the updated shift voltage dRu is used in the soft bit read in the next read operation and thereafter, thereby preventing the inclusion of a memory cell transistor MT in a hard error state, as shown in Figure 14.

[0132] 1.3 Effects of the embodiment According to the embodiment, it is possible to improve the data error correction capability of the memory system 1. The effects of the embodiment will be described below.

[0133] In the memory system 1 according to the embodiment, the controller 10 is configured to perform soft bit correction on a plurality of memory cell transistors MT included in a certain page (first page) based on the second hard bit data, the first soft bit data, and the second soft bit data. The controller 10 is also configured to determine a new shift voltage dRu based on the shift voltage dRu when the HE condition based on the corrected data corrected by the soft bit correction is satisfied. More specifically, when the data corrected by the soft bit correction on the first page includes a memory cell transistor MT in a hard error state having data "0", the controller 10 calculates the shift voltage dRu1 so that the voltage ARt(-3) is a low voltage. When the data corrected by the soft bit correction on the first page includes a memory cell transistor MT in a hard error state having data "1", the controller 10 calculates the shift voltage dRu2 so that the voltage ARt(+3) is a high voltage. When the data corrected by the soft bit correction on the first page does not include a memory cell transistor MT in a hard error state having data "0", the controller 10 maintains the shift voltage dRu1. Moreover, when no memory cell transistor MT in a hard error state having data "1" is included, the controller 10 maintains the shift voltage dRu2. Then, the controller 10 is configured to use the shift voltage dRu calculated as described above in a soft bit read in a read operation of a second page different from the first page after the read operation of the first page. With the above configuration, it is possible to suppress the occurrence of a memory cell transistor MT in a hard error state during a soft bit read of the second page after the soft bit read of the first page. Therefore, it is possible to suppress the failure of soft bit correction due to the existence of a memory cell transistor MT in a hard error state. Therefore, it is possible to improve the data error correction capability of the memory system 1.

[0134] 2. Modifications The above-described embodiment can be modified in various ways.

[0135] A memory system according to a modified example will be described below.

[0136] 2.1 First modified example In the embodiment, the case where the HE condition is the presence of a memory cell transistor MT in a hard error state has been described, but this is not limited thereto. The HE condition may be set for each state based on at least one of the ratio and the number of memory cell transistors MT in a hard error state. Note that the configuration of the memory system 1 according to the first modification is substantially the same as the configuration of the memory system according to the embodiment, and therefore the description thereof will be omitted. In the following, the operation of the memory system 1 according to the first modification will be mainly described with respect to the points that are different from the operation of the memory system according to the embodiment.

[0137] The HE conditions in the first modification include a first HE condition and a second HE condition, similar to the HE conditions in the embodiment.

[0138] In the first modification, the first HE condition is that, for memory cell transistors MT whose bit value in the channel matrix 122 is "0", the ratio R0HE (percentage) of memory cell transistors MT in a hard error state to the number of failed bits is equal to or greater than a reference ratio R0c0 (R0HE≧R0c0). Here, the number of failed bits is the number of memory cell transistors MT whose bit value in the channel matrix 122 is "0" and which become failed bits when read out with the tracking voltage ARt. Thus, the ratio R0HE is the ratio of the value N0[1] to the sum of the values ​​N0[1], N0[2], N0[3], and N0[4]. The ratio R0c0 is, for example, 5 percent.

[0139] The second HE condition is that the ratio R1HE (percentage) of memory cell transistors MT in a hard error state to the number of failed bits for memory cell transistors MT whose bit value in the channel matrix 122 is "1" is equal to or greater than the reference ratio R1c0 (R1HE≧R1c0). Here, the number of failed bits is the number of memory cell transistors MT whose bit value in the channel matrix 122 is "1" and which become failed bits when read out with the tracking voltage ARt. Thus, the ratio R1HE is the ratio of the value N1[8] to the sum of the values ​​N1[5], N1[6], N1[7], and N1[8]. The ratio R1c0 is, for example, 5 percent.

[0140] When the first HE condition is satisfied, the shift voltage calculation circuit 164 may change the shift voltage dRu1. When the second HE condition is satisfied, the shift voltage calculation circuit 164 may change the shift voltage dRu2.

[0141] In the first modified example, the first HE condition may be, instead of the condition for the ratio R0HE (R0HE≧R0c0), that the number of memory cell transistors MT in a hard error state in which the bit value in the channel matrix 122 is "0" is five or more (5 bits) (N0[1]≧5). In this case, the second HE condition may be, instead of the condition for the ratio R1HE (R1HE≧R1c0), that the number of memory cell transistors MT in a hard error state in which the bit value in the channel matrix 122 is "1" is five or more (5 bits) (N1[8]≧5).

[0142] Furthermore, in the first modification, the first HE condition may be, instead of the above condition, that both the condition for the ratio R0HE (R0HE≧R0c0) and the condition for the number of memory cell transistors MT in a hard error state (N0[1]≧5) are satisfied. In this case, the second HE condition may be that both the condition for the ratio R1HE (R1HE≧R1c0) and the condition for the number of memory cell transistors MT in a hard error state (N1[8]≧5) are satisfied.

[0143] The method of calculating the shift voltages dRu1 and dRu2 can be the same as the method of calculating the shift voltages dRu1 and dRu2 according to the embodiment, and therefore the description thereof will be omitted.

[0144] The first modified example also provides the same effects as the embodiment.

[0145] 2.2 Second variant In the embodiment and the first modified example, the shift voltage dRu is calculated based on the result of fitting the data in the channel matrix 122, but this is not limited to the above. For example, the shift voltage dRu may be determined according to the ratio of memory cell transistors MT in a hard error state. Note that the configuration of the memory system 1 according to the second modified example is substantially the same as the configuration of the memory system according to the embodiment and the first modified example, and therefore the description thereof will be omitted. In the following, the operation of the memory system 1 according to the second modified example will be mainly described with respect to the differences from the operation of the memory system according to the embodiment and the first modified example.

[0146] In the second modified example, when the first HE condition is satisfied, in the processing of S16, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 in accordance with the proportion R0HE of memory cell transistors MT in a hard error state in which the bit value in the channel matrix 122 is “0”.

[0147] More specifically, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 based on, for example, the ratio R0HE and a plurality of reference ratios R0c1 and R0c2 (percentages). When the ratio R0HE is less than the ratio R0c1, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 so that the voltage ARt(-3) is lowered by, for example, the shift voltage dR1 used in S8. That is, the calculated shift voltage dRu1 is a voltage (4×dR1 / 3). When the ratio R0HE is equal to or greater than the ratio R0c1 and less than the ratio R0c2, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 so that the voltage ARt(-3) is lowered by, for example, the voltage (2×dR1) obtained by multiplying the shift voltage dR1 used in S8 by 2. That is, the calculated shift voltage dRu1 is a voltage (5×dR1 / 3). Furthermore, when the ratio R0HE is equal to or greater than the ratio R0c2, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 so that the voltage ARt(-3) is lowered by, for example, the voltage (3×dR1) obtained by multiplying the shift voltage dR1 used in S8 by 3. That is, the calculated shift voltage dRu1 is the voltage (2×dR1). The ratios R0c1 and R0c2 are, for example, 10 percent and 20 percent, respectively. The reference ratio for calculating the shift voltage dRu1 may be one, or three or more.

[0148] Furthermore, when the second HE condition is satisfied, in the process of S16, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 according to the proportion R1HE of memory cell transistors MT in a hard error state in which the bit value in the channel matrix 122 is "1".

[0149] More specifically, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 based on, for example, the ratio R1HE and a plurality of reference ratios R1c1 and R1c2 (percentages). When the ratio R1HE is less than the ratio R1c1, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 so that the voltage ARt(+3) is increased by, for example, the shift voltage dR2 used in S8. That is, the calculated shift voltage dRu2 is a voltage (4×dR2 / 3). When the ratio R1HE is equal to or greater than the ratio R1c1 and less than the ratio R1c2, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 so that the voltage ARt(+3) is increased by, for example, the voltage (2×dR2) obtained by multiplying the shift voltage dR2 used in S8 by 2. That is, the calculated shift voltage dRu2 is a voltage (5×dR2 / 3). Furthermore, when the ratio R1HE is equal to or greater than the ratio R1c2, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 so that the voltage ARt(+3) is higher by, for example, the voltage (3×dR2) obtained by multiplying the shift voltage dR2 used in S8 by 3. That is, the calculated shift voltage dRu2 is the voltage (2×dR2). Note that the ratios R1c1 and R1c2 are, for example, 10 percent and 20 percent, respectively. Furthermore, the reference ratio for calculating the shift voltage dRu2 may be one, or three or more.

[0150] The second modified example also provides the same effects as those of the embodiment and the first modified example.

[0151] 2.3 Third variant In the embodiment, the first modification, and the second modification, the shift voltage dRu is calculated when the soft bit correction is successful, but this is not limited to the above. Even when the soft bit correction is unsuccessful, the controller 10 may be configured to calculate the shift voltage dRu based on the channel matrix 122 when the soft bit correction is unsuccessful. Note that the configuration of the memory system 1 according to the third modification is substantially the same as the configuration of the memory system according to the embodiment, the first modification, and the second modification, and therefore the description thereof will be omitted. In the following, the operation of the memory system 1 according to the third modification will be mainly described with respect to the differences from the operation of the memory system according to the embodiment, the first modification, and the second modification.

[0152] The read operation of the memory system 1 according to the third modification will be described with reference to Fig. 15. Fig. 15 is a flowchart for explaining the flow of correction processing based on soft bit data in the memory system according to the third modification. The overall flow of the read operation in the third modification can be the same as the overall flow of the read operation according to the embodiment, and therefore the description will be omitted.

[0153] In S21, variables i2 and i3 are initialized (i2=i3=0). Then, the process proceeds to S22. The processes of S22 and S24 to S27 can be similar to the processes of S11, S12, S14, and S16 to S18, respectively, except that the variable i2 is used instead of the variable i1.

[0154] In S23, the controller 10 judges whether the soft bit correction for the i2th ECC frame is successful. If the soft bit correction for the i2th ECC frame is successful (S23; Yes), the process proceeds to S24. If the soft bit correction for the i2th ECC frame is unsuccessful (S23; NO), the process proceeds to S28.

[0155] In S28, the controller 10 determines whether the variable i3 is equal to or greater than a preset value. In the example of FIG. 15, the preset value is 2, but the preset value is not limited to this and may be 1 or an integer equal to or greater than 3. If the variable i3 is equal to or greater than the preset value (S28; Yes), the process proceeds to S26. If the variable i3 is less than the preset value (S28; NO), the process proceeds to S29. By the process of S28, the number of times the process of S29 described below is executed is set to a preset value or less.

[0156] In S29, the controller 10 calculates the shift voltages dRu1 and dRu2 based on the channel matrix when the soft bit correction fails. The soft bit correction fails when there are many memory cell transistors MT in a hard error state. The calculation of the shift voltages dRu1 and dRu2 can be the same as the calculation of the shift voltages dRu1 and dRu2 in the embodiment, the first modification, and the second modification. Then, the process proceeds to S30.

[0157] In S30, the controller 10 increments the variable i3 (i3++), and the process then proceeds to S31.

[0158] In S31, the controller 10 performs the same process as in S8 using the shift voltage dRu calculated in S29. Note that in S31, the second hard bit data may be, for example, the same as the second hard bit data in the process of S8. Then, the process proceeds to S22.

[0159] In this manner, the controller 10 repeats the processes of S22 to S31 until the i2th ECC frame becomes the last ECC frame in S26.

[0160] In this manner, the correction process based on the soft bit data in the third modified example is executed.

[0161] In the third modification, if the soft bit correction fails in S23, the generation of soft bit data may be executed multiple times in the read operation for the same page.

[0162] The third modified example also provides the same effects as the embodiment, the first modified example, and the second modified example.

[0163] 3. Other In the above-mentioned embodiment, the first modification, the second modification, and the third modification, the case where the second hard bit data and the soft bit data are acquired by the second hard bit read and the soft bit read in the process of S8 has been shown. However, this is not limited to this. The second hard bit data and the soft bit data may be generated based on the result of the threshold voltage tracking of S4 instead of performing the second hard bit read and the soft bit read. Supplementally, in the threshold voltage tracking, the controller 10 executes a read process using a plurality of read voltages. The plurality of read voltages are set, for example, centered on a threshold voltage (center voltage) estimated to be close to the intersection point of the “Er” state and the “A” state. Then, the controller 10 calculates the tracking voltage ARt using these read results. In the above-mentioned threshold voltage tracking, the number of read voltages used in the threshold voltage tracking is greater than the number of read voltages used to acquire the second hard bit data and the soft bit data. As a result, in another example, the controller 10 may generate second hard bit data and soft bit data using read results from the read voltages closest to each of the multiple read voltages used for threshold voltage tracking, namely, voltages ARt(-3), ARt(-2), ARt(-1), ARt(+1), ARt(+2), and ARt(+3), as well as the tracking voltage ARt.

[0164] In addition, in the above-mentioned embodiment, the first modification, the second modification, and the third modification, the case where the threshold voltage distribution includes two states has been shown, but this is not limited thereto. The memory system 1 may be configured such that the threshold voltage distribution includes, for example, four, eight, or more states depending on the threshold voltages of the multiple memory cell transistors MT. In this case, for example, the shift voltage calculation circuit 164 may be configured to calculate the shift voltage dRdef based on the result of the threshold voltage tracking. More specifically, the shift voltage dRdef may be determined based on the difference in threshold voltage between adjacent states, etc. The calculation of the shift voltage dRdef may be performed in the process of S6.

[0165] Although some embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0166] 1...memory system, 2...host device, 10...controller, 11...processor, 12...built-in memory, 13...buffer memory, 14...host I / F, 15...NAND I / F, 16...ECC circuit, 20...memory device, 21...memory cell array, 22...input / output circuit, 23...logic control circuit, 24...register, 25...sequencer, 26...voltage generation circuit, 27...row decoder module, 28...sense amplifier module, 121...LLR table, 122...channel matrix, 123...shift voltage table, 161...encoding circuit, 162...decoding circuit, 162a...hard decision decoding circuit, 162b...soft decision decoding circuit, 163...channel matrix generation circuit, 164...shift voltage calculation circuit.

Claims

1. a semiconductor memory including a plurality of first memory cells each configured to non-volatilely store data according to a threshold voltage; A controller; Equipped with The controller: performing a first error correction on the first memory cells based on the first hard bit data and the first soft bit data obtained using the first soft bit voltages; determining a second shift voltage different from the first shift voltage based on a first shift voltage which is a potential difference between the plurality of first soft bit voltages when a first condition based on the corrected data corrected by the first error correction is satisfied; The memory system is configured as follows.

2. The semiconductor memory includes: a plurality of second memory cells, each configured to non-volatilely store data according to a threshold voltage; Further including, The controller, after the first error correction, performing a second error correction based on the second hard bit data and the second soft bit data obtained using the second soft bit voltages for the second plurality of memory cells; It is configured as follows: the plurality of second soft bit voltages are determined using the second shift voltage; 2. The memory system of claim 1.

3. the first hard bit data is obtained using a first hard bit voltage that is between a first voltage that is the lowest of the plurality of first soft bit voltages and a second voltage that is the highest of the plurality of first soft bit voltages; the first shift voltage is a potential difference between adjacent voltages among the plurality of first soft bit voltages in a range equal to or less than the first hard bit voltage; The controller: determining a fourth shift voltage different from the third shift voltage based on a third shift voltage that is a potential difference between adjacent voltages among the plurality of first soft bit voltages in a range equal to or greater than the first hard bit voltage when a second condition is satisfied; It is configured as follows:

2. The memory system of claim 1.

4. the second shift voltage is higher than the first shift voltage, and the fourth shift voltage is higher than the third shift voltage; 4. The memory system of claim 3.

5. The controller: When the first error correction is successful, the second shift voltage and the fourth shift voltage can be determined. Consists of 4. The memory system of claim 3.

6. The controller, based on a result of the first error correction, calculating a first quantity of the second memory cells, the threshold voltage of which is less than the first voltage, among a plurality of second memory cells that are included in the plurality of first memory cells and store a first value in the corrected data, and a second quantity of the third memory cells, the threshold voltage of which is equal to or greater than the second voltage, among a plurality of third memory cells that are included in the plurality of first memory cells and store a second value in the corrected data that is different from the first value; 6. The memory system of claim 5.

7. the first condition includes the first quantity being equal to or greater than one; the second condition includes the first quantity being equal to or greater than 1; 7. The memory system of claim 6.

8. The controller: calculating the second shift voltage based on a result of fitting using a quantity of the second memory cells included in each of a plurality of threshold voltage ranges included between the first voltage and the second voltage; calculating the fourth shift voltage based on a result of fitting using a quantity of the third memory cells included in each of a plurality of threshold voltage ranges included between the first voltage and the second voltage; It is configured as follows:

8. The memory system of claim 7.

9. The controller: Calculating the second shift voltage so that the second memory cells are not included in a range below the lowest voltage of the first soft bit voltages when a potential difference between the first hard bit data and adjacent voltages among the first soft bit voltages is changed from the first shift voltage to the second shift voltage, below the first hard bit voltage; calculating the fourth shift voltage so that the third memory cells are not included in a range equal to or higher than the highest voltage of the first soft bit voltages when a potential difference between the first hard bit data and adjacent voltages among the first soft bit voltages is changed from the third shift voltage to the fourth shift voltage at or higher than the first hard bit voltage; It is configured as follows:

9. The memory system of claim 8.

10. the first condition includes a first ratio for the first quantity being equal to or greater than a first reference ratio; the second condition includes a second ratio for the second quantity being equal to or greater than a second reference ratio; 7. The memory system of claim 6.

11. the first percentage being a ratio of the first quantity to a quantity of the second plurality of memory cells having a threshold voltage less than the first hard bit voltage; The second percentage is a ratio of the second quantity to a quantity of the third plurality of memory cells having a threshold voltage equal to or greater than the first hard bit voltage.

11. The memory system of claim 10.

12. the first condition includes the first quantity being equal to or greater than a first reference quantity; the second condition includes the second quantity being equal to or greater than a second reference quantity; 7. The memory system of claim 6.

13. The controller: determining the second shift voltage in response to a magnitude of a first percentage of the first quantity; determining the fourth shift voltage in response to a magnitude of a second percentage of the second quantity; It is configured as follows:

7. The memory system of claim 6.

14. The semiconductor memory includes: a first word line connected to the plurality of first memory cells; a plurality of second memory cells, each configured to store data in a non-volatile manner according to a threshold voltage, connected to the first word line together with the plurality of first memory cells; Further preparation, the first hard bit data and the first soft bit data each include data for the first memory cell and the plurality of second memory cells; 2. The memory system of claim 1.

15. The controller: When the first error correction fails, at least one of a fifth shift voltage different from the first shift voltage and a sixth shift voltage different from the second shift voltage is calculated; performing a second error correction based on second soft bit data obtained using second hard bit data and a plurality of second soft bit voltages determined using at least one of the fifth shift voltage and the sixth shift voltage for the plurality of first memory cells; It is configured as follows:

6. The memory system of claim 5.

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