Semiconductor storage device and manufacturing method thereof

Abstract

To provide a semiconductor storage device capable of suppressing a decrease in a cell current flowing through a memory cell, and the manufacturing method thereof.SOLUTION: A semiconductor storage device according to an embodiment comprises a laminate where an electrode layer and a first insulation layer are alternately stacked in a first direction. A semiconductor layer extends along the first direction in the laminate. A second insulation layer is provided between the laminate and the semiconductor layer. A third insulation layer is provided between the laminate and the second insulation layer. A first thickness of the third insulation layer between the electrode layer and the second insulation layer is greater than a second thickness of the third insulation layer between the first insulation layer and the second insulation layer. The third insulation layer inclines in the first direction in a step region changing from the first thickness to the second thickness. A fourth insulation layer is provided between the electrode layer and the third insulation layer. A seventh insulation layer is provided between the electrode layer and the first insulation layer and between the electrode layer and the fourth insulation layer.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device and a manufacturing method thereof. [Background technology]

[0002] A NAND flash memory in which memory cells are arranged three-dimensionally is known as a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-097675 A [Patent Document 2] International Patent Application Publication No. 2002 / 061839 [Patent Document 3] JP 2013-065638 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device capable of suppressing a decrease in a cell current flowing through a memory cell and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] The semiconductor memory device according to this embodiment includes a stack in which electrode layers and first insulating layers are alternately stacked in a first direction. The semiconductor layer extends along the first direction within the stack. The second insulating layer is provided between the stack and the semiconductor layer. The third insulating layer is provided between the stack and the second insulating layer. A first thickness of the third insulating layer between the electrode layer and the second insulating layer is thicker than a second thickness of the third insulating layer between the first insulating layer and the second insulating layer. The third insulating layer is inclined with respect to the first direction in a step region where the first thickness changes to the second thickness. The fourth insulating layer is provided between the electrode layer and the third insulating layer. The seventh insulating layer is provided between the electrode layer and the first insulating layer and between the electrode layer and the fourth insulating layer. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. [Diagram 3] FIG. 1 is a schematic cross-sectional view illustrating a memory cell array. [Figure 4] FIG. 1 is a schematic cross-sectional view illustrating a memory cell array. [Diagram 5] FIG. 1 is a schematic cross-sectional view illustrating a memory cell array. [Figure 6] FIG. 1 is a schematic cross-sectional view illustrating a memory cell array. [Figure 7] 3A to 3C are cross-sectional views showing an example of a method for manufacturing the array chip according to the first embodiment. [Figure 8] 8 is a cross-sectional view showing the method for manufacturing the array chip, subsequent to FIG. 7. [Figure 9] 9 is a cross-sectional view showing the method for manufacturing the array chip, subsequent to FIG. 8. [Figure 10] 10 is a cross-sectional view showing the method for manufacturing the array chip, subsequent to FIG. 9. [Figure 11] 11 is a cross-sectional view showing the method for manufacturing the array chip, subsequent to FIG. 10. [Figure 12] 12 is a cross-sectional view showing the method for manufacturing the array chip, subsequent to FIG. 11. [Figure 13] 13 is a cross-sectional view showing the method for manufacturing the array chip, subsequent to FIG. 12. [Figure 14] 14 is a cross-sectional view showing the method for manufacturing the array chip, subsequent to FIG. 13. [Figure 15] 15 is a cross-sectional view showing the method for manufacturing the array chip, subsequent to FIG. 14. [Figure 16] 10A to 10C are cross-sectional views showing an example of a method for manufacturing an array chip according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual. In the specification and the drawings, the same elements are given the same reference numerals.

[0008] (First embodiment) 1 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 1 according to the first embodiment. Hereinafter, the stacking direction of the stacked body 20 is defined as the Z direction. A direction that intersects with, for example, is perpendicular to, the Z direction is defined as the Y direction. A direction that intersects with, for example, is perpendicular to each of the Z direction and the Y direction is defined as the X direction. In this specification, the Z direction is an example of the first direction. The X direction or the Y direction is an example of the second direction.

[0009] The semiconductor memory device 1 includes an array chip 2 having a memory cell array, and a CMOS chip 3 having a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded together at a bonding surface B1, and are electrically connected to each other via wiring joined at the bonding surfaces. Fig. 1 shows a state in which the array chip 2 is mounted on the CMOS chip 3.

[0010] The CMOS chip 3 includes a substrate 30, a transistor 31, a via 32, wirings 33 and 34, and an interlayer insulating layer 35.

[0011] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an NMOS or PMOS transistor provided on the substrate 30. The transistor 31 constitutes, for example, a CMOS circuit that controls a memory cell array of the array chip 2. The multiple transistors 31 constitute logic circuits such as a sense amplifier, a row decoder, a column decoder, etc. Semiconductor elements such as resistor elements and capacitor elements other than the transistors 31 may be formed on the substrate 30.

[0012] The via 32 electrically connects the transistor 31 and the wiring 33, or the wiring 33 and the wiring 34. The wirings 33 and 34 form a multi-layer wiring structure in the interlayer insulating layer 35. The wiring 34 is embedded in the interlayer insulating layer 35 and is exposed almost flush with the surface of the interlayer insulating layer 35. The wirings 33 and 34 are electrically connected to the transistor 31 and the like. The via 32 and the wirings 33 and 34 are made of low-resistance metals such as copper and tungsten. The interlayer insulating layer 35 covers and protects the transistor 31, the via 32, and the wirings 33 and 34. The interlayer insulating layer 35 is made of an insulating layer such as a silicon oxide film containing silicon and oxygen.

[0013] The array chip 2 includes a stack 20, columns CL, slits ST (LI), source layers BSL, a metal layer 40, contact plugs CCw, a contact plug 29, and bonding pads 50.

[0014] The stack 20 is provided above the transistor 31 and is located in the Z direction with respect to the substrate 30. The stack 20 is configured by alternately stacking a plurality of electrode layers 21 and a plurality of insulating layers 22 along the Z direction. The stack 20 configures a memory cell array. The electrode layer 21 is made of a conductive metal such as tungsten. The insulating layer 22 is made of an insulating layer such as a silicon oxide film containing silicon and oxygen. The insulating layer 22 insulates the electrode layers 21 from each other. That is, the plurality of electrode layers 21 are stacked in an insulated state from each other. The number of stacked electrode layers 21 and insulating layers 22 is arbitrary. The insulating layer 22 may be, for example, a porous insulating layer or an air gap.

[0015] One or more electrode layers 21 at the top and bottom ends of the stack 20 in the Z direction function as a source side select gate SGS and a drain side select gate SGD, respectively. The electrode layer 21 between the source side select gate SGS and the drain side select gate SGD functions as a word line WL. The word line WL is the gate electrode of the memory cell MC. The drain side select gate SGD is the gate electrode of the drain side select transistor. The source side select gate SGS is provided in an upper region of the stack 20. The drain side select gate SGD is provided in a lower region of the stack 20. The upper region refers to the region of the stack 20 closer to the CMOS chip 3, and the lower region refers to the region of the stack 20 farther from the CMOS chip 3 (closer to the metal layer 40).

[0016] The semiconductor memory device 1 has a plurality of memory cells MC connected in series between a source-side select transistor and a drain-side select transistor. A structure in which the source-side select transistor, the memory cells MC, and the drain-side select transistor are connected in series is called a "memory string" or a "NAND string." The memory string is connected to a bit line BL, for example, through a via 28. The bit line BL is a wiring 23 provided below the stack 20 and extending in the X-direction.

[0017] A plurality of pillars CL are provided in the stack 20. The pillars CL extend in the stacking direction (Z direction) of the stack 20 so as to penetrate the stack 20, and are provided from a via 28 connected to the bit line BL to the source layer BSL. The internal structure of the pillars CL will be described later. In this embodiment, since the pillars CL have a high aspect ratio, they are formed in two stages in the Z direction. However, there is no problem if the pillars CL are in one stage or three or more stages.

[0018] Although not shown in FIG. 1, a plurality of slits ST (see FIG. 2) are provided in the stack 20. The slits ST extend in the Y direction and penetrate the stack 20 in the stacking direction (Z direction) of the stack 20. The slits ST are filled with an insulating material such as a silicon oxide film containing silicon and oxygen, and the insulating material is configured in a plate shape. The slits ST electrically separate the electrode layers 21 of the stack 20. Alternatively, the inner wall of the slits ST may be covered with an insulating layer such as a silicon oxide film, and a conductive material may be further embedded inside the insulating layer. In this case, the conductive material also functions as a source wiring that reaches the source layer BSL.

[0019] A source layer BSL is provided on the stacked body 20. The source layer BSL is an example of a first semiconductor layer. The source layer BSL is provided corresponding to the stacked body 20. The source layer BSL has a first face F1 and a second face F2 opposite to the first face F1. The stacked body 20 (memory cell array) is provided on the first face F1 side of the source layer BSL, and a metal layer 40 is provided on the second face F2 side. The source layer BSL is commonly connected to one end of the plurality of pillars CL, and applies a common source potential to the plurality of pillars CL in the same memory cell array 2m. That is, the source layer BSL functions as a common source electrode of the memory cell array 2m. For the source layer BSL, a conductive material such as doped polysilicon is used. For the metal layer 40, a metal material having a lower resistance than the source layer BSL, such as copper, aluminum, or tungsten, is used. Note that 2s is a step portion of the electrode layer 21 provided to connect a contact to each electrode layer 21. The staircase portion 2s will be described later with reference to FIG.

[0020] On the other hand, a bonding pad 50 is provided on the stacked body 20 in a region where the source layer BSL is not provided. The bonding pad 50 is connected to a metal wire or the like (not shown) and receives a power supply or a signal from outside the semiconductor memory device 1. The bonding pad 50 is provided so as to be connected to one end of the contact plug 29 in the Z direction. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact plug 29, the wiring 24, and the wiring 34. Therefore, the external power supply supplied from the bonding pad 50 is supplied to the transistor 31. Alternatively, a signal is supplied to the transistor 31 or the memory cell array 2m via the bonding pad 50.

[0021] The contact plugs CCw are provided on the periphery of the laminate 20 and extend in the Z direction within the interlayer insulating layer 25. The contact plugs CCw are electrically connected between the electrode layers 21 (word lines WL) and the wiring 24. The contact plugs CCw are provided in step portions 2s formed in a step-like shape at the end of the laminate 20 and are electrically connected to each electrode layer 21. The contact plugs CCw are provided to transmit a word line voltage from the CMOS chip 3 to each electrode layer 21. The contact plugs CCw are made of a low-resistance metal such as copper or tungsten.

[0022] The contact plug 29 is provided on the periphery of the laminate 20, and extends in the Z direction through the interlayer insulating layer 25. The contact plug 29 is a contact plug provided from the wiring 24 to the bonding pad 50.

[0023] The contact plug 29 is electrically connected between the bonding pad 50 and the wiring 24. The contact plug 29 is used to supply a power supply voltage or a signal from the bonding pad 50 to the array chip 2 or the CMOS chip 3. For example, a low-resistance metal such as copper or tungsten is used for the contact plug 29. The power supply voltage may be a high-level power supply voltage VDD or a low-level reference voltage (for example, a ground voltage) VSS. The signal may be an external control signal or write data or read data.

[0024] In this embodiment, the array chip 2 and the CMOS chip 3 are formed separately and are bonded together at a bonding surface B1. Therefore, the array chip 2 does not include a transistor 31. The CMOS chip 3 does not include a stacked body 20 (memory cell array). The transistor 31 and the stacked body 20 are both on the first surface F1 side of the source layer BSL. The transistor 31 is on the opposite side to the second surface F2 of the source layer BSL on which the metal layer 40 is located.

[0025] Below the stack 20, a via 28, a wiring 23, and a wiring 24 are provided. The wirings 23 and 24 are embedded in an interlayer insulating layer 25. The wiring 24 is exposed to the surface of the interlayer insulating layer 25 in a substantially flush manner. The wirings 23 and 24 are electrically connected to the semiconductor body 210 of the columnar body CL, etc. The via 28, the wiring 23, and the wiring 24 are made of a low-resistance metal such as copper or tungsten. The interlayer insulating layer 25 covers and protects the stack 20, the via 28, the wiring 23, and the wiring 24. The interlayer insulating layer 25 is made of an insulating layer such as a silicon oxide film containing silicon and oxygen.

[0026] The interlayer insulating layer 25 and the interlayer insulating layer 35 are bonded to each other at a bonding surface B1, and the wiring 24 and the wiring 34 are also bonded to each other at a substantially flush surface B1. As a result, the array chip 2 and the CMOS chip 3 are electrically connected to each other via the wiring 24 and the wiring 34.

[0027] FIG. 2 is a schematic plan view showing the stack 20. The stack 20 includes a staircase portion 2s and a memory cell array 2m. The staircase portion 2s is provided at an end of the stack 20. The memory cell array 2m is sandwiched or surrounded by the staircase portion 2s. The slit ST(LI) is provided from the staircase portion 2s at one end of the stack 20 through the memory cell array 2m to the staircase portion 2s at the other end of the stack 20. The slit SHE is provided at least in the memory cell array 2m. The slit SHE is shallower than the slit ST(LI) and extends approximately parallel to the slit ST(LI). The slit SHE is provided to electrically separate the electrode layer 21 for each drain side selection gate SGD. Alternatively, the slit ST may be a source wiring LI that is electrically separated from the electrode layer 21 of the stack 20 and electrically connected to the source layer BSL. That is, the slit ST may be a source wiring LI that is electrically isolated from the electrode layer 21 of the stack 20 that constitutes the memory cell array and is electrically connected to the source layer BSL.

[0028] The portion of the stack 20 sandwiched between the two slits ST shown in FIG. 2 is called a block. The block constitutes, for example, the minimum unit of data erasure. The slit SHE is provided within the block. The stack 20 between the slit ST and the slit SHE is called a finger. The drain side selection gate SGD is divided into each finger. Therefore, when writing and reading data, one finger in the block can be selected by the drain side selection gate SGD.

[0029] Each of Fig. 3 to Fig. 6 is a schematic cross-sectional view illustrating a memory cell array. Fig. 4 shows a cross-section taken along line 4-4 in Fig. 3, and Fig. 5 shows a cross-section taken along line 5-5 in Fig. 3. Fig. 6 shows an enlarged cross-section of a portion enclosed by a dashed line 6 in Fig. 3.

[0030] As shown in FIG. 3, each of the multiple pillars CL is provided in a memory hole MH provided in the stack 20. Each pillar CL penetrates the stack 20 from the upper end of the stack 20 along the Z direction and is provided in the stack 20 and the source layer BSL. Each of the multiple pillars CL includes a semiconductor body 210, a memory film 220, and a core layer 230. The pillar CL includes a core layer 230 provided in the center thereof, a semiconductor body (semiconductor layer) 210 provided around the core layer 230, and a memory film 220 provided around the semiconductor body 210. The semiconductor body 210 extends in the stacking direction (Z direction) in the stack 20. The semiconductor body 210 is electrically connected to the source layer BSL. The memory film 220 is provided between the semiconductor body 210 and the electrode layer 21, and has a charge trapping layer. A plurality of pillars CL selected one by one from each finger are commonly connected to one bit line BL through the via 28 in Fig. 1. Each of the pillars CL is provided, for example, in the region of the memory cell array 2m.

[0031] As shown in FIG. 3 and FIG. 6, a block insulating layer 21a and a barrier film 21b constituting a part of the memory film 220 are provided between the electrode layer 21 and the insulating layer 22 and between the electrode layer 21 and the block insulating layer 224. The block insulating layer 21a as a seventh insulating layer is provided between the electrode layer 21 and the insulating layer 22 and between the electrode layer 21 and the block insulating layer 224. The block insulating layer 21a is, for example, a silicon oxide or a metal oxide. One example of a metal oxide is an aluminum oxide containing aluminum and oxygen. For example, when the electrode layer 21 is tungsten, the barrier film 21b is, for example, a laminated film of titanium nitride and titanium. The block insulating layer 21a suppresses back tunneling of charges from the electrode layer 21 to the memory film 220. The barrier film 21b is a conductive material that improves adhesion between the electrode layer 21 and the block insulating layer 21a. For example, a conductive metal compound such as a laminated film of titanium nitride and titanium is used for the barrier film 21b.

[0032] 4 and 5, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. As shown in FIG. 4, a core layer 230 is located at the center of the memory hole MH, and a semiconductor body 210 and a memory film 220 are provided around the core layer 230.

[0033] The semiconductor body 210 has, for example, a cylindrical shape having a bottom. The semiconductor body 210 is made of, for example, polysilicon. The semiconductor body 210 is, for example, undoped silicon. The semiconductor body 210 may also be p-type silicon. The semiconductor body 210 becomes the channels of the drain side select transistor STD, the memory cell MC, and the source side select transistor STS. One end of the multiple semiconductor bodies 210 in the same memory cell array 2m is electrically connected in common to the source layer BSL.

[0034] The memory film 220 is provided between the inner wall of the memory hole MH and the semiconductor body 210. The memory film 220 has, for example, a cylindrical shape. The memory cells MC have a storage area between the semiconductor body 210 and the electrode layer 21 that serves as the word line WL, and are stacked in the Z direction. The memory film 220 includes, for example, block insulating layers 21a and 224, cover insulating layers 221a and 221b, a charge trapping film 222, and a tunnel insulating layer 223. Each of the semiconductor body 210, the charge trapping film 222, and the tunnel insulating layer 223 extends in the Z direction.

[0035] As shown in Fig. 5 and Fig. 6, cover insulating layers 221a and 221b as the fifth and sixth insulating layers are provided between the insulating layer 22 and the charge trapping film 222. As shown in Fig. 5, in the memory hole MH, the cover insulating layer 221a is provided around the charge trapping film 222. The cover insulating layer 221b is provided around the cover insulating layer 221a. For the cover insulating layers 221a and 221b, an insulating layer such as silicon oxide containing silicon and oxygen is used. The cover insulating layers 221a and 221b protect the charge trapping film 222 from being etched when a sacrificial layer (not shown) is replaced with the electrode layer 21 (replacement step).

[0036] 4 and 6, a block insulating layer 224 serving as a fourth insulating layer is provided between the electrode layer 21 and the charge trapping film 222. The block insulating layer 224, together with the block insulating layer 21a, suppresses back tunneling of charges from the electrode layer 21 to the memory film 220 side.

[0037] The charge trapping film 222 as the third insulating layer is provided between the stack 20 and the tunnel insulating layer 223. The charge trapping film 222 is provided between the cover insulating layers 221a, 221b and the tunnel insulating layer 223, and between the block insulating layer 224 and the tunnel insulating layer 223. As shown in FIG. 6, the thickness (first thickness) T1 of the charge trapping film 222 between the electrode layer 21 and the tunnel insulating layer 223 is thicker than the thickness (second thickness) T2 of the charge trapping film 222 between the insulating layer 22 and the tunnel insulating layer 223. In the step region STP where the thickness of the charge trapping film 222 changes, the charge trapping film 222 is constricted in the radial direction (Y direction and X direction) of the memory hole MH. The sidewalls of the step region STP of the charge trapping film 222 are inclined with respect to the Z direction, the Y direction, and the X direction, and are formed in a tapered shape. The taper means that the charge trapping film 222 is inclined with respect to any one of the Z direction, the X direction, and the Y direction. Also, the taper is not necessarily flat, but may include a curved surface.

[0038] As shown in FIG. 6, in the step region STP where the thickness of the charge trapping film 222 changes, the cover insulating layer 221b is embedded in the constricted portion (recess) of the charge trapping film 222. Therefore, the total thickness T3 in the Y direction of the cover insulating layers 221a and 221b is thicker than the thickness T4 in the Y direction of the block insulating layer 224. As a result, the side surface F222 of the charge trapping film 222 on the center side of the memory hole MH is almost flat along the side wall of the memory hole MH. That is, the side surface of the charge trapping film 222 on the center side of the memory hole MH is not recessed in the Y direction and the X direction, and does not protrude. Accordingly, the semiconductor body 210 and the tunnel insulating layer 223 are also almost flat along the side wall of the memory hole MH, and are not recessed in the Y direction and the X direction, and do not protrude.

[0039] Since the cover insulating layer 221b is embedded in the narrowed portion of the charge trapping film 222, both side surfaces of the cover insulating layer 221b in the Z direction are formed in a tapered shape inclined in the Z direction, Y direction, and X direction to correspond to the side walls of the step region STP of the charge trapping film 222.

[0040] The cover insulating layer 221a is provided between the cover insulating layer 221b and the insulating layer 22, and is provided between adjacent block insulating layers 224 in the Z direction. Both side walls in the Z direction of the block insulating layer 224 are also formed in a tapered shape inclined with respect to the Z direction, the Y direction, and the X direction. Accordingly, both side surfaces of the cover insulating layer 221a in the Z direction are also formed in a tapered shape inclined with respect to the Z direction, the Y direction, and the X direction in correspondence with the side walls of the block insulating layer 224.

[0041] The block insulating layer 224 and the cover insulating layer 221a may be made of, for example, a silicon oxide film. For example, the film density (g / cm 3 ) is lower than the film density of the cover insulating layer 221b.

[0042] The charge trapping film 222 is, for example, an insulating layer such as silicon nitride containing silicon and nitrogen. The charge trapping film 222 has trap sites that trap charges within the film. A relatively thick portion of the charge trapping film 222 sandwiched between the electrode layer 21, which becomes the word line WL, and the semiconductor body 210 constitutes the storage region of the memory cell MC as a charge trapping portion. The threshold voltage of the memory cell MC changes depending on the presence or absence of charge in the charge trapping portion, or the amount of charge trapped in the charge trapping portion. This allows the memory cell MC to hold information.

[0043] The tunnel insulating layer 223 as the second insulating layer is provided between the stack 20 and the semiconductor body 210. More specifically, the tunnel insulating layer 223 is provided between the semiconductor body 210 and the charge trapping film 222. For example, an insulating layer such as a silicon oxide film containing silicon and oxygen or a silicon oxynitride film containing silicon oxide and silicon nitride is used for the tunnel insulating layer 223. The tunnel insulating layer 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 to the charge trapping film 222 (write operation), and when holes are injected from the semiconductor body 210 to the charge trapping film 222 (erase operation), the electrons and holes pass through (tunnel) the potential barrier of the tunnel insulating layer 223.

[0044] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The core layer 230 has, for example, a columnar shape. The core layer 230 is made of, for example, an insulating layer such as silicon oxide containing silicon and oxygen.

[0045] According to this embodiment, the thickness T2 of the charge trapping film 222 is relatively thin between the insulating layer 22 and the tunnel insulating layer 223, and has a constricted portion (recess). The cover insulating layers 221a, 221b are embedded in the constricted portion (recess) of the charge trapping film 222 and are formed relatively thick. As a result, the charge stored in the charge trapping film 222 facing the electrode layer 21 in the Y direction is separated (pseudo-separated) to a certain extent by the constricted portion in the Z direction. In other words, the charge stored in the charge trapping film 222 corresponding to each memory cell MC is made difficult to move to other memory cells MC adjacent in the Z direction by the constricted portion, and data degradation can be suppressed.

[0046] On the other hand, the thickness T1 of the charge trapping film 222 is relatively thick between the electrode layer 21 and the tunnel insulating layer 223, and the thickness of the block insulating layer 224 is accordingly thin. Therefore, the thickness of the block insulating layers 21a, 224 and the charge trapping film 222 between the electrode layer 21 and the tunnel insulating layer 223 can be made substantially equal to the thickness of the cover insulating layers 221a, 221b and the charge trapping film 222 between the insulating layer 22 and the tunnel insulating layer 223. This allows the side surface F222 of the charge trapping film 222 to be substantially flattened along the inner wall of the memory hole MH. As a result, the tunnel insulating layer 223 and the semiconductor body 210 deposited on the side surface F222 of the charge trapping film 222 are also formed substantially flat and conformal along the inner wall of the memory hole MH. That is, the tunnel insulating layer 223 and the semiconductor body 210 are not recessed in the X direction or the Y direction, and are not protruding. Therefore, the resistance of the semiconductor body 210 hardly changes depending on the position in the Z direction, and a local decrease in the cell current flowing through the memory cell MC can be suppressed.

[0047] Furthermore, since the thickness T1 of the charge trapping film 222 between the electrode layer 21 and the tunnel insulating layer 223 is relatively large, the charge trapping film 222 corresponding to each memory cell MC can store a sufficient amount of charge.

[0048] Furthermore, not only the block insulating layer 21a but also the block insulating layer 224 is provided between the electrode layer 21 and the charge trapping film 222. Therefore, the charge stored in the charge trapping film 222 is less likely to tunnel to the electrode layer 21, and back tunneling of the charge from the electrode layer 21 to the memory film 220 can be suppressed.

[0049] Next, a method for manufacturing the semiconductor memory device 1 according to this embodiment will be described.

[0050] 7 to 15 are cross-sectional views showing an example of a method for manufacturing the array chip 2 according to the first embodiment.

[0051] First, as shown in FIG. 7, insulating layers 22 and sacrificial layers 121 are alternately stacked in the Z direction on a semiconductor substrate 10 using, for example, a chemical vapor deposition (CVD) method. This forms a stack 20 stacked in the Z direction. The insulating layers 22 are, for example, silicon oxide layers. The sacrificial layers 121 are, for example, insulating layers such as silicon nitride layers containing silicon and nitrogen. The sacrificial layers 121 are replaced with the material of the electrode layers 21 in a later process. The insulating layers 22 become interlayer insulating layers between the electrode layers 21.

[0052] 8, for example, a memory hole MH is formed in the stacked body 20 extending along the Z direction by using lithography and RIE (Reactive Ion Etching). The semiconductor substrate 10 is omitted in the figures from FIG. 8 onward. The memory hole MH penetrates the stacked body 20 which constitutes the insulating layer 22 and the sacrificial layer 121.

[0053] Next, as shown in FIG. 9, a sacrificial layer 121a is formed on the sacrificial layer 121 exposed on the inner wall of the memory hole MH by using a selective growth method. The sacrificial layer 121a is, for example, an insulating layer such as a silicon nitride film containing silicon and nitrogen. The sacrificial layer 121a is selectively formed on the exposed surface of the sacrificial layer 121 without being formed on the insulating layer 22. For example, a gas containing halogen, such as SiHX3, SiX4 (X=F, Cl, Br, I), etc., is flowed into the memory hole MH at a low temperature of about 450° C., and selectively adsorbed on the exposed surface of the insulating layer 22. This prevents the growth of Si precursors, such as dichlorosilane SiH2Cl2 and hexachlorodisilane Si2Cl6, on the insulating layer 22, prevents the formation of silicon nitride on the insulating layer 22, and causes these precursors to be adsorbed on the exposed surface of the sacrificial layer 121. This selectively deposits the sacrificial layer 121a on the exposed surface of the sacrificial layer 121. At this time, since the sacrificial layer 121a is formed isotropically, the sacrificial layer 121a has inclinations on both side surfaces in the Z direction.

[0054] Next, as shown in FIG. 10, a cover insulating layer 221a is formed on the insulating layer 22 exposed on the inner wall of the memory hole MH by using a selective growth method. The cover insulating layer 221a is, for example, an insulating layer such as a silicon oxide film containing silicon and oxygen. The cover insulating layer 221a is selectively formed on the exposed surface of the insulating layer 22 without being formed on the sacrificial layer 121a. For example, an inhibitor that prevents the growth of a Si precursor to the sacrificial layer 121a, such as a gas containing Si, for example, dichlorosilane SiH2Cl2 or hexachlorodisilane Si2Cl6, is flowed into the memory hole MH and selectively adsorbed on the exposed surface of the sacrificial layer 121a. This prevents the formation of a silicon oxide film on the sacrificial layer 121a and causes the insulating layer 22 to adsorb these precursors. This selectively deposits the cover insulating layer 22 on the insulating layer 22. At this time, the cover insulating layer 221a is formed so as to fill the gap between the sacrificial layers 121a adjacent in the Z direction. Therefore, the cover insulating layer 221a is formed in a tapered shape with an inclination on both side surfaces in the Z direction along the side surface of the sacrificial layer 121a. Moreover, the cover insulating layer 221a and the sacrificial layer 121a are formed almost flat along the inside of the memory hole MH.

[0055] Next, as shown in FIG. 11, in the memory hole MH, the materials of the cover insulating layer 221b, the charge trapping film 222, the tunnel insulating layer 223, and the semiconductor body 210 are formed in this order on the cover insulating layer 221a and the sacrificial layer 121a. The materials of the cover insulating layer 221b, the charge trapping film 222, the tunnel insulating layer 223, and the semiconductor body 210 are deposited, for example, by ALD (Atomic Layer Deposition) or CVD. The cover insulating layer 221b and the tunnel insulating layer 223 are insulating layers such as a silicon oxide film containing silicon and oxygen. The tunnel insulating layer 223 may be a silicon oxynitride layer containing silicon, oxygen, and nitrogen. The semiconductor body 210 is a semiconductor layer containing a semiconductor such as polysilicon. The charge trapping film 222 is an insulating layer such as a silicon nitride film containing silicon and nitrogen. At this time, since the cover insulating layer 221a and the sacrificial layer 121a are approximately flat along the inside of the memory hole MH, the materials of the cover insulating layer 221b, the charge trapping film 222, the tunnel insulating layer 223 and the semiconductor body 210 are also formed on the cover insulating layer 221a and the sacrificial layer 121a so as to be approximately flat along the inside of the memory hole MH and have an approximately uniform film thickness.

[0056] Next, as shown in Fig. 12, the sacrificial layers 121, 121a are selectively etched and removed using a solution or gas containing phosphoric acid. This exposes the cover insulating layer 221b in the space left after the sacrificial layers 121, 121a are removed. The cover insulating layer 221b functions as an etching stopper, and the charge trapping film 222 is protected. Also, the insulating layer 22 and the cover insulating layer 221a are left behind.

[0057] Next, the cover insulating layer 221b is isotropically etched using a solution or gas containing hydrofluoric acid. As a result, the cover insulating layer 221b is selectively removed, and the charge trapping film 222 is exposed in the space left after the removal of the sacrificial layers 121 and 121a. At this time, a part of the cover insulating layer 221b is left between the cover insulating layer 221a and the charge trapping film 222. In addition, since the cover insulating layer 221b is isotropically etched, it has a slope on the side surface in the Z direction.

[0058] Next, as shown in FIG. 13, a material of the charge trapping film 222 (for example, an insulating layer such as a silicon nitride film containing silicon and nitrogen) is further deposited on the surface of the charge trapping film 222 exposed to the space. At this time, the material of the charge trapping film 222 is additionally deposited on the surface of the charge trapping film 222 by using the selective growth method described with reference to FIG. 9. The charge trapping film 222 is formed so as to fill in the gap between the cover insulating layers 221b adjacent in the Z direction. Thus, the charge trapping film 222 grows along the side surface of the tapered cover insulating layer 221b. Thus, the charge trapping film 222 has an inclination on both side surfaces in the Z direction and is formed in a tapered shape. In addition, in the Y direction, the thickness of the charge trapping film 222 between the space and the tunnel insulating layer 223 is thicker than the thickness of the charge trapping film 222 between the insulating layer 22 and the tunnel insulating layer 223. In the step region STP where the thickness of the charge trapping film 222 changes, the charge trapping film 222 has a taper. On the other hand, the cover insulating layer 221b has a taper on the side surface corresponding to the step region STP.

[0059] 14, a material for the block insulating layer 224 (for example, an insulating layer such as a silicon oxide film containing silicon and oxygen) is deposited on the surface of the cover insulating layer 221b exposed in the space. At this time, the material for the block insulating layer 224 is additionally deposited on the surface of the charge trapping film 222 by using the selective growth method described with reference to FIG. 10. Note that the film density (g / cm) of each of the block insulating layer 224 and the cover insulating layer 221a is 3 ) is lower than the film density of the cover insulating layer 221b.

[0060] The block insulating layer 224 is formed to fill the gap between the cover insulating layers 221a adjacent in the Z direction. Therefore, the block insulating layer 224 grows along the side surface of the tapered cover insulating layer 221a, and is formed in a tapered shape with an inclination on both side surfaces in the Z direction. The thickness of the cover insulating layers 221a and 221b in the Y direction is thicker than that of the block insulating layer 224.

[0061] 15, a material for block insulating layer 21a (e.g., an insulating layer such as an aluminum oxide film containing aluminum and oxygen) is deposited on the surfaces of block insulating layer 224 and insulating layer 22 exposed to the space. Next, a material for barrier film 21b (e.g., a laminated film of titanium nitride and titanium, or a single layer film) is deposited on the surface of block insulating layer 21a exposed to the space.

[0062] 6, the material of the electrode layer 21 (for example, tungsten) is embedded inside the block insulating layer 21a in the space. The sacrificial layer 121 is replaced with the electrode layer 21 by this replacement process.

[0063] Thereafter, vias 28, wiring 24, etc. are formed to complete the array chip 2. A CMOS chip 3 is formed separately from the array chip 2. The array chip 2 and the CMOS chip 3 are bonded together at a bonding surface B1. Furthermore, a metal layer 40, a bonding pad 50, etc. are formed to complete the semiconductor memory device 1.

[0064] As described above, according to the embodiment, the charge trapping film 222 is selectively grown additionally between the electrode layer 21 and the tunnel insulating layer 223 to make it relatively thick. Also, the cover insulating layer 221a is selectively grown between the insulating layer 22 and the tunnel insulating layer 223 to form the cover insulating layers 221a, 221b relatively thick. This allows the charge trapping film 222 corresponding to each memory cell MC to be formed thick, and a constricted portion is formed in the charge trapping film 222 between the memory cells MC. This makes it difficult for the charge stored in the charge trapping film 222 corresponding to each memory cell MC to move to another memory cell MC adjacent in the Z direction due to the constricted portion. That is, the memory cells MC adjacent in the Z direction are pseudo-isolated. As a result, data degradation can be suppressed.

[0065] In addition, the charge trapping film 222 is selectively grown between the electrode layer 21 and the tunnel insulating layer 223 to be relatively thick, and the cover insulating layer 221a is selectively grown between the insulating layer 22 and the tunnel insulating layer 223 to form the cover insulating layers 221a and 221b to be relatively thick. This allows the side surface F222 of the charge trapping film 222 to be substantially flattened along the inner wall of the memory hole MH. As a result, the tunnel insulating layer 223 and the semiconductor body 210 deposited on the side surface F222 of the charge trapping film 222 are also formed conformally along the inner wall of the memory hole MH. This makes it possible to suppress a local decrease in the cell current flowing through the memory cell MC.

[0066] Second embodiment 16 is a cross-sectional view showing an example of a manufacturing method for the array chip 2 according to the second embodiment. The second embodiment differs from the first embodiment in the method of forming the cover insulating layer 221a.

[0067] After the steps described with reference to FIGS. 7 to 9, as shown in FIG. 16, the material of the cover insulating layer 221a is deposited on the entire inner wall of the memory hole MH by using the ALD method or the CVD method.

[0068] Next, the material of the cover insulating layer 221a is isotropically etched back using a wet etching method or a CDE (Chemical Dry Etching) method. This exposes the sacrificial layer 121a on the inner wall of the memory hole MH, and selectively leaves the cover insulating layer 221a on the insulating layer 22. In this manner, the cover insulating layer 221a shown in FIG. 10 may be formed.

[0069] Thereafter, the steps described with reference to FIGS. 11 to 15 are carried out to obtain the structure shown in FIG.

[0070] Other manufacturing steps and configurations of the second embodiment may be the same as those of the first embodiment, and therefore the second embodiment can achieve the same effects as the first embodiment.

[0071] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0072] 1. Semiconductor memory device 2. Array chip 20 Laminate 21 Electrode layer 21b Barrier film 22 Insulating layer CL columnar body MH Memory Hole 210 Semiconductor Body 220 Memory Film 230 Core Layer 21a, 224 Block insulation layer 221a, 221b Cover insulating layer 222 Charge trapping film 223 Tunnel Insulation Layer

Claims

1. a laminate in which electrode layers and first insulating layers are alternately laminated in a first direction; a semiconductor layer extending along the first direction within the stack; A second insulating layer provided between the laminate and the semiconductor layer; a third insulating layer provided between the laminate and the second insulating layer, a first thickness of the third insulating layer between the electrode layer and the second insulating layer being thicker than a second thickness of the third insulating layer between the first insulating layer and the second insulating layer, and the third insulating layer being inclined with respect to the first direction in a step region where the first thickness changes to the second thickness; a fourth insulating layer provided between the electrode layer and the third insulating layer; a seventh insulating layer provided between the electrode layer and the first insulating layer and between the electrode layer and the fourth insulating layer.

2. a fifth insulating layer and a sixth insulating layer provided between the first insulating layer and the third insulating layer; 2 . The semiconductor memory device according to claim 1 , wherein a thickness of said fifth insulating layer and said sixth insulating layer in a second direction perpendicular to said first direction is greater than a thickness of said fourth insulating layer in said second direction.

3. 3. The semiconductor memory device according to claim 2, wherein said fifth insulating layer is provided between said sixth insulating layer and said first insulating layer, and is provided between said fourth insulating layers adjacent to each other in said first direction.

4. 3. The semiconductor memory device according to claim 2, wherein said sixth insulating layer is embedded in a recess in said third insulating layer having said second thickness.

5. 5. The semiconductor memory device according to claim 4, wherein said sixth insulating layer is inclined with respect to said first direction in a region corresponding to said step region.

6. the third insulating layer is an insulating layer containing silicon and nitrogen, the fourth to sixth insulating layers are insulating layers containing silicon and oxygen, 3. The semiconductor memory device according to claim 2, wherein said seventh insulating layer is an insulating layer containing silicon and aluminum.

7. 7. The semiconductor memory device according to claim 6, wherein a concentration of impurities other than silicon and oxygen contained in said fourth insulating layer is lower than a concentration of impurities other than silicon and oxygen contained in said fifth insulating layer.

8. forming a stack by alternately stacking first sacrificial layers and first insulating layers in a first direction; forming a hole extending along the first direction in the laminate; Selectively depositing a material of the first sacrificial layer on the first sacrificial layer in the hole; selectively forming a fifth insulating layer on the first insulating layer in the hole; forming, in the hole, materials of a sixth insulating layer, a third insulating layer, a second insulating layer and a semiconductor layer in this order on the first sacrificial layer and the fifth insulating layer; Selectively removing the first sacrificial layer from the stack; selectively removing the sixth insulating layer exposed in a space after the first sacrificial layer is removed to expose the third insulating layer in the space; selectively depositing a material of the third insulating layer on the third insulating layer exposed to the space; forming a fourth insulating layer on the third insulating layer exposed to the space; forming a seventh insulating layer on the first insulating layer and the fourth insulating layer in the space; forming an electrode layer material on the inside of the seventh insulating layer within the space.

9. 9. The method of claim 8, wherein the fifth insulating layer is selectively deposited on the first insulating layer at the inner wall of the hole.

10. 9. The method of claim 8, wherein the fifth insulating layer is deposited over the entire inner wall of the hole and then etched to selectively leave the fifth insulating layer on the inner wall of the hole on the first insulating layer.

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