Semiconductor storage device

Abstract

To provide a semiconductor storage device capable of suppressing fluctuations in a threshold voltage of a memory cell transistor.SOLUTION: A semiconductor storage device includes: a substrate; a memory pillar MP extending from the substrate to a first direction; and a control circuit in which a plurality of word lines WL_e are provided opposite to one side surface of the memory pillar to form a NAND string 50e, a plurality of word lines WL_o are provided opposite to the other side surface, sandwiching the memory pillar to form a NAND string 50o, a Vread voltage is applied to all of the word lines WL_e and all of the word lines WL_o upon completion of a read operation of a word line W_e_n, and then, after decreasing the voltage of all of the word lines WL_e, the voltage of all of the word lines WL_o, a select gate line SGD, and the voltage of a select gate line SGD and a select gate line SGS are decreased.SELECTED DRAWING: Figure 20

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device. [Background technology]

[0002] A NAND flash memory is known as a non-volatile semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-168163 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments is to provide a semiconductor memory device capable of suppressing fluctuations in the threshold voltage of a memory cell transistor. [Means for solving the problem]

[0005] A semiconductor manufacturing apparatus according to an embodiment includes a substrate, a memory pillar extending from the substrate in a first direction, a first conductive layer disposed on the substrate, spaced apart from the substrate in the first direction and parallel to a substrate surface of the substrate and facing the memory pillar, a second conductive layer disposed on the substrate, adjacent to the first conductive layer via the memory pillar in a second direction intersecting the first direction and parallel to the substrate surface and facing the memory pillar, a third conductive layer disposed between the substrate and the first conductive layer, parallel to the substrate surface and facing the memory pillar, and a third conductive layer disposed between the substrate and the second conductive layer, adjacent to the third conductive layer in the second direction via the memory pillar. a fourth conductive layer that is arranged parallel to the substrate surface and faces the memory pillar; a fifth conductive layer that is arranged on the first conductive layer parallel to the substrate surface and faces the memory pillar; a sixth conductive layer that is arranged on the second conductive layer adjacent to the fifth conductive layer via the memory pillar in the second direction and parallel to the substrate surface and faces the memory pillar; a seventh conductive layer that is arranged between the substrate and the third conductive layer parallel to the substrate surface and faces the memory pillar; and a seventh conductive layer that is arranged between the substrate and the fourth conductive layer adjacent to the seventh conductive layer via the memory pillar in the second direction and parallel to the substrate surface and faces the memory pillar. an eighth conductive layer, a ninth conductive layer provided on the fifth conductive layer in parallel to the substrate surface and facing the memory pillar, a tenth conductive layer provided on the sixth conductive layer adjacent to the ninth conductive layer in the second direction via the memory pillar, in parallel to the substrate surface and facing the memory pillar, a first memory cell formed between the first conductive layer and the memory pillar, a second memory cell formed between the second conductive layer and the memory pillar, a third memory cell formed between the third conductive layer and the memory pillar, a fourth memory cell formed between the fourth conductive layer and the memory pillar, and a fifth conductive layer and the memory pillar. a fifth memory cell formed between the sixth conductive layer and the memory pillar, a sixth memory cell formed between the sixth conductive layer and the memory pillar, a seventh memory cell formed between the seventh conductive layer and the memory pillar, an eighth memory cell formed between the eighth conductive layer and the memory pillar, a ninth memory cell formed between the ninth conductive layer and the memory pillar, and a tenth memory cell formed between the tenth conductive layer and the memory pillar; applying a first voltage to the first conductive layer, applying a second voltage lower than the first voltage to the second conductive layer, the fourth conductive layer, and the sixth conductive layer, and applying a second voltage lower than the first voltage to the third conductive layer, the fifth conductive layer, the seventh conductive layer, the eighth conductive layer,applying a third voltage higher than the first voltage to the ninth conductive layer and the tenth conductive layer, then applying the third voltage to the first conductive layer, the second conductive layer, the fourth conductive layer, and the sixth conductive layer, then applying a fourth voltage lower than the first voltage to the first conductive layer, the third conductive layer, the fifth conductive layer, the seventh conductive layer, and the ninth conductive layer, and then applying a fifth voltage lower than the first voltage to the second conductive layer, the fourth conductive layer, the sixth conductive layer, the eighth conductive layer, and the tenth conductive layer; A control circuit. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing a configuration of a memory system including a semiconductor memory device according to a first embodiment. [Diagram 2] 1 is a schematic diagram showing a circuit configuration of a memory cell array in a semiconductor memory device according to a first embodiment. [Diagram 3] 3 is a schematic diagram showing a planar layout of select gate lines, bit lines, and memory pillars according to the first embodiment. FIG. [Figure 4] FIG. 2 is a schematic diagram showing a planar layout of word lines and memory pillars according to the first embodiment. [Diagram 5] 5 is a cross-sectional view of the semiconductor memory device shown in FIGS. 3 and 4 taken along line B1-B2. FIG. [Figure 6] 5 is a cross-sectional view of the semiconductor memory device shown in FIGS. 3 and 4 taken along line A1-A2. FIG. [Figure 7] 6 is a cross-sectional view of the memory cell transistor shown in FIG. 5 along the line C1-C2. [Figure 8] 8 is a cross-sectional view of the memory cell transistor shown in FIG. 7 along the line D1-D2. [Figure 9] 8 is a cross-sectional end view showing a modification of the memory cell transistor shown in FIG. 7. [Figure 10] 10 is a cross-sectional view of the memory cell transistor shown in FIG. 9 taken along line E1-E2. [Figure 11] 2 is a diagram showing an equivalent circuit of a memory pillar (two adjacent NAND strings) in the semiconductor memory device according to the first embodiment. FIG. [Figure 12]3 is a diagram for explaining electrical connections of a voltage generating circuit, a driver set, and a select gate line or a word line according to the first embodiment. FIG. [Figure 13] 3 is a diagram for explaining electrical connections of a voltage generating circuit, a driver set, and a select gate line or a word line according to the first embodiment. FIG. [Figure 14] 4 is a schematic diagram for explaining an electrical connection between an even word line driver and a row decoder according to the first embodiment. FIG. [Figure 15] 4 is a schematic diagram for explaining electrical connection between an odd-word line driver and a row decoder according to the first embodiment. FIG. [Figure 16] 2 is a schematic diagram for explaining electrical connection between a voltage generating circuit 27 and an even-word line driver 28 according to the first embodiment. FIG. [Figure 17] 2 is a schematic diagram for explaining electrical connection between a voltage generating circuit 27 and an odd-word line driver 28 according to the first embodiment. FIG. [Figure 18] 4 is a diagram illustrating a schematic diagram of a change in threshold voltage of a memory cell transistor in the semiconductor memory device of the first embodiment. FIG. [Figure 19] 4 is a diagram illustrating a timing chart of various signals during a data read operation in the semiconductor memory device of the first embodiment. FIG. [Figure 20] FIG. 4 is a diagram illustrating an example of voltages in the semiconductor memory device of the first embodiment. [Figure 21] FIG. 4 is a diagram illustrating an example of voltages in the semiconductor memory device of the first embodiment. [Figure 22] 11 is a diagram illustrating a timing chart of various signals during a data read operation in a semiconductor memory device of a comparative example. FIG. [Diagram 23] FIG. 11 is a diagram showing an example of voltages in a semiconductor memory device according to a comparative example of the first embodiment. [Figure 24] FIG. 11 is a diagram showing an example of voltages in a semiconductor memory device according to a comparative example of the first embodiment. [Diagram 25]FIG. 11 is a diagram illustrating a timing chart of various signals during a data read operation in the semiconductor memory device according to the modified example of the first embodiment. [Figure 26] 13 is a diagram illustrating a timing chart of various signals during a data read operation in the semiconductor memory device of the second embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same or similar parts are denoted by the same or similar reference numerals.

[0008] (First embodiment) 1 is a block diagram showing an example of the configuration of a memory system 3 including a semiconductor memory device 1 according to the first embodiment. The configuration of the memory system 3 including the semiconductor memory device 1 according to the first embodiment is not limited to the configuration shown in FIG.

[0009] 1, the memory system 3 includes a semiconductor memory device 1 and a memory controller 2. The memory system 3 is, for example, a solid state drive (SSD) or a memory card such as an SDTM card. The memory system 3 may also include a host device (not shown).

[0010] The semiconductor memory device 1 is connected to, for example, a memory controller 2 and is controlled using the memory controller 2. The memory controller 2 receives commands necessary for the operation of the semiconductor memory device 1 from, for example, a host device, and transmits the commands to the semiconductor memory device 1. The memory controller 2 transmits the commands to the semiconductor memory device 1 and controls reading data from the semiconductor memory device 1, writing data to the semiconductor memory device 1, or erasing data from the semiconductor memory device 1. In this embodiment, the semiconductor memory device 1 is, for example, a NAND type flash memory.

[0011] 1, the semiconductor memory device 1 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a sequencer 24, a register 25, a ready / busy control circuit 26, a voltage generation circuit 27, a driver set 28, a row decoder 29, a sense amplifier 30, an input / output pad group 71, and a logic control pad group 72. In the semiconductor memory device 1, various operations are executed, such as a write operation for storing write data DAT in the memory cell array 21, and a read operation for reading read data DAT from the memory cell array 21. The configuration of the semiconductor memory device 1 according to this embodiment is not limited to the configuration shown in FIG.

[0012] The memory cell array 21 is connected to, for example, a sense amplifier 30, a row decoder 29, and a driver set 28. The memory cell array 21 includes blocks BLKO, BLK1, ..., BLKn (n is an integer equal to or greater than 1). As will be described in detail later, each of the blocks BLK includes a plurality of string units SU (SU0, SU1, SU2, ...). Each of the string units SU includes a plurality of non-volatile memory cells associated with bit lines and word lines. The block BLK is, for example, a data erase unit. Data held in memory cell transistors MT (FIG. 2) included in the same block BLK is erased all at once.

[0013] In the semiconductor memory device 1, for example, a triple-level cell (TLC) method or a quadruple level cell (QLC) method can be applied. In the TLC method, 3 bits of data are held in each memory cell, and in the QLC method, 4 bits of data are held in each memory cell. Note that each memory cell may hold 2 bits or less of data, or 5 bits or more of data.

[0014] The input / output circuit 22 is connected to, for example, a register 25, a logic control circuit 23, and a sense amplifier 30. The input / output circuit 22 controls transmission and reception of data signals DQ<7:0> between the memory controller 2 and the semiconductor memory device 1.

[0015] The data signal DQ<7:0> is an 8-bit signal. The data signal DQ<7:0> is the entity of data transmitted and received between the semiconductor memory device 1 and the memory controller 2, and includes a command CMD, data DAT, address information ADD, status information STS, and the like. The command CMD includes, for example, a command for executing a command transmitted from a host device (memory controller 2) to the semiconductor memory device 1. The data DAT includes write data DAT to the semiconductor memory device 1 or read data DAT from the semiconductor memory device 1. The address information ADD includes, for example, a column address and a row address for selecting a plurality of non-volatile memory cells associated with a bit line and a word line. The status information STS includes, for example, information regarding the status of the semiconductor memory device 1 regarding a write operation and a read operation.

[0016] More specifically, the input / output circuit 22 includes an input circuit and an output circuit, which perform the following processes. The input circuit receives write data DAT, address information ADD, and a command CMD from the memory controller 2. The input circuit transmits the received write data DAT to the sense amplifier 70, and transmits the received address information ADD and command CMD to the register 25. Meanwhile, the output circuit receives status information STS from the register 25, and receives read data DAT from the sense amplifier 70. The output circuit transmits the received status information STS and read data DAT to the memory controller 2.

[0017] The logic control circuit 23 is connected to, for example, the memory controller 2 and the sequencer 24. The logic control circuit 23 receives, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protect signal WPn from the memory controller 2. The logic control circuit 23 controls the input / output circuit 22 and the sequencer 24 based on the received signals.

[0018] The chip enable signal CEn is a signal for enabling the semiconductor memory device 1. The command latch enable signal CLE is a signal for notifying the input / output circuit 22 that the signal DQ input to the semiconductor memory device 1 is a command CMD. The address latch enable signal ALE is a signal for notifying the input / output circuit 22 that the signal DQ input to the semiconductor memory device 1 is address information ADD. The write enable signal WEn and the read enable signal REn are signals for instructing the input / output circuit 22 to input and output, for example, a data signal DQ, respectively. The write protect signal WPn is a signal for instructing the semiconductor memory device 1 to prohibit writing and erasing data.

[0019] The sequencer 24 is connected to, for example, a ready / busy control circuit 26, a sense amplifier 30, and a driver set 28. The sequencer 24 controls the operation of the entire semiconductor memory device 1 based on a command CMD held in a command register. For example, the sequencer 24 controls the sense amplifier 30, a row decoder 29, a voltage generating circuit 27, and a driver set 28, etc., to execute various operations such as a write operation and a read operation.

[0020] The register 25 includes, for example, a status register (not shown), an address register (not shown), and a command register (not shown). The status register receives status information STS from the sequencer 24, holds it, and transmits the status information STS to the input / output circuit 22 based on an instruction from the sequencer 24. The address register receives address information ADD from the input / output circuit 22, holds it. The address register transmits a column address in the address information ADD to the sense amplifier 70, and transmits a row address in the address information ADD to the row decoder 29. The command register receives a command CMD from the input / output circuit 22, holds it, and transmits the command CMD to the sequencer 24.

[0021] The ready / busy control circuit 26 generates a ready / busy signal R / Bn under the control of the sequencer 24, and transmits the generated ready / busy signal R / Bn to the memory controller 2. The ready / busy signal R / Bn is a signal for notifying whether the semiconductor memory device 1 is in a ready state in which it can accept commands from the memory controller 2, or in a busy state in which it cannot accept commands.

[0022] The voltage generating circuit 27 is connected to, for example, a driver set 28 and the like. The voltage generating circuit 27 generates voltages used for write operations, read operations, and the like based on the control of the sequencer 24, and supplies the generated voltages to the driver set 28.

[0023] The driver set 28 includes, for example, an even word line driver 28A (FIG. 12) and an odd word line driver 28B (FIG. 12). The driver set 28 is connected to the memory cell array 21, the sense amplifier 70, and the row decoder 29. The driver set 28 generates various voltages to be applied to the select gate line SGD (FIG. 2), the word line WL (FIG. 2), the source line SL (FIG. 2), and the like in various operations such as a read operation and a write operation, based on the voltage supplied from the voltage generating circuit 27. The driver set 28 supplies the generated voltages to the even word line driver 28A, the odd word line driver 28B, the sense amplifier 30, the row decoder 29, the source line SL, and the like.

[0024] The row decoder 29 receives a row address from the address register and decodes the received row address. Based on the result of the decoding, the row decoder 29 selects a block BLK on which various operations such as a read operation and a write operation are to be performed. The row decoder 29 can supply a voltage supplied from the driver set 28 to the selected block BLK.

[0025] The sense amplifier 30 receives, for example, a column address from an address register and decodes the received column address. Based on the result of the decoding, the sense amplifier 30 executes a transmission / reception operation of data DAT between the memory controller 2 and the memory cell array 21. The sense amplifier 30 includes, for example, a sense amplifier unit (not shown) provided for each bit line. The sense amplifier 30 enables a voltage to be supplied to the bit line BL using the sense amplifier unit. For example, the sense amplifier 30 can supply a voltage to the bit line using the sense amplifier unit. The sense amplifier 30 senses data read from the memory cell array 21, generates read data DAT, and transmits the generated read data DAT to the memory controller 2 via the input / output circuit 22. The sense amplifier 30 receives write data DAT from the memory controller 2 via the input / output circuit 22 and transmits the received write data DAT to the memory cell array 21.

[0026] The input / output pad group 71 transmits the data signal DQ<7:0> received from the memory controller 2 to the input / output circuit 22. The input / output pad group 71 transmits the data signal DQ<7:0> received from the input / output circuit 22 to the memory controller 2.

[0027] The logic control pad group 72 transfers the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn received from the memory controller 2 to the logic control circuit 23. The logic control pad group 72 transfers the ready / busy signal R / Bn received from the ready / busy control circuit 26 to the memory controller 2.

[0028] Fig. 2 is an example of a circuit configuration of the memory cell array 21 shown in Fig. 1. Fig. 2 is a diagram showing the circuit configuration of one of the blocks BLK included in the memory cell array 21. For example, each of the blocks BLK included in the memory cell array 21 has the circuit configuration shown in Fig. 2. The configuration of the memory cell array 21 according to this embodiment is not limited to the configuration shown in Fig. 2. In the description of Fig. 2, a description of a configuration that is the same as or similar to that of Fig. 1 may be omitted.

[0029] As shown in FIG. 2, the block BLK includes a plurality of string units SU (SU0, SU1, SU2, SU3). In this embodiment, the write operation and the read operation are performed in units of the string unit SU (page). Each of the string units SU includes a plurality of NAND strings 50. For example, the string units SU0 and SU2 include a plurality of NAND strings 50e, and the string units SU1 and SU3 include a plurality of NAND strings 50o. Note that, although FIG. 2 shows an example in which each block BLK includes four string units SU0, SU1, SU2, SU3, the number of string units included in each block is not limited to four. For example, each block BLK may include six or eight string units.

[0030] Each of the NAND strings 50 includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. The memory cell transistors MT include a control gate and a charge storage layer, and retain data in a non-volatile manner. The memory cell transistors MT are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2.

[0031] The gate of the selection transistor ST1 in each of the string units SU is connected to a selection gate line SGD (SGD0, SGD1, ...). The selection gate lines SGD are independently controlled by a row decoder 29. The gate of the selection transistor ST2 in each of the even-numbered string units SUe (SU0, SU2, ...) is connected to, for example, an even-numbered selection gate line SGSe, and the gate of the selection transistor ST2 in each of the odd-numbered string units SUo (SU1, SU3, ...) is connected to, for example, an odd-numbered selection gate line SGSo. The even-numbered selection gate line SGSe and the odd-numbered selection gate line SGSo may be connected to each other and controlled in the same way, or may be provided independently and independently controllable.

[0032] The control gates of the memory cell transistors MT (MT0 to MT7) included in the string units SUe in the same block BLK are commonly connected to the word lines WLe (WLe0 to WLe7). The control gates of the memory cell transistors MT (MT0 to MT7) included in the string units SUo in the same block BLK are commonly connected to the word lines WLo (WLo0 to WLo7). The select gate lines WLe and WLo are independently controlled by the row decoder 29.

[0033] The drains of the select transistors ST1 of the NAND strings 50 in the same column in the memory cell array 21 are commonly connected to a bit line BL (BL0 to BL(L-1), where (L-1) is a natural number equal to or greater than 2). That is, the bit line BL commonly connects the NAND strings 50 between the multiple string units SU. The sources of the multiple select transistors ST2 are commonly connected to a source line SL. The source line SL is, for example, electrically connected to the driver set 28, and is supplied with a voltage from the voltage generation circuit 27 or the driver set 28 by the control of the voltage generation circuit 27 and the driver set 28 using the sequencer 24. The semiconductor memory device 1 according to the embodiment may also include multiple source lines SL. For example, each of the multiple source lines SL may be electrically connected to the driver set 28, and each of the multiple source lines SL may be supplied with a different voltage from each other from the voltage generation circuit 27 or the driver set 28 by the control of the voltage generation circuit 27 and the driver set 28 using the sequencer 24.

[0034] The string unit SU includes a plurality of NAND strings 50 connected to different bit lines BL and to the same select gate line SGD. The block BLK includes a plurality of string units SU that share a word line WL. The memory cell array 21 includes a plurality of blocks BLK that share a bit line BL. In the memory cell array 21, the above-mentioned select gate line SGS, word line WL, and select gate line SGD are stacked above the source line layer, and the memory cell transistors MT are stacked three-dimensionally.

[0035] 3 is a diagram showing a planar layout of the select gate lines SGD in a plane (XY plane) parallel to the source line layer of a certain block BLK. As shown in FIG. 3, in the semiconductor memory device 1 according to this embodiment, for example, four select gate lines SGD are included in one block BLK. The planar layout of the select gate lines SGD according to one embodiment is not limited to the layout shown in FIG. 3. In the description of FIG. 3, descriptions of configurations that are the same as or similar to those in FIG. 1 and FIG. 2 may be omitted.

[0036] As shown in FIG. 3, in the semiconductor memory device 1 according to this embodiment, for example, three wiring layers 10-0a, 10-0b, and 10-0c extending in the X direction are connected using a first connection portion 10-0d extending in the Y direction. The wiring layers 10-0a and 10-0c are located at both ends in the Y direction. The wiring layers 10-0a and 10-0b are adjacent to each other in the Y direction with another wiring layer (wiring layer 10-1a) sandwiched therebetween. The first connection portion 10-0d is located at one end in the X direction. The three wiring layers 10-0a, 10-0b, and 10-0c function as a select gate line SGD0. In this embodiment, for example, the Y direction is perpendicular or substantially perpendicular to the X direction.

[0037] The wiring layers 10-1a and 10-1b extending in the X direction are connected using a second connection portion 10-1d extending in the Y direction. The wiring layer 10-1a is located between the wiring layers 10-0a and 10-0b. The wiring layer 10-1b is located between the wiring layer 10-0b and another wiring layer (wiring layer 10-2a). The second connection portion 10-1d is located at the other end opposite the first connection portion 10-0d in the X direction. The two wiring layers 10-1a and 10-1b function as a select gate line SGD1.

[0038] The wiring layers 10-2a and 10-2b extending in the X direction are connected by a first connection portion 10-2d extending in the Y direction. Similarly, the wiring layers 10-3a and 10-3b extending in the X direction are connected by a second connection portion 10-3d extending in the Y direction. The wiring layer 10-2a is located between the wiring layer 10-1b and the wiring layer 10-3a. The wiring layer 10-3a is located between the wiring layer 10-2a and the wiring layer 10-2b. The wiring layer 10-2b is located between the wiring layer 10-3a and the wiring layer 10-3b. The wiring layer 10-3b is located between the wiring layer 10-2b and the wiring layer 10-0c. The first connection portion 10-2d is located at one end on the same side as the first connection portion 10-0d in the X direction. The second connection portion 10-3d is located at the other end opposite the first connection portion 10-0d in the X direction. The two wiring layers 10-2a and 10-2b function as a select gate line SGD2. The two wiring layers 10-3a and 10-3b function as a select gate line SGD3.

[0039] In this embodiment, the wiring layers are connected using the first connection parts 10-0d, 10-2d or the second connection parts 10-1d, 10-3d, but the present invention is not limited to this configuration. For example, each wiring layer is independent, and the wiring layers 10-0a, 10-0b, and 10-0c are controlled to receive the same voltage, the wiring layers 10-1a and 10-1b are controlled to receive the same voltage, the wiring layers 10-2a and 10-2b are controlled to receive the same voltage, and the wiring layers 10-3a and 10-3b are controlled to receive the same voltage.

[0040] The string unit SU including the NAND string 50e of the memory pillar MP adjacent to the wiring layers 10-0a, 10-0b, and 10-0c is called SU0. The string unit SU including the NAND string 50o of the memory pillar MP adjacent to the wiring layers 10-1a and 10-1b is called SU1. The string unit SU including the NAND string 50e of the memory pillar MP adjacent to the wiring layers 10-2a and 10-2b is called SU2. The string unit SU including the NAND string 50o of the memory pillar MP adjacent to the wiring layers 10-3a and 10-3b is called SU3.

[0041] In the block BLK, adjacent wiring layers 10 are insulated from each other in the Y direction. The region that insulates adjacent wiring layers 10 is called a slit SLT2. In the slit SLT2, for example, an insulating film (not shown) is embedded in the region from a surface parallel to the source line layer to at least the layer in which the wiring layer 10 is provided. In addition, in the memory cell array 21, for example, a plurality of blocks BLK shown in FIG. 3 are arranged in the Y direction. As with the wiring layers 10 adjacent to each other in the Y direction in the block BLK, an insulating film (not shown) is embedded between adjacent blocks BLK in the Y direction, and adjacent blocks BLK in the Y direction are also insulated from each other. The region that insulates adjacent blocks BLK is called a slit SLT1. As with the slit SLT2, in the slit SLT1, an insulating film is embedded in the region from a surface parallel to the source line layer to at least the layer in which the wiring layer 10 is provided.

[0042] A plurality of memory pillars MP (MP0 to MP15) are provided between the wiring layers 10 adjacent to each other in the Y direction. The plurality of memory pillars MP are provided in a memory cell portion. Each of the plurality of memory pillars MP is provided along the Z direction. In one embodiment, for example, the Z direction is a direction perpendicular or substantially perpendicular to the XY directions, and perpendicular or substantially perpendicular to a direction parallel to the source line layer. The Z direction is an example of a first direction. The Y direction is an example of a second direction.

[0043] Specifically, memory pillars MP4 and MP12 are provided between the wiring layers 10-0a and 10-1a. Memory pillars MP0 and MP8 are provided between the wiring layers 10-1a and 10-0b. Memory pillars MP5 and MP13 are provided between the wiring layers 10-0b and 10-1b. Memory pillars MP1 and MP9 are provided between the wiring layers 10-1b and 10-2a. Memory pillars MP6 and MP14 are provided between the wiring layers 10-2a and 10-3a. Memory pillars MP2 and MP10 are provided between the wiring layers 10-3a and 10-2b. Memory pillars MP7 and MP15 are provided between the wiring layers 10-2b and 10-3b. Memory pillars MP3 and MP11 are provided between the wiring layers 10-3b and 10-0c.

[0044] The memory pillar MP is a structure that forms the select transistors ST1 and ST2 and the memory cell transistor MT. The detailed structure of the memory pillar MP will be described later.

[0045] The memory pillars MP0 to MP3 are arranged along the Y direction. The memory pillars MP8 to MP11 are arranged along the Y direction at positions adjacent to the memory pillars MP0 to MP3 in the X direction. That is, the memory pillars MP0 to MP3 and the memory pillars MP8 to MP11 are arranged in parallel.

[0046] Memory pillars MP4 to MP7 and memory pillars MP12 to MP15 are each arranged along the Y direction. Memory pillars MP4 to MP7 are located between memory pillars MP0 to MP3 and memory pillars MP8 to MP11 in the X direction. Memory pillars MP12 to MP15 are located so as to sandwich memory pillars MP8 to MP11 together with memory pillars MP4 to MP7 in the X direction. That is, memory pillars MP4 to MP7 and memory pillars MP12 to MP15 are arranged in parallel.

[0047] Two bit lines BL0 and BL1 are provided above the memory pillars MP0 to MP3. The bit line BL0 is commonly connected to the memory pillars MP1 and MP2. The bit line BL1 is commonly connected to the memory pillars MP0 and MP3. Two bit lines BL2 and BL3 are provided above the memory pillars MP4 to MP7. The bit line BL2 is commonly connected to the memory pillars MP4 and MP5. The bit line BL3 is commonly connected to the memory pillars MP6 and MP7.

[0048] Two bit lines BL4 and BL5 are provided above the memory pillars MP8 to MP11. The bit line BL4 is commonly connected to the memory pillars MP9 and MP10. Two bit lines BL6 and BL7 are provided above the memory pillars MP12 to MP15. The bit line BL6 is commonly connected to the memory pillars MP12 and MP13. The bit line BL7 is commonly connected to the memory pillars MP14 and MP15.

[0049] As described above, the memory pillar MP is provided at a position straddling two wiring layers 10 in the Y direction, and is provided so as to be embedded in a part of one of the slits SLT2 among the multiple slits SL2. Furthermore, one slit SLT2 is provided between memory pillars MP adjacent to each other in the Y direction.

[0050] It should be noted that no memory pillar MP is provided between the wiring layer 10-0a and the wiring layer 10-0b adjacent to each other with the slit SLT1 interposed therebetween.

[0051] Fig. 4 is a diagram showing a planar layout of the word lines WL in the XY plane. The layout shown in Fig. 4 corresponds to the layout of one block of Fig. 3, and is a layout of the wiring layer 11 provided below the wiring layer 10 shown in Fig. 3. The planar layout of the word lines WL according to one embodiment is not limited to the layout shown in Fig. 4. In the description of Fig. 4, descriptions of configurations that are the same as or similar to those in Figs. 1 to 3 may be omitted.

[0052] 4, nine wiring layers 11 (wiring layers 11-0 to 11-7, where wiring layer 11-0 includes wiring layers 11-0a and 11-0b) extending in the X direction are arranged along the Y direction. Each of the wiring layers 11-0 to 11-7 is arranged below each of the wiring layers 10-0 to 10-7 in the Z direction. An insulating film is provided between the wiring layers 11-0 to 11-7 and the wiring layers 10-0 to 10-7, so that the wiring layers 11-0 to 11-7 and the wiring layers 10-0 to 10-7 are insulated from each other.

[0053] Each wiring layer 11 functions as a word line WL7. The other word lines WL0 to WL6 have the same configuration and function as the word line WL7. In the example shown in FIG. 4, the wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b function as the word line WLe7. The wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are connected using a first connection portion 11-8 extending in the Y direction. The first connection portion 11-8 is provided at one end in the X direction. In the first connection portion 11-8, the wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are connected to the row decoder 29. In one embodiment, the first connection portion 11-8 and the wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b may be collectively referred to as the wiring layer 11e.

[0054] Moreover, the wiring layers 11-1, 11-3, 11-5, and 11-7 function as the word line WLo7. The wiring layers 11-1, 11-3, 11-5, and the wiring layer 11-7 are connected using a second connection portion 11-9 extending in the Y direction. The second connection portion 11-9 is provided at the other end opposite to the first connection portion 11-8 in the X direction. The wiring layers 11-1, 11-3, 11-5, and 11-7 are connected to the row decoder 29 through the second connection portion 11-9. In one embodiment, the second connection portion 11-9 and the wiring layers 11-1, 11-3, 11-5, and 11-7 may be collectively referred to as the wiring layer 11o.

[0055] A memory cell section is provided between the first connection section 11-8 and the second connection section 11-9. In the memory cell section, the wiring layers 11 adjacent to each other in the Y direction are separated by slits SLT2 shown in Fig. 3. Similarly to the slits SLT2, the wiring layers 11 between the blocks BLK adjacent to each other in the Y direction are separated by slits SLT1. The memory cell section includes memory pillars MP0 to MP15, similar to Fig. 3.

[0056] The select gate line SGS and the word lines WL0 to WL6 have the same configuration as the word line WL7 shown in FIG.

[0057] Fig. 5 is a diagram showing an end surface of the B1-B2 cut portion shown in Fig. 4. The cut end surface of the block BLK according to this embodiment is not limited to the cut end surface shown in Fig. 5. In the description of Fig. 5, descriptions of configurations that are the same as or similar to those in Figs. 1 to 4 may be omitted.

[0058] As shown in FIG. 5, the wiring layer 12 is provided above the source line layer 13 along the Z direction. The source line layer 13 functions as a source line SL. The wiring layer 12 may be provided on a p-type well region in a semiconductor substrate (substrate) instead of the source line layer 13 shown in FIG. 5. In this case, the source line SL is electrically connected to the p-type well region in the semiconductor substrate. The wiring layer 12 functions as a select gate line SGS. Eight wiring layers 11 are stacked above the wiring layer 12 along the Z direction. The wiring layer 11 functions as a word line WL. The eight wiring layers 11 correspond one-to-one to the word lines WL0 to WL7. FIG. 4 is a diagram showing a planar layout of the wiring layer 11 functioning as the word line WL, and FIG. 3 is a diagram showing a planar layout of the wiring layer 10 functioning as the select gate line SGD. The planar layout of the wiring layer 12 functioning as the select gate line SGS is, for example, a layout in which the wiring layer 10 functioning as the select gate line SGD shown in FIG. 3 is replaced with the wiring layer 12 functioning as the select gate line SGS.

[0059] The wiring layer 12 functions as an even-numbered select gate line SGSe or an odd-even-numbered select gate line SGSo. The even-numbered select gate line SGSe and the odd-even-numbered select gate line SGSo are alternately arranged in the Y direction via slits SLT2. A memory pillar MP is provided between the even-numbered select gate line SGSe and the odd-even-numbered select gate line SGSo adjacent in the Y direction.

[0060] The wiring layer 11 functions as an even word line WLe or an odd word line WLo. The even word lines WLe and odd word lines WLo are alternately arranged in the Y direction via slits SLT2. A memory pillar MP is provided between the word lines WLe and WLo adjacent in the Y direction. A memory cell, which will be described later, is provided between the memory pillar MP and the word line WLe, and between the memory pillar MP and the word line WLo.

[0061] A slit SLT1 is provided between blocks BLK adjacent in the Y direction. As described above, an insulating layer is provided in the slit SLT1. However, a contact plug or a groove-shaped structure formed using a conductor may be provided in the slit SLT1, which is an insulator. When a contact plug or a groove-shaped structure formed using a conductor is provided in the slit SLT1, a voltage can be applied in the source line layer 13. The width of the slit SLT1 in the Y direction is larger than the width of the slit SLT2 in the Y direction.

[0062] 3 and 5, the memory pillars MP are electrically connected to the bit lines BL. For example, the memory pillar MP0 and the bit line BL1 are connected via a contact plug 16. Furthermore, the memory pillar MP1 and the bit line BL0 are connected via a contact plug 16, the memory pillar MP2 and the bit line BL1 are connected via a contact plug 16, and the memory pillar MP3 and the bit line BL0 are connected via a contact plug 16. Similarly, each of the memory pillars MP4 to MP7 is connected to the bit line BL2 or BL3, the memory pillars MP8 to MP11 are connected to the bit line BL4 or BL5, and the memory pillars MP12 to MP15 are connected to the bit line BL6 or BL7.

[0063] FIG. 6 is a diagram showing an end surface of the A1-A2 cut portion of the semiconductor memory device shown in FIG. 3. The cut portion end surface of the block BLK according to an embodiment is not limited to the cut portion end surface shown in FIG. 6. In the description of FIG. 6, the description of the same or similar configuration as in FIG. 1 to FIG. 5 may be omitted. The stacked structure of the source line layer 13, the wiring layer 12, the wiring layer 11, and the wiring layer 10, and the configuration of the memory cell section are as described using FIG. 5, so the description here is omitted. Note that in FIG. 6, the configuration present in the depth direction of the A1-A2 cut portion end surface is drawn with dotted lines.

[0064] As shown in FIG. 6, in the first connection region, the wiring layer 10, the wiring layer 11, and the wiring layer 12 are provided, for example, in a stepped shape and are drawn out from the source line layer 13. That is, when viewed in the XY plane, the upper surfaces of the ends of the wiring layer 10, the eight-layer wiring layer 11, and the wiring layer 12 are exposed in the first connection region. Contact plugs 17 are provided on the upper surfaces of the ends of the wiring layer 10, the eight-layer wiring layer 11, and the wiring layer 12 exposed in the first connection region. The contact plugs 17 are connected to a metal wiring layer 18. For example, the metal wiring layer 18 is used to electrically connect the wiring layer 10 functioning as the even-numbered select gate lines SGD0 and SGD2, the wiring layer 11 functioning as the even word line WLe, and the wiring layer 12 functioning as the even select gate line SGSe to the even word line driver 28A via the row decoder 29 (FIG. 1).

[0065] As in the first connection region, in the second connection region, the wiring layer 10, the wiring layer 11, and the wiring layer 12 are provided, for example, in a stepped shape and are drawn out from the source line layer 13. When viewed in the XY plane, the upper surfaces of the ends of the wiring layer 10, the eight-layer wiring layer 11, and the wiring layer 12 are exposed in the second connection region. Contact plugs 19 are provided on the upper surface of the end of the wiring layer 10 exposed in the second connection region, and on the upper surfaces of the ends of the eight-layer wiring layer 11 and the wiring layer 12, and the contact plugs 19 are connected to the metal wiring layer 20. For example, the odd-numbered select gate lines SGD1 and SGD3, the wiring layer 11 functioning as the odd word line WLo, and the wiring layer 12 functioning as the odd select gate line SGSo are electrically connected to the odd word line driver 28B via the row decoder 29 (FIG. 1) using the metal wiring layer 20.

[0066] The wiring layer 10 may be electrically connected to the row decoder 29, or the even word line driver 28A and the odd word line driver 28B, via the second connection region instead of the first connection region 7, or may be electrically connected to the row decoder 29, or the even word line driver 28A and the odd word line driver 28B, via both the first connection region and the second connection region.

[0067] FIG. 7 is a diagram showing an end surface of a C1-C2 cut portion of a memory cell transistor according to this embodiment, and FIG. 8 is a diagram showing an end surface of a D1-D2 cut portion of the memory cell transistor shown in FIG. 7. FIGS. 7 and 8 are cut portion end surface views showing an area including two memory cell transistors MT. In a first example, a charge storage layer included in a memory cell transistor MT is an insulating film. The first example of the memory cell transistor according to this embodiment is not limited to the structure shown in FIGS. 7 and 8. In the description of FIGS. 7 and 8, description of configurations that are the same as or similar to those in FIGS. 1 to 6 may be omitted.

[0068] As shown in FIGS. 7 and 8, the memory pillar MP includes an insulating layer 30 (an example of an insulator), a semiconductor layer 31, and insulating layers 32 to 34 provided along the Z direction. The insulating layer 30 is formed using, for example, a silicon oxide film. The semiconductor layer 31 is provided so as to surround the periphery of the insulating layer 30, and functions as a region in which the channel of the memory cell transistor MT is formed. The semiconductor layer 31 (an example of the first channel and the second channel) is formed using, for example, a polycrystalline silicon layer. The semiconductor layer 31 is not separated between the memory cell transistors MT in the same memory pillar MP, but is provided continuously. Therefore, the channels formed in each of the two memory cell transistors MT share a part of the memory pillar MP.

[0069] As described above, the semiconductor layer 31 is continuous between two opposing memory cell transistors MT. Therefore, the channels formed in each of the two opposing memory cell transistors MT share a part of the memory pillar MP. Specifically, in the left memory cell transistor MT and the right memory cell transistor MT opposing each other in FIG. 7 and FIG. 8, the channel formed in the first memory cell and the channel formed in the second memory cell share a part of the memory pillar MP. Here, two channels sharing a part of the memory pillar MP means that the two channels are formed in the same memory pillar MP and partially overlap each other. In one embodiment, the above configuration may be referred to as two memory cell transistors MT sharing a channel or two memory cell transistors MT facing each other.

[0070] The insulating layer 32 is provided so as to surround the periphery of the semiconductor layer 31, and functions as a gate insulating film of the memory cell transistor MT. The insulating layer 32 is formed, for example, using a stacked structure of a silicon oxide film and a silicon nitride film. The insulating layer 33 is provided so as to surround the periphery of the semiconductor layer 31, and functions as a charge storage layer of the memory cell transistor MT. The insulating layer 33 is formed, for example, using a silicon nitride film. The insulating layer 34 is provided so as to surround the periphery of the insulating layer 33, and functions as a block insulating film of the memory cell transistor MT. The insulating layer 34 is formed, for example, using a silicon oxide film. An insulating layer 37 is buried in the slit SLT2 except for the memory pillar MP portion. The insulating layer 37 is formed, for example, using a silicon oxide film. The insulating layer 33 (charge storage layer, charge storage film) of the left memory cell transistor MT (first memory cell) and the insulating layer 33 (charge storage layer, charge storage film) of the right memory cell transistor MT (second memory cell) facing each other are connected by an insulating layer 33 (film) including, for example, a silicon nitride film.

[0071] In the first example of the embodiment, for example, an AlO layer 35 is provided around the memory pillar MP. For example, a barrier metal layer 36 is provided around the AlO layer 35. The barrier metal layer 36 is formed using, for example, a TiN film. A wiring layer 11 functioning as a word line WL is provided around the barrier metal layer 36. The wiring layer 11 is formed using, for example, a film made of tungsten.

[0072] As a result, one memory pillar MP includes two memory cell transistors MT and MT, or two select transistors ST1 and ST2, along the Y direction at a certain position on the Z axis.

[0073] <1-6-2. Second example> FIG. 9 is a diagram showing a modification of the memory cell transistor shown in FIG. 7, and is a diagram showing an end surface of the C1-C2 cut portion of the memory cell transistor shown in FIG. 5. FIG. 10 is a diagram showing an end surface of the E1-E2 cut portion of the memory cell transistor shown in FIG. 9. FIGS. 9 and 10 are cut portion end surface views showing an area including two memory cell transistors MT. In the second example, the charge storage layer included in the memory cell transistor MT is a conductive film. The second example of the memory cell transistor according to the embodiment is not limited to the structure shown in FIGS. 10 and 11. In the description of FIGS. 10 and 11, description of configurations that are the same as or similar to those in FIGS. 1 to 9 may be omitted.

[0074] As shown in FIGS. 10 and 11, the memory pillar MP includes an insulating layer 48 and an insulating layer 43, a semiconductor layer 40, an insulating layer 41, a conductive layer 42, and insulating layers 46a to 46c provided along the Z direction. The insulating layer 48 is formed using, for example, a silicon oxide film. The semiconductor layer 40 is provided so as to surround the periphery of the insulating layer 48. The semiconductor layer 40 functions as a region in which a channel of the memory cell transistor MT is formed. The semiconductor layer 40 is formed using, for example, a polycrystalline silicon layer. As with the first example of the memory pillar MP shown in FIG. 8, the semiconductor layer 40 is provided continuously without being separated between the memory cell transistors MT in the same memory pillar MP.

[0075] The insulating layer 41 is provided around the semiconductor layer 40 and functions as a gate insulating film for each memory cell transistor MT. The insulating layer 41 is separated into two regions in the XY plane shown in Fig. 10. Each of the insulating layer 41 separated into two regions functions as a gate insulating film for two memory cell transistors MT in the same memory pillar MP. The insulating layer 41 is formed using, for example, a stacked structure of a silicon oxide film and a silicon nitride film.

[0076] The conductive layer 42 is provided around the insulating layer 41, and is separated into two regions along the Y direction by an insulating layer 43. Each of the conductive layer 42 separated into two regions functions as a charge storage layer for each of the two memory cell transistors MT. The conductive layer 42 is formed using, for example, a polycrystalline silicon layer.

[0077] The insulating layer 43 is formed of, for example, a silicon oxide film. Around the conductive layer 42, insulating layers 46a, 46b, and 46c are sequentially provided from the side closer to the conductive layer 42. The insulating layers 46a and 46c are formed of, for example, a silicon oxide film, and the insulating layer 46b is formed of, for example, a silicon nitride film. The insulating layers 46a, 46b, and 46c function as block insulating films for the memory cell transistors MT. The insulating layers 46a, 46b, and 46c are separated into two regions along the Y direction. The insulating layer 43 is provided between the insulating layer 46c separated into two regions. The insulating layer 43 is also buried in the slit SLT2. The insulating layer 43 is formed of, for example, a silicon oxide film.

[0078] In the second example of the present embodiment, for example, an AlO layer 45 is provided around the memory pillar MP. For example, a barrier metal layer 47 is provided around the AlO layer 45. The barrier metal layer 47 is formed using, for example, a TiN film. A wiring layer 11 functioning as a word line WL is provided around the barrier metal layer 47. As in the first example of the memory pillar MP according to the present embodiment, the wiring layer 11 in the second example of the memory pillar MP according to the present embodiment is formed using, for example, a film made of tungsten.

[0079] In the second example of the memory pillar MP according to this embodiment, similarly to the first example of the memory pillar MP, one memory pillar MP includes two memory cell transistors MT and MT or two select transistors ST1 and ST2 along the Y direction at a certain position on the Z axis. Although not shown, an insulating layer is provided between memory cell transistors adjacent in the Z direction. The insulating layer, insulating layer 43, and insulating layer 46 insulate the conductive layer 42 from each individual memory cell transistor.

[0080] Fig. 11 is an equivalent circuit diagram of a memory pillar (two adjacent NAND strings) in the semiconductor memory device 1 according to this embodiment. The equivalent circuit diagram of the memory pillar according to this embodiment is not limited to the equivalent circuit diagram shown in Fig. 11. In the description of Fig. 11, descriptions of configurations that are the same as or similar to those in Figs. 1 to 10 may be omitted.

[0081] As shown in FIG. 11, two NAND strings 50e, 50o are formed in one memory pillar MP. Each of the NAND strings 50e, 50o has a selection transistor ST1, memory cell transistors MT0-MT7, and a selection transistor ST2 electrically connected in series. The NAND strings 50e and 50o are provided to face each other. Therefore, the selection transistor ST1, memory cell transistors MT0-MT7, and selection transistor ST2 included in the NAND string 50e and the selection transistor ST1, memory cell transistors MT0-MT7, and selection transistor ST2 included in the NAND string 50o are provided to face each other in a one-to-one relationship. Specifically, the select transistor ST1 included in the NAND string 50e is arranged to face the select transistor ST1 included in the NAND string 50o, the memory cell transistors MT0 to MT7 included in the NAND string 50e are arranged to face the memory cell transistors MT0 to MT7 included in the NAND string 50o in a one-to-one relationship, and the select transistor ST2 included in the NAND string 50e is arranged to face the select transistor ST2 included in the NAND string 50o.

[0082] In the following description, we will mainly describe an example that includes two memory pillars MP: a first memory pillar MP (e.g., MP4 in FIG. 4) and a second memory pillar MP (e.g., MP0 in FIG. 4) adjacent to the first memory pillar MP.

[0083] The select transistors ST1 of the NAND strings 50e provided in the first memory pillar MP and the second memory pillar MP are connected to, for example, a common select gate line SGD0. The select transistors ST1 of the NAND strings 50o provided in the first memory pillar MP and the second memory pillar MP are connected to, for example, a common select gate line SGD1. The memory cell transistors MT0 to MT7 of the NAND strings 50e provided in the first memory pillar MP and the second memory pillar MP are connected to, for example, common word lines WLe0 to WLe7. The memory cell transistors MT0 to MT7 of the NAND strings 50o provided in the first memory pillar MP and the second memory pillar MP are connected to, for example, common word lines WLo0 to WLo7. The select transistors ST2 of the NAND strings 50e provided in the first memory pillar MP and the second memory pillar MP are connected to, for example, a common even select gate line SGSe. The select transistors ST2 of the NAND strings 50o provided in the first memory pillar MP and the second memory pillar MP are, for example, each connected to a common odd-numbered select gate line SGSo.

[0084] As described above, the select transistor ST1, memory cell transistors MT0 to MT7, and select transistor ST2 included in the NAND string 50e correspond to the select transistor ST1, memory cell transistors MT0 to MT7, and select transistor ST2 included in the NAND string 50o. In two opposing transistors, the sources and drains are electrically connected to each other. Specifically, in the NAND strings 50e and 50o, the sources and drains of the opposing select transistors ST1 are electrically connected to each other, the sources and drains of the opposing memory cell transistors MT0 to MT7 are electrically connected to each other, and the sources and drains of the opposing select transistors ST2 are electrically connected to each other. This is because the channels formed in the opposing transistors share a part of the memory pillar MP.

[0085] The two NAND strings 50e, 50o in the same memory pillar MP are connected to the same bit line BL and the same source line SL.

[0086] The manner in which the select gate line SGD is selected will be described with reference to FIG. 3 and FIG. 4. When any of the select gate lines SGD0 to SGD3 is selected, a voltage that turns on the select transistor ST1 is supplied to one of the wiring layers 10-0 to 10-3 corresponding to each select gate line. For example, when the wiring layer 10-1 is selected, the eight select transistors ST1 provided in the memory pillars MP0, MP1, MP4, MP5, MP8, MP9, MP12, and MP13 are turned on. This selects eight memory cell transistors MT belonging to the memory pillar. That is, one page is formed by the eight memory cell transistors MT. The operation when a wiring layer other than the wiring layer 10-1 is selected is the same as that described above, and therefore will not be described.

[0087] In this embodiment, for example, the TLC method is applied as a write method for the memory cell transistors MT. A plurality of memory cell transistors MT to which the TLC method is applied form eight threshold distributions (write levels). The eight threshold distributions are called, for example, the "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level in order from the lowest threshold voltage. Different 3-bit data is assigned to the "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, respectively.

[0088] The semiconductor memory device 1 according to this embodiment repeatedly executes a program loop in a write operation. The program loop includes, for example, a program operation and a verify operation. The program operation is an operation of increasing the threshold voltage of a selected memory cell transistor MT by injecting electrons into a charge storage layer in the selected memory cell transistor MT. Alternatively, the program operation is an operation of maintaining the threshold voltage of the selected memory cell transistor MT by prohibiting the injection of electrons into the charge storage layer. The verify operation is an operation of checking whether the threshold voltage of the selected memory cell transistor MT has reached a target level by performing a read operation using a verify voltage following the program operation. The selected memory cell transistor MT whose threshold voltage has reached the target level is then write-prohibited.

[0089] In the semiconductor memory device 1 according to this embodiment, the threshold voltage of a selected memory cell transistor MT is raised to a target level by repeatedly executing a program loop including the above-mentioned program operation and verify operation.

[0090] The electrons stored in the charge storage layer may be stored in an unstable state. Therefore, from the time when the above-mentioned program operation is completed, the electrons stored in the charge storage layer of the memory cell transistor MT may be discharged from the charge storage layer over time. When the electrons are discharged from the charge storage layer, the threshold voltage of the memory cell transistor MT decreases. Therefore, in a read operation performed after the completion of the write operation, the read operation is performed using a read voltage lower than the verify voltage in order to deal with such a decrease in the threshold voltage of the memory cell transistor that may occur over time. The read operation may include a verify operation.

[0091] 12 and 13 are diagrams for explaining electrical connections of the sequencer 24, the voltage generating circuit 27, the driver set 28, the row decoder 29, the select gate line SGD, or the word line WL according to this embodiment. The electrical connections of the sequencer 24, the voltage generating circuit 27, the driver set 28, the row decoder 29, the select gate line SGD, or the word line WL according to this embodiment are not limited to the surface shown in FIG. 12. In the explanation of FIG. 12 and FIG. 13, explanations of configurations that are the same as or similar to those in FIG. 1 to FIG. 11 may be omitted. The circuit including the sequencer 24, the voltage generating circuit 27, the driver set 28, and the row decoder 29 is an example of a control circuit.

[0092] As shown in FIG. 12, the wiring layer 11 functioning as the even word line WLe may be electrically connected to the even word line driver 28A, and the wiring layer 11 functioning as the odd word line WLo may be electrically connected to the odd word line driver 28B. As described above, the even word line driver 28A and the odd word line driver 28B are included in the driver set 28. The driver set 28 is electrically connected to the voltage generating circuit 27. As shown in FIG. 12 and FIG. 13, the even word line driver 28A and the odd word line driver 28B may generate various voltages using the voltage supplied from the voltage generating circuit 27. Then, the even word line driver 28A may supply the generated voltage to the even word line WLe of each block BLK via the row decoder 29A. Also, the odd word line driver 28B may supply the generated voltage to the odd word line WLo of each block BLK via the row decoder 29B. The row decoder 29A and the row decoder 29B are included in the row decoder 29.

[0093] As shown in FIG. 13 and as described above, the sequencer 24 can control the driver set 28 and the like to perform various operations such as write operations and read operations.

[0094] FIG. 14 is a schematic diagram for explaining the electrical connection between the even word line driver 28A and the row decoder 29A according to the present embodiment.

[0095] Signal lines SGe0, SGe1, SGe2, and signal lines CGe0, . . . , CGe7 as signal lines CGe are connected to the even word line driver 28A. Note that, for example, the number of signal lines CGe connected is the same as the number of even word lines WL arranged in the Z direction in the block BLK.

[0096] The signal line SG0 is connected to the even-numbered select gate line SGSe in each block BLK via a transistor TR_SGe0. The transistor TR_SGe0 functions as a switch for turning on and off the signal from the signal line SGe0 by the block decoder 29A1.

[0097] The signal lines CGe0 to CGe7 are connected to the even word lines WLe0 to WLe7 in the respective blocks BLK via the transistors TR_CGe0 to TRCGe7. The transistors TR_CGe0 to TRCGe7 function as switches for turning on and off the signals from the signal lines CGe0 to CGe7 by the block decoder 29A1.

[0098] The signal line SGe1 is connected to the select gate line SGD0 in each block BLK via a transistor TR_SGe1. The transistor TR_SGe1 functions as a switch for turning on and off the signal from the signal line SGe1 by the block decoder 29A1.

[0099] The signal line SGe2 is connected to the select gate line SGD2 in each block BLK via a transistor TR_SGe2. The transistor TR_SGe2 functions as a switch for turning on and off the signal from the signal line SGe2 by the block decoder 29A1.

[0100] FIG. 15 is a schematic diagram for explaining the electrical connection between the odd-word line driver 28B and the row decoder 29B according to the present embodiment.

[0101] Signal lines SGo0, SGo1, SGo2, and signal lines CGo0 to CGo7 as signal lines CGo are connected to the odd-word line driver 28. Note that, for example, the signal lines CGo are the same in number as the odd-word lines WL arranged in the Z direction in the block BLK.

[0102] The signal line SGo0 is connected to the odd-numbered select gate line SGSo in each block BLK via a transistor TR_SGo0. The transistor TR_SGo0 functions as a switch for turning on and off the signal from the signal line SGo0 by the block decoder 29B1.

[0103] The signal lines CGo0 to CGo7 are connected to the odd word lines WLo0 to WLo7 in the respective blocks BLK via the transistors TR_CGo0 to TRCGo7. The transistors TR_CGo0 to TRCGo7 function as switches for turning on and off the signals from the signal lines CGo0 to CGo7 by the block decoder 29B1.

[0104] The signal line SGo1 is connected to the select gate line SGD1 in each block BLK via a transistor TR_SGo1. The transistor TR_SGo1 functions as a switch for turning on and off the signal from the signal line SGo1 by the block decoder 29B1.

[0105] The signal line SGo2 is connected to the select gate line SGD3 in each block BLK via a transistor TR_SGo2. The transistor TR_SGo1 functions as a switch for turning on and off the signal from the signal line SGo2 by the block decoder 29B1.

[0106] Although not shown in FIGS. 14 and 15, the select gate lines SGD and SGSe are provided with a mechanism that allows them to be connected to Vss (ground potential) when not in operation.

[0107] FIG. 16 is a schematic diagram for explaining the electrical connection between the voltage generating circuit 27 and the even word line driver 28A according to the present embodiment.

[0108] Voltages Vread, Vneg, and Vcg, which will be described later, are generated, for example, by a first charge pump circuit 27A, a second charge pump circuit 27B, and a third charge pump circuit 27C in the voltage generating circuit 27. Then, Vread, Vneg, and Vcg are held by a first regulator circuit 28A1, a second regulator circuit 28A2, and a third regulator circuit 28A3 in the even word line driver 28A, respectively. After that, Vread, Vneg, and Vcg are appropriately added together and supplied to signal lines CGe0, . . . CGe7.

[0109] FIG. 17 is a schematic diagram for explaining the electrical connection between the voltage generating circuit 27 and the odd-word line driver 28B according to the present embodiment.

[0110] Vread, Vneg, and Vcg are respectively held by a first regulator circuit 28B1, a second regulator circuit 28B2, and a third regulator circuit 28B3 in the odd-numbered word line driver 28 B. After that, Vread, Vneg, and Vcg are appropriately added together and supplied to signal lines CGe0, . . . CGe7.

[0111] (First embodiment) FIG. 18 is a diagram illustrating a schematic diagram of a change in threshold voltage of a memory cell transistor in the semiconductor memory device of the first embodiment.

[0112] After the read operation is completed and the connections between the signal lines CGe0 to CGe7 and the even word lines WLe0 to WLe7 are turned off by the transistors TR_CGe0 to TRCGe7, the effective threshold voltages of the memory cell transistors MT may vary.

[0113] For example, as shown by the dashed lines in Figure 18, the threshold voltages of the memory cell transistors MT at the "Er" level, "A" level, and "B" level are effectively higher. At this time, for example, the amount of change in the threshold voltage at the "Er" level is greater than the amount of change in the threshold voltage at the "A" level. Also, the amount of change in the threshold voltage at the "A" level is greater than the amount of change in the threshold voltage at the "B" level.

[0114] Also, for example, as shown by the dashed lines in FIG. 18, the threshold voltages of the memory cell transistors MT at the "E" level, "F" level, and "G" level are effectively lowered. At this time, for example, the amount of change in the threshold voltage at the "G" level is greater than the amount of change in the threshold voltage at the "F" level. Also, the amount of change in the threshold voltage at the "F" level is greater than the amount of change in the threshold voltage at the "E" level. Note that the manner in which the threshold voltages effectively change is not limited to that shown in FIG. 18.

[0115] If a read operation is performed in a state in which the threshold voltage has effectively changed, the accuracy of the read operation decreases.

[0116] Note that Vread is higher than the threshold voltage of the memory cell transistor MT at the "G" level. Vread is a voltage that turns on the memory cell transistor MT regardless of the data held in the memory cell transistor MT. Vread is, for example, 5V. However, Vread is not limited to 5V.

[0117] Moreover, Vneg is lower than the threshold voltage of the memory cell transistor MT at the "Er" level. Vneg is a voltage that turns off the memory cell transistor MT regardless of the data held in the memory cell transistor MT. Vneg is, for example, -3V. However, Vneg is not limited to -3V.

[0118] FIG. 19 is a diagram illustrating a timing chart of various signals during a data read operation in the semiconductor memory device of this embodiment.

[0119] An example of a read operation in the semiconductor memory device of this embodiment will be described. In the following description, a memory cell transistor MT having a control gate connected to a word line WLe4 (an example of a word line WL_e_n and a first conductive layer) will be referred to as a memory cell transistor MT4 of the NAND string 50e (an example of a first memory cell storing first information), a memory cell transistor MT having a control gate connected to a word line WLe5 (an example of a word line WL_e_n+1 and a fifth conductive layer) will be referred to as a memory cell transistor MT5 of the NAND string 50e (an example of a fifth memory cell storing fifth information), a memory cell transistor MT having a control gate connected to a word line WLe6 (an example of a word line WL_e_n+2 and a ninth conductive layer) will be referred to as a memory cell transistor MT6 of the NAND string 50e (an example of a ninth memory cell storing ninth information), a memory cell transistor MT having a control gate connected to a word line WLe3 (an example of a word line WL_e_n-1 and a third conductive layer) will be referred to as a memory cell transistor MT3 of the NAND string 50e (an example of a third memory cell storing third information), a word line WLe2 (an example of a word line WL_e_n-2 and a memory cell transistor MT having a control gate connected to a word line WLo4 (an example of a word line WL_o_n and a second conductive layer) of the NAND string 50e; a memory cell transistor MT4 (an example of a second memory cell storing second information) of the NAND string 50o; a memory cell transistor MT having a control gate connected to a word line WLo5 (an example of a word line WL_o_n+1 and a sixth conductive layer); a memory cell transistor MT5 (an example of a sixth memory cell storing sixth information) of the NAND string 50o; a memory cell transistor MT having a control gate connected to a word line WLo6 (an example of a word line WL_o_n+2 and a tenth conductive layer); a memory cell transistor MT6 (an example of a tenth memory cell storing tenth information) of the NAND string 50o; and a memory cell transistor MT having a control gate connected to a word line WLo3 (an example of a word line WL_o_n-1 and a fourth conductive layer).The memory cell transistor MT3 of the NAND string 50o (an example of a fourth memory cell storing fourth information) and the memory cell transistor MT having a control gate connected to the word line WLo2 (an example of the word line WL_o_n-1 and the eighth conductive layer) are defined as the memory cell transistor MT2 of the NAND string 50o (an example of an eighth memory cell storing eighth information).

[0120] Hereinafter, as an example, a read operation executed on a memory cell transistor MT4 that belongs to a string unit SU0 selected by select gate lines SGD0 and SGSe and is connected to a word line WLe4 will be described.

[0121] In the following, the read operation of the memory cell transistor MT4 of the NAND string 50e connected to the word line WLe4 will be described as, for example, a first operation, a second operation, a third operation, a fourth operation, a fifth operation, a sixth operation, and a seventh operation. Here, in this embodiment, the second operation is performed after the first operation. The third operation is performed after the second operation. The fourth operation is performed after the third operation. The fifth operation is performed after the fourth operation. The sixth operation is performed after the fourth operation. The seventh operation is performed after the sixth operation.

[0122] First, at time 101, a first operation is performed. The first operation is an operation to start a read operation. Specifically, the block decoder 29A1 corresponding to the block BLK to be operated outputs a high-level block selection signal BLKSEL, thereby turning on TR_CGe0, ..., TRCGe7, and connecting the signal line CGe and the word line WLe. Also, the block decoder 29B1 corresponding to the block BLK to be operated outputs a high-level block selection signal BLKSEL, thereby turning on TR_CGo0, ..., TRCGo7, and connecting the signal line CGo and the word line WLo.

[0123] Next, at time 102, a second operation is performed. Specifically, the voltage generation circuit 27 applies Vsg to the select gate lines SGSe, SGSo, SGD0, SGD1, SGD2, and SGD3. Vsg is a voltage that turns on the selection transistors ST1 and ST2 connected to the select gate lines SGSe, SGSo, SGD0, SGD1, SGD2, and SGD3.

[0124] As described above, when a read operation is performed on memory cell transistor MT4 which belongs to string unit SU0 selected by select gate line SGD0 and select gate line SGSe and is connected to word line WLe4, NAND string 50e becomes the selected NAND string (selected SU), and NAND string 50o becomes the unselected NAND string (unselected SU).

[0125] In the second operation, Vread is applied to the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, WLe7, WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7. Vread is an example of a third voltage.

[0126] The second operation is an operation in which the voltages of all word lines WLe and word lines WLo belonging to the block BLK to be operated on are increased to electrically connect the channels of the NAND strings 50e and 50o to the bit lines BL and / or source lines SL, and the potentials of the channels of the NAND strings 50e and 50o are set to constant potentials.

[0127] Next, at time 103, a third operation is performed. Specifically, Vss is applied to the select gate line SGSo, the select gate line SGD1, the select gate line SGD2, and the select gate line SGD3. This turns off the select transistor ST1 of the NAND string 50e connected to the select gate line SGD2 and the select transistor ST1 of the NAND string 50o connected to the select gate lines SGD1 and SGD3. Also, the select transistor ST2 of the NAND string 50o connected to the select gate line SGSo is turned off. In other words, the select transistor ST1 of the NAND strings 50e and 50o belonging to the string units SU1, SU2, and SU3 selected by the string units SU1, SU2, and SU3 is turned off. Also, the select transistor ST2 of the string units SU1 and SU3 selected by the select gate line SGSo is turned off. Also, Vss is a ground potential. Vss is, for example, 0V (0 volts).

[0128] In the third operation, Vcg is applied to the word line WLe4. Vcg is a read voltage used for a read operation. Vcg is an example of a first voltage. In FIG. 19, three different voltages are applied as Vcg. The types of voltages applied as Vcg are not limited to three.

[0129] In the third operation, Vneg is applied to the word lines WLo3, WLo4, and WLo5. Vneg is an example of the second voltage.

[0130] The third operation is an operation for reading information from the memory cell transistor MT4 that belongs to the string unit SU0 and is connected to the word line WLe4.

[0131] Next, at time 104, a fourth operation is performed. Specifically, Vsg is applied to select gate line SGSo, select gate line SGD1, select gate line SGD2, and select gate line SGD3. Also, Vread is applied to word line WLe4, word line WLo3, word line WLo4, and word line WLo5.

[0132] The fourth operation is an operation in which the voltages of all word lines WLe and word lines WLo belonging to the block BLK to be operated on are increased to electrically connect the channels of the NAND strings 50e and 50o to the bit lines BL and / or source lines SL, and the potentials of the channels of the NAND strings 50e and 50o are again brought to constant potentials.

[0133] Next, at time 105, a fifth operation is performed. Specifically, the voltages of the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are lowered. For example, the voltages of the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are lowered to Vss.

[0134] Next, at time 106, a sixth operation is performed. Specifically, the voltages of the word lines WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7 are lowered. For example, the voltages of the word lines WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7 are lowered to Vss. In addition, Vss is applied to the select gate lines SGSe, SGSo, SGD0, SGD1, SGD2, and SGD3.

[0135] It should be noted that Vss is an example of the fourth voltage and the fifth voltage.

[0136] Next, at time 108, a seventh operation is performed. Specifically, the block decoder 29A1 corresponding to the block BLK to be operated sets the block selection signal BLKSEL to a low level, thereby turning off TR_CGe0, ..., TRCGe7, and disconnecting the signal line CGe and the word line WLe. Also, the block decoder 29B1 corresponding to the block BLK to be operated sets the block selection signal BLKSEL to a low level, thereby turning off TR_CGo0, ..., TRCGo7, and disconnecting the signal line CGo and the word line WLo.

[0137] Next, the effects of the semiconductor memory device of this embodiment will be described.

[0138] Fig. 22 is a diagram showing a timing chart of various signals during a data read operation in a semiconductor memory device of a comparative embodiment. The semiconductor device of the comparative embodiment is different from the semiconductor device of the embodiment shown in Fig. 19 in that the fifth and sixth operations are performed together. 19, in the first embodiment, the voltage of the word line WLe is lowered as a fifth operation at time 105, and the voltages of the word line WLo, select gate line SGD, and select gate line SGS are lowered as a sixth operation at the following time 106. In contrast, in the comparative embodiment, the voltage of the word line WLe is lowered as a fifth operation at time 206, and the voltages of the word line WLo, select gate line SGD, and select gate line SGS are lowered as a sixth operation at time 206, as shown in FIG.

[0139] After the voltage of the select gate line SG is lowered as the fifth and sixth operations at time 206, when the voltage of the select gate line SG becomes lower than the threshold voltage of the select transistor ST at time 207, the select transistor ST is turned off as shown in FIG. 23. As a result, the channel of the NAND string 50e and the channel of the NAND string 50o are in a floating state. In this state, when the voltage of the word line WL is further lowered, the voltage of the channel of the NAND string 50e and the channel of the NAND string 50o is further lowered through the capacitive coupling between the word line WL and the channel, and becomes a negative voltage (a voltage lower than the voltage Vss). For example, if the voltage of the word line WLe and the word line WLo is Vint at the time when the select transistor ST is turned off, the voltage of the channel of the NAND string 50e and the channel of the NAND string 50o becomes −Vint from Vss (0V). That is, electrons remain in the channel of the NAND string 50e and the channel of the NAND string 50o. Note that the voltage Vint is a schematic voltage. The electrons in the channel are gradually discharged to the bit line BL and the source line SL via the select transistor ST, for example. As a result, the voltage of the channel gradually approaches Vss (0 V) from a negative voltage, as shown in FIG.

[0140] In this state, at time 208, as a seventh operation, the signal line CGe and the word line WLe are disconnected, and the signal line CGo and the word line WLo are disconnected, so that the word lines WLe and WLo are in a floating state. Then, due to an increase in the channel voltage caused by the movement of electrons from inside the channel to outside the channel, the voltage of the word line WL gradually increases through the capacitive coupling between the word line WL and the channel. For example, by maintaining the state in which the voltage of the word line WL is increased in this way, the threshold voltages of all the memory cell transistors MT included in a certain block BLK may effectively change as shown in FIG. 18. In this case, in order to suppress the effective change in the threshold voltage of the memory cell transistor MT, It is preferable to suppress the rise in voltage of the word line WL after the read operation is completed.

[0141] Therefore, in the semiconductor memory device of the embodiment, as shown in FIG. 19, after performing the fifth operation at time 105 to lower the voltage of the word line WLe, the sixth operation is performed at time 106 to lower the voltages of the word line WLo, the select gate line SGD, and the select gate line SGS. Here, as described with reference to FIG. 11, two NAND strings 50e and 50o are formed in one memory pillar MP, and the opposing memory cell transistors MT0 to MT7 share a channel. As a result, as shown in FIG. 20, after the fifth operation and before the sixth operation, the memory cell transistor MT connected to the word line WLo can be kept on even if the voltage of the word line WLe drops. Therefore, the channel of the NAND string 50e is electrically connected to the bit line BL and / or the source line BL via the channel of the NAND string 50o, and the voltage is maintained without becoming a negative voltage. In this state, when the sixth operation is performed at time 106 to lower the voltages of the word line WLo, the select gate line SGD, and the select gate line SGS, the select transistor ST is turned off as shown in FIG. 21. As a result, the channel of the NAND string 50e and the channel of the NAND string 50o are in a floating state. In this state, when the voltage of the word line WL is further lowered, the voltages of the channels of the NAND string 50e and the NAND string 50o become negative voltages (voltages lower than the voltage Vss) through the capacitive coupling between the word line WL and the channel. On the other hand, the channels of the NAND string 50e and the NAND string 50o are also capacitively coupled with the word line WLe, which is already at the voltage Vss. Therefore, for example, if the voltage of the word line WLo is Vint at the time when the select transistor ST is turned off, the voltages of the channels of the NAND string 50e and the NAND string 50o become −Vint / 2 from Vss (0V). Therefore, according to the first embodiment, it is possible to suppress a decrease in the channel voltage caused by the capacitive coupling between the word line WL and the channel, compared to the comparative embodiment. This makes it possible to suppress an increase in the voltage of the word line WL caused by the capacitive coupling between the word line WL and the channel, which occurs when electrons in the channel move out of the channel. In addition, it is possible to suppress a change in the effective threshold voltage of the memory cell transistor. That is, according to the first embodiment, it is possible to provide a semiconductor memory device in which the change in the effective threshold voltage of the memory cell transistor is suppressed, compared to the comparative embodiment.

[0142] FIG. 25 is a diagram illustrating a timing chart of various signals during a data read operation in a semiconductor memory device according to a modification of this embodiment.

[0143] The first, second, third and fourth operations of the semiconductor memory device of the modification of this embodiment are similar to the first, second, third and fourth operations of the semiconductor memory device of this embodiment.

[0144] Next, the fifth operation is performed. Specifically, the voltages of the word lines WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7 are lowered. For example, the voltages of the word lines WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7 are lowered to Vss.

[0145] Next, a sixth operation is performed. Specifically, the voltages of the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are lowered. For example, the voltages of the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are lowered to Vss. In addition, Vss is applied to the select gate lines SGSe, SGSo, SGD0, and SGD1.

[0146] The seventh operation is similar to the seventh operation of the semiconductor memory device of the present embodiment.

[0147] In the semiconductor memory device of the modified embodiment of the present invention, the voltages of the word lines WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7 are lowered, and then the voltages of the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are lowered. This allows the memory cell transistor MT connected to the word line WLe to be kept on even if the voltage of the word line WLo is lowered. This allows the increase in the voltage of the word line WL caused by the capacitive coupling between the word line WL and the channel, which occurs when electrons in the channel move out of the channel, to be suppressed.

[0148] According to the semiconductor memory device of this embodiment, it is possible to provide a semiconductor memory device capable of suppressing fluctuations in the threshold voltage of the memory cell transistor.

[0149] Second embodiment FIG. 26 is a diagram illustrating a timing chart of various signals during a data read operation in the semiconductor memory device of this embodiment.

[0150] In the semiconductor memory device of this embodiment, after the sixth operation of the semiconductor memory device of the first embodiment, the voltages of WLe0, word line WLe1, word line WLe2, word line WLe3, word line WLe4, word line WLe5, word line WLe6 and word line WLe7 are increased.

[0151] For example, in the fifth operation, the voltages of the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are lowered to Vneg. Next, in the sixth operation, the voltages of the word lines WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7 are lowered to Vss. Also, Vss is applied to the select gate lines SGSe, SGSo, SGD0, and SGD1. Next, the voltages of the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are increased to, for example, Vss. Next, the seventh operation of the semiconductor memory device of the first embodiment is performed.

[0152] In the semiconductor memory device of this embodiment, Vneg is an example of the second voltage and the fourth voltage.

[0153] In the semiconductor memory device of this embodiment, Vss is an example of a fifth voltage and a sixth voltage.

[0154] In the semiconductor memory device of this embodiment, the voltages of the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are lowered to Vneg, which is lower than Vss. Even in this case, the channel potential is maintained. Next, the voltages of the word lines WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7 are lowered to Vss. Here, for example, Vss is applied to select gate line SGSe, select gate line SGSo, select gate line SGD0, and select gate line SGD1, and the voltages of word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are increased to Vss at the timing when the channel is about to become floating. Then, the decrease in channel voltage caused by the decrease in voltage of word line WLo is cancelled out by the increase in channel voltage caused by the increase in voltage of word line WLe. This makes it possible to provide a semiconductor memory device capable of suppressing fluctuations in the threshold voltage of memory cell transistors.

[0155] In addition, in the semiconductor memory device of the modified example of this embodiment, after the sixth operation of the semiconductor memory device of the modified example of the first embodiment, the voltages of WLe0, word line WLe1, word line WLe2, word line WLe3, word line WLe4, word line WLe5, word line WLe6 and word line WLe7 may be increased.

[0156] For example, in the fifth operation of the semiconductor memory device according to the modified example of the first embodiment, the voltages of the word lines WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7 are lowered to, for example, Vneg. Next, in the sixth operation, the voltages of the word lines WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, and WLe7 are lowered to, for example, Vss. Also, Vss is applied to the select gate lines SGSe, SGSo, SGD0, and SGD1. Next, the voltages of the word lines WLo0, WLo1, WLo2, WLo3, WLo4, WLo5, WLo6, and WLo7 are increased to, for example, Vss. Next, a seventh operation is performed in the semiconductor memory device of the first embodiment, which makes it possible to provide a semiconductor memory device capable of suppressing fluctuations in the threshold voltage of the memory cell transistor.

[0157] In the semiconductor memory device according to the modified example of this embodiment, Vneg is an example of the second voltage and the fourth voltage.

[0158] In the semiconductor memory device according to the modified example of this embodiment, Vss is an example of the fifth voltage and the sixth voltage.

[0159] Although some embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0160] 1: Semiconductor memory device 2: Memory controller 3: Memory system 10: Wiring layer 11: Wiring layer 12: Wiring layer 13: Source line layer 16: Contact plug 17: Contact plug 18: Metal wiring layer 19: Contact plug 20: Metal wiring layer 21: Memory cell array 22: Input / output circuit 23: Logic control circuit 24: Sequencer 25: Register 26: Busy control circuit 27: Voltage generation circuit 27A: First charge pump circuit 27B: Second charge pump circuit 27C: Third charge pump circuit 28: Driver set 28A: Even word line driver 28A1: First regulator circuit 28A2: Second regulator circuit 28A3: Third regulator circuit 28B: Odd word line driver 28B1: First regulator circuit 28B2: Second regulator circuit 28B3: Third regulator circuit 29: Row decoder 29A: Row decoder 29B: Row decoder 30: Sense amplifier 31: Semiconductor layer 32: Insulation layer 33: Insulation layer 34: Insulation layer 35: AlO layer 36: Barrier metal layer 37: Insulation layer 40: Semiconductor layer 41: Insulation layer 42: Conductive layer 43: Insulation layer 45: AlO layer 46: Insulation layer 47: Barrier metal layer 48: Insulation layer 50: NAND string 70: Sense amplifier 71: Input / output pad group 72: Logic control pad group BL: Bit line BLK: Block C: Coupling capacitance CEn: Chip enable signal CG: Signal line CLE: Command latch enable signal CMD: Command DAT: Data DQ: Signal SU: String unit MP: Same memory pillar MT: Memory cell transistor R: Resistance component REn: Read enable signal SG: Signal line SGD: Select gate line SGS: Select gate line SL: Source line SL: Slit ST: Select transistor STS: Status information WLe: Even word line WLo: Odd word line WPn: Write protect signal

Claims

1. A substrate; a memory pillar extending in a first direction from the substrate; a first conductive layer provided on the substrate, spaced apart from the substrate in the first direction, parallel to a substrate surface of the substrate, and facing the memory pillar; a second conductive layer disposed on the substrate, adjacent to the first conductive layer via the memory pillar in a second direction intersecting the first direction, parallel to the substrate surface, and facing the memory pillar; a third conductive layer provided between the substrate and the first conductive layer and parallel to the substrate surface and facing the memory pillar; a fourth conductive layer between the substrate and the second conductive layer, adjacent to the third conductive layer in the second direction via the memory pillar, and provided parallel to the substrate surface and facing the memory pillar; a fifth conductive layer provided on the first conductive layer in parallel with the substrate surface and facing the memory pillar; a sixth conductive layer disposed on the second conductive layer, adjacent to the fifth conductive layer in the second direction with the memory pillar interposed therebetween, parallel to the substrate surface, and facing the memory pillar; a seventh conductive layer provided between the substrate and the third conductive layer, parallel to the substrate surface, and facing the memory pillar; an eighth conductive layer between the substrate and the fourth conductive layer, adjacent to the seventh conductive layer in the second direction with the memory pillar interposed therebetween, and provided parallel to the substrate surface and facing the memory pillar; a ninth conductive layer provided on the fifth conductive layer in parallel with the substrate surface and facing the memory pillar; a tenth conductive layer disposed on the sixth conductive layer, adjacent to the ninth conductive layer in the second direction with the memory pillar interposed therebetween, parallel to the substrate surface, and opposed to the memory pillar; a first memory cell formed between the first conductive layer and the memory pillar; a second memory cell formed between the second conductive layer and the memory pillar; a third memory cell formed between the third conductive layer and the memory pillar; a fourth memory cell formed between the fourth conductive layer and the memory pillar; a fifth memory cell formed between the fifth conductive layer and the memory pillar; a sixth memory cell formed between the sixth conductive layer and the memory pillar; a seventh memory cell formed between the seventh conductive layer and the memory pillar; an eighth memory cell formed between the eighth conductive layer and the memory pillar; a ninth memory cell formed between the ninth conductive layer and the memory pillar; a tenth memory cell formed between the tenth conductive layer and the memory pillar; applying a first voltage to the first conductive layer, applying a second voltage lower than the first voltage to the second conductive layer, the fourth conductive layer, and the sixth conductive layer, and applying a third voltage higher than the first voltage to the third conductive layer, the fifth conductive layer, the seventh conductive layer, the eighth conductive layer, the ninth conductive layer, and the tenth conductive layer, and then applying the third voltage to the first conductive layer, the second conductive layer, the fourth conductive layer, and the sixth conductive layer; and then applying a fourth voltage lower than the first voltage to the first conductive layer, the third conductive layer, the fifth conductive layer, the seventh conductive layer, and the ninth conductive layer; and applying a fifth voltage lower than the first voltage to the second conductive layer, the fourth conductive layer, the sixth conductive layer, the eighth conductive layer, and the tenth conductive layer; A control circuit; A semiconductor memory device comprising:

2. the fourth voltage and the fifth voltage are higher than the second voltage; the fourth voltage and the fifth voltage are equal; The semiconductor device according to claim 1.

3. The control circuit includes: After applying the fifth voltage, which is lower than the first voltage, to the second conductive layer, the fourth conductive layer, the sixth conductive layer, the eighth conductive layer, and the tenth conductive layer, applying a sixth voltage lower than the first voltage and higher than the fourth voltage to the first conductive layer, the third conductive layer, the fifth conductive layer, the seventh conductive layer, and the ninth conductive layer; 2. The semiconductor memory device according to claim 1.

4. the second voltage and the fourth voltage are equal; the fifth voltage and the sixth voltage are equal; 4. The semiconductor memory device according to claim 3.

5. A substrate; a memory pillar extending in a first direction from the substrate; a first conductive layer provided on the substrate, spaced apart from the substrate in the first direction, parallel to a substrate surface of the substrate, and facing the memory pillar; a second conductive layer disposed on the substrate, adjacent to the first conductive layer via the memory pillar in a second direction intersecting the first direction, parallel to the substrate surface, and facing the memory pillar; a third conductive layer provided between the substrate and the first conductive layer and parallel to the substrate surface and facing the memory pillar; a fourth conductive layer between the substrate and the second conductive layer, adjacent to the third conductive layer in the second direction via the memory pillar, and provided parallel to the substrate surface and facing the memory pillar; a fifth conductive layer provided on the first conductive layer in parallel with the substrate surface and facing the memory pillar; a sixth conductive layer disposed on the second conductive layer, adjacent to the fifth conductive layer in the second direction with the memory pillar interposed therebetween, parallel to the substrate surface, and facing the memory pillar; a seventh conductive layer provided between the substrate and the third conductive layer, parallel to the substrate surface, and facing the memory pillar; an eighth conductive layer between the substrate and the fourth conductive layer, adjacent to the seventh conductive layer in the second direction with the memory pillar interposed therebetween, and provided parallel to the substrate surface and facing the memory pillar; a ninth conductive layer provided on the fifth conductive layer in parallel with the substrate surface and facing the memory pillar; a tenth conductive layer disposed on the sixth conductive layer, adjacent to the ninth conductive layer in the second direction with the memory pillar interposed therebetween, parallel to the substrate surface, and opposed to the memory pillar; a first memory cell formed between the first conductive layer and the memory pillar; a second memory cell formed between the second conductive layer and the memory pillar; a third memory cell formed between the third conductive layer and the memory pillar; a fourth memory cell formed between the fourth conductive layer and the memory pillar; a fifth memory cell formed between the fifth conductive layer and the memory pillar; a sixth memory cell formed between the sixth conductive layer and the memory pillar; a seventh memory cell formed between the seventh conductive layer and the memory pillar; an eighth memory cell formed between the eighth conductive layer and the memory pillar; a ninth memory cell formed between the ninth conductive layer and the memory pillar; a tenth memory cell formed between the tenth conductive layer and the memory pillar; applying a first voltage to the first conductive layer, applying a second voltage lower than the first voltage to the second conductive layer, the fourth conductive layer, and the sixth conductive layer, and applying a third voltage higher than the first voltage to the third conductive layer, the fifth conductive layer, the seventh conductive layer, the eighth conductive layer, the ninth conductive layer, and the tenth conductive layer, and then applying the third voltage to the first conductive layer, the second conductive layer, the fourth conductive layer, and the sixth conductive layer; and then applying a fourth voltage lower than the first voltage to the second conductive layer, the fourth conductive layer, the sixth conductive layer, the eighth conductive layer, and the tenth conductive layer; and then applying a fifth voltage lower than the first voltage to the first conductive layer, the third conductive layer, the fifth conductive layer, the seventh conductive layer, and the ninth conductive layer; A control circuit; A semiconductor memory device comprising:

6. the fourth voltage and the fifth voltage are higher than the second voltage; the fourth voltage and the fifth voltage are equal; 6. The semiconductor device according to claim 5.

7. The control circuit includes: After applying the fifth voltage to the first conductive layer, the third conductive layer, the fifth conductive layer, the seventh conductive layer, and the ninth conductive layer, applying a sixth voltage lower than the first voltage and higher than the fourth voltage to the second conductive layer, the fourth conductive layer, the sixth conductive layer, the eighth conductive layer, and the tenth conductive layer; 6. The semiconductor memory device according to claim 5.

8. the second voltage and the fourth voltage are equal; the fifth voltage and the sixth voltage are equal; 8. The semiconductor memory device according to claim 7.

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