Semiconductor device

Abstract

To provide a semiconductor device that has a transfer switch circuit capable of transferring a high voltage, and has high reliability while preventing an increase in area.SOLUTION: An E-type transistor TR2 is provided, which is a switch element configured to apply a voltage to and block the voltage from a gate electrode of a memory cell. The E-type transistor TR2 includes a pair of diffusion layers 8 formed opposite to each other with a control gate 1 interposed therebetween. The E-type transistor TR2 is electrically connected to a voltage source that provides a voltage of 15 V or more. A first wiring layer and a second wiring layer are laminated in order above the E-type transistor TR2. A wiring 15 connected to the control gate 1 is formed in the first wiring layer. The wiring 15 is formed above the control gate 1 within an active region of the E-type transistor TR2, and is formed so as to extend continuously to at least one of the pair of diffusion layers 8 by 0.1 μm or more.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] To write or erase data to a NAND-type nonvolatile memory, a positive voltage of, for example, 15 V or more is applied to the semiconductor channel or gate electrode in which the memory cell is formed. In order to selectively apply the voltage required for writing, reading, or erasing to the semiconductor channel or gate electrode, a transfer switch circuit that transfers high voltage is provided between the voltage source and the memory cell. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2009 / 0161427 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present embodiment is to provide a semiconductor device including a transfer switch circuit capable of transferring a high voltage, which has high reliability while suppressing an increase in area. [Means for solving the problem]

[0005] The semiconductor device of the present invention comprises an electrically programmable and erasable memory cell transistor, a selection transistor formed by connecting current terminals of the memory cell transistors in series and connected to one end of the selection transistor, and a switch element provided for applying and blocking a voltage to the gate electrode of the memory cell transistor in order to control the threshold value of the memory cell transistor. The switch element is a first n-type MOSFET having a gate insulating film thickness in the range of 13 nm to 50 nm and having a first end of the current terminal formed thereon. The first n-type MOSFET has a first source diffusion layer and a first drain diffusion layer having a first n-type impurity density and formed near the gate electrode, and a second source diffusion layer and a second drain diffusion layer having a second n-type impurity density higher than the first impurity density and formed with a contact electrode. The second end of the first n-type MOSFET is electrically connected to a voltage source that provides a voltage of 15 V or more. A first wiring layer is formed on the upper side of the semiconductor substrate of the first n-type MOSFET, and a second wiring layer is further formed above the first wiring layer. A first wiring connected to the gate electrode of the first n-type MOSFET is formed in the first wiring layer. The first wiring is formed on the gate electrode within the active region of the first n-type MOSFET, and is further formed continuously extending by 0.1 μm or more onto the first source diffusion layer or the first drain diffusion layer. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram illustrating an example of a configuration of a NAND type nonvolatile memory to which a first embodiment is applied. [Diagram 2] 2 is an equivalent circuit diagram of one NAND cell in the memory cell array 101. FIG. [Diagram 3] FIG. 1 is a diagram showing an equivalent circuit of a memory cell array 101 in which NAND cells are arranged in a matrix. [Figure 4] FIG. 2 is a circuit diagram illustrating an example of a high voltage switch. [Diagram 5]FIG. 11 is a diagram illustrating an example of a voltage waveform during a switch operation in a comparative example. [Figure 6] 11 is a plan view illustrating an example of the structure of an E-type transistor TR2 in the comparative example. FIG. [Figure 7A] 7 shows a cross-sectional view taken along line AA' shown in FIG. [Figure 7B] 7 shows a cross-sectional view taken along line BB' shown in FIG. [Figure 7C] 7 shows a cross-sectional view taken along line CC' shown in FIG. [Figure 7D] 7 shows a cross-sectional view taken along line DD' shown in FIG. 6. [Figure 8] FIG. 11 is a plan view illustrating an example of the structure of a D-type transistor TR1 in the comparative example. [Figure 9A] 9 shows a cross-sectional view taken along line AA' shown in FIG. [Figure 9B] 9 shows a cross-sectional view taken along line BB' shown in FIG. [Figure 9C] 9 shows a cross-sectional view taken along line CC' shown in FIG. [Figure 9D] 9 shows a cross-sectional view taken along line DD' shown in FIG. [Figure 10A] FIG. 11 is a diagram showing the fluctuation in resistance value of a diffusion layer 8 in a comparative example. [Figure 10B] FIG. 11 is a diagram showing the fluctuation in resistance value of a diffusion layer 8 in a comparative example. [Figure 11] 2 is a plan view illustrating an example of the structure of an E-type transistor TR2 in the first embodiment. FIG. [Figure 12A] 12 shows a cross-sectional view taken along line AA' shown in FIG. [Figure 12B] 12 shows a cross-sectional view taken along line BB' shown in FIG. [Figure 12C] 12 shows a cross-sectional view taken along line CC' shown in FIG. [Figure 12D] 12 shows a cross-sectional view taken along line DD' shown in FIG. [Figure 13] 2 is a plan view illustrating an example of the structure of a D-type transistor TR1 in the first embodiment. FIG. [Figure 14A] 14 shows a cross-sectional view taken along line AA' shown in FIG. [Figure 14B] 14 shows a cross-sectional view taken along line BB' shown in FIG. [Figure 14C] 14 shows a cross-sectional view taken along line CC' shown in FIG. [Figure 14D] 14 shows a cross-sectional view taken along line DD' shown in FIG. [Figure 15] FIG. 4 is a diagram illustrating an example of a voltage waveform during a switch operation in the first embodiment. [Figure 16] 11 is a plan view illustrating an example of the structure of an E-type transistor TR2 in a modified example of the first embodiment. FIG. [Figure 17A] 17 shows a cross-sectional view taken along line AA' shown in FIG. [Figure 17B] 17 shows a cross-sectional view taken along line CC' shown in FIG. [Figure 18] FIG. 11 is a plan view illustrating an example of the structure of a D-type transistor TR1 in a modified example of the first embodiment. [Figure 19A] 19 shows a cross-sectional view taken along line AA' shown in FIG. [Figure 19B] 19 shows a cross-sectional view taken along line CC' shown in FIG. [Figure 20] 13 is a plan view illustrating an example of the structure of an E-type transistor TR2 in another modified example of the first embodiment. FIG. [Figure 21] FIG. 13 is a plan view illustrating an example of the structure of a D-type transistor TR1 in another modified example of the first embodiment. [Figure 22] 13 is a plan view illustrating an example of the structure of an E-type transistor TR2 in the second embodiment. FIG. [Figure 23A] 23 shows a cross-sectional view taken along line AA' shown in FIG. [Figure 23B] 23 shows a cross-sectional view taken along line BB' shown in FIG. [Figure 23C] 23 shows a cross-sectional view taken along line CC' shown in FIG. [Figure 23D]23 shows a cross-sectional view taken along line DD' shown in FIG. [Figure 24] FIG. 11 is a circuit diagram illustrating an example of a high voltage switch according to a third embodiment. [Diagram 25] FIG. 13 is a diagram illustrating an example of a voltage waveform during a switch operation according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. (First embodiment) FIG. 1 is a block diagram showing an example of the configuration of a NAND type nonvolatile memory to which the first embodiment is applied. As shown in FIG. 1, the NAND type nonvolatile memory of the embodiment is composed of a memory cell array 101 and a peripheral circuit section. The peripheral circuit section is a section that drives a circuit according to an external signal and performs program writing and erasing operations. The peripheral circuit section includes a bit line control circuit (sense amplifier and data latch) 102, a column decoder 103, an address buffer 104, a row decoder 105, a data input / output buffer 106, and a substrate potential control circuit 107. The peripheral circuit section also includes a voltage source circuit group 120 and a high voltage transfer switch circuit 121. The voltage source circuit group 120 also includes a write high voltage generation circuit 109, a write intermediate voltage generation circuit 110, a read intermediate voltage generation circuit 111, and an erase high voltage generation circuit 112.

[0008] The memory cell array 101 includes multiple EEPROM (Electrically Erasable Programmable Read-Only Memory) memory cells. EEPROM memory cells usually have a MOSFET (Metal-Oxide-Semivonductor Field Effect Transistor) structure in which a charge storage layer and a control gate are stacked on a semiconductor channel. This memory cell stores data in a non-volatile manner based on the difference in threshold between the state in which charges are injected into the charge storage layer and the state in which the charges are discharged. Charges are injected and discharged by a tunnel current through a tunnel insulating film between the charge storage layer and the substrate channel.

[0009] Among EEPROMs, the so-called NAND type EEPROM, which is a NAND cell unit formed by connecting multiple memory cells in series, requires fewer select transistors than NOR type EEPROM, making it possible to achieve high density. Also, in NOR type flash memory, in order to make it less susceptible to the short channel effect during erasure, a tunnel current is passed through a tunnel insulating film between the charge storage layer and the substrate channel to erase. For example, in order to increase the number of memory cells erased per unit time, multiple memory cells are erased simultaneously. For this purpose, a positive voltage of 15V or more is applied to the gate electrode of the semiconductor channel in which the memory cell is formed, to extract electrons from the charge storage layer to the substrate, or to inject holes and recombine with the electrons. On the other hand, when writing, the semiconductor channel voltage is kept at 0V, and a voltage of 15V or more is applied to the word line connected to the gate electrode of the selected memory cell to inject electrons from the channel into the charge storage layer, thereby writing to the memory cell. In this way, in NAND type EEPROM, a voltage of 15V or more is applied to the semiconductor channel and gate electrode.

[0010] FIG. 2 is an equivalent circuit diagram of one NAND cell in the memory cell array 101. The memory cell of the NAND type nonvolatile memory has a MOSFET structure in which a charge storage layer and a control gate electrode are stacked on a semiconductor channel via an insulating film. The source-drain electrodes (current terminals) of adjacent memory cells M1 to M8 are connected in series to form one NAND cell. Furthermore, between the end memory cell M1 and the bit line BL, which is a data transfer line, a select gate transistor ST1 is formed for switching between selected and unselected memory cell blocks. On the other hand, between the opposite end memory cell M8 and the source line SL, a select gate transistor ST2 is formed for switching between selected and unselected memory cell blocks. In FIG. 2, the number of memory cells constituting one NAND cell is eight, but of course it may be eight or more, for example, 96, 112, 128, 256, or more. Also, one NAND cell may be formed of seven or less memory cells.

[0011] FIG. 3 is a diagram showing an equivalent circuit of a memory cell array 101 in which NAND cells are arranged in a matrix. FIG. 3 shows an example of the configuration of a memory cell array 101 in which the NAND cell assembly structure shown in FIG. 2 is densely integrated. The control gate electrodes of adjacent memory cells M1 are connected in parallel. These parallel-connected control gate electrodes are shared by the parallel-connected memory cells M1 as a select gate line CG(1). The same is true for memory cells M2 to M8. That is, the control gate electrodes of adjacent memory cells M2, M3, ..., M8 are connected in parallel. These parallel-connected control gate electrodes are shared by the parallel-connected memory cells M2, M3, ..., M8 as select gate lines CG(2), CG(3), ..., CG(8). The select gate lines CG(1) to CG(8) forming the control gate lines of the memory cells M1 to M8 are also called word lines WL.

[0012] The control gate electrodes of adjacent select transistors ST1 are also connected in parallel. These parallel-connected control gate electrodes are shared by the parallel-connected select transistors ST1 as a select gate line SG(1). The same is true for select transistor ST2.

[0013] Furthermore, bit lines BL, which are data transfer lines, are formed in a direction perpendicular to each of the select gate lines CG(1), CG(2), ..., CG(8), SG(1), and SG(2). The bit lines BL are connected to one end of the source-drain electrode of the select gate transistor ST1 arranged in a direction perpendicular to the bit lines BL. Meanwhile, source lines SL are formed in a direction parallel to the select gate lines CG(1), CG(2), ..., CG(8), SG(1), and SG(2). The source lines SL are connected to one end of the source-drain electrode of the select gate transistor ST2. As a result, a plurality of memory cells are densely arranged in a matrix, forming a circuit equivalent to the memory cell array 101. In FIG. 3, a collection of a plurality of NAND cells surrounded by a dotted rectangle is called a block.

[0014] Returning to Fig. 1, the peripheral circuitry of the NAND type nonvolatile memory of the embodiment will be described. The bit line control circuit 102 is a circuit for writing and reading data to and from the memory cell array 101. The bit line control circuit 102 is mainly composed of a CMOS flip-flop, and performs operations such as latching data for writing and sensing the potential of the bit line BL for reading. The bit line control circuit 102 is connected to a data input / output buffer 106. The bit line control circuit 102 transmits and receives write data and read data to and from an external device via the data input / output buffer 106.

[0015] The address buffer 104 receives an address ADR from an external device, which is the target of data writing / reading. Based on the received address ADR, the address buffer 104 outputs a row address to the row decoder 105 and a column address to the column decoder 103. The column decoder 103 decodes the column address input from the address buffer 104 and outputs it to the bit line control circuit 102. The bit line control circuit 102 selects one of the bit lines based on the decoded column address. When reading data, the control circuit detects and amplifies data read from the memory cell to the bit line. When writing data, the control circuit transfers write data to the bit line.

[0016] The row decoder 105 decodes the row address input from the address buffer 104, and selects a block to be read or written based on the decoded row address. The row decoder 105 then transfers a plurality of voltages required for write, read, and erase operations to the select gate lines CG(1), CG(2), ..., CG(8), SG(1), and SG(2) of the selected block. The NAND type nonvolatile memory needs to transfer a voltage higher than the power supply voltage (for example, 5V or less) to the control gate electrodes of the memory cells in the selected block. For this reason, the row decoder 105 includes a voltage conversion circuit (so-called level shifter) that converts the power supply voltage supplied from the outside into a high voltage.

[0017] The substrate potential control circuit 107 controls the potential of a silicon substrate (or a well region in which memory cells are formed) on which the memory cell array 101 is formed. The voltage source circuit group 120 generates voltages required by memory cells and the like when writing or reading. The voltage source circuit group 120 includes several types of voltage generation circuits according to the level of the voltage to be generated and the purpose of use. For example, as shown in FIG. 1, the voltage source circuit group 120 includes four voltage generation circuits, namely, a write high voltage generation circuit 109, a write intermediate voltage generation circuit 110, a read intermediate voltage generation circuit 111, and an erase high voltage generation circuit 112. In the memory cell array 101, a high voltage transfer switch circuit 121 is formed between the row decoder 105 and the voltage source circuit group 120 to selectively apply voltages required for writing, reading, and erasing to the control gate electrodes of memory cells in a selected block.

[0018] FIG. 4 is a circuit diagram showing an example of a high-voltage switch that transfers the voltage generated by the write high-voltage generating circuit 109 to the row decoder 105 in the high-voltage transfer switch circuit 121. The high-voltage switch shown in FIG. 4 is formed of a high-voltage transistor and controls the passage and interruption of a high voltage. The high-voltage switch is mainly used in the high-voltage transfer switch circuit 121, but may also be used in other peripheral circuits. The high-voltage transfer switch circuit 121 is provided with high-voltage switches shown in FIG. 4 corresponding to each of a plurality of paths for transferring a voltage from the voltage source circuit group 120 to the row decoder 105. For example, the voltages generated by the write intermediate voltage generating circuit 110, the read intermediate voltage generating circuit 111, and the erase high-voltage generating circuit 112 are transferred by different high-voltage transfer switch circuits. The high-voltage transfer switch circuit 121 shown in FIG. 4 may be used for these high-voltage transfer switch circuits.

[0019] 4, in the high-voltage switch of the embodiment, a high-voltage depletion-type MOS transistor (hereinafter referred to as a D-type transistor) TR1 and a high-voltage enhancement-type MOS transistor (hereinafter referred to as an E-type transistor) TR2 are inserted in series between an input terminal Tin and an output terminal Tout. That is, the D-type transistor TR1 and the E-type transistor TR2 are connected via a node N2. The gate electrodes of the D-type transistor TR1 and the E-type transistor TR2 are commonly connected to a terminal Tg. The E-type transistor TR2 (first n-type MOSFET) is a so-called switch element, and the D-type transistor TR1 functions as a resistance element for the switch element.

[0020] A discharge circuit is provided between the E-type transistor TR2 and the output terminal Tout. In FIG. 4, the output side of the E-type transistor TR2 is grounded via a resistor R1 and a switch S1. The high-voltage switch is usually used with the switch S1 open (non-conducting state), and when discharging the voltage (hereinafter referred to as the output voltage) Vout of the output terminal Tout, the switch S1 is closed. In this way, the high-voltage switch shown in FIG. 4 is a switch circuit that outputs or blocks the voltage (hereinafter referred to as the input voltage) Vin applied to the input terminal Tin to the output terminal Tout. The switch operation is controlled by the voltage (hereinafter referred to as the gate voltage) Vg applied from the terminal Tg to the gate electrode of the D-type transistor TR1 and the gate electrode of the E-type transistor TR2, and the discharge by the switch S1. The discharge method is not limited to the above-mentioned circuit or method. For example, it may be connected to a power source with a lower voltage than the input voltage Vin via another high-voltage switch formed in the high-voltage transfer switch circuit 121.

[0021] Prior to the description of the high-voltage switch of the embodiment, the operation and structure of a high-voltage switch of a comparative example will be described. FIG. 5 is a diagram showing an example of a voltage waveform during switch operation in the comparative example. FIG. 5 shows, from the top to the bottom, the waveforms of the gate voltage Vg, the input voltage Vin, the voltage of the node N2 (hereinafter referred to as the node N2 voltage Vn2), and the output voltage Vout. In addition, the vertical axis of each waveform is voltage and the horizontal axis is time. FIG. 5 shows a voltage waveform in a sequence in which the voltage Vp3 applied to the input terminal Tin is transferred to the output terminal Tout three times and discharged twice between each transfer. For example, after applying a write voltage of the voltage Vp3 to the gate electrode of a memory cell, a so-called verify operation is performed to check whether the threshold value of the memory cell has been sufficiently written. In FIG. 5, periods tc1 and tc2 are the time range of the verify operation, and periods tb1, tb2, and tb3 are the time range of the write operation to the memory cell. After the write operation, in order to input a voltage lower than voltage Vp3 (for example, a voltage of 10 V or less required for reading) to the row decoder 105, the output terminal Tout needs to be discharged. In FIG. 5, the output terminal Tout is discharged twice, at periods tc1 and tc2.

[0022] In the sequence of FIG. 5, the voltage Vp3 is set to a voltage of 15V or more and 30V or less. For example, the voltage Vp1 applied to the terminal Tg is set to a voltage of 17V or more and 35V or less. In the above sequence, the output voltage Vout and the gate voltage Vg are set to the GND potential as the initial reset voltage so that the difference between the comparative example and the embodiment is clear. In addition, in three periods of periods tb1, tb2, and tb3, the voltage Vp3 given as the input voltage Vin is transferred to the output voltage Vout, making it easy to understand the change in the voltage waveform caused by the repeated voltage transfer. Repeated voltage transfers as in the above sequence are performed as a well-known method for, for example, verifying whether the memory cell has been sufficiently written and realizing a narrower threshold distribution of the memory cell.

[0023] In particular, since node N2 does not have a terminal to which a voltage is applied from the outside, the potential is determined by the current from other terminals and by capacitive coupling, but the initial voltage during period ta differs from the voltages during periods tc1 and tc2 due to the charge accumulated before that. The details of this operation are explained below.

[0024] First, in the initial state period (period ta), the gate voltage Vg is applied with a GND voltage of 0V. During this period, the output voltage Vout is also the GND voltage. Also, a voltage of 15V to 30V, which is the voltage Vp3, is applied to the input voltage Vin. Also, the threshold voltage Vth1 of the D-type transistor TR1 is, for example, a value of 0V or less and -4V or more, which is a depletion type MOSFET. On the other hand, the threshold voltage Vth2 of the E-type transistor TR2 is, for example, a value higher than 0V and 3V or less, which is an enhancement type MOSFET. Therefore, due to the relationship between the gate voltage Vg, the input voltage Vin, the node N2 voltage Vn2, and the output voltage Vout, the D-type transistor TR1 and the E-type transistor TR2 are in a cutoff state during the initial state period. The node N2 is at a voltage (=voltage Vp6) which is -Vth1 in the initial state. The voltage Vp6 is sufficiently lower than the voltage Vp3, which reduces the drain voltage of the E-type transistor TR2 and suppresses the deterioration of the reliability of the E-type transistor TR2 due to the application of the drain voltage.

[0025] Next, the gate voltage Vg is increased from the timing of time t1 to make the D-type transistor TR1 conductive. FIG. 5 shows a case where a ramp voltage is applied from time t1 to time t4, and as the gate voltage Vg increases, the node N2 voltage Vn2 increases by a voltage of Vg-Vth1. Next, when the gate voltage Vg becomes higher than the threshold voltage Vth2 at the timing of time t2, the E-type transistor TR2 becomes conductive, and the output voltage Vout increases above the GND voltage. Between this time t2 and time t4, a current flows between the drain electrode and the source electrode of the E-type transistor TR2, charging the output voltage Vout. At this time, since the supply capacity of each voltage generating circuit of the voltage source circuit group 120 is finite, the voltage (input voltage Vin) on the input terminal Tin side drops from voltage Vp3 to voltage Vp4 in order to charge the wiring capacitance on the output terminal Tout side. Here, the voltage Vp4 is set to a voltage lower than the voltage Vp3, for example, in the range of 0.2V to 3V.

[0026] At this time, since the gate voltage is boosted with the drain voltage applied, hot carriers are generated in the E-type transistor TR2, and the threshold voltage Vth2 fluctuates in the upward direction. Next, from time t4 to time t5, in the voltage range from voltage Vp4 to voltage Vp3, the D-type transistor TR1 and the E-type transistor TR2 are in a conductive state, and the input voltage Vin is transferred to the output voltage Vout. At this time, the voltage difference between the input voltage Vin and the node N2 voltage Vn2, and between the node N2 voltage Vn2 and the output voltage Vout is smaller than between time t1 to time t4, and the generation of hot carriers is less than between time t1 to time t4. Note that from time t4 to t5, the output voltage Vout rises from voltage Vp4 to voltage Vp3, but by making the slope (degree of rise) of the transfer voltage smaller than between time t1 to time t4, it is possible to prevent the waveform from overshooting. This operation is performed in order to ensure a precise write voltage and pulse width (periods tb1, tb2, tb3) and reduce the threshold width of the memory cell.

[0027] Next, the timing of cutting off the D-type transistor TR1 and the E-type transistor TR2 is shown. Between time t6 and time t8, the gate voltage Vg drops from the voltage Vp1 to the GND voltage. The degree of voltage drop over time at this time is defined as slope SL1. At this time, due to the capacitive coupling between the gate electrode connected to the terminal Tg and the node N2, the node N2 voltage Vn2 also drops between time t6 and time t8. The degree of voltage drop over time at this time is defined as slope SL2. As will be described in detail later, the node N2 has a capacitance between the D-type transistor TR1 and the substrate electrode (semiconductor substrate 14) on which the E-type transistor TR2 is formed, in addition to the gate electrode, so the slope SL2 has a gentler voltage gradient than the slope SL1. Therefore, between time t6 and time t7, the gate voltage Vg of the D-type transistor TR1 changes to < the node N2 voltage Vn2 - the threshold voltage Vth1, and the D-type transistor TR1 goes from a conductive state to a cut-off state. At this time, since the output voltage Vout is maintained at the voltage Vp3, the gate voltage Vg<node N2 voltage Vn2+threshold voltage Vth2 and the gate voltage Vg<output voltage Vout, so that the E-type transistor TR2 is also turned off.

[0028] Next, at the timing from time t7 to time t8 after the D-type transistor TR1 and the E-type transistor TR2 are cut off, the gate voltage Vg drops, and the node N2 voltage Vn2 drops to voltage Vp5 due to the capacitive coupling between the gate electrode connected to the terminal Tg and the node N2. Here, between time t7 and time t9, the switch S1 is turned on, and the output voltage Vout is discharged to GND. If the potential drop gradient of the discharge is slope SL3, the slope SL3 is set to be a gentler voltage gradient than the slope SL2 at least in the range from time t7 to time t8. Therefore, between time t7 and time t9, both the D-type transistor TR1 and the E-type transistor TR2 are maintained in the cut off state, so the charge accumulated in the node N2 is maintained, and the node N2 voltage Vn2 is maintained at the point where it has dropped to voltage Vp5. The voltage Vp5 is 1V or more higher than the voltage Vp6, for example, a voltage between 5V and voltage Vp3. During a period tc1, the switch S1 is switched from a conductive state to a cut-off state to perform a verify operation. During the verify operation, the voltage generated by the read intermediate voltage generation circuit 111 is transferred by another high voltage transfer circuit and then transferred to the row decoder 105. Therefore, Vout of the high voltage switch that transfers the voltage generated by the write high voltage generation circuit 109 to the row decoder 105 is set to GND during the period tc1.

[0029] Comparing the initial state period (period ta) with the period tc1 after the switch S1 is turned on, the node N2 voltage Vn2 is boosted to the voltage Vp5 during repeated pulse application, compared to the voltage Vp6 in the initial state. That is, in period tc1, a drain voltage stress higher than that in the initial state is applied to the drain of the E-type transistor TR2. As a result, electrons are trapped in the silicon nitride film 401 on the n-type diffusion layer 8 connected to the drain electrode of the E-type transistor TR2, which increases the resistance, raises the threshold value, and reduces the current driving capability. (The structure of the E-type transistor TR2 will be described in detail later.) Furthermore, as a sequence for transferring the second voltage Vp3, the gate voltage Vg is increased from time t10 to place the D-type transistor TR1 in a conductive state. Note that the timing from time t10 to time t18 is the same time interval as the timing from time t1 to time t9, and the gate voltage Vg and the output voltage Vout have the same waveform.

[0030] Between time t10 and time t11, unlike the initial state (between time t1 and time t2), even if the gate voltage Vg rises, the D-type transistor TR1 is also in a cutoff state as long as the node N2 voltage Vn2 is sufficiently higher than the gate voltage Vg, so the value of the voltage Vp5 is maintained. Next, at the timing of time t11, when the gate voltage Vg-threshold voltage Vth1 becomes higher than the voltage Vp5, the D-type transistor TR1 becomes conductive, and the node N2 voltage Vn2 rises above the voltage Vp5. Furthermore, when the gate voltage Vg becomes higher than the threshold voltage Vth2 at a timing after time t11, the E-type transistor TR2 becomes conductive, and the output voltage Vout rises above the GND voltage. Between this time t11 and time t13, a current flows between the drain electrode and the source electrode of the E-type transistor TR2, charging the output voltage Vout. At this time, since the supply capacity of each voltage generating circuit of the voltage source circuit group 120 is finite, the voltage on the input terminal Tin side (input voltage Vin) drops from voltage Vp3 to voltage Vp4 in order to charge the wiring capacitance on the output terminal Tout side. Here, voltage Vp4 is a voltage lower than voltage Vp3, for example, in the range of 0.2V to 3V.

[0031] At this time, since the gate voltage rises while the drain voltage is applied, hot carriers are generated in the E-type transistor TR2, and the threshold voltage Vth2 of the E-type transistor TR2 fluctuates in an upward direction. When comparing the node N2 voltage Vn2 at the first pulse timing (=time t3) and the second pulse timing (=time t12), which have the same gate voltage Vg, the voltage is higher at the second pulse timing (see points Pa and Pb indicated by black circles in Figure 5). At this time, the gate voltage Vg and the output voltage Vоut are the same, so more hot carriers are generated during the second pulse timing, from time t10 to time t13, compared to the first pulse timing, from time t1 to time t4, and the amount of degradation is greater.

[0032] The operation from time t12 to time t18 is the same as the operation from time t3 to time t9, so a description thereof will be omitted. However, by repeating the transfer and cut-off operations of voltage Vp3, there is a problem in that reliability deteriorates due to hot carriers in the same way from the second to the third time, compared to the first time at the start of the initial state.

[0033] In order to improve the deterioration of reliability due to such hot carriers, for example, measures such as increasing the gate length of E-type transistor TR2 can be considered. However, since the current driving capacity per unit channel width decreases as the gate length is increased, in order to ensure the current driving capacity of the entire circuit, it is necessary to increase the channel width as well, which poses the problem of an increase in the circuit area.

[0034] Next, the structures of the D-type transistor TR1 and the E-type transistor TR2 in the high voltage switch of the comparative example will be described. FIG. 6 is a plan view illustrating an example of the structure of the E-type transistor TR2 in the comparative example. FIG. 8 is a plan view illustrating an example of the structure of the D-type transistor TR1 in the comparative example. In the plan views and cross-sectional views shown below, the direction in which the control gate 1 extends, which is parallel to the surface of the semiconductor substrate 14, is defined as the X direction. The direction in which the control gate 1 extends, which is parallel to the surface of the semiconductor substrate 14, is defined as the Y direction. The direction in which the control gate 1 extends, which is parallel to the surface of the semiconductor substrate 14, is defined as the Z direction.

[0035] For ease of understanding, FIGS. 6 and 8 show a planar structure below the contact plug 10, a first wiring layer, and a second wiring layer, and other wiring layers are omitted. The first wiring layer is provided with a wiring 15 shown by a two-dot chain line and a wiring 16 shown by a dashed line. The second wiring layer is provided with a wiring 100 shown by a one-dot chain line. The first wiring layer is formed between the second wiring layer and the semiconductor substrate 14. In addition, in the comparative example shown in FIGS. 6 and 8, the wiring 100 is formed so that at least a part of the wiring 100 overlaps with the upper part of the diffusion layer 8 of the transistor described later. In addition, there is a region between the diffusion layer 8 and the wiring 100 where the wirings 15 and 16 are not formed. In addition, as shown in FIGS. 6 and 8, in the comparative example, within the range of the active region width b of the transistor defined by the length of the diffusion layer 8 in the Y direction, the wiring 15 is formed only on the control gate 1.

[0036] FIG. 7A shows a cross-sectional view taken along line A-A' in FIG. 6. FIG. 7B shows a cross-sectional view taken along line B-B' in FIG. 6. FIG. 7C shows a cross-sectional view taken along line C-C' in FIG. 6. FIG. 7D shows a cross-sectional view taken along line D-D' in FIG. 6. FIG. 9A shows a cross-sectional view taken along line A-A' in FIG. 8. FIG. 9B shows a cross-sectional view taken along line B-B' in FIG. 8. FIG. 9C shows a cross-sectional view taken along line C-C' in FIG. 8. FIG. 9D shows a cross-sectional view taken along line D-D' in FIG. 8. In each figure, the same parts are denoted by the same reference numerals.

[0037] Next, the structures of the E-type transistor TR2 and the D-type transistor TR1 will be described with reference to Fig. 7C and Fig. 9C. The E-type transistor TR2 and the D-type transistor TR1 are, for example, a transistor having a p-type impurity (for example, boron) concentration of 10 15 cm -3 The gate insulating film 18 is formed on a p-type semiconductor substrate 14 (for example, a silicon substrate) as described below. A gate insulating film 18 is formed on the semiconductor substrate 14. The gate insulating film 18 is formed of, for example, a silicon oxide film or a silicon oxynitride film. The film thickness of the gate insulating film 18 is, for example, about 13 nm to 40 nm. By making the film thickness of the gate insulating film 18 about 13 nm or more, even if a voltage of 10 V or more is applied between the gate insulating film 18 and the semiconductor substrate 14, no tunnel leakage occurs and deterioration of the reliability of the transistor can be suppressed.

[0038] In addition, in the semiconductor substrate 14 in the region in which the E-type transistor TR2 is formed, for example, a peak concentration of 1×10 14 cm -3 5×10 or more 17 cm -3 P-type impurities (e.g., boron) are added (not shown) so as to satisfy the following range. By adding such p-type impurities, when the back bias is in the range of -1.5V to -5V, the threshold value of the transistor formed on this region can be set to be higher than 0V and equal to or less than about 3V. Therefore, an E-type transistor TR2, which is an enhancement type transistor, can be formed.

[0039] On the other hand, as shown in FIG. 9C, in the region of the semiconductor substrate 14 where the D-type transistor TR1 is to be formed, for example, ion implantation is used to implant ions from a depth of about 0.1 μm to a depth of about 0.5 μm from the surface to a peak concentration of 1×10 15 cm -3 5×10 or more 16 cm -3An n-type impurity (e.g., phosphorus or arsenic) is additionally added so as to satisfy the following range, forming an n-type impurity region 600. By forming the n-type impurity region 600, when the back bias is in the range of -1.5 V to -5 V, the threshold value of the transistor formed on this region can be set to be lower than 0 V and higher than -4 V. A D-type transistor TR1 that serves as a depletion mode transistor can be formed.

[0040] Other components are common to the E-type transistor TR2 and the D-type transistor TR1, and will be described with reference to FIG. 7C. A first conductive layer 17 is formed on the gate insulating film 18. The first conductive layer 17 is doped with, for example, n-type impurities (e.g., phosphorus or arsenic) or p-type impurities (e.g., boron) at a concentration of 1×10 18 cm -3 ~1×10 21 cm -3The first conductive layer 17 is a polysilicon film doped with a concentration of about 1000 nm. Its thickness is, for example, about 10 nm to 500 nm. The first conductive layer 17 is formed in an element formation region partitioned by an element isolation region 13. A structure for electrically isolating adjacent element formation regions including the element isolation region 13 is formed, for example, as follows. First, a p-type well 11 and a stopper region 4 for preventing punch-through are formed in a p-type semiconductor substrate 14 using a photolithography technique, an ion implantation technique, or the like. A p-type impurity (for example, boron) is implanted to a predetermined depth and a predetermined concentration in the p-type well 11 and the stopper region 4. Next, a gate insulating film (not shown) of the memory cell and a gate insulating film 18 of the peripheral transistors including the E-type transistor TR2 and the D-type transistor TR1 are formed on the entire surface of the semiconductor substrate 14 using a thermal oxidation technique or the like. Next, a film that will be the material of the first conductive layer 17 is deposited using a CVD method or the like. Using photolithography, these laminated films are patterned so that the surface of the semiconductor substrate 14 in the region where the element isolation region 13 is to be formed is exposed. Furthermore, using anisotropic etching or the like, an opening in the semiconductor substrate 14 is etched to a depth of, for example, 0.1 μm to 0.3 μm to form a trench (deep groove). Finally, using CVD technology, CMP technology, or the like, an insulating film such as a silicon oxide film is embedded in the trench to form the element isolation region 13, completing a structure that electrically isolates adjacent element formation regions. Using such a formation method, the first conductive layer 17 can be formed on a flat surface without any steps.

[0041] The control gate 1 is formed on the first conductive layer 17. The control gate 1 is doped with, for example, n-type impurities (for example, phosphorus or arsenic) or p-type impurities (for example, boron) at a concentration of 1×10 17 cm -3 ~1×10 21 cm -3The control gate 1 is a conductive polysilicon film doped with a concentration of about 10 ...

[0042] A silicon oxide film 400 is formed on the control gate 1 and the diffusion layer 8. The silicon oxide film 400 is formed to a thickness in the range of, for example, 3 nm to 15 nm. A silicon nitride film 401 is further formed on the silicon oxide film 400. The silicon nitride film 401 is formed to a thickness in the range of, for example, 10 nm to 100 nm. A diffusion layer 8 having n-type conductivity is formed from the surface to a predetermined depth in a predetermined region of the semiconductor substrate 14. The diffusion layer 8 has a surface concentration of, for example, 1×10 17 cm -3 ~1×10 20 cm -3 The diffusion layer 8 is doped with n-type impurities (e.g., phosphorus, arsenic, or antimony) so that the junction depth of the diffusion layer 8 is about 10 nm to 300 nm, for example. The diffusion layer 8 is formed in a self-aligned manner with respect to a stacked gate structure consisting of the first conductive layer 17 and the control gate 1, and functions as an LDD (Lightly Doped Drain) region that is a source electrode or a drain electrode. In addition, in a region of the semiconductor substrate 14 adjacent to the diffusion layer 8, a diffusion layer 9 having n-type conductivity is formed from the surface to a predetermined depth. The diffusion layer 9 is formed to have a higher impurity concentration than the diffusion layer 8, and has a surface concentration of, for example, 1×10 18 cm -3 ~1×10 22 cm -3The diffusion layer 9 is doped with n-type impurities (e.g., phosphorus, arsenic, or antimony) so that the junction depth of the diffusion layer 9 is about 40 nm to 500 nm, for example. That is, the diffusion layer 9 is formed so that the junction depth is deeper and has lower resistance than the diffusion layer 8. The diffusion layer 9 functions as a contact region for the source electrode and the drain electrode. That is, the diffusion layer 9 is a necessary portion for reducing the contact resistance with the source electrode and the drain electrode, and has a junction depth of about 1×10 20 cm -3 More than 1×10 22 cm -3 The points with impurity peak concentrations of 1×10 17 cm -3 More than 1×10 19 cm -3 This is different from the diffusion layer 8 (LDD region) having the following peak impurity concentration:

[0043] An interlayer insulating film 27 (e.g., a silicon oxide film) is laminated on the entire surface of the silicon nitride film 401. A contact plug 10 is formed on the diffusion layer 9. The contact plug 10 is formed above the upper surface of the silicon nitride film 401 laminated on the control gate 1. The contact plug 10 is made of, for example, W (tungsten). The contact plug 10 is formed in a hole drilled in the interlayer insulating film 27 through the silicon oxide film 400 and the silicon nitride film 401, and electrically connects the control gate 1 (gate electrode) or the diffusion layer 9 (source electrode or drain electrode) to a predetermined wiring formed in an upper wiring layer (e.g., a first wiring layer). A barrier metal (not shown) made of, for example, Ti (titanium) or TiN is formed on the lower surface of the contact plug 10.

[0044] The first wiring layer includes wirings 15 and 16. A barrier metal (not shown) made of, for example, Ti (titanium) or TiN is formed on the upper surface of the contact plug 10. The wiring 16 is electrically connected to the diffusion layer 9 via the contact plug 10 (see FIGS. 7A and 9A). The wiring 15 is electrically connected to the control gate 1 via the contact plug 10 (see FIGS. 7B and 9B). A second wiring layer is formed above the first wiring layer with an interlayer insulating film 27 interposed therebetween. For example, the wiring 100 is formed in the second wiring layer.

[0045] 6 and 8, in the comparative example, when viewed from the Z direction, the wiring 15 is formed mainly above the control gate 1, and there is no region where the wiring 15 overlaps the diffusion layer 8. Moreover, in the region where the wiring 100 overlaps the diffusion layer 8, there is a wide region where the wiring 15 and the wiring 16 are not formed (see FIGS. 7D and 9D).

[0046] 10A and 10B are diagrams showing the resistance value fluctuation of the diffusion layer 8 in the comparative example. Specifically, Figures 10A and 10B show the resistance value fluctuation when the thickness of the silicon oxide film 400 formed on the diffusion layer 8 of the E-type transistor TR2 shown in Figure 7D is changed. Figure 10A shows the simulation result of the resistance value fluctuation when no fixed charge exists in the silicon oxide film 400 and the silicon nitride film 401.

[0047] 10A, as the thickness of the silicon oxide film 400 increases, the resistance of the diffusion layer 8 increases. The diffusion layer 8 used in the simulation is formed by ion-implanting impurities into the semiconductor substrate 14 having the silicon oxide film 400 deposited on the entire surface thereof under the following conditions: 11 cm -3 From 1×10 12 cm -3 After implanting p-type impurities (e.g., boron) to obtain an impurity concentration in the range of 5×10 11 cm -3From 3×10 12 cm -3 10A, the resistance value of the diffusion layer 8 tends to increase as the thickness of the silicon oxide film 400 increases. This tendency is believed to be due to the fact that, when the diffusion layer 8 is formed by ion implantation, the thicker the silicon oxide film 400 is, the more the amount of n-type impurities (e.g., phosphorus) that do not reach the semiconductor substrate 14 and remain in the silicon oxide film 400 increases.

[0048] On the other hand, FIG. 10B shows that the interface between the silicon oxide film 400 and the silicon nitride film 401 is 1.15×10 12 cm -2 10B shows the resistance value fluctuation when the silicon oxide film 400 is present. In FIG. 10B, black circles show the simulation results, and white circles show the actual measurement results. As shown in FIG. 10B, the actual measurement value of the resistance of the diffusion layer 8 decreases as the thickness of the silicon oxide film 400 increases. The simulation values ​​also show a similar decreasing trend, so it can be seen that the fluctuation trend of the actual measurement values ​​matches the simulation results. Furthermore, comparing FIG. 10A with FIG. 10B, the resistance value of the diffusion layer 8 is larger overall in the case where the silicon nitride film 401 is present (FIG. 10B) than in the case where the silicon nitride film 401 is not present (FIG. 10A) within the range of the thickness of the silicon oxide film 400 shown in FIG. 10A and 10B. This is considered to be due to the phenomenon that the diffusion layer 8 is depleted by electrons accumulated at a distance from the diffusion layer 8 by the thickness of the silicon oxide film 400 (electrons trapped at the interface between the silicon oxide film 400 and the silicon nitride film 401).

[0049] In view of the above, it is found that in the process of forming a plurality of wiring layers when manufacturing a NAND nonvolatile memory including a high-voltage switch, electrons are accumulated at the interface state between the silicon oxide film 400 and the silicon nitride film 401, or in the silicon nitride film 401 with a high electron capture level, and the resistance value of the diffusion layer 8 increases. In general, when processing a wiring layer using an etching technique or forming a wiring layer using a PVD technique (when depositing a metal material), a voltage is applied to the semiconductor substrate 14 on which various films are formed, and electrons are generated from the upper side of the wiring layer and move through the silicon oxide film toward the semiconductor substrate 14. This is known as an antenna effect. In the comparative example, in the region where the wirings 15 and 16 are not formed, there is a wide region where the wiring 100 faces the diffusion layer 8. For this reason, the amount and location of the electric charge generated by processing the wiring layer change depending on the arrangement of the wiring 100, and there is a problem that the resistance of the diffusion layer 8 changes unexpectedly.

[0050] An increase in the resistance of the diffusion layer 8 reduces the current driving capability of the transistor. Conversely, a decrease in the resistance of the diffusion layer 8 reduces the amount of voltage drop in the diffusion layer 8 when a high voltage is applied to the drain electrode to turn the transistor off, resulting in a problem of a deterioration in the junction breakdown voltage, since a high voltage is applied up to the vicinity of the gate.

[0051] Next, the operation and structure of the high-voltage switch according to this embodiment will be described with reference to the drawings. In the following description, common parts will be given common reference symbols. Also, the description of the parts that are the same as those in the comparative example will be omitted.

[0052] First, the structures of the D-type transistor TR1 and the E-type transistor TR2 in the high-voltage switch of this embodiment will be described. Fig. 11 is a plan view illustrating an example of the structure of the E-type transistor TR2 in the first embodiment. Fig. 13 is a plan view illustrating an example of the structure of the D-type transistor TR1 in the first embodiment.

[0053] FIG. 12A shows a cross-sectional view taken along line A-A' in FIG. 11. FIG. 12B shows a cross-sectional view taken along line B-B' in FIG. 11. FIG. 12C shows a cross-sectional view taken along line C-C' in FIG. 11. FIG. 12D shows a cross-sectional view taken along line D-D' in FIG. 11. FIG. 14A shows a cross-sectional view taken along line A-A' in FIG. 13. FIG. 14B shows a cross-sectional view taken along line B-B' in FIG. 13. FIG. 14C shows a cross-sectional view taken along line C-C' in FIG. 13. FIG. 14D shows a cross-sectional view taken along line D-D' in FIG. 13.

[0054] The diffusion layer 9 (region functioning as a source electrode) of the D-type transistor TR1 shown in FIG. 13 and the diffusion layer 9 (region functioning as a drain electrode) of the E-type transistor TR2 shown in FIG. 11 are formed separately and are electrically connected via an upper wiring not shown.

[0055] 11 and 13 show a planar structure below contact plug 10 and a first wiring layer and a second wiring layer among a plurality of wiring layers formed above contact plug 10, with the other wiring layers not shown. Wiring 15 shown by a two-dot chain line and wiring 16 shown by a dashed line are arranged in the first wiring layer. Wiring 100 shown by a one-dot chain line is arranged in the second wiring layer. The first wiring layer is formed between the second wiring layer and semiconductor substrate 14.

[0056] In the high voltage switch of the first embodiment, the structures of the D-type transistor TR1 and the E-type transistor TR2 are the same as those of the comparative example. The characteristic structure of the first embodiment, which is different from the comparative example, is the shape and arrangement of the wiring 15 (first wiring). As shown in FIGS. 11 and 13, within the range of the active region width b of the transistor, the length of the wiring 15 in the X direction is formed to be longer than the length of the control gate 1 in the X direction. Specifically, as shown in FIGS. 12C and 14C, the length of the wiring 15 in the X direction is formed to be longer than the length of the control gate 1 in the X direction. In addition, the end of the wiring 15 on one side in the X direction (left side of the paper) is arranged to the left of the end of the control gate 1 on one side in the X direction, and the end of the wiring 15 on the other side in the X direction (right side of the paper) is arranged to the right of the end of the control gate 1 on the other side in the X direction.

[0057] That is, one end of the wiring 15 in the X direction is located above the diffusion layer 8 arranged on one side of the control gate 1 in the X direction, and the other end of the wiring 15 in the X direction is located above the diffusion layer 8 arranged on the other side of the control gate 1 in the X direction. The pair of diffusion layers 8 arranged on both sides of the control gate 1 in the X direction correspond to a first source diffusion layer and a first drain diffusion layer. By making the shape and arrangement of the wiring 15 as described above, it is possible to provide a region in which the wiring 15 is formed between the diffusion layer 8 and the wiring 100 as shown in Figs. 12D and 14D. It is preferable that the distance between the end of the wiring 15 on one side in the X direction and the end of the control gate 1 on one side, and the distance between the end of the wiring 15 on the other side in the X direction and the end of the control gate 1 on the other side in the X direction are at least 0.1 μm or more.

[0058] In this way, the wiring 15 electrically connected to the control gate 1 is formed so as to extend continuously from the upper part of the control gate 1 onto the diffusion layer 8 connected to the source electrode or drain electrode of the transistor. That is, the width of the first wiring in the direction parallel to the surface of the semiconductor substrate and the direction of the distance between the source diffusion layer and the drain diffusion layer is formed wider than the width of the gate electrode. Therefore, the region of the wiring 100 formed on the diffusion layer 8 where the wiring 15, 16 are not formed (see FIGS. 11 and 13) is much narrower than the comparative example (see FIGS. 7 and 9). Therefore, in the structure of this embodiment, in the region where the wiring 100 and the diffusion layer 8 face each other, a region is provided in which the wiring 15 electrically connected to the control gate 1 is disposed between the wiring 100 and the diffusion layer 8. Therefore, the amount of electric charges that are generated during the shape processing of the wiring 100 or during the formation of the wiring layer (when depositing the metal material) and move toward the semiconductor substrate 14 through the interlayer insulating film 27 is captured by the wiring 15 and reaches the silicon nitride film 401 formed above the diffusion layer 8, which can be greatly reduced. Therefore, even if the arrangement or shape of the wiring 100 is changed, it is possible to suppress fluctuations in the resistance of the diffusion layer 8. That is, compared to the comparative example, it is possible to suppress a decrease in the current driving capability of the transistor caused by an increase in the resistance of the diffusion layer 8, and it is also possible to suppress a decrease in the junction breakdown voltage of the transistor caused by a decrease in the resistance of the diffusion layer 8.

[0059] In addition, in this embodiment, the wiring 15 electrically connected to the control gate 1 is formed by extending continuously from the upper part of the control gate 1 to the upper part of the diffusion layer 8, so that the resistance value fluctuation of the diffusion layer 8 near the end of the control gate 1 can be suppressed compared to the comparative example in which the wiring 15 is not formed on the upper part of the diffusion layer 8. In addition, the diffusion layer 8 near the end of the control gate 1 is easily affected by depletion due to a change in the voltage applied to the control gate 1, and is a region in which the threshold value and current drive capacity of the transistor are likely to fluctuate. In contrast, in this embodiment, the wiring 15 electrically connected to the control gate 1 is formed by extending continuously from the upper part of the control gate 1 to the upper part of the diffusion layer 8, so that the fluctuation of the threshold value and current drive capacity of the transistor can also be suppressed.

[0060] In the above, it has been explained that the structure of the high-voltage switch of this embodiment can suppress fluctuations in the resistance value of the diffusion layer 8 due to charges generated when forming the wiring 100 in the second wiring layer, but it goes without saying that it can also suppress fluctuations in the resistance value of the diffusion layer 8 due to charges generated when forming a wiring layer above the second wiring layer.

[0061] Next, the operation of the high voltage switch of this embodiment will be described. Fig. 15 is a diagram that shows an example of a voltage waveform during switch operation in the first embodiment. As shown in Fig. 4, the circuit of the high voltage switch of this embodiment is the same as the circuit of the high voltage switch shown in the comparative example, but the structure of the high voltage switch is different from that of the comparative example. Therefore, the voltage waveform of the high voltage switch of this embodiment shown in Fig. 15 is different from the voltage waveform of the high voltage switch of the comparative example shown in Fig. 5.

[0062] FIG. 15 shows the waveforms of the gate voltage Vg, the input voltage Vin, the node N2 voltage Vn2, and the output voltage Vout, in that order from the top of the page. The vertical axis of each waveform is voltage, and the horizontal axis is time. FIG. 15 shows voltage waveforms in the same sequence as the switch operation when obtaining the voltage waveform of the comparative example shown in FIG. 5. That is, the voltage waveforms are shown in a sequence in which the voltage Vp3 applied to the input terminal Tin is transferred to the output terminal Tout three times, and discharged twice between each transfer. Note that in FIG. 15, the voltage Vp3 is set to a voltage of 15V or more and 30V or less, as in the comparative example shown in FIG. 5. For example, the voltage Vp1 applied to the terminal Tg is set to a voltage of 17V or more and 35V or less.

[0063] Since node N2 does not have a terminal to which a voltage is applied from the outside, the potential is determined by the current from other terminals and by capacitive coupling, but the initial voltage during period ta differs from the voltage during periods tc1 and tc2 due to the charge accumulated before that. The details of this operation are explained below.

[0064] First, in the initial state period (period ta), the gate voltage Vg is applied with a GND voltage of 0V. During this period, the output voltage Vout is also the GND voltage. Also, a voltage of 15V to 30V, which is the voltage Vp3, is applied to the input voltage Vin. Also, the threshold voltage Vth1 of the D-type transistor TR1 is, for example, a value of 0V or less and -4V or more, which is a depletion type MOSFET. On the other hand, the threshold voltage Vth2 of the E-type transistor TR2 is, for example, a value higher than 0V and 3V or less, which is an enhancement type MOSFET. Therefore, due to the relationship between the gate voltage Vg, the input voltage Vin, the node N2 voltage Vn2, and the output voltage Vout, the D-type transistor TR1 and the E-type transistor TR2 are in a cutoff state during the initial state period. The node N2 is at a voltage (=voltage Vp6) which is -Vth1 in the initial state. The voltage Vp6 is sufficiently lower than the voltage Vp3, which reduces the drain voltage of the E-type transistor TR2 and suppresses the deterioration of the reliability of the E-type transistor TR2 due to the application of the drain voltage.

[0065] Next, the gate voltage Vg is increased from time t1 to place the D-type transistor TR1 in a conductive state. In FIG. 15, a ramp voltage is applied from time t1 to time t4, and as the gate voltage Vg increases, the node N2 voltage Vn2 increases to a voltage of Vg-Vth1. Next, when the gate voltage Vg becomes higher than the threshold voltage Vth2 at time t2, the E-type transistor TR2 is placed in a conductive state, and the output voltage Vout increases above the GND voltage. Between time t2 and time t4, a current flows between the drain and source electrodes of the E-type transistor TR2, charging the output voltage Vout.

[0066] The high-voltage switch of this embodiment has a different structure from the high-voltage switch of the comparative example. Specifically, when viewed from the Z direction, the wiring 15 electrically connected to the control gate 1 has an area overlapping not only the control gate 1 but also at least a part of the diffusion layer 8 formed on both sides of the control gate 1 in the X direction. Since the node N2 includes the diffusion layer 8, as the gate voltage Vg increases, the node N2 voltage Vn2 increases due to the capacitive coupling between the wiring 15 and the diffusion layer 8. Therefore, in the comparative example shown in FIG. 5, the node N2 voltage Vn2 is boosted from the voltage Vp6 to the voltage Vp4 between time t1 and time t4, but in this embodiment shown in FIG. 15, the node N2 voltage Vn2 is boosted from the voltage Vp6 to the voltage Vp4 between time t1 and time t3. That is, the node N2 voltage Vn2 can be boosted in a shorter time than in the comparative example. At this time, since the supply capacity of each voltage generating circuit of the voltage source circuit group 120 is finite, the voltage on the input terminal Tin side (input voltage Vin) drops from voltage Vp3 to voltage Vp4 in order to charge the wiring capacitance on the output terminal Tout side. Here, voltage Vp4 is a voltage lower than voltage Vp3, for example, in the range of 0.2V to 3V.

[0067] At this time, since the gate voltage is boosted while the drain voltage is applied, hot carriers are generated in the E-type transistor TR2, and the threshold voltage Vth2 fluctuates in an upward direction. Here, under the same voltage stress, the shorter the transition time of the drain voltage and gate voltage, the smaller the hot carrier degradation. As described above, in the case of this embodiment, the transition time is between time t2 and time t3, and in the comparative example, it is between time t2 and time t4. That is, since the transition time is shorter in the embodiment than in the comparative example, hot carrier degradation during the initial pulse boost can be suppressed.

[0068] Next, from time t4 to time t5, in the voltage range from voltage Vp4 to voltage Vp3, D-type transistor TR1 and E-type transistor TR2 are in a conductive state, so that input voltage Vin is transferred to output voltage Vout. At this time, the voltage differences between input voltage Vin and node N2 voltage Vn2, and between node N2 voltage Vn2 and output voltage Vout are smaller than those between time t1 and time t3, and the generation of hot carriers is suppressed.

[0069] Next, the timing of cutting off the D-type transistor TR1 and the E-type transistor TR2 is shown. At the timing from time t6 to time t8, the gate voltage Vg drops from the voltage Vp1 to the GND voltage. Due to the capacitive coupling between the gate electrode connected to the terminal Tg and the node N2, the node N2 voltage Vn2 also drops from time t6 to time t8. Here, in the high-voltage switch of this embodiment, the wiring 15 electrically connected to the control gate 1 is formed so as to cover at least a part of the diffusion layer 8. Since the node N2 includes the diffusion layer 8, as the gate voltage Vg drops, the node N2 voltage Vn2 drops due to the capacitive coupling between the wiring 15 and the diffusion layer 8. For this reason, in the comparative example shown in FIG. 5, the node N2 voltage Vn2 drops from the voltage Vp3 to the voltage Vp5 from time t6 to time t8, but in this embodiment shown in FIG. 15, the node N2 voltage Vn2 drops from the voltage Vp3 to the voltage Vp7 (<voltage Vp5) from time t6 to time t8. If the degree of voltage decrease with time at this time is designated as a slope SL4, the slope SL4 is greater than the slope SL2 of the comparative example shown in FIG.

[0070] Since the node N2 has a capacitance between the substrate electrode (semiconductor substrate 14) on which the D-type transistor TR1 and the E-type transistor TR2 are formed, in addition to the gate electrode, the slope SL4 is gentler than the slope SL1. That is, since the rate of decrease in the gate voltage Vg is greater than the rate of decrease in the node N2 voltage Vn2 per unit time, the gate voltage Vg becomes negative with respect to the node N2 voltage Vn2. Therefore, the current driving capability of the D-type transistor TR1 and the E-type transistor TR2 is lower than that of the voltage transfer state in the period tb1, and they transition from the voltage transfer state to the cutoff state more quickly. Between time t6 and time t7, the gate voltage Vg<node N2 voltage Vn2-threshold voltage Vth1 in the D-type transistor TR1, and the D-type transistor TR1 transitions from the conductive state to the cutoff state. At this time, since the output voltage Vout is maintained at the voltage Vp3, the gate voltage Vg<node N2 voltage Vn2+threshold voltage Vth2, and the gate voltage Vg<output voltage Vout, and since the slope SL1>slope SL4, the E-type transistor TR2 also becomes cut off.

[0071] Next, at the timing from time t7 to time t8 after the D-type transistor TR1 and the E-type transistor TR2 are cut off, the gate voltage Vg drops, and the node N2 voltage Vn2 drops to voltage Vp7 due to the capacitive coupling between the gate electrode connected to the terminal Tg and the node N2. Here, between time t7 and time t9, the switch S1 is turned on, and the output voltage Vout is discharged to GND. At least in the range from time t7 to time t8, the slope SL3, which is the potential drop gradient of the discharge, is gentler than the slope SL4. The reason why the slope SL3 is gentler than the slope SL4 is that the wiring capacitance connected to the output terminal Tout is larger than the capacitance of the gate wiring and the capacitance of the node N2, and it takes time to discharge. Therefore, between time t7 and time t9, both the D-type transistor TR1 and the E-type transistor TR2 are maintained in the cut off state, so the charge stored in the node N2 is maintained, and the node N2 voltage Vn2 is maintained at the point where it has dropped to voltage Vp7. The voltage Vp7 is, for example, 1 V or more lower than the voltage Vp5, 5 V or more lower than the voltage Vp3, and equal to or higher than the voltage Vp6 (=-Vth1).

[0072] In this embodiment, the voltage Vp7 becomes closer to the voltage Vp6, so that the difference between the node N2 voltage Vn2 in the period ta, which is the initial state period, and the node N2 voltage Vn2 in the periods tc1 and tc2 after the second and subsequent pulses are applied becomes smaller than the difference in the comparative example. Therefore, it is possible to suppress the problems seen in the comparative example, that is, the problem of reliability being deteriorated due to hot carriers being more likely to be generated when the gate voltage Vg rises due to the node N2 voltage Vn2 in the periods tc1 and tc2 rising higher than in the initial state period, and the problem of reliability being deteriorated due to the application of a voltage to the drain electrode of the E-type transistor TR2 in the periods tc1 and tc2.

[0073] In this embodiment, when comparing the node N2 voltage Vn2 at the first pulse timing (=time t3) and the second pulse timing (=time t12) when the gate voltage Vg is equal, the two are almost equal (see points Pc and Pd indicated by black circles in FIG. 15). That is, compared to the comparative example shown in FIG. 5, the increase in the node N2 voltage Vn2 at the second pulse timing compared to the first pulse timing can be made smaller. At this time, since the gate voltage Vg and the output voltage Vout are the same, the amount of hot carriers generated from the second pulse timing, that is, from time t10 to time t13, can be suppressed more than in the comparative example, and deterioration of reliability can be suppressed.

[0074] Furthermore, as described above, between time t6 and time t8, the D-type transistor TR1 and the E-type transistor TR2 have a lower current driving capability than the voltage transfer state during period tb1, and therefore transition from the voltage transfer state to the cut-off state at a higher speed. At the same voltage stress, the shorter the transition time between the drain voltage and the gate voltage, the smaller the hot carrier degradation. Therefore, the high voltage switch of this embodiment can suppress the degradation of the reliability of the D-type transistor TR1 and the E-type transistor TR2 due to the generation of hot carriers during the voltage drop between time t6 and time t8, compared to the comparative example. Note that during period tc1, the verify operation is performed by switching the switch S1 from the conductive state to the cut-off state.

[0075] The operation from time t12 to time t18 is the same as the operation from time t3 to time t9, so a description thereof will be omitted, but by repeating the transfer and cutoff operations of voltage Vp3, there is a possibility that hot carriers will be generated from the second to third times compared to the first time of the rise in the initial state. However, since the amount of hot carriers generated can be suppressed compared to the comparative example, deterioration of the reliability of D-type transistor TR1 and E-type transistor TR2 can be suppressed.

[0076] In a high-voltage switch such as that shown in the comparative example, in order to improve the deterioration of reliability due to hot carriers, for example, measures such as lengthening the gate length of the E-type transistor TR2 can be considered. However, since the current driving capacity per unit channel width decreases as the gate length is extended, in order to ensure the current driving capacity of the entire circuit, it is necessary to increase the channel width as well, which causes a problem of increasing the circuit area. In contrast, according to the high-voltage switch of this embodiment, it is possible to suppress the deterioration of reliability due to hot carrier generation without lengthening the gate length of the E-type transistor TR2, and it is not necessary to increase the channel width to ensure the current driving amount. Therefore, it is possible to improve reliability without increasing the circuit area.

[0077] Furthermore, in the embodiment, in each of the periods tb1, tb2, and tb3 in which the input voltage Vin is transferred to the output voltage Vout, the resistance of the diffusion layer 8 can be reduced compared to the comparative example by the capacitive coupling between the wiring 15 and the diffusion layer 8. Therefore, a higher current driving capability can be realized. On the other hand, in the periods tc1 and tc2 in which the input voltage Vin is not transferred to the output voltage Vout, the node N2 voltage Vn2 can be reduced compared to the comparative example by the capacitive coupling between the wiring 15 and the diffusion layer 8. This allows the leakage current between the source electrode and the drain electrode of the E-type transistor TR2 to be reduced to the same level as the period ta, which is the initial state period. Therefore, the influence of the leakage current fluctuation between the initial pulse (first pulse) and the repeated pulse (second and subsequent pulses) in the circuit connected to the output terminal Tout can be reduced.

[0078] Furthermore, in the structure of the high-voltage switch in this embodiment, in the region where the wiring 100 and the diffusion layer 8 face each other, a region is provided in which the wiring 15 electrically connected to the control gate 1 is disposed between the wiring 100 and the diffusion layer 8 (see, for example, FIG. 12D). When the voltage of the wiring facing the diffusion layer 8 without a conductor drops, the wiring exerts a voltage effect on the diffusion layer 8 that is inversely proportional to the distance between the wiring and the diffusion layer 8. As shown in FIG. 12D, in this embodiment, a silicon oxide film 400, a silicon nitride film 401, an interlayer insulating film 27, and the wiring 15 are laminated in this order on the diffusion layer 8. This structure is a so-called MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure, considering the wiring 15 as a gate electrode and the diffusion layer 8 as a semiconductor whose electron concentration fluctuates. Therefore, by providing the wiring 15 between the diffusion layer 8 and the wiring 100, the influence of the voltage fluctuation of the wiring 100 is reduced, and the decrease in the electron density of the diffusion layer 8 and depletion, as well as the resistance fluctuation caused by these, can be suppressed. It is assumed that the wiring 100 is not electrically connected to the high-voltage switch shown in FIG. 4 and a voltage different from that used in the high-voltage switch is applied thereto (for example, the wiring 100 is a so-called passing wiring that transfers a voltage from a voltage source to a voltage-using part). Even if the voltage of the wiring 100 fluctuates according to the passing signal, the influence of the fluctuation on the diffusion layer 8 can be suppressed by the wiring 15. Furthermore, even if the voltage of the wiring 100 drops to, for example, a GND voltage (0 V), the resistance fluctuation of the diffusion layer 8 can be suppressed and the driving force of the transistor can be maintained.

[0079] Furthermore, by connecting the wiring 15 to the control gate 1, it is possible to improve the reliability and characteristics of the transistor used in the high-voltage switch without requiring an additional power supply or wiring. (Modification of the first embodiment) Next, a modified example of the first embodiment described above will be described. In the semiconductor device of this modified example, the structures of the D-type transistor TR1 and the E-type transistor TR2 of the high-voltage switch are different from those of the first embodiment described above. The circuit configuration and switch operation of the high-voltage switch are the same as those of the first embodiment described above, so a description thereof will be omitted. Below, the differences from the first embodiment will be described.

[0080] Fig. 16 is a plan view illustrating an example of the structure of an E-type transistor TR2 in the modification of the first embodiment, and Fig. 18 is a plan view illustrating an example of the structure of a D-type transistor TR1 in the modification of the first embodiment.

[0081] Fig. 17A shows a cross-sectional view taken along line A-A' shown in Fig. 16. Fig. 17B shows a cross-sectional view taken along line C-C' shown in Fig. 16. Fig. 19A shows a cross-sectional view taken along line A-A' shown in Fig. 18. Fig. 19B shows a cross-sectional view taken along line C-C' shown in Fig. 18.

[0082] 16 and 18 show a planar structure below contact plug 10 and a first wiring layer and a second wiring layer among a plurality of wiring layers formed above contact plug 10, with the other wiring layers not shown. Wiring 15 shown by a two-dot chain line and wiring 16 shown by a dashed line are arranged in the first wiring layer. Wiring 100 shown by a one-dot chain line is arranged in the second wiring layer. The first wiring layer is formed between the second wiring layer and semiconductor substrate 14.

[0083] The characteristic structure of this modified example is the shape and arrangement of the wiring 15 connected to the control gate 1. As shown in FIGS. 17B and 19B, the length of the wiring 15 in the X direction is longer than the length of the control gate 1 in the X direction. The end of the wiring 15 on one side in the X direction (left side of the paper) is disposed to the left of the end of the control gate 1 on one side in the X direction, and the end of the wiring 15 on the other side in the X direction (right side of the paper) is disposed to the right of the end of the control gate 1 on the other side in the X direction. That is, the end of the wiring 15 on one side in the X direction is located above the diffusion layer 9 disposed on one side in the X direction of the control gate 1, and the end of the wiring 15 on the other side in the X direction is located above the diffusion layer 9 disposed on the other side in the X direction of the control gate 1. The pair of diffusion layers 9 disposed on both sides of the control gate 1 in the X direction correspond to a second source diffusion layer and a second drain diffusion layer. It is preferable that the distance between one end of the wiring 15 in the X direction and one end of the control gate 1, and the distance between the other end of the wiring 15 in the X direction and the other end of the control gate 1 in the X direction are at least 0.1 μm or more.

[0084] 17A and 19A, the end of the wiring 15 is located above the diffusion layer 9 in the Y direction. That is, according to this modification, the wiring 15 is formed so as to completely cover the region above the diffusion layer 8. In other words, in this modification, the wiring 15 is always formed between the diffusion layer 8 and the wiring 100. The diffusion layer 9 has a higher concentration of n-type impurities than the diffusion layer 8, and is less likely to be depleted. When the wiring 100 is used as a passing signal wiring, for example, even if the voltage of the wiring 100 located above the diffusion layer 8 fluctuates, the depletion of the diffusion layer 8 can be prevented. Therefore, deterioration of reliability such as fluctuations in the threshold value and current driving capacity of the transistor can be further suppressed.

[0085] In the structure of this embodiment, in the entire region where the wiring 100 and the diffusion layer 8 face each other, the wiring 15 electrically connected to the control gate 1 is disposed between the wiring 100 and the diffusion layer 8. Therefore, the amount of electric charges that are generated during the shape processing of the wiring 100 or during the formation of the wiring layer (when the metal material is deposited) and move toward the semiconductor substrate 14 through the interlayer insulating film 27 and reach the silicon nitride film 401 formed above the diffusion layer 8 can be greatly reduced. Therefore, even if the arrangement or shape of the wiring 100 is changed, the fluctuation in the resistance of the diffusion layer 8 can be suppressed. That is, the decrease in the current driving ability of the transistor due to the increase in the resistance of the diffusion layer 8 can be further suppressed than in the first embodiment. In addition, the decrease in the junction breakdown voltage of the transistor due to the decrease in the resistance of the diffusion layer 8 can also be further suppressed.

[0086] In the above-mentioned modification, the wiring 15 is formed so as to cover the entire region of the diffusion layer 8. However, for example, as shown in FIGS. 20 and 21, the wiring 15 may be formed so as to cover at least a partial region of the diffusion layer 8 located between the control gate 1 and the diffusion layer 9 in the X direction. FIG. 20 is a plan view for explaining an example of the structure of an E-type transistor TR2 in another modification of the first embodiment. FIG. 21 is a plan view for explaining an example of the structure of a D-type transistor TR1 in another modification of the first embodiment. In this case, the influence of upper layer wiring such as the wiring 100 can be suppressed by the wiring 15 above the region where the drain current and source current of the transistor mainly flow, so that the reliability and characteristics of the transistor can be improved more than those of the first embodiment. Second embodiment Next, a second embodiment will be described. The semiconductor device of this embodiment differs from the first embodiment in the structure of the E-type transistor TR2 of the high-voltage switch. The circuit configuration and switch operation of the high-voltage switch and the structure of the D-type transistor TR1 are the same as those of the first embodiment, so their explanations are omitted. Below, the differences from the first embodiment will be described.

[0087] Fig. 22 is a plan view illustrating an example of the structure of an E-type transistor TR2 in the second embodiment. Fig. 23A shows a cross-sectional view taken along line A-A' in Fig. 22. Fig. 23B shows a cross-sectional view taken along line B-B' in Fig. 22. Fig. 23C shows a cross-sectional view taken along line CC' in Fig. 22. Fig. 23D shows a cross-sectional view taken along line D-D' in Fig. 22.

[0088] 22 shows a planar structure below the contact plug 10, and a first wiring layer and a second wiring layer among a plurality of wiring layers formed above the contact plug 10, with the other wiring layers not shown. In the first wiring layer, a wiring 15 shown by a two-dot chain line and a wiring 16 shown by a dashed line are arranged. In the second wiring layer, a wiring 100 shown by a one-dot chain line is arranged. The first wiring layer is formed between the second wiring layer and the semiconductor substrate 14. The shape and arrangement of the wiring 15 are similar to those of the first embodiment shown in FIG.

[0089] The characteristic structure of this embodiment is a region (well region) to which an impurity is added, which is formed in the depth direction from the surface of the semiconductor substrate 14. The structure above the surface of the semiconductor substrate 14 is similar to that of the first embodiment shown in FIG. 12C, and therefore will not be described. The E-type transistor TR2 of this embodiment is characterized in that an n-type well 402 having an n-type conductivity is formed in a semiconductor substrate 14 having a p-type conductivity, a p-type well 11 having a side surface and a bottom surface covered by the n-type well 402 is formed, and a p-type region 403 having a side surface and a bottom surface covered by the p-type well 11 is further formed. The p-type region 403 is formed to have a lower impurity concentration than the p-type well 11.

[0090] As a result, the p-type well 11 and the p-type region 403 are surrounded by the n-type well 402, and the p-type well 11 and the p-type region 403 are electrically isolated from the semiconductor substrate 14. By electrically isolating the p-type well 11 and the p-type region 403 from the p-type semiconductor substrate 14, the voltage of the p-type well 11 and the p-type region 403 can be changed to a negative voltage depending on the operation, independently of the semiconductor substrate 14. Such a structure is a so-called double well structure. Since the double well structure can reduce the area of ​​the p-type well 11 to be smaller than the area of ​​the semiconductor substrate 14 as a conductor, for example, when the voltage of the p-type well 11 and the p-type region 403 is applied, the load of the boost circuit is reduced compared to the case of applying the voltage of the semiconductor substrate 14, and power consumption is reduced.

[0091] The E-type transistor TR2 is formed in the p-type region 403. The E-type transistor TR2 is formed in an element formation region partitioned by an element isolation region 13 formed in the surface region of the semiconductor substrate 14. The element isolation region 13 is a so-called shallow trench isolation (STI) formed by embedding an insulating film such as a silicon oxide film in a trench formed to a depth of, for example, 0.1 μm to 0.5 μm.

[0092] Furthermore, an n-type well 402 forming a double well structure is formed to a predetermined depth from the surface of the semiconductor substrate 14, and is formed to a position deeper than the p-type well 11. In order to keep the potential of the n-type well 402 constant and to prevent current leakage due to crystal defects generated by ion implantation, the n-type well 402 has a peak impurity concentration of, for example, 1×10 16 cm -3 Higher 1×10 18 cm -3 In this manner, an n-type well 402 is formed in the semiconductor substrate 14, with the pn junction boundary with the p-type well 11 at a depth of, for example, 2 μm or more (typically, a depth of about 2 μm to 4 μm).

[0093] As described above, the E-type transistor TR2 is used as a high-voltage switch (switch transistor) that transfers and blocks a high voltage to the word line WL connected to the control gate electrode of the memory cell. The switch transistor is a transistor for selecting a plurality of memory blocks. In order to uniformly control the threshold voltages of the selected plurality of memory cell transistors, the switch transistor needs to uniformize the well potential. Therefore, the switch transistor needs a well portion with low resistance. In addition, the switch transistor needs to transfer a voltage of 15V or more to the word line WL. Therefore, when the E-type transistor TR2 having n-type conductivity is used as a switch transistor, it is necessary to suppress the substrate bias effect. In order to satisfy these two requirements, it is desirable to form a p-type region 403 with a low concentration of p-type impurities above the p-type well 11, for example, in a region within a depth of 1 μm from the surface of the semiconductor substrate 14. In this case, the p-type impurity concentration of the p-type region 403 is 1×10 16 cm -3 In addition, it is desirable that the density of p-type impurities is 1×10 16 cm -3 The bottom portion of the p-type well 11 is formed by ion implantation or the like so as to have a higher peak.

[0094] In this manner, in this embodiment, the voltage of the p-type well 11 and the p-type region 403 can be made negative (for example, a voltage between 0.5V and 5V) by applying a positive voltage (for example, a voltage between 0.5V and 5V) to the n-type well 402 of the semiconductor substrate 14 with the GND voltage (0V) as a reference. Therefore, in the high voltage switch shown in FIG. 4, even if the output voltage Vоut becomes a negative voltage, the voltage of the p-type well 11 and the p-type region 403 can be maintained at a voltage more negative than the output voltage Vоut, thereby preventing the diffusion layer 8 and the p-type well 11 from being reverse biased and increasing the leakage current. Therefore, it is possible to prevent the circuit from malfunctioning due to the leakage current. Since the output terminal Tоut is electrically connected to the gate electrode of the memory cell via, for example, a switching element, a structure in which a negative voltage is applied to the gate electrode of the memory cell can be realized. (Third embodiment) Next, a third embodiment will be described. In the semiconductor device of this embodiment, the circuit configuration of the high-voltage switch is different from that of the first and second embodiments shown in FIG. 4. FIG. 24 is a circuit diagram showing an example of a high-voltage switch in the third embodiment. As shown in FIG. 24, in the high-voltage switch of this embodiment, an E-type transistor TR3 is inserted between the input terminal Tin and the output terminal Tout. A discharge circuit is provided between the E-type transistor TR3 and the output terminal Tout. That is, the high-voltage switch of this embodiment has a structure in which the D-type transistor TR1 is extracted from the high-voltage switch shown in FIG. 4, and the node N2 is used as the input terminal Tin. The structure (planar structure, cross-sectional structure) of the E-type transistor TR3 can be the structure of the E-type transistor TR2 described in the first embodiment, the modified example, and the second embodiment.

[0095] Fig. 25 is a diagram showing an example of voltage waveforms during switching operation in the third embodiment. As shown in Fig. 25, the voltage waveforms of the gate voltage Vg, the input voltage Vin, and the output voltage Vout during switching operation in this embodiment are similar to the voltage waveforms during switching operation in the first embodiment shown in Fig. 15. Here, during each of periods tb1, tb2, and tb3 during which the input voltage Vin is transferred to the output voltage Vout, the resistance of the diffusion layer 8 can be reduced compared to the comparative example due to the capacitive coupling between the wiring 15 and the diffusion layer 8. Therefore, a higher current driving capability can be realized.

[0096] The present invention is not limited to the above-mentioned embodiment. For example, the method of forming the element isolation region 13 and the interlayer insulating film 27 is not limited to the above-mentioned method, and other methods of converting silicon into a silicon oxide film or a silicon nitride film, such as a method of injecting oxygen ions into deposited silicon or a method of oxidizing deposited silicon, may be used. In addition, TiO2, Al2O3, a tantalum oxide film, strontium titanate, barium titanate, zirconium lead titanate, or a laminated film of these may be used for the charge storage layer.

[0097] In the above embodiment, silicon having a p-type conductivity is used as the semiconductor substrate 14, but other single crystal semiconductor substrates containing silicon, such as SiGe mixed crystal and SiGeC mixed crystal, may be used. Furthermore, the gate electrode may be made of SiGe mixed crystal, SiGeC mixed crystal, silicide such as TiSi, NiSi, CoSi, TaSi, WSi, MoSi, or metal such as polycide, Ti, Al, Cu, TiN, or W. Furthermore, the gate electrode may be polycrystalline or may have a laminated structure of these. Furthermore, the gate electrode may be made of amorphous Si, amorphous SiGe, or amorphous SiGeC, or may have a laminated structure of these. Furthermore, although a floating gate type NAND memory cell is exemplified as the memory cell, it may be a NOR type memory cell, an AND type memory cell, or a virtual ground type memory cell, and it may have a word line switch structure having a double well connected to a plurality of word lines. Of course, the memory cell may be a MOS type memory cell that stores charge in an insulating film instead of a floating gate electrode.

[0098] Furthermore, in the above-described embodiment, the present invention has been described based on an example in which the present invention is applied to a semiconductor integrated circuit device, for example, a semiconductor memory. However, semiconductor integrated circuit devices incorporating the above-described semiconductor memory, for example, a processor, a system LSI, etc., also fall within the scope of the present invention.

[0099] Although the present invention has been described above using the first, second, and third embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made in the implementation stage without departing from the gist of the invention. In addition, the above-mentioned embodiments include various inventions, and various inventions can be extracted by appropriate combinations of the disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, if at least one of the problems described in the Problems to be Solved by the Invention column can be solved and at least one of the effects described in the Effects of the Invention column can be obtained, the configuration from which the constituent elements are deleted can be extracted as the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0100] 1...control gate, 4...Stopper area, 8...diffusion layer, 9...diffusion layer, 10…Contact plug, 11...p-type well, 13...element isolation region, 15…Wiring, 16…Wiring, 100…Wiring,

Claims

1. an electrically erasable and programmable memory cell transistor; The current terminals of the memory cell transistors are connected in series, and a select transistor is connected to one end of the series. a switch element for applying and blocking a voltage to a gate electrode of the memory cell transistor in order to control a threshold value of the memory cell transistor; Equipped with the switch element is a first n-type MOSFET having a gate insulating film having a thickness in the range of 13 nm to 50 nm and having a first end of a current terminal formed thereon; The first n-type MOSFET is a first source diffusion layer and a first drain diffusion layer having a first n-type impurity concentration and formed near the gate electrode; a second source diffusion layer and a second drain diffusion layer having a second n-type impurity density higher than the first n-type impurity density and having contact electrodes formed thereon; having a second end of the first n-type MOSFET is electrically connected to a voltage source capable of providing a voltage of 15 V or more; a first wiring layer is formed on an upper side of a semiconductor substrate of the first n-type MOSFET; Furthermore, a second wiring layer is formed above the first wiring layer, a first wiring connected to the gate electrode of the first n-type MOSFET is formed in the first wiring layer; the first wiring is formed on the gate electrode within an active region of the first n-type MOSFET, and is further formed continuously extending by 0.1 μm or more onto the first source diffusion layer or the first drain diffusion layer.

2. 2. The semiconductor device according to claim 1, wherein said first wiring is formed so as to extend onto said second source diffusion layer or said second drain diffusion layer.

3. 3. The semiconductor device according to claim 1, wherein the first n-type MOSFET is an enhancement type transistor having a positive threshold voltage.

4. 4. The semiconductor device according to claim 3, wherein the first n-type MOSFET is formed in a second p-type region surrounded by a first n-type well region formed in the p-type semiconductor substrate, and the p-type semiconductor substrate and the second p-type region can be electrically isolated by the first n-type well region.

5. a second end of the current terminal of the first n-type MOSFET is connected to a first end of the current terminal of a second n-type MOSFET having a gate insulating film thickness in the range of 13 nm to 50 nm; the second n-type MOSFET is a depletion-type transistor having a negative threshold; a second end of the current terminal of the second n-type MOSFET is electrically connected to the voltage source capable of providing a voltage of 15 V or more; 4. The semiconductor device according to claim 3, wherein the gate electrode of the first n-type MOSFET is electrically connected to the gate electrode of the second n-type MOSFET.

6. a strip-shaped gate electrode formed on a surface of a semiconductor substrate via a gate insulating film; a pair of diffusion layers formed in the semiconductor substrate so as to sandwich the gate electrode; Equipped with a first switch transistor that transfers or blocks an input voltage applied to one of the pair of diffusion layers as an output voltage to the other of the pair of diffusion layers connected to the other of the pair of diffusion layers in response to a gate voltage applied to the gate electrode; a first wiring formed above the gate electrode; the first switch transistor is a first n-type MOSFET having a gate insulating film having a thickness in the range of 13 nm to 50 nm, the gate insulating film having a first end of a current terminal formed therein; The pair of diffusion layers of the first n-type MOSFET are a first source diffusion layer and a first drain diffusion layer having a first n-type impurity density and formed in the vicinity of the gate electrode; a second source diffusion layer and a second drain diffusion layer having a second n-type impurity density higher than the first n-type impurity density and having contact electrodes formed thereon; having one of the pair of diffusion layers includes the first source diffusion layer and the second source diffusion layer; the other of the pair of diffusion layers includes the first drain diffusion layer and the second drain diffusion layer, a width of the first wiring in a direction parallel to a surface of the semiconductor substrate and corresponding to a distance between the pair of diffusion layers is wider than a width of the gate electrode; the first wiring is formed so as to continuously cover up to at least a partial region of at least one of the pair of diffusion layers.

7. 7. The semiconductor device according to claim 6, wherein a second wiring is formed above the first wiring, at least a portion of the second wiring is formed above at least one of the pair of diffusion layers, and at least a portion of the first wiring is formed so as to be sandwiched above and below between at least one of the pair of diffusion layers and the second wiring.

8. The semiconductor device according to claim 6 , wherein the first wiring is electrically connected to the gate electrode via a contact plug.

9. the first switch transistor is an enhancement type n-type transistor, 7. The semiconductor device according to claim 6, further comprising a second switch transistor which is a depletion-type n-type transistor, one of the pair of diffusion layers of the first switch transistor and the other of the pair of diffusion layers of the second switch transistor being electrically connected, and the gate electrode of the second switch transistor and the gate electrode of the first switch transistor being electrically connected.

10. the second switch transistor is a second n-type MOSFET having a gate insulating film having a thickness in the range of 13 nm to 50 nm, the gate insulating film having a first end of a current terminal formed therein; the first wiring is also formed above the gate electrode of the second switch transistor, a width of the first wiring in a direction parallel to a surface of the semiconductor substrate and corresponding to a distance between the pair of diffusion layers of the second switch transistor is wider than a width of the gate electrode; 10. The semiconductor device according to claim 9, wherein the first wiring is formed so as to continuously cover an upper portion of at least a partial region of at least one of the pair of diffusion layers of the second switch transistor.

11. 11. The semiconductor device according to claim 6, wherein the first switch transistor is formed in a p-type well surrounded by an n-type well region formed in the semiconductor substrate, and the semiconductor substrate and the p-type well are formed so as to be electrically separable by the n-type well region.

12. 7. The semiconductor device according to claim 6, wherein the first wiring is formed so as to cover up to above at least a partial region of at least one of the second source diffusion layer of the first switch transistor or the second drain diffusion layer of the first switch transistor.

13. 13. The semiconductor device according to claim 12, wherein said first wiring is formed so as to cover an entire region above said pair of diffusion layers.

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