Memory system

Abstract

To provide a memory system including a controller capable of appropriately controlling a memory unit.SOLUTION: A memory system according to the embodiment includes: a memory cell unit 100 including a memory cell array 120a (120b) including a plurality of memory cells and divided into a plurality of memory cell blocks and a drive circuit that drives the plurality of memory cells; and a controller 200 that controls the memory unit. Each of the plurality of memory cells includes a resistive change memory element, and a switching element connected in series with the resistive change memory element. The controller is configured to control the memory unit such that the number of predetermined accesses to each of the plurality of memory cell blocks increases or decreases according to the distance from the driving circuit to each of the plurality of memory cell blocks.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a memory system. [Background technology]

[0002] There has been proposed a memory system including a memory unit including a memory cell array and a controller that controls the memory unit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-006539 A Summary of the Invention [Problem to be solved by the invention]

[0004] A memory system including a controller capable of accurately controlling a memory unit is provided. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a memory unit including a memory cell array including a plurality of memory cells and divided into a plurality of memory cell blocks, a drive circuit for driving the plurality of memory cells, and a controller for controlling the memory unit, wherein each of the plurality of memory cells includes a resistive memory element and a switching element connected in series to the resistive memory element, and the controller is configured to control the memory unit so that the number of predetermined accesses to each of the plurality of memory cell blocks increases or decreases according to the distance from the drive circuit to each of the plurality of memory cell blocks. [Brief description of the drawings]

[0006] [Figure 1]1 is a block diagram showing a basic configuration of a memory system according to a first embodiment. [Diagram 2] 1 is a diagram illustrating a schematic diagram of an overall configuration of an area in which a memory cell array is provided according to a first embodiment. [Diagram 3] 1 is a perspective view illustrating a schematic partial configuration of a region in which a memory cell array is provided according to a first embodiment. [Figure 4] 1 is a cross-sectional view illustrating a schematic configuration of a magnetoresistance effect element according to a first embodiment. [Diagram 5] FIG. 2 is a cross-sectional view illustrating a schematic configuration of a selector according to the first embodiment. [Figure 6] FIG. 4 is a diagram illustrating a current-voltage characteristic of a selector according to the first embodiment. [Figure 7] FIG. 2 is a diagram illustrating a schematic configuration of a sub-memory unit according to the first embodiment. [Figure 8] FIG. 2 is a functional block diagram showing a functional configuration of a controller in the first embodiment. [Figure 9] 4 is a flowchart showing the operation of the memory system according to the first embodiment. [Figure 10] FIG. 11 is a diagram illustrating a schematic configuration of a sub-memory unit according to a first modified example of the first embodiment. [Figure 11] FIG. 13 is a diagram illustrating a schematic configuration of a sub-memory unit according to a second modified example of the first embodiment. [Figure 12] FIG. 11 is a block diagram showing a basic configuration of a memory system according to a second embodiment. [Figure 13] FIG. 11 is a functional block diagram showing a functional configuration of a controller according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] (First embodiment) FIG. 1 is a block diagram showing a basic configuration of a memory system according to the first embodiment.

[0009] 1 includes a memory unit 100 and a controller 200, and a host (host device) 300 can be connected to the controller 200. The memory unit 100 and the controller 200 may be provided in the same package, or may be provided in separate packages.

[0010] The memory unit 100 includes one or more sub-memory units. In the example shown in Fig. 1, the memory unit 100 includes a sub-memory unit 110a and a sub-memory unit 110b. The sub-memory units 110a and 110b have the same basic configuration, and the sub-memory units 110a and 110b include memory cell arrays 120a and 120b and control circuits 130a and 130b, respectively. The sub-memory units 110a and 110b may be provided in the same package or in separate packages.

[0011] In the following description, the sub-memory units 110a and 110b may be referred to as sub-memory units 110, the memory cell arrays 120a and 120b may be referred to as memory cell arrays 120, and the control circuits 130a and 130b may be referred to as control circuits 130.

[0012] Fig. 2 is a diagram showing a schematic overall configuration of the region in which the memory cell array 120 is provided. Fig. 3 is a perspective view showing a schematic partial configuration of the region in which the memory cell array 120 is provided.

[0013] 2 and 3 are directions that intersect with each other, and more specifically, the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0014] 2, a plurality of memory cells 30 are arranged at positions where a plurality of wirings 10 each extending in the X direction intersect with a plurality of wirings 20 each extending in the Y direction. That is, a plurality of memory cells 30 included in the memory cell array 120 are arranged in a matrix in the X direction and the Y direction. One of the wirings 10 and the wirings 20 corresponds to a word line, and the other of the wirings 10 and the wirings 20 corresponds to a bit line.

[0015] 3, a plurality of memory cells 30 are provided between a plurality of wirings 10 and a plurality of wirings 20. Each memory cell 30 includes a magnetoresistance effect element (resistance change memory element) 40 and a selector (switching element) 50 connected in series to the magnetoresistance effect element 40. The magnetoresistance effect element 40 and the selector 50 included in the memory cell 30 are stacked in the Z direction.

[0016] In the example shown in FIG. 3, the magnetoresistance effect element 40 is provided on the upper layer side of the selector 50, but the magnetoresistance effect element 40 may be provided on the lower layer side of the selector 50.

[0017] FIG. 4 is a cross-sectional view that illustrates a schematic configuration of the magnetoresistance effect element 40. As shown in FIG.

[0018] The magnetoresistance effect element 40 is a magnetic tunnel junction (MTJ) element and a nonvolatile memory element. The magnetoresistance effect element 40 has a structure in which a memory layer (first magnetic layer) 41, a reference layer (second magnetic layer) 42, and a tunnel barrier layer (nonmagnetic layer) 43 are stacked in the Z direction.

[0019] The memory layer 41 is a ferromagnetic layer having a variable magnetization direction, and is formed of, for example, a CoFeB layer containing cobalt (Co), iron (Fe) and boron (B). The variable magnetization direction means that the magnetization direction changes for a given write current.

[0020] The reference layer 42 is a ferromagnetic layer having a fixed magnetization direction. For example, the reference layer 42 has a structure in which a CoFeB layer containing cobalt (Co), iron (Fe) and boron (B) and a superlattice layer of cobalt (Co) and platinum (Pt) are stacked. The fixed magnetization direction means that the magnetization direction does not change with respect to a predetermined write current.

[0021] The tunnel barrier layer 43 is an insulating layer provided between the memory layer 41 and the reference layer 42, and is formed of, for example, an MgO layer containing magnesium (Mg) and oxygen (O).

[0022] When the magnetization direction of the memory layer 41 is parallel to the magnetization direction of the reference layer 42, the magnetoresistance effect element 40 is in a low resistance state with a relatively low resistance. When the magnetization direction of the memory layer 41 is antiparallel to the magnetization direction of the reference layer 42, the magnetoresistance effect element 40 is in a high resistance state with a relatively high resistance. Therefore, the magnetoresistance effect element 40 can store binary data in a non-volatile manner according to the resistance state. In addition, the magnetoresistance effect element 40 can be set to one of a low resistance state and a high resistance state according to the direction of the write current flow.

[0023] The magnetoresistance effect element 40 is a STT (spin transfer torque) type magnetoresistance effect element and has perpendicular magnetization, that is, the magnetization direction of the memory layer 41 is perpendicular to the film surface, and the magnetization direction of the reference layer 42 is perpendicular to the film surface.

[0024] Note that, although Figure 4 shows an example of a bottom-free type magnetoresistance effect element in which the memory layer 41 is located on the lower side of the reference layer 42, a top-free type magnetoresistance effect element in which the memory layer 41 is located on the upper side of the reference layer 42 may also be used.

[0025] FIG. 5 is a cross-sectional view showing a schematic configuration of the selector 50. As shown in FIG.

[0026] The selector 50 is a two-terminal switching element and has a structure in which a first electrode 51, a second electrode 52, and a selector material layer (switching material layer) 53 are stacked in the Z direction. The selector material layer 53 is formed of, for example, a material in which a metal element (e.g., arsenic) is added to an insulating material (e.g., silicon oxide).

[0027] 6 is a diagram showing a schematic diagram of the current-voltage characteristics of the selector 50. The horizontal axis represents the voltage applied between the two terminals of the selector 50, and the vertical axis represents the current flowing between the two terminals of the selector 50.

[0028] As shown in FIG. 6, the selector 50 has the characteristic of transitioning from an off state to an on state when the voltage applied between the two terminals increases and reaches a threshold voltage Vth, and transitioning from an on state to an off state when the voltage applied between the two terminals decreases and reaches a hold voltage Vhold.

[0029] 3, when a voltage is applied between the wiring 10 and the wiring 20, and the voltage applied to the selector 50 reaches a threshold voltage Vth, the selector 50 turns on and a current flows through the magnetoresistance effect element 40 connected in series to the selector 50. This makes it possible to write to or read from the magnetoresistance effect element 40.

[0030] Returning to the explanation of Fig. 1, the control circuit 130 (130a, 130b) controls the memory cell array 120 (120a, 120b) based on an instruction from the controller 200. The control circuit 130 includes a drive circuit for driving the memory cells 30 included in the memory cell array 120. In addition, when a logical address is sent from the controller 200 to the memory unit 100, the control circuit 130 may have a function of converting the logical address into a physical address.

[0031] The controller 200 controls the memory unit 100 based on instructions from the host 300, and includes a control circuit 210 and a memory 220. The control circuit 210 includes a CPU (central processing unit) and the like, and the memory 220 includes a DRAM (dynamic random access memory) and the like.

[0032] The controller 200 also includes interfaces (I / F) 230a, 230b, and 240. Information is transmitted and received between the controller 200 and the memory unit 100 via the interfaces 230a and 230b, and information is transmitted and received between the controller 200 and the host 300 via the interface 240.

[0033] FIG. 7 is a diagram showing a schematic configuration of the sub memory unit 110. As shown in FIG.

[0034] The driving circuit 141 and the driving circuit 142 are included in the control circuit 130 (130a, 130b) shown in FIG. 1, and drive the multiple memory cells 30 shown in FIG. 2 and FIG. 3. The driving circuit 141 is provided along the end of the memory cell array 120 in the X direction, and is connected to the multiple wirings 10 shown in FIG. 2 and FIG. 3. The driving circuit 142 is provided along the end of the memory cell array 120 in the Y direction, and is connected to the multiple wirings 20 shown in FIG. 2 and FIG. 3. In the following description, the driving circuit 141 and the driving circuit 142 may be referred to as the driving circuit 140.

[0035] The memory cell array 120 includes a plurality of memory cells 30, and is divided into a plurality of memory cell blocks. In the example shown in Fig. 7, the memory cell array 120 is divided into 16 memory cell blocks BLK (BLK11 to BLK71) in a matrix shape, and each memory cell block BLK has a rectangular shape. An additional explanation will be given below.

[0036] As already explained, when the voltage applied to the selector 50 reaches the threshold voltage Vth, the selector 50 turns on and a current flows through the magnetoresistance effect element 40 connected in series to the selector 50. In other words, a current flows through the memory cell 30, making it possible to write to or read from the magnetoresistance effect element 40.

[0037] When the selector 50 transitions from the off state to the on state, a spike current flows through the memory cell 30, and a spike voltage is applied to the memory cell 30. This may cause problems such as deterioration of the memory cell 30 due to breakdown of the tunnel barrier layer 43, read disturbance, etc. As a result, the characteristics and reliability of the memory cell 30 may deteriorate.

[0038] The magnitude of the spike current (spike voltage) depends on the parasitic capacitance and parasitic resistance associated with the memory cell 30. The main factors of the parasitic capacitance and parasitic resistance are considered to be the wiring (wiring 10 and wiring 20) connected to the memory cell 30 and the global wiring (global word line and global bit line) in the drive circuit 140 (drive circuit 141 and drive circuit 142).

[0039] When the global wiring is thick, the influence of the parasitic capacitance and parasitic resistance of the global wiring is greater than the influence of the parasitic capacitance and parasitic resistance of the wiring 10 and the wiring 20. Therefore, the memory cell 30 closer to the drive circuit 140 has a larger spike current (spike voltage) than the memory cell 30 farther from the drive circuit 140. Conversely, when the global wiring is thin, the memory cell 30 farther from the drive circuit 140 has a larger spike current (spike voltage) than the memory cell 30 closer to the drive circuit 140.

[0040] Therefore, in this embodiment, the memory unit 100 is controlled so that the number of accesses to the memory cells 30 generating a large spike current (spike voltage) is relatively small. This makes it possible to equalize the degree of deterioration of the memory cells 30 when viewed as a whole of the memory unit 100, and thus to extend the life of the entire memory unit 100.

[0041] For example, when a memory cell 30 closer to the drive circuit 140 has a larger spike current (spike voltage) than a memory cell 30 farther from the drive circuit 140, the number of accesses to the memory cell 30 closer to the drive circuit 140 is controlled to be relatively smaller. Conversely, when a memory cell 30 farther from the drive circuit 140 has a larger spike current (spike voltage) than a memory cell 30 closer to the drive circuit 140, the number of accesses to the memory cell 30 farther from the drive circuit 140 is controlled to be relatively smaller.

[0042] To perform the above-mentioned control, in this embodiment, the memory cell array 120 is divided into a plurality of memory cell blocks BLK according to the distance from the drive circuit 140 to each of the plurality of memory cell blocks BLK (BLK11 to BLK71).

[0043] 7, the distance from the drive circuit 140 corresponds to the total distance (D1+D2) of the distance D1 from the drive circuit 141 and the distance D2 from the drive circuit 142. For example, the distance D1 from the drive circuit 141 corresponds to the distance from the drive circuit 141 to the center position of each memory cell block BLK, and the distance D2 from the drive circuit 142 corresponds to the distance from the drive circuit 142 to the center position of each memory cell block BLK.

[0044] The total distance (D1+D2) is smallest for memory cell block BLK11 and largest for memory cell block BLK71. Memory cell blocks BLK21 and BLK22 are in the same group with the same total distance, memory cell blocks BLK31 to BLK33 are in the same group with the same total distance, memory cell blocks BLK41 to BLK44 are in the same group with the same total distance, memory cell blocks BLK51 to BLK53 are in the same group with the same total distance, and memory cell blocks BLK61 and BLK62 are in the same group with the same total distance.

[0045] FIG. 8 is a functional block diagram showing the functional configuration of the controller 200 for performing the above-mentioned control.

[0046] The controller 200 includes a determination unit 250, a storage unit 260, and a storage unit 270. The determination unit 250 mainly corresponds to the control circuit 210 in Fig. 1. The storage unit 260 and the storage unit 270 mainly correspond to the memory 220 in Fig. 1.

[0047] The storage unit 260 stores a first value based on the number of predetermined accesses actually made to each of the memory cell blocks BLK for each of the memory cell blocks BLK in each of the one or more memory cell arrays 120. In the example of Fig. 1 and Fig. 7, the storage unit 260 stores a first value based on the number of predetermined accesses made to each of the memory cell blocks BLK (BLK11 to BLK71) for each of the memory cell blocks BLK (BLK11 to BLK71) included in each of the memory cell arrays 120a and 120b. Specifically, the storage unit 260 has a function as a counter that counts the number of predetermined accesses.

[0048] The predetermined access corresponds to at least one of a write access (access for writing data to the memory cell 30) and a read access (access for reading data from the memory cell 30). That is, the number of predetermined accesses may be the total number of write accesses and read accesses, or may be only the number of write accesses, or may be only the number of read accesses.

[0049] The first value increases as the number of predetermined accesses increases. For example, the first value may be the value of the number of predetermined accesses itself, or may be a value associated with the number of predetermined accesses.

[0050] The storage unit 270 stores a second value based on the permitted number of predetermined accesses to each of the memory cell blocks BLK for each of the memory cell blocks BLK in each of the one or more memory cell arrays 120. In the example of Figures 1 and 7, the storage unit 270 stores a second value based on the permitted number of predetermined accesses to each of the memory cell blocks BLK (BLK11 to BLK71) for each of the memory cell blocks BLK (BLK11 to BLK71) included in each of the memory cell arrays 120a and 120b.

[0051] As can be seen from the above, the degree of deterioration of the memory cell 30 depends on the number of accesses to the memory cell 30 and the distance from the drive circuit 140. Therefore, the number of allowable accesses to the memory cell 30 varies depending on the distance from the drive circuit 140. For example, the allowable number of accesses corresponds to an upper limit of the number of accesses, and the memory cell 30 that has reached the allowable number of accesses cannot be accessed.

[0052] Based on the above, the second value is stored in the storage unit 270 so that the number of times the predetermined access is permitted for each of the multiple memory cell blocks BLK (BLK11 to BLK71) increases or decreases according to the distance from the drive circuit 140. The second value increases as the number of times the predetermined access is permitted increases. For example, the second value may be the value of the number of times the predetermined access is permitted itself, or may be a value associated with the number of times the predetermined access is permitted. The second value also increases or decreases according to the distance from the drive circuit 140, similar to the number of times the predetermined access is permitted. Usually, the second value is the same between memory cell blocks BLK having the same total distance (D1+D2). That is, the second value is the same between memory cell blocks BLK belonging to the same group.

[0053] The determination unit 250 determines a memory cell block BLK to be written to from among a plurality of memory cell blocks BLK included in one of the one or more memory cell arrays 120, based on a first value stored in the storage unit 260 and a second value stored in the storage unit 270. In the examples of Figures 1 and 7, the determination unit 250 determines a memory cell block BLK to be written to from among a plurality of memory cell blocks BLK (BLK11 to BLK71) included in one of the memory cell arrays 120a and 120b.

[0054] As already described, the storage unit 260 and the storage unit 270 mainly correspond to the memory 220 in FIG. 1. Since a volatile memory such as a DRAM is usually used for the memory 220, when the power supply of the controller 200 is turned off, the first value and the second value stored in the storage unit 260 and the storage unit 270 do not remain in the storage unit 260 and the storage unit 270. Therefore, when the power supply of the controller 200 is changed from an on state to an off state, the first value and the second value stored in the storage unit 260 and the storage unit 270 are saved in the sub-memory unit 110 (110a, 110b) or the host 300 in FIG. 1. When the power supply of the controller 200 is changed from an off state to an on state, the first value and the second value stored in the sub-memory unit 110 or the host 300 are set in the storage unit 260 and the storage unit 270.

[0055] Next, the operation of the memory system according to this embodiment will be described with reference to the flowchart shown in FIG. 9 as well as FIGS.

[0056] When a write command is sent from the host 300 (S11), the controller 200 performs the following operations.

[0057] First, the controller 200 provisionally selects one memory cell block BLK from among the multiple memory cell blocks BLK included in the memory cell arrays 120a and 120b, and acquires a first value stored in the memory unit 260 and a second value stored in the memory unit 270 for the provisionally selected memory cell block BLK (S12).

[0058] The determination unit 250 determines whether the provisionally selected memory cell block BLK satisfies a predetermined condition based on the first value and the second value (S13). For example, if the first value is the number of predetermined accesses and the second value is the number of times the predetermined accesses are permitted, the determination unit 250 determines whether the first value is smaller than the second value for the provisionally selected memory cell block BLK.

[0059] If a predetermined condition is satisfied (if the first value is smaller than the second value), the provisionally selected memory cell block BLK is selected (determined) as the memory cell block BLK to which data should be written, and data is written to the selected memory cell block BLK (S14).

[0060] If the first value is equal to or greater than the second value, another memory cell block BLK is tentatively selected, and steps S12 and S13 are performed for the other memory cell block BLK. In this manner, steps S12 and S13 are performed until a predetermined condition is satisfied, and data is written to the memory cell block BLK for which the predetermined condition is satisfied (S14).

[0061] As described above, in this embodiment, for each of the multiple memory cell blocks BLK in each of one or more memory cell arrays 120, a first value based on a predetermined number of accesses and a second value based on the allowed number of accesses are stored, and the memory cell block BLK to which writing should be performed is determined based on the first value and the second value.

[0062] Therefore, by setting the second value according to the position of the memory cell block BLK, even if the magnitude of the effect of the spike current (spike voltage) generated when the memory cell 30 is accessed differs depending on the position of the memory cell 30 in the memory cell array 120, the degree of deterioration of the multiple memory cells 30 included in the memory unit 100 can be made uniform, and the life of the entire memory unit 100 can be extended.

[0063] In particular, in the case where the magnitude of the effect of the spike current (spike voltage) increases or decreases depending on the distance from the drive circuit 140, by setting a second value for each of the multiple memory cell blocks BLK so that the number of permitted accesses increases or decreases depending on the distance from the drive circuit 140, it is possible to accurately equalize the degree of deterioration of the multiple memory cells 30 included in the memory unit 100.

[0064] By setting the second value as described above, the controller 200 can control the memory unit 100 so that the number of predetermined accesses to each of the memory cell blocks BLK increases or decreases according to the distance from the drive circuit 140 to each of the memory cell blocks BLK. For example, based on the first value acquired from the storage unit 260 and the second value acquired from the storage unit 270, the determination unit 250 selects (determines) the memory cell block BLK having the largest difference between the first value and the second value, thereby making it possible to effectively perform the above-mentioned control.

[0065] As can be seen from the above, in this embodiment, instead of controlling to equalize the number of predetermined accesses among a plurality of memory cell blocks BLK as in general wear leveling, taking into consideration that spike currents (spike voltages) differ among the plurality of memory cell blocks BLK, control is performed so that the number of predetermined accesses to each of the plurality of memory cell blocks BLK has a gradient according to the distance from the drive circuit 140. By such control, it is possible to equalize the degree of deterioration of the memory cells 30 among the plurality of memory cell blocks BLK.

[0066] FIG. 10 is a diagram showing a first modified example of the memory system according to the present embodiment, and is a diagram showing a schematic configuration of a sub-memory unit 110. In FIG.

[0067] 7, each memory cell block BLK has a rectangular shape, but in this modification, each memory cell block BLK has a triangular shape obtained by dividing a rectangle in half. In this modification, similar to the example shown in FIG 7, a group is formed by memory cell blocks BLK having the same total distance (D1+D2), which is the distance D1 from the drive circuit 141 and the distance D2 from the drive circuit 142.

[0068] The total distance (D1+D2) is smallest for memory cell block BLK11 and largest for memory cell block BLK81. Also, memory cell blocks BLK21 to BLK23 are in a group with the same total distance, memory cell blocks BLK31 to BLK35 are in a group with the same total distance, memory cell blocks BLK41 to BLK47 are in a group with the same total distance, memory cell blocks BLK51 to BLK57 are in a group with the same total distance, memory cell blocks BLK61 to BLK65 are in a group with the same total distance, and memory cell blocks BLK71 to BLK73 are in a group with the same total distance.

[0069] In this modification, the memory cell blocks BLK are further divided according to the distance from the drive circuit 140, so that the effects of the above-described embodiment can be more effectively achieved.

[0070] FIG. 11 is a diagram showing a second modified example of the memory system according to the present embodiment, and is a diagram showing a schematic configuration of a sub-memory unit 110. In FIG.

[0071] In the example shown in Figure 7, the distance from the drive circuit 140 corresponds to the sum of the distance D1 from the drive circuit 141 and the distance D2 from the drive circuit 142 (D1 + D2), but in this modified example, the distance from the drive circuit 140 corresponds to the shorter distance DS of the distance D1 from the drive circuit 141 and the distance D2 from the drive circuit 142.

[0072] In the example of FIG. 11, memory cell blocks BLK11 to BLK17 are in a group with the same distance DS, memory cell blocks BLK21 to BLK25 are in a group with the same distance DS, memory cell blocks BLK31 to BLK33 are in a group with the same distance DS, and memory cell block BLK41 is in another group.

[0073] In this modified example, it is possible to obtain the same effects as those of the above-described embodiment.

[0074] Second Embodiment Next, a second embodiment will be described. Note that the basic points are the same as those in the first embodiment, and therefore the description of the points described in the first embodiment will be omitted.

[0075] FIG. 12 is a block diagram showing a basic configuration of a memory system according to the second embodiment.

[0076] The basic configuration of the memory system shown in Fig. 12 is similar to the configuration of the first embodiment shown in Fig. 1. In this embodiment, the sub-memory units 110a and 110b are provided with temperature detectors 150a and 150b, respectively, and the temperature detectors 150a and 150b can detect the ambient temperatures (nearby temperatures) of the memory cell arrays 120a and 120b, respectively.

[0077] As in the first embodiment, in the following description, the sub-memory units 110a and 110b may each be referred to as sub-memory units 110, the memory cell arrays 120a and 120b may each be referred to as memory cell arrays 120, the control circuits 130a and 130b may each be referred to as control circuits 130, and the temperature detectors 150a and 150b may each be referred to as temperature detectors 150.

[0078] 12, the sub-memory units 110a and 110b are provided with temperature detectors 150a and 150b, respectively, but the sub-memory units 110a and 110b may share one temperature detector 150. That is, one temperature detector 150 may be provided in the memory unit 100, and one temperature detector 150 may be shared by a plurality of sub-memory units 110. Furthermore, in the case of a memory system in which the memory unit 100 and the controller 200 are packaged together, the temperature detector 150 may be provided in the memory system, not necessarily in the memory unit 100.

[0079] FIG. 13 is a functional block diagram showing the functional configuration of the controller 200 in this embodiment.

[0080] The basic functional configuration of the controller 200 shown in Fig. 13 is similar to the functional configuration shown in Fig. 8 of the first embodiment. In this embodiment, the controller 200 is provided with a stored value change unit 280. The stored value change unit 280 changes the second value stored in the storage unit 270 in accordance with the ambient temperature of each of the one or more memory cell arrays 120. A further explanation will be given below.

[0081] The characteristics and reliability of the memory cell 30 (e.g., read disturb probability and dielectric breakdown failure rate of the tunnel barrier layer) usually depend on the temperature of the memory cell 30 (particularly, the temperature of the magnetoresistance effect element 40). For example, the read disturb probability generally deteriorates as the temperature of the memory cell 30 increases. Furthermore, the reliability of the memory cell 30 varies depending on the temperature dependency of the write current Ic. That is, the characteristics and reliability of the memory cell 30 may deteriorate as the temperature increases or may deteriorate as the temperature decreases.

[0082] In this embodiment, based on the temperature dependence of the characteristics and reliability of the memory cells 30, the second values ​​of each of the multiple memory cell blocks BLK stored in the memory unit 270 are changed in accordance with the ambient temperature (nearby temperature) of the memory cell array 120 detected by the temperature detector 150.

[0083] Specifically, the second value stored in the memory unit 270 is changed in accordance with the ambient temperature (temperature in the vicinity) of the memory cell array 120 so as to change the degree to which the number of permitted specified accesses increases or decreases (increase rate or decrease rate) according to the distance from the drive circuit 140.

[0084] For example, if the characteristics or reliability of the memory cell 30 deteriorates at high temperatures, the second value is changed so that the degree to which the permitted number of predetermined accesses increases or decreases according to the distance from the drive circuit 140 is greater at high temperatures than at low temperatures. Conversely, if the characteristics or reliability of the memory cell 30 deteriorates at low temperatures, the second value is changed so that the degree to which the permitted number of predetermined accesses increases or decreases according to the distance from the drive circuit 140 is greater at low temperatures than at high temperatures.

[0085] The basic configuration and basic control method of this embodiment are the same as those of the first embodiment, and the same effects as those of the first embodiment can be obtained in this embodiment. Moreover, by performing the control as described above, the degree to which the number of predetermined accesses increases or decreases according to the distance from the drive circuit 140 can be effectively changed according to the temperature around the memory cell array 120, that is, according to the temperature of the usage environment, and the life of the entire memory unit 100 can be effectively extended.

[0086] In the above-described first and second embodiments, a magnetoresistance effect element is used as the resistance change memory element, but other resistance change memory elements may be used.

[0087] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0088] 10, 20... Wiring 30... Memory cell 40...Magnetoresistance effect element 41: memory layer; 42: reference layer; 43: tunnel barrier layer 50...Selector (switching element) 51...first electrode 52...second electrode 53...selector material layer 100…Memory unit 110, 110a, 110b...sub memory units 120, 120a, 120b...Memory cell array 130, 130a, 130b...Control circuit 140, 141, 142...Drive circuit 150, 150a, 150b...Temperature detector 200: controller 210: control circuit 220: memory 230a, 230b, 240... interfaces 250: Determination unit 260, 270: Storage unit 280: Storage value change unit 300…Host

Claims

1. a memory unit including a memory cell array including a plurality of memory cells and divided into a plurality of memory cell blocks, and a drive circuit for driving the plurality of memory cells; A controller for controlling the memory unit; A memory system comprising: Each of the plurality of memory cells includes a resistance change memory element and a switching element connected in series to the resistance change memory element; The controller is configured to control the memory unit such that a number of predetermined accesses to each of the plurality of memory cell blocks increases or decreases according to a distance from the drive circuit to each of the plurality of memory cell blocks.

23. A memory system comprising:

2. The controller: storing a first value for each of the plurality of memory cell blocks based on the number of times the predetermined access has been made to each of the plurality of memory cell blocks; storing a second value for each of the plurality of memory cell blocks based on the number of times the predetermined access to each of the plurality of memory cell blocks is permitted; and determining a memory cell block to be written from among the plurality of memory cell blocks based on the first value and the second value stored for each of the plurality of memory cell blocks.

2. The memory system of claim 1.

3. The number of times the predetermined accesses to each of the plurality of memory cell blocks is permitted increases or decreases according to the distance from the drive circuit.

3. The memory system according to claim 2.

4. the plurality of memory cells included in the memory cell array are arranged in a first direction and a second direction intersecting the first direction; The drive circuit includes a first drive circuit provided along an end of the memory cell array in the first direction, and a second drive circuit provided along an end of the memory cell array in the second direction.

2. The memory system of claim 1.

5. The distance from the drive circuit corresponds to the sum of a first distance from the first drive circuit and a second distance from the second drive circuit.

5. The memory system according to claim 4.

6. The distance from the drive circuit corresponds to the shorter of a first distance from the first drive circuit and a second distance from the second drive circuit.

5. The memory system according to claim 4.

7. The memory system further includes a temperature detector for detecting an ambient temperature of the memory cell array.

2. The memory system of claim 1.

8. The controller is configured to change the degree to which the number of predetermined accesses increases or decreases according to the distance from the drive circuit, depending on the temperature around the memory cell array.

8. The memory system of claim 7.

9. a memory unit including one or more memory cell arrays each including a plurality of memory cells, each of the one or more memory cell arrays being divided into a plurality of memory cell blocks; A controller for controlling the memory unit; A memory system comprising: Each of the plurality of memory cells includes a resistance change memory element and a switching element connected in series to the resistance change memory element; The controller: storing a first value for each of the plurality of memory cell blocks in each of the one or more memory cell arrays, the first value being based on a predetermined number of accesses made to each of the plurality of memory cell blocks; storing a second value for each of the plurality of memory cell blocks in each of the one or more memory cell arrays, the second value being based on the number of times the predetermined access is permitted for each of the plurality of memory cell blocks; and determining a memory cell block to be written from among the plurality of memory cell blocks included in one of the one or more memory cell arrays based on the first value and the second value stored for each of the plurality of memory cell blocks in each of the one or more memory cell arrays.

23. A memory system comprising:

10. The controller determines a memory cell block in which the number of the predetermined accesses is less than the permitted number of the predetermined accesses as a memory cell block in which the writing should be performed.

10. The memory system of claim 9.

11. The memory system further includes a temperature detector for detecting an ambient temperature of each of the one or more memory cell arrays.

10. The memory system of claim 9.

12. The controller is configured to modify the second value stored for each of the plurality of memory cell blocks of each of the one or more memory cell arrays in response to an ambient temperature of each of the one or more memory cell arrays.

12. The memory system of claim 11.

13. The predetermined access corresponds to at least one of a write access and a read access.

10. The memory system according to claim 1 or 9.

14. The resistance change memory element and the switching element included in each of the plurality of memory cells are stacked.

10. The memory system according to claim 1 or 9.

15. The resistance change memory element is a magnetoresistance effect element.

10. The memory system according to claim 1 or 9.

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