Semiconductor device

Abstract

To provide a semiconductor device which can prevent removal of resin from a semiconductor chip.SOLUTION: A semiconductor device comprises: a first semiconductor chip which has a first surface including a first region and a second region adjacent to the first region; a second semiconductor chip which is provided on the first region; and resin which is provided on the second region and comes into contact with the second semiconductor chip. At least part of a boundary face between the first semiconductor chip and the resin has an irregular surface.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] Among semiconductor devices, there are some in which a semiconductor element is sealed with a molding resin. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-2539 [Patent Document 2] US Patent Application Publication US2004 / 0108602 [Patent Document 3] JP 2001-338932 A Summary of the Invention [Problem to be solved by the invention]

[0004] For example, if the adhesion between the molding resin and the semiconductor element is poor, the molding resin may peel off from the semiconductor element.

[0005] An object of the present disclosure is to provide a semiconductor device capable of suppressing peeling of resin from a semiconductor chip. [Means for solving the problem]

[0006] The semiconductor device disclosed herein comprises a first semiconductor chip having a first surface including a first region and a second region adjacent to the first region, a second semiconductor chip provided on the first region, and a resin provided on the second region and in contact with the second semiconductor chip, wherein at least a portion of the interface between the first semiconductor chip and the resin is uneven. [Brief description of the drawings]

[0007] [Figure 1] 1 is a perspective view of a storage device according to a first embodiment. [Diagram 2] 1 is a schematic plan view of a semiconductor device according to a first embodiment, as viewed from above. [Diagram 3] 3 is a cross-sectional view taken along line III-III shown in FIG. 2. [Figure 4] 3 is an enlarged cross-sectional view of a hole taken along line III-III in FIG. 2. [Diagram 5] 3 is an enlarged cross-sectional view of a first modified example of a hole portion taken along line III-III in FIG. 2. [Figure 6] 3 is an enlarged cross-sectional view of a second modified example of the hole portion taken along the line III-III shown in FIG. 2. [Figure 7] 1 is a plan view of a cross section of a convex portion parallel to the XY plane as viewed from above. [Figure 8] 1 is a plan view of a cross section of a convex portion parallel to the XY plane as viewed from above. [Figure 9] 1 is a plan view of a cross section of a convex portion parallel to the XY plane as viewed from above. [Figure 10] 1 is a plan view of a cross section of a convex portion parallel to the XY plane as viewed from above. [Figure 11] 1 is a plan view of a cross section of a unit protrusion parallel to the XY plane as viewed from above. [Figure 12] 1 is a plan view of a cross section of a unit protrusion parallel to the XY plane as viewed from above. [Figure 13] 1 is a plan view of a cross section of a unit protrusion parallel to the XY plane as viewed from above. [Figure 14] 1 is a plan view of a cross section of a unit protrusion parallel to the XY plane as viewed from above. [Figure 15] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 16] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 17] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 18]2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 19] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 20] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 21] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 22] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 23] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 24] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 25] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 26] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 27] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 28] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 29] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 30] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 31] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 32] 2A to 2C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 33] FIG. 13 is a schematic cross-sectional view for explaining a structural example of a semiconductor device according to a second embodiment, showing a cross-sectional view parallel to the YZ plane. [Diagram 34] 5A to 5C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the second embodiment. [Diagram 35]5A to 5C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the second embodiment. [Diagram 36] 5A to 5C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the second embodiment. [Figure 37] 5A to 5C are schematic diagrams illustrating a manufacturing process of the semiconductor device according to the second embodiment. [Figure 38] FIG. 13 is a schematic cross-sectional view for explaining a structural example of a semiconductor device according to a third embodiment, showing a cross-sectional view parallel to the YZ plane. [Figure 39] 13 is a schematic cross-sectional view for explaining an example of the pad and via structure according to the fourth embodiment, showing a cross-sectional view parallel to the YZ plane. FIG. [Diagram 40] 13 is a schematic cross-sectional view for explaining an example of the structure of a concave surface and a convex portion according to the fourth embodiment, showing a cross-sectional view parallel to the YZ plane. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In order to facilitate understanding of the description, the same components in each drawing are denoted by the same reference numerals as much as possible, and duplicated description will be omitted.

[0009] Each drawing may show an X-axis, a Y-axis, and a Z-axis. The X-axis, the Y-axis, and the Z-axis form a right-handed three-dimensional Cartesian coordinate system. Hereinafter, the direction of the X-axis arrow may be called the X-axis + direction, and the direction opposite to the arrow may be called the X-axis - direction, and the same applies to the other axes. The Z-axis + direction and the Z-axis - direction may be called "upper" and "lower", respectively. Planes perpendicular to the X-axis, Y-axis, or Z-axis may be called the YZ plane, ZX plane, or XY plane, respectively. The Z-axis direction may be called the "upper / lower direction". "Upper", "lower", and "upper / lower direction" are terms that indicate the relative positional relationship within the drawing, and are not terms that define the orientation based on the vertical direction.

[0010] In addition, unless otherwise specifically explained, the dimensions of components shown in each drawing may be shown differently from their actual dimensions in order to make the explanation easier to understand.

[0011] In this specification, the term "connection" includes not only a physical connection but also an electrical connection, and unless otherwise specified, includes not only a direct connection but also an indirect connection via another object.

[0012] In this specification, the term "formed above" does not only mean a case where the material is formed in contact with the material above, but also includes a case where the material is formed above via another object, unless otherwise specified. The same applies to "formed below" and the like.

[0013] [First embodiment] The configuration of the semiconductor device according to the first embodiment will be described below. Fig. 1 is a perspective view of the memory device according to the first embodiment. As shown in Fig. 1, the memory device 16 includes four semiconductor devices 10 and a wiring board 25. Note that the memory device 16 may include three or less or five or more semiconductor devices 10.

[0014] The four semiconductor devices 10 are stacked in a stepped manner so that the second semiconductor chip 22 is exposed when viewed from above. The upper and lower semiconductor devices 10 are bonded together by a die attach film 24. The lowest semiconductor device 10 is bonded to the upper surface 25a of the wiring board 25 by the die attach film 24.

[0015] The four semiconductor devices 10 and the wiring board 25 are electrically connected via bonding wires 81.

[0016] Fig. 2 is a schematic plan view of the semiconductor device according to the first embodiment as viewed from above, and Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2.

[0017] As shown in FIGS. 2 and 3, the semiconductor device 10 includes a first semiconductor chip 21, a second semiconductor chip 22, and a sealing resin .

[0018] The first semiconductor chip 21 has a surface 21a (an example of a "first surface") on the upper side. The surface 21a is approximately parallel to the XY plane, and has a rectangular shape when viewed from above.

[0019] The surface 21a includes a first region 31 and a second region 32 adjacent to the first region 31. The second semiconductor chip 22 is provided on the first region 31. In this embodiment, the entire periphery of the first region 31 contacts the second region 32. In other words, the first region 31 is surrounded by the second region 32. Note that a configuration in which a portion of the entire periphery of the first region 31 contacts the second region 32 may also be used.

[0020] When surface 21a is viewed in a plane along a direction perpendicular to surface 21a (hereinafter sometimes referred to as when viewed in a plane from above), first semiconductor chip 21 has opposing sides 121a (an example of a "first side") and 121b (an example of a "second side"), and opposing sides 121c and 121d.

[0021] In this embodiment, sides 121a and 121b are long sides substantially parallel to the X-axis, and are located in the +Y-axis direction and the -Y-axis direction, respectively. Sides 121c and 121d are short sides substantially parallel to the Y-axis, and are located in the +X-axis direction and the -X-axis direction, respectively. Surface 21a may be square.

[0022] The second semiconductor chip 22 has sides 122a and 122b facing each other, and sides 122c and 122d facing each other, when viewed from above in a plan view.

[0023] In this embodiment, the sides 122a and 122b are long sides substantially parallel to the X-axis and are located in the +Y-axis direction and the -Y-axis direction, respectively. The sides 122c and 122d are short sides substantially parallel to the Y-axis and are located in the +X-axis direction and the -X-axis direction, respectively. The first region 31 may be a square.

[0024] That is, when viewed in a plan view from above, first region 31 has a rectangle that is long in the X-axis direction, and completely overlaps second semiconductor chip 22. When viewed in a plan view from above, second region 32 is a region obtained by removing the rectangle defined by the outline of first region 31, i.e., second semiconductor chip 22, from the rectangle defined by the outline of first semiconductor chip 21.

[0025] First region 31 is located closer to side 121a than to side 121b. In particular, distance d1 between side 121a of first semiconductor chip 21 and side 122a of second semiconductor chip 22 is smaller than distance d2 between side 121b of first semiconductor chip 21 and side 122b of second semiconductor chip 22.

[0026] A distance d3 between side 121c of first semiconductor chip 21 and side 122c of second semiconductor chip 22 is smaller than distance d2. A distance d4 between side 121d of first semiconductor chip 21 and side 122d of second semiconductor chip 22 is smaller than distance d2. Distances d3 and d4 are, for example, approximately the same.

[0027] The sealing resin 23 is provided on the second region 32 and is in contact with the second semiconductor chip 22. When viewed in a plan view from above, the entirety of the second semiconductor chip 22 is exposed from the sealing resin 23.

[0028] In detail, the sealing resin 23 is, for example, an epoxy resin. When viewed from above in a plan view, the second region 32 is covered with the sealing resin 23. Four faces of the second semiconductor chip 22 perpendicular to the XY plane, i.e., the side faces, are in contact with the sealing resin 23.

[0029] Meanwhile, the entire upper surface 22c (one example of an "upper surface") of the second semiconductor chip 22 is exposed from the sealing resin 23. Note that a configuration may be adopted in which a part of the surface 22c of the second semiconductor chip 22 is exposed from the sealing resin 23 when viewed in a plan view from above.

[0030] A plurality of bonding pads 73 are provided in a line substantially parallel to the X-axis direction on the front surface 22c of the second semiconductor chip 22. Bonding wires 81 are connected to the bonding pads 73.

[0031] The first semiconductor chip 21 includes a semiconductor layer 61, an insulating layer 62, a plurality of pads 51 (an example of a "first pad"), and a plurality of dummy pads 56 (an example of a "first pad").

[0032] The semiconductor layer 61 is, for example, a complementary metal oxide semiconductor (CMOS). The upper surface of the semiconductor layer 61 includes a circuit formation region 21b (see FIG. 2) in which a CMOS circuit is formed. An insulating layer 62 containing, for example, silicon and oxygen is provided above the semiconductor layer 61. In this embodiment, the surface 21a is the upper surface of the insulating layer 62.

[0033] A plurality of pads 51 and a plurality of dummy pads 56 are formed in the first region 31 on the surface 21a. The pads 51 and the dummy pads 56 include, for example, copper, and are exposed from the insulating layer 62. The first region 31 is approximately flat.

[0034] A via 53 is connected below the pad 51. The via 53 is electrically connected to a CMOS circuit in the circuit formation region 21b through a wiring layer 62a formed in an insulating layer 62, for example.

[0035] The second semiconductor chip 22 includes a semiconductor layer 71, an insulating layer 72, a plurality of pads 52 (an example of a "second pad"), and a plurality of dummy pads 57 (an example of a "second pad").

[0036] The semiconductor layer 71 includes, for example, silicon. In the second semiconductor chip 22, a hole 22b penetrating the semiconductor layer 71 is formed. Also, an insulating layer may be used instead of the semiconductor layer 71. The insulating layer may be, for example, silicon oxide or silicon nitride.

[0037] The insulating layer 74 includes, for example, polyimide. The insulating layer 74 is provided on the upper surface of the semiconductor layer 71, the upper surface of the sealing resin 23, and the side wall of the hole 22b. The bonding pad 73 includes, for example, copper, and is provided on the upper surface of the insulating layer 74 and the bottom surface of the hole 22b.

[0038] A memory array 72a is provided on the lower surface of the semiconductor layer 71. The memory array 72a includes, for example, a plurality of stacked memory chips. An insulating layer 72 covering the memory array 72a is provided below the semiconductor layer 71. The insulating layer 72 includes, for example, silicon and oxygen.

[0039] In a region 131 facing the first region 31 on the surface 22a (an example of a "second surface") below the insulating layer 72, a plurality of pads 52 and a plurality of dummy pads 57 are formed. The pads 52 and the dummy pads 57 include, for example, copper, and are exposed from the insulating layer 72. The region 131 is approximately flat.

[0040] A via 54 is connected above the pad 52. The memory array 72a is electrically connected to the via 54 through, for example, a via 72b and a wiring layer 72d formed in the insulating layer 72. The bonding pad 73 is electrically connected to the via 54 through, for example, a via 72c and a wiring layer 72e formed in the insulating layer 72.

[0041] The pads 51 and dummy pads 56 formed on the first semiconductor chip 21 are bonded to the pads 52 and dummy pads 57 formed on the second semiconductor chip 22, respectively, whereby the first semiconductor chip 21 and the second semiconductor chip 22 are bonded together.

[0042] In detail, the pad 51 and the dummy pad 56, and the pad 52 and the dummy pad 57 are respectively bonded by annealing. Between the insulating layer 62 and the insulating layer 72, an attractive force due to, for example, hydrogen bonding acts.

[0043] Fig. 4 is an enlarged cross-sectional view of the hole taken along line III-III shown in Fig. 2. As shown in Figs. 2 to 4, in the second region 32 on the surface 21a, at least a part of the interface 36 between the first semiconductor chip 21 and the sealing resin 23 is uneven.

[0044] In this embodiment, the second region 32 includes a third region 33 located between the side 121a of the first semiconductor chip 21 and the first region 31 (see FIG. 2). An interface 36 in at least a part of the third region 33 is uneven (see FIG. 3).

[0045] In detail, as described above, the first region 31 and the region 131 are substantially flat, and therefore the bonding surfaces 37 of the first semiconductor chip 21 and the second semiconductor chip 22 are also substantially flat. The third region 33 includes a plurality of concave surfaces 39 formed to be recessed below a plane 38 including the bonding surfaces 37 of the first semiconductor chip 21 and the second semiconductor chip 22.

[0046] The sealing resin 23 has a protrusion 23a that fits into at least a part of a hole 39a whose inner wall is the concave surface 39. In this embodiment, the protrusion 23a fits into the entire hole 39a. That is, the first semiconductor chip 21 has projections and recesses, and the sealing resin 23 also has projections and recesses.

[0047] The shape of a cross section perpendicular to the surface 21a of the protrusion 23a and the hole 39a, for example, a cross section taken along the cutting line III-III (hereinafter, sometimes referred to as a first cross section), and the shape of the first cross section of the pad 51 and the dummy pad 56 are a first shape. In this embodiment, the first shape is, for example, a rectangle. In the hole 39a having the concave surface 39 as an inner wall, the shape of the bottom surface 39b and the shape of the opening 39c are substantially the same.

[0048] In this embodiment, the configuration in which the first cross section of the protrusion 23a and the hole 39a has a rectangular shape has been described, but the present invention is not limited to this. Fig. 5 is an enlarged cross-sectional view of a first modified hole taken along the line III-III shown in Fig. 2. As shown in Fig. 5, the first modified hole 39a has an area of ​​the opening 39c larger than the area of ​​the bottom surface 39b.

[0049] In detail, the shape of the first cross section of the first modified example of the protrusion 23a and the hole 39a is substantially the same as the shape of the first cross section of the pad 51 and the via 53.

[0050] Fig. 6 is an enlarged cross-sectional view of the second modified example of the hole taken along the line III-III shown in Fig. 2. As shown in Fig. 6, the shape of the first cross section of the second modified example of the protrusion 23a and the hole 39a is substantially the same as the shape of the first cross section of a case in which a plurality of vias 53 are provided below the pad 51.

[0051] Further, the first cross-sectional shapes of the plurality of protrusions 23a and holes 39a are not limited to the same configuration, and may be partially or entirely different from one another. Incidentally, the entire second region 32 of the surface 21a of the first semiconductor chip 21 that is not joined to the second semiconductor chip 22 may have irregularities. For example, the second region 32 on the negative Y-axis direction side in FIG. 3 also has irregularities (not shown, but for example, a hole similar to the hole 39a). The sealing resin 23 is in contact with the hole.

[0052] 7 to 10 are plan views of the cross section of the protrusion 23a parallel to the XY plane as viewed from above. As shown in FIG. 7, the concave surface 39 exhibits a geometric pattern when viewed from above. More specifically, the concave surface 39 exhibits a lattice pattern. Specifically, in the examples shown in FIGS. 7, 8, 9, and 10, the concave surface 39 exhibits a checkered pattern, a band pattern, a mesh pattern, and a houndstooth pattern, respectively. These lattice patterns can be generated by arranging a plurality of unit protrusions 23b, each of which has a square shape in a cross section parallel to the XY plane, according to a predetermined rule.

[0053] In the example shown in Figures 7 and 8, a part or all of the unit convex portions 23b are separated to form a plurality of convex portions 23a. In the example shown in Figures 9 and 10, a plurality of unit convex portions 23b are connected together to form a single convex portion 23a. In the example shown in Figure 7, the unit convex portion 23b and the convex portion 23a are the same.

[0054] Figures 11 to 14 are plan views of a cross section of unit convex portion 23b parallel to the XY plane when viewed from above. Figures 11 to 14 show an example in which unit convex portion 23b and convex portion 23a are the same. As shown in Figures 11 to 14, when viewed from above, concave surface 39 has a contour of a square, a rectangle, a circle, or an ellipse, respectively.

[0055] [Method of manufacturing semiconductor device] A method for manufacturing the semiconductor device 10 will be described below as an example of a method for manufacturing the semiconductor device according to this embodiment.

[0056] 15, an insulating layer 72 including a memory array 72a, vias 72b and 72c, a wiring layer 72d, a pad 52, and a dummy pad 57 is formed on an array wafer 211. A lower surface of the insulating layer 72 is covered with, for example, an alkali-soluble protective film 212.

[0057] 16, the ends of the array wafer 211 in the +Y-axis direction and the -Y-axis direction are trimmed. In addition, on the lower surface of the protective film 212, a BG protective tape 213 is provided.

[0058] 17, the array wafer 211 is placed on a dicing tape 214. After the BG protective tape 213 is removed from the array wafer 211, the array wafer 211 is cleaned. Then, the array wafer 211 is diced from the upper surface to form grooves 215. The material formed on the array wafer 211 is divided into each second semiconductor chip 22 at the grooves 215.

[0059] 18, each second semiconductor chip 22 is transferred from the dicing tape 214 to the dicing tape 216. Then, the protective film 212 is removed. As pretreatment for the process of bonding the second semiconductor chip 22 to the first semiconductor chip 21, the array wafer 211 is subjected to a nitrogen plasma treatment and a water washing treatment.

[0060] 19, a CMOS circuit is formed on the upper surface of the CMOS wafer 311. Then, an insulating layer 62 including pads 51, dummy pads 56 and 56a, and a wiring layer 62a is formed on the upper surface of the CMOS wafer 311. Details of the dummy pad 56a will be described later.

[0061] 20, a protective film 312 is formed on the upper surface of the insulating layer 62. Then, grooves 315 are formed on the CMOS wafer 311 by a laser grooving process in which a laser is irradiated from the upper surface. The CMOS wafer 311 is divided into each first semiconductor chip 21 at the grooves 315.

[0062] 21, the protective film 312 is removed. As pretreatment for bonding the second semiconductor chip 22 to the first semiconductor chip 21, the CMOS wafer 311 is subjected to a nitrogen plasma treatment and a water washing treatment. Then, the second semiconductor chip 22 is bonded to the first semiconductor chip 21. At this time, of the multiple dummy pads 56, the dummy pad 56a is not bonded to the dummy pad 57 and is exposed. Thereafter, the CMOS wafer 311 is annealed.

[0063] 22, the CMOS wafer 311 is wet-etched to remove the dummy pads 56a. As a result, a part of the front surface 21a of the first semiconductor chip 21 becomes a concave surface 39, and a hole 39a is formed. For example, if a via 53 is formed below the dummy pad 56a, the via 53 is also removed by wet etching together with the dummy pad 56a.

[0064] 23, sealing resin 23 is provided above CMOS wafer 311. As a result, first semiconductor chip 21, second semiconductor chip 22, and groove portion 315 are sealed with sealing resin 23. Then, sealing resin 23 enters hole portion 39a having concave surface 39 as an inner wall, thereby forming convex portion 23a. As a result, part of interface 36 between first semiconductor chip 21 and sealing resin 23 becomes uneven.

[0065] 24, the upper surface of the sealing resin 23 is subjected to chemical mechanical polishing, so that the upper surface of the semiconductor layer 71, i.e., the surface 22c of the second semiconductor chip 22, is exposed from the sealing resin 23. Then, the CMOS wafer 311 is subjected to a degassing annealing process.

[0066] Next, as shown in FIG. 25, a film is formed on the surface 22c of the second semiconductor chip 22 by a PEP (Photo Engraving Process) method, a resist is applied, exposed, developed, and peeled off, and then a hole 22b penetrating to the insulating layer 72 is formed in the semiconductor layer 71 by reactive ion etching.

[0067] Next, as shown in FIG. 26, after film formation, resist coating, exposure, development, and peeling are performed on the surface 22c of the second semiconductor chip 22 by the PEP method, an insulating layer 74 containing, for example, polyimide is formed above the semiconductor layer 71.

[0068] 27, a film is formed on the upper surface of the insulating layer 74 by the PEP method, followed by resist coating, exposure, development, and peeling, to form an insulating layer 75 which is a resist. Then, nickel and gold are vapor-deposited to form a bonding pad 73.

[0069] Next, as shown in FIG. 28, the insulating layer 75 is removed, for example, by an etching process.

[0070] Next, as shown in FIGS. 29 and 30, the CMOS wafer 311 is diced along the dicing lines 104X and 104Y to be separated into a plurality of semiconductor devices 10 (see FIG. 30).

[0071] In detail, a plurality of semiconductor devices 10 are formed on the CMOS wafer 311 (see FIG. 29). For example, when viewed from above in a plan view, the CMOS wafer 311 is diced along a dicing line 104X that extends between sides 121a and 122a and is substantially parallel to the X-axis. Also, the CMOS wafer 311 is diced along a dicing line 104Y that extends between sides 121c and 122c and is substantially parallel to the Y-axis.

[0072] This produces a semiconductor device 10 in which the side surface 40 that connects to the second region 32 at the edge 121a of the surface 21a, i.e., the Y-axis + direction surface of the CMOS wafer 311 and the Y-axis + direction surface of the insulating layer 62, are exposed at the diced cut surface, as shown in FIG.

[0073] The CMOS wafer 311 may be configured to be diced along a dicing line extending between the side 121d and the side 122d substantially parallel to the Y-axis.

[0074] 31 and 32, the CMOS wafer 311 may be configured to be diced along dicing lines 105X and 105Y passing through approximately the center of the groove 315, and separated into a plurality of semiconductor devices 11.

[0075] In this configuration, the sealing resin 23 is provided from the second region 32 to the side surface 40. In detail, for example, the lower surface of the CMOS wafer 311 is polished, and thereby the lower bottom of the groove portion 315 is removed.

[0076] That is, the CMOS wafer 311 between the two adjacent semiconductor devices 11 is removed. As a result, only the sealing resin 23 is provided between the two adjacent semiconductor devices 11.

[0077] In this case, when dicing is performed along the dicing lines 105X and 105Y, the CMOS wafer 311 is not cut, but the sealing resin 23 is cut.

[0078] As a result, semiconductor device 11 is produced in which side surface 40 is not exposed at the diced cut surface (see FIG. 32).

[0079] (effect) If the entire upper surface 22c of the second semiconductor chip 22 is covered with the sealing resin 23, the sealing resin 23 in the third region 33 is supported from above by the sealing resin 23 covering the surface 22c of the second semiconductor chip 22. This prevents the sealing resin 23 in the third region 33 from peeling off.

[0080] On the other hand, when at least a part of the front surface 22c of the second semiconductor chip 22 is exposed from the sealing resin 23 in a plan view from above, the sealing resin 23 in the third region 33 is weakly supported from above. For this reason, the sealing resin 23 may peel off during dicing.

[0081] Furthermore, since the degree of adhesion between the silicon contained in first semiconductor chip 21 and sealing resin 23 is low, sealing resin 23 is even more likely to peel off during dicing.

[0082] In contrast, in the semiconductor devices 10 and 11 (see FIGS. 3 and 32), the interface 36 between the first semiconductor chip 21 and the sealing resin 23 is uneven. This can increase the degree of adhesion between the first semiconductor chip 21 and the sealing resin 23, thereby preventing the sealing resin 23 from peeling off during dicing.

[0083] [Second embodiment] A semiconductor device 12 according to a second embodiment will be described. In the second and subsequent embodiments, the description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects due to similar configurations will not be mentioned in each embodiment.

[0084] As shown in FIG. 33, in the semiconductor device 12, at the uneven interface 36, a part of the sealing resin 23 comes into contact with a metal having the same composition as the pads 51 and the dummy pads 56.

[0085] In this embodiment, the via 53 is provided below the dummy pad 56a. At the uneven interface 36, the dummy pad 56a and the via 53 are exposed from the insulating layer 62. The dummy pad 56a and the via 53 exposed from the insulating layer 62 contact the sealing resin 23.

[0086] [Method of manufacturing semiconductor device] In the manufacturing method of the semiconductor device 12, instead of a process of removing the dummy pads 56a in the CMOS wafer 311 by wet etching (see FIG. 22), a process of forming grooves 315 by a laser grooving process (see FIG. 20) is performed, followed by a process of forming irregularities in the third region 33 by a laser.

[0087] Specifically, a protective film 312 is formed on the upper surface of the insulating layer 62, as shown in FIG.

[0088] 35, the CMOS wafer 311 is irradiated with a laser from the upper surface thereof to form grooves 315. The CMOS wafer 311 is divided into the first semiconductor chips 21 at the grooves 315. Then, for example, a laser with a weakened output is irradiated onto the third region 33 to remove the protective film 312, the insulating layer 62, the dummy pads 56, and the vias 53.

[0089] 36, the protective film 312 is removed. As pretreatment for bonding the second semiconductor chip 22 to the first semiconductor chip 21, the CMOS wafer 311 is subjected to a nitrogen plasma treatment and a water washing treatment. Then, the second semiconductor chip 22 is bonded to the first semiconductor chip 21. At this time, of the multiple dummy pads 56, the dummy pads 56a and the vias 53 that have been partially removed by the laser are exposed from the insulating layer 62. Thereafter, the CMOS wafer 311 is annealed.

[0090] 37, sealing resin 23 is provided above CMOS wafer 311. As a result, first semiconductor chip 21, second semiconductor chip 22, and groove portion 315 are sealed with sealing resin 23. As a result, in third region 33, interface 36 between sealing resin 23 and first semiconductor chip 21 becomes uneven.

[0091] [Third embodiment] A semiconductor device 13 according to the third embodiment will be described. Fig. 38 is a cross-sectional view of the semiconductor device according to the third embodiment. Fig. 38 can be viewed in the same way as Fig. 3.

[0092] 38, the semiconductor device 13 is different from the semiconductor device 10 according to the first embodiment in that the hole 22b penetrates the semiconductor layer 71 and the insulating layer 72, and a barrier metal 73a is provided below the bonding pad 73. The barrier metal 73a contains, for example, titanium or titanium and nitrogen.

[0093] The holes 22b in the semiconductor devices 11 and 12 shown in FIGS. 33 and 34, respectively, may be configured to penetrate the semiconductor layer 71 and the insulating layer 72, similar to the semiconductor device 13.

[0094] [Fourth embodiment] A semiconductor device according to the fourth embodiment will be described below. Fig. 39 is a cross-sectional view of a pad and a via according to the fourth embodiment.

[0095] As shown in FIG. 39, pad 51 includes a metal layer 51a (an example of a “first metal layer”) and a metal layer 51b (an example of a “second metal layer”) provided between metal layer 51a and insulating layer 62.

[0096] In this embodiment, the metal layer 51b is provided between the pad 51 and the via 53 and the insulating layer 62. Note that the via 53 may not be provided.

[0097] Although not shown, the dummy pad 56 and the dummy pad 56 a have the same configuration as the pad 51 .

[0098] By removing the dummy pad 56a and the via 53 below the dummy pad 56a by wet etching (see Figure 22), a metal layer 39d (an example of a "third metal layer") having the same composition and shape as the metal layer 51b is exposed on the concave surface 39, as shown in Figure 40.

[0099] Next, the sealing resin 23 is provided above the CMOS wafer 311. In detail, the sealing resin 23 enters the hole 39a having the metal layer 39d as an inner wall, thereby forming a protrusion 23a.

[0100] After removing the dummy pad 56a and the via 53 below, a wet etching process is performed to remove the barrier metal 52a, thereby forming a hole 39a (see FIG. 5) from which the metal layer 39d has been removed.

[0101] In the (a) embodiment, a configuration in which the interface 36 in the third region 33 is uneven has been described, but the present invention is not limited to this. The interface 36 in a part or all of the second region 32 may be uneven. Specifically, the interface 36 between the side 121c of the first semiconductor chip 21 and the second semiconductor chip 22, and between the side 121d of the first semiconductor chip 21 and the second semiconductor chip 22 may also be uneven. Moreover, the interface 36 between the side 121b of the first semiconductor chip 21 and the second semiconductor chip 22 may also be uneven.

[0102] (b) In the embodiment, the first semiconductor chip 21 and the second semiconductor chip 22 are bonded together by bonding the pads 51 and the dummy pads 56, and the pads 52 and the dummy pads 57, respectively, but the present invention is not limited to this. The first semiconductor chip 21 and the second semiconductor chip 22 may be bonded together by a resin such as a die attach film.

[0103] (c) In the embodiment, for example, as shown in Fig. 4, a configuration has been described in which the convex portion 23a of the sealing resin 23 completely enters the hole portion 39a, but the present invention is not limited to this. A void may be formed in a portion between the sealing resin 23 and the concave surface 39. Even in such a case, an interface 36 between the sealing resin 23 and the first semiconductor chip 21, which has a convex shape, is formed by a portion where the sealing resin 23 and the concave surface 39 are in close contact with each other, i.e., a portion where no void is formed. This ensures a degree of contact between the first semiconductor chip 21 and the sealing resin 23, and therefore prevents the sealing resin 23 from peeling off during dicing.

[0104] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Any design modifications made by a person skilled in the art to these specific examples are also included within the scope of the present disclosure as long as they have the features of the present disclosure. The elements of each of the above-mentioned specific examples and their arrangements, conditions, shapes, etc. are not limited to those exemplified and can be changed as appropriate. The combination of each of the elements of each of the above-mentioned specific examples can be changed as appropriate as long as no technical contradiction occurs. [Explanation of symbols]

[0105] 10, 11, 12, 13, 14...Semiconductor device 21…First semiconductor chip 21a…Surface 22…Second semiconductor chip 23…Sealing resin 23a…Convex part 31...First area 32…Second area 33…Third area 36...interface 37…Laminating surface 38…Plane 39…Concave 39a…hole part 39b…Bottom surface 39c…Aperture 39d…metal layer 40…Side 51...Pad 51a, 51b...metal layer 52…Pad 53, 54…Beer 56, 56a, 57…Dummy pads 61...Semiconductor layer 62...Insulating layer 71...Semiconductor layer 72...Insulating layer 72a…Memory array 73…Bonding pad 74, 75...insulating layer 81...Bonding wire 104X, 104Y, 105X, 105Y...Dicing lines 121a, 121b, 121c, 121d, 122a, 122b, 122c, 122d...sides 131, 132, 133...area 211...Array wafer 215…Groove 311…CMOS wafer 315…Groove

Claims

1. a first semiconductor chip having a first surface including a first region and a second region adjacent to the first region; a second semiconductor chip provided on the first region; a resin provided on the second region and in contact with the second semiconductor chip; At least a part of the interface between the first semiconductor chip and the resin is uneven. Semiconductor device.

2. the second semiconductor chip is attached to the first region; the second region includes a concave surface formed by being recessed from a plane including bonding surfaces of the first semiconductor chip and the second semiconductor chip, the resin has a protrusion that enters at least a part of a hole having the concave surface as an inner wall; The semiconductor device according to claim 1 .

3. A first pad is formed on the first surface, The second semiconductor chip has a second pad formed thereon; the first pads and the second pads are joined together to bond the first semiconductor chip and the second semiconductor chip together; a cross section of the first pad perpendicular to the first surface has a first shape; A cross-sectional shape of the protrusion perpendicular to the first surface is the first shape. The semiconductor device according to claim 2 .

4. the first semiconductor chip has a first side and a second side opposed to each other when the first surface is viewed in a plan view along a direction perpendicular to the first surface, the first region is located closer to the first side than to the second side, the second region includes a third region located between the first side and the first region, The interface in at least a part of the third region is uneven. The semiconductor device according to claim 1 .

5. the first semiconductor chip has a side surface connected to the second region at a side of the first surface; The resin is provided from the second region to the side surface. The semiconductor device according to claim 1 .

6. the second region includes a concave surface formed to be recessed from a plane including bonding surfaces of the first semiconductor chip and the second semiconductor chip, When the first surface is viewed in a plan view along a direction perpendicular to the first surface, the concave surface exhibits a geometric pattern. The semiconductor device according to claim 1 .

7. the second region is formed recessed from a plane including bonding surfaces of the first semiconductor chip and the second semiconductor chip, and includes a concave surface having a rectangular, circular, or elliptical outline when the first surface is viewed in a plan view along a direction perpendicular to the first surface; The semiconductor device according to claim 1 .

8. the second region includes a concave surface formed by being recessed from a plane including bonding surfaces of the first semiconductor chip and the second semiconductor chip, The hole portion having the concave surface as an inner wall has an opening area larger than an area of ​​a bottom surface. The semiconductor device according to claim 1 .

9. the second region includes a concave surface formed by being recessed from a plane including bonding surfaces of the first semiconductor chip and the second semiconductor chip, In the hole portion having the concave surface as an inner wall, the shape of the bottom surface and the shape of the opening are substantially the same. The semiconductor device according to claim 1 .

10. A first pad is formed on the first surface, The second semiconductor chip has a second pad formed thereon; the first pads and the second pads are joined together to bond the first semiconductor chip and the second semiconductor chip together; At the uneven interface, a part of the resin is in contact with a metal having the same composition as the first pad. The semiconductor device according to claim 1 .

11. an insulating layer and a first pad exposed from the insulating layer are formed in the first region; The second semiconductor chip has a second pad formed thereon; the first pads and the second pads are joined together to bond the first semiconductor chip and the second semiconductor chip together; the second region includes a concave surface formed by being recessed from a plane including bonding surfaces of the first semiconductor chip and the second semiconductor chip, the first pad includes a first metal layer and a second metal layer provided between the first metal layer and the insulating layer; a third metal layer having the same composition as the second metal layer is exposed on the concave surface; The semiconductor device according to claim 1 .

12. the first semiconductor chip comprises silicon; The semiconductor device according to claim 1 .

13. The second semiconductor chip is provided with a plurality of stacked memory chips. The semiconductor device according to claim 1 .

14. When the first surface is viewed in a plan view along a direction perpendicular to the first surface, at least a portion of an upper surface of the second semiconductor chip is exposed from the resin. The semiconductor device according to claim 1 .

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