Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing the heat generation of a transmission coil by flowing a current in constant to the transmission coil in a transformer.SOLUTION: A semiconductor device comprises a semiconductor substrate, a first coil, a second coil, a third coil; a fourth coil, a leading wire, and an insulation layer. The leading wire is formed at the same layer as the first and second coils on the semiconductor substrate. The first and second coils are adjacent to each other via the leading wire in a plan view, and are electrically connected in serial via the leading wire. The insulation layer covers the first coil, the second coil, and the leading wire. The third coil is formed on the first coil so as to be opposite to the first coil via the insulation layer. The fourth coil is formed on the second coil so as to be opposite to the second coil via the insulation layer. The third and fourth coils are adjacent to each other in the plan view, and are electrically connected to each other.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] WO 2014 / 097425 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a transformer configured with coils facing each other with an insulating layer interposed therebetween. Another semiconductor device having a transformer configured with coils facing each other with an insulating layer interposed therebetween is the semiconductor device described in JP 2011-082212 A (Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 097425 [Patent Document 2] JP 2011-082212 A Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Documents 1 and 2 only show examples of a transformer in which a receiving coil is on an upper layer of a transmitting coil. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate, a first coil, a second coil, a third coil, and a fourth coil, a lead wire, and an insulating layer. The lead wire is formed in the same layer as the first coil and the second coil on the semiconductor substrate. The first coil and the second coil are adjacent to each other through the lead wire in a plan view, and are electrically connected to each other in series through the lead wire. The insulating layer covers the first coil, the second coil, and the lead wire. The third coil is formed on the first coil so as to face the first coil through the insulating layer. The fourth coil is formed on the second coil so as to face the second coil through the insulating layer. The third coil and the fourth coil are adjacent to each other in a plan view, and are electrically connected to each other. Effect of the Invention

[0006] According to the semiconductor device of the present disclosure, it is possible to suppress heat generation in the transmitter coil caused by a constant current flowing through the transmitter coil in a transformer in which the transmitter coil is placed above the receiver coil. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram of a semiconductor device DEV1. [Diagram 2] 4 is an explanatory diagram showing an example of signal transmission from a control circuit CC to a drive circuit DR. FIG. [Diagram 3] FIG. 2 is a first plan view of the semiconductor chip CHP3. [Figure 4] FIG. 2 is a second plan view of the semiconductor chip CHP3. [Diagram 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] 1 is a manufacturing process diagram of the semiconductor chip CHP3. [Figure 7] FIG. 11 is a cross-sectional view illustrating a first insulating film forming step S2. [Figure 8] FIG. 11 is a cross-sectional view illustrating a wiring forming step S3. [Figure 9] FIG. 11 is a cross-sectional view illustrating a second insulating film forming step S4. [Figure 10] FIG. 11 is a cross-sectional view illustrating a via plug forming step S5. [Figure 11] FIG. 11 is a cross-sectional view illustrating a first coil forming step S6. [Figure 12] FIG. 11 is a cross-sectional view illustrating an insulating layer forming step S7. [Figure 13] FIG. 11 is a cross-sectional view illustrating a second coil forming step S8. [Figure 14] FIG. 2 is a plan view of a semiconductor chip CHP3 in the semiconductor device DEV2. [Figure 15] FIG. 2 is a plan view of a semiconductor chip CHP3 in the semiconductor device DEV3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated.

[0009] (First embodiment) A description will be given of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is referred to as a semiconductor device DEV1.

[0010] (Configuration of semiconductor device DEV1) The configuration of the semiconductor device DEV1 will be described below.

[0011] <Schematic configuration of semiconductor device DEV1> The schematic configuration of the semiconductor device DEV1 will be described below.

[0012] Fig. 1 is a block diagram of the semiconductor device DEV1. As shown in Fig. 1, the semiconductor device DEV1 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3.

[0013] The semiconductor chip CHP1 has a control circuit CC, a transmission circuit TX1, and a reception circuit RX2, and the semiconductor chip CHP2 has a drive circuit DR, a reception circuit RX1, and a transmission circuit TX2. The control circuit CC is electrically connected to the transmission circuit TX1 and the reception circuit RX2. The drive circuit DR is electrically connected to the reception circuit RX1 and the transmission circuit TX2.

[0014] The semiconductor chip CHP3 has a transformer TR1, a transformer TR2, and leads PL1 and PL2.

[0015] The transformer TR1 has a transmitting coil CL1 and a receiving coil CL2. The transmitting coil CL1 has a coil CL11 and a coil CL12, and the receiving coil CL2 has a coil CL21 and a coil CL22. The transmitting coil CL1 and the receiving coil CL2 are electrically connected to a transmitting circuit TX1 and a receiving circuit RX1, respectively.

[0016] More specifically, one end of the coil CL11 is electrically connected to the transmission circuit TX1, the other end of the coil CL11 is electrically connected to one end of the coil CL12, and the other end of the coil CL12 is electrically connected to the transmission circuit TX1. Also, one end of the coil CL21 is electrically connected to the reception circuit RX1, the other end of the coil CL21 is electrically connected to one end of the coil CL22 via the lead line PL1, and the other end of the coil CL22 is electrically connected to the reception circuit RX1. The lead line PL1 is connected to a reference potential. The reference potential is, for example, a ground potential.

[0017] The transformer TR2 has a transmitting coil CL3 and a receiving coil CL4. The transmitting coil CL3 has a coil CL31 and a coil CL32, and the receiving coil CL4 has a coil CL41 and a coil CL42. The transmitting coil CL3 and the receiving coil CL4 are electrically connected to the transmitting circuit TX2 and the receiving circuit RX2, respectively.

[0018] More specifically, one end of the coil CL31 is electrically connected to the transmission circuit TX2, the other end of the coil CL31 is electrically connected to one end of the coil CL32, and the other end of the coil CL32 is electrically connected to the transmission circuit TX2. Also, one end of the coil CL41 is electrically connected to the reception circuit RX2, the other end of the coil CL41 is electrically connected to one end of the coil CL42 via the lead line PL2, and the other end of the coil CL42 is electrically connected to the reception circuit RX2. The lead line PL2 is connected to a reference potential.

[0019] In the semiconductor device DEV1, a signal is transmitted from the control circuit CC to the driving circuit DR by the transmitting circuit TX1, the transformer TR1, and the receiving circuit RX1. Also, in the semiconductor device DEV1, a signal is transmitted from the driving circuit DR to the control circuit CC by the transmitting circuit TX2, the transformer TR2, and the receiving circuit RX2.

[0020] FIG. 2 is an explanatory diagram showing an example of signal transmission from the control circuit CC to the drive circuit DR. As shown in FIG. 2, the control circuit CC inputs a signal SG1 to the transmission circuit TX1. The signal SG1 is a square wave. The transmission circuit TX1 modulates the signal SG1 to a signal SG2 and sends the signal SG2 to the transmission coil CL1. When the signal SG2 flows to the transmission coil CL1, a signal SG3 corresponding to the signal SG2 flows to the reception coil CL2 due to induced electromotive force. The reception circuit RX1 amplifies the signal SG3 and demodulates it to a signal SG4 (square wave), and outputs it to the drive circuit DR. In this way, a signal is transmitted from the control circuit CC to the drive circuit DR. Note that the signal is also transmitted from the drive circuit DR to the control circuit CC in the same manner. In this way, in the semiconductor device DEV1, the signal transmission between the transmission circuit TX1 and the reception circuit RX1 and the signal transmission between the transmission circuit TX2 and the reception circuit RX2 are performed by a pulse communication method.

[0021] <Detailed configuration of the CHP3 semiconductor chip> The detailed configuration of the semiconductor chip CHP3 will be described below.

[0022] Fig. 3 is a first plan view of the semiconductor chip CHP3. Fig. 4 is a second plan view of the semiconductor chip CHP3. Fig. 5 is a cross-sectional view taken along line VV in Fig. 4. As shown in Figs. 3, 4, and 5, the semiconductor chip CHP3 includes a semiconductor substrate SUB, an insulating film IF1, wiring WL1, wiring WL2, wiring WL3, and wiring WL4, an insulating film IF2, via plugs VP1, VP2, VP3, and VP4, via plugs VP5, VP6, VP7, and VP8, a transmitting coil CL1, a receiving coil CL4, wiring WL5, wiring WL6, wiring WL7, and wiring WL8, a lead line PL2, an insulating layer IL, a receiving coil CL2, a lead line PL1, a transmitting coil CL3, pads PD1, PD2, PD3, pads PD4, and PD5, a guard ring GR, and a passivation film PF.

[0023] The semiconductor substrate SUB is made of, for example, single crystal silicon. The insulating film IF1 is disposed on the semiconductor substrate SUB. The insulating film IF1 is made of, for example, silicon oxide. The wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4 are disposed on the insulating film IF1. The wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4 are made of, for example, aluminum or an aluminum alloy. The insulating film IF2 is disposed on the insulating film IF1 so as to cover the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4.

[0024] Via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7, and VP8 are embedded in the insulating film IF2. The material of the via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7, and VP8 is, for example, tungsten.

[0025] The transmitting coil CL1 (coil CL11, coil CL12), the receiving coil CL4 (coil CL41, coil CL42), and the lead-out wire PL2 are disposed on the insulating film IF2. From another perspective, the coil CL11, coil CL12, coil CL41, coil CL42, and the lead-out wire PL2 are formed in the same layer on the semiconductor substrate SUB. The constituent material of the coil CL11, coil CL12, coil CL41, coil CL42, and the lead-out wire PL2 is, for example, aluminum or an aluminum alloy.

[0026] The coils CL11 and CL12 are spirally wound in plan view. The coils CL11 and CL12 are adjacent to each other in plan view. The coils CL11 and CL12 are electrically connected to each other in series. More specifically, the outermost end of the coil CL11 and the outermost end of the coil CL12 are electrically connected to each other. No other lead wires in the same layer as the coils CL11, CL12, CL41, CL42, and lead wire PL2 are formed between the coils CL11 and CL12. From another perspective, the coils CL11 and CL12 are directly adjacent to each other in plan view.

[0027] The innermost end of the coil CL11 is electrically connected to the wiring WL1 by a via plug VP1. The innermost end of the coil CL12 is electrically connected to the wiring WL2 by a via plug VP2. The innermost end of the coil CL41 is electrically connected to the wiring WL3 by a via plug VP3. The outermost end of the coil CL42 is electrically connected to the wiring WL4 by a via plug VP4. The lead wire PL2 is electrically connected to a pad (not shown) disposed on the insulating layer IL.

[0028] The wiring WL5, wiring WL6, wiring WL7, and wiring WL8 are disposed on the insulating film IF2. The wiring WL5, wiring WL6, wiring WL7, and wiring WL8 are made of, for example, aluminum or an aluminum alloy. The wiring WL5 is electrically connected to the wiring WL1 by a via plug VP5, and the wiring WL6 is electrically connected to the wiring WL2 by a via plug VP6. The wiring WL7 is electrically connected to the wiring WL3 by a via plug VP7, and the wiring WL8 is electrically connected to the wiring WL4 by a via plug VP8. The wiring WL5, wiring WL6, wiring WL7, and wiring WL8 are each electrically connected to a pad (not shown) disposed on the insulating layer IL.

[0029] The coil CL11 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view. The coil CL12 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. That is, the winding direction of the coil CL11 may be opposite to the winding direction of the coil CL12. From another perspective, the coils CL11 and CL12 are configured in a serial aiding configuration.

[0030] The coil CL41 and the coil CL42 are spirally wound in a plan view. The coil CL41 and the coil CL42 are adjacent to each other in a plan view. The coil CL41 and the coil CL42 are electrically connected to each other in series. More specifically, the outermost end of the coil CL41 and the outermost end of the coil CL42 are electrically connected to each other. A lead line PL2 is formed between the coil CL41 and the coil CL42. From another perspective, the coil CL41 and the coil CL42 are adjacent to each other via the lead line PL2 in a plan view and are electrically connected in series via the lead line PL2.

[0031] The coil CL41 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view. The coil CL42 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. That is, the winding direction of the coil CL41 may be opposite to the winding direction of the coil CL42. From another perspective, the coil CL41 and the coil CL42 are configured in series to cooperate with each other.

[0032] The insulating layer IL is disposed on the insulating film IF2 so as to cover the coils CL11, CL12, CL41, CL42, the lead wire PL2, the wiring WL5, WL6, WL7, and WL8. Although not shown, the insulating layer IL may be formed by stacking a plurality of insulating films. The constituent material of each insulating film constituting the insulating layer IL is, for example, silicon oxide.

[0033] The receiving coil CL2 (coil CL21, coil CL22), the transmitting coil CL3 (coil CL31, coil CL32), and the lead wire PL1 are disposed on the insulating layer IL. The constituent material of the coil CL21, coil CL22, coil CL31, coil CL32, and the lead wire PL1 is, for example, aluminum or an aluminum alloy.

[0034] The coils CL21 and CL22 face the coils CL11 and CL12, respectively, with the insulating layer IL interposed therebetween. From another perspective, the coils CL21 and CL22 overlap the coils CL11 and CL12 in a plan view. From yet another perspective, the coils CL21 and CL22 are magnetically coupled to the coils CL11 and CL12, respectively. Since the coils CL21 and CL22 are on the insulating layer IL as described above, the coils CL21 and CL22 are disposed on the coils CL11 and CL12, respectively, with the insulating layer IL interposed therebetween.

[0035] The coils CL21 and CL22 are spirally wound in a plan view. The coils CL21 and CL22 are adjacent to each other in a plan view. The coils CL21 and CL22 are electrically connected in series to each other. More specifically, the outermost end of the coil CL21 and the outermost end of the coil CL22 are electrically connected to each other. A lead wire PL1 is formed between the coils CL21 and CL22. From another perspective, the coils CL21 and CL22 are adjacent to each other via the lead wire PL1 in a plan view and are electrically connected in series to each other via the lead wire PL1.

[0036] The coil CL21 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view. The coil CL22 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. That is, the winding direction of the coil CL21 may be opposite to the winding direction of the coil CL22. From another point of view, the coil CL21 and the coil CL22 are configured in series to cooperate with each other.

[0037] The coils CL31 and CL32 face the coils CL41 and CL42, respectively, with the insulating layer IL interposed therebetween. From another perspective, the coils CL31 and CL32 overlap the coils CL41 and CL42 in a plan view. From yet another perspective, the coils CL31 and CL32 are magnetically coupled to the coils CL41 and CL42, respectively. As described above, the coils CL31 and CL32 are on the insulating layer IL, and therefore the coils CL31 and CL32 are disposed on the coils CL41 and CL42, respectively, with the insulating layer IL interposed therebetween.

[0038] The coils CL31 and CL32 are spirally wound in plan view. The coils CL31 and CL32 are adjacent to each other in plan view. The coils CL31 and CL32 are electrically connected to each other in series. More specifically, the outermost end of the coil CL31 and the outermost end of the coil CL32 are electrically connected to each other. No other lead wires in the same layer as the coils CL21, CL22, CL31, CL32, and lead wire PL1 are formed between the coils CL31 and CL32. From another perspective, the coils CL31 and CL32 are directly adjacent to each other in plan view.

[0039] The coil CL31 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view. The coil CL32 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. That is, the winding direction of the coil CL31 may be opposite to the winding direction of the coil CL32. From another perspective, the coil CL31 and the coil CL32 are configured in series to cooperate with each other.

[0040] The distance between coil CL11 and coil CL21 or between coil CL12 and coil CL22 is, for example, 6 μm or more and 10 μm or less. The distance between coil CL11 and coil CL21 or between coil CL12 and coil CL22 may be 10 μm or more and 14 μm or less. The distance between coil CL41 and coil CL31 or between coil CL42 and coil CL32 is, for example, 6 μm or more and 10 μm or less. The distance between coil CL41 and coil CL31 or between coil CL42 and coil CL32 may be 10 μm or more and 14 μm or less.

[0041] The pads PD1, PD2, PD3, PD4, and PD5 are disposed on the insulating layer IL. The pads PD1, PD2, PD3, PD4, and PD5 are made of, for example, aluminum or an aluminum alloy. The pad PD1 is connected to the innermost end of the coil CL21. The pad PD2 is connected to the innermost end of the coil CL22. The pad PD3 is connected to the innermost end of the coil CL31. The pad PD4 is connected to the innermost end of the coil CL32. The pad PD5 is connected to the end of the lead wire PL1 on the opposite side to the coils CL21 and CL22.

[0042] The guard ring GR is disposed on the insulating layer IL. The guard ring GR has a first portion GR1 and a second portion GR2. The first portion GR1 surrounds the receiving coil CL2 in a planar view. The second portion GR2 surrounds the transmitting coil CL3 in a planar view. The pad PD5 is in contact with the guard ring GR (first portion GR1). Therefore, the guard ring GR is connected to the reference potential in the same manner as the lead-out line PL1. The constituent material of the guard ring GR is, for example, aluminum or an aluminum alloy.

[0043] The passivation film PF is disposed on the insulating layer IL so as to cover the receiving coil CL2 (coil CL21, coil CL22), the transmitting coil CL3 (coil CL31, coil CL32), the lead wire PL1, the pads PD1, PD2, PD3, PD4, PD5, and the guard ring GR. The pads PD1, PD2, PD3, PD4, and PD5 are exposed from the openings in the passivation film PF. The constituent material of the passivation film PF is, for example, silicon nitride.

[0044] <Manufacturing method of semiconductor chip CHP3> A method for manufacturing the semiconductor chip CHP3 will be described below.

[0045] Fig. 6 is a manufacturing process diagram of the semiconductor chip CHP3. As shown in Fig. 6, the manufacturing method of the semiconductor chip CHP3 includes a preparation step S1, a first insulating film forming step S2, a wiring forming step S3, a second insulating film forming step S4, a via plug forming step S5, a first coil forming step S6, an insulating layer forming step S7, a second coil forming step S8, and a passivation film forming step S9.

[0046] In the preparation step S1, a semiconductor substrate SUB is prepared. After the preparation step S1, a first insulating film forming step S2 is performed. FIG. 7 is a cross-sectional view for explaining the first insulating film forming step S2. As shown in FIG. 7, in the first insulating film forming step S2, an insulating film IF1 is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. After the first insulating film forming step S2, a wiring forming step S3 is performed.

[0047] 8 is a cross-sectional view for explaining the wiring formation step S3. As shown in FIG. 8, in the wiring formation step S3, wiring WL1, wiring WL2, wiring WL3, and wiring WL4 are formed on the insulating film IF1. In the wiring formation step S3, first, the constituent materials of the wiring WL1, wiring WL2, wiring WL3, and wiring WL4 are formed by, for example, a sputtering method. Second, the formed constituent materials of the wiring WL1, wiring WL2, wiring WL3, and wiring WL4 are patterned by, for example, dry etching using a resist pattern formed by a photolithography method as a mask. After the wiring formation step S3, a second insulating film formation step S4 is performed.

[0048] 9 is a cross-sectional view for explaining the second insulating film forming step S4. In the second insulating film forming step S4, as shown in FIG. 9, the insulating film IF2 is formed on the insulating film IF1 so as to cover the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4. In the second insulating film forming step S4, first, the constituent material of the insulating film IF2 is formed by, for example, a CVD method. Second, the constituent material of the formed insulating film IF2 is planarized by, for example, a CMP (Chemical Mechanical Polishing) method. After the second insulating film forming step S4, a via plug forming step S5 is performed.

[0049] 10 is a cross-sectional view for explaining the via plug forming step S5. As shown in FIG. 10, in the via plug forming step S5, via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7, and VP8 are embedded in the insulating film IF2. In the via plug forming step S5, first, via holes are formed in the insulating film IF2 by dry etching using a resist pattern formed by photolithography as a mask. Second, the constituent materials of the via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7, and VP8 are embedded in the via holes by, for example, CVD.

[0050] Thirdly, the constituent materials of the via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7 and VP8 protruding from the via holes are removed by, for example, a CMP method. After the via plug forming step S5, a first coil forming step S6 is performed.

[0051] FIG. 11 is a cross-sectional view for explaining the first coil forming step S6. As shown in FIG. 11, in the first coil forming step S6, the transmitting coil CL1, the receiving coil CL4, the drawing line PL2, the wiring WL5, the wiring WL6, the wiring WL7, and the wiring WL8 are formed on the insulating film IF2. In the first coil forming step S6, first, the constituent materials of the transmitting coil CL1, the receiving coil CL4, the drawing line PL2, the wiring WL5, the wiring WL6, the wiring WL7, and the wiring WL8 are formed into a film by, for example, sputtering. Second, the constituent materials of the formed transmitting coil CL1, the receiving coil CL4, the drawing line PL2, the wiring WL5, the wiring WL6, the wiring WL7, and the wiring WL8 are patterned by, for example, dry etching using a resist pattern formed by photolithography as a mask. After the first coil forming step S6, the insulating layer forming step S7 is performed.

[0052] Fig. 12 is a cross-sectional view illustrating the insulating layer forming step S7. In the insulating layer forming step S7, as shown in Fig. 12, an insulating layer IL is formed on the insulating film IF2 so as to cover the transmitting coil CL1, the receiving coil CL4, the lead wire PL2, the wiring WL5, the wiring WL6, the wiring WL7, and the wiring WL8. The insulating layer IL is formed by repeating the same steps as the second insulating film forming step S4. After the insulating layer forming step S7, a second coil forming step S8 is performed.

[0053] FIG. 13 is a cross-sectional view for explaining the second coil forming step S8. As shown in FIG. 11, in the second coil forming step S8, the receiving coil CL2, the transmitting coil CL3, the drawing line PL1, the pads PD1 to PD5, and the guard ring GR are formed on the insulating layer IL. In the second coil forming step S8, first, the constituent materials of the receiving coil CL2, the transmitting coil CL3, the drawing line PL1, the pads PD1 to PD5, and the guard ring GR are formed as films by, for example, sputtering. Second, the constituent materials of the formed receiving coil CL2, the transmitting coil CL3, the drawing line PL1, the pads PD1 to PD5, and the guard ring GR are patterned by, for example, dry etching using a resist pattern formed by photolithography as a mask. After the second coil forming step S8, a passivation film forming step S9 is performed.

[0054] In the passivation film forming process S9, a passivation film PF is formed on the insulating layer IL so as to cover the receiving coil CL2, the transmitting coil CL3, the lead wire PL1, the pads PD1 to PD5, and the guard ring GR. In the passivation film forming process S9, first, the constituent material of the passivation film PF is deposited by, for example, a CVD method. Second, the constituent material of the passivation film PF is patterned by, for example, dry etching using a resist pattern formed by a photolithography method as a mask. In this way, the structure of the semiconductor chip CHP3 shown in Figures 3 to 5 is formed.

[0055] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below.

[0056] In the semiconductor device DEV1, the transformers TR1 and TR2 are integrated into a semiconductor chip CHP3. Since semiconductor elements such as transistors are not formed on the semiconductor chip CHP3, it is possible to optimize the manufacturing process of the semiconductor chip CHP3 in accordance with the transformers TR1 and TR2.

[0057] In the semiconductor device DEV1, no lead is formed between the coil CL11 and the coil CL12. In addition, in the semiconductor device DEV1, no lead is formed between the coil CL31 and the coil CL32. Therefore, no current flows through the coils CL11, CL12, CL31, and CL32 at all times (current flows only during transmission). Therefore, the semiconductor device DEV1 can suppress heat generation in the semiconductor chip CHP3. Furthermore, as a result of suppressing heat generation in the semiconductor chip CHP3, it is also possible to suppress electromigration from occurring in the coils CL11, CL12, CL31, and CL32.

[0058] In the semiconductor device DEV1, a lead line PL1 is formed between the coils CL21 and CL22, and a lead line PL2 is formed between the coils CL41 and CL42. The lead lines PL1 and PL2 are connected to a reference potential. Therefore, in the semiconductor device DEV1, it is possible to stabilize the potential at the connection between the coils CL21 and CL22 and the connection between the coils CL41 and CL42. In the semiconductor device DEV1, it is possible to suppress common mode noise by configuring the coils CL11 and CL12 (coils CL31 and CL32) in a series complementary configuration.

[0059] Second embodiment A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment will be referred to as a semiconductor device DEV2. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0060] <Configuration of semiconductor device DEV2> The configuration of the semiconductor device DEV2 will be described below.

[0061] The semiconductor device DEV2 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV1.

[0062] Fig. 14 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV2. As shown in Fig. 14, in the semiconductor device DEV2, the semiconductor chip CHP3 does not have a lead line PL1. Instead, in the semiconductor device DEV2, the coil CL21 and the coil CL22 are adjacent to each other via the pad PD5 in a plan view and are electrically connected in series to each other via the pad PD5.

[0063] In addition, in the semiconductor device DEV2, the semiconductor chip CHP3 further includes a pad PD6. The pad PD6 is disposed on the insulating layer IL. The material of the pad PD6 is, for example, aluminum or an aluminum alloy. In the semiconductor device DEV2, the coils CL31 and CL32 are adjacent to each other via the pad PD6 in a plan view, and are electrically connected in series via the pad PD6. However, since the pad PD6 is not connected to the reference potential, the pad PD6 is not exposed from the passivation film PF.

[0064] In the semiconductor device DEV2, the pad PD2 is formed between the coils CL21 and CL22, so that the pad PD5 is spaced apart from the guard ring GR (first portion GR1). In the semiconductor device DEV2, the guard ring GR further has a connection portion GR3 that connects the first portion GR1 and the second portion GR2. Although not shown, in the semiconductor device DEV2, the connection portion GR3 is exposed from the passivation film PF, so that a reference potential is supplied to the guard ring GR. In these respects, the configuration of the semiconductor device DEV2 differs from the configuration of the semiconductor device DEV1.

[0065] <Effects of semiconductor device DEV2> The effects of the semiconductor device DEV2 will be described below.

[0066] In the semiconductor device DEV1, the pad PD5 and the guard ring GR (first portion GR1) are in contact with each other, and the contact portion becomes a singular point that causes a decrease in breakdown voltage due to electric field concentration. However, in the semiconductor device DEV2, the pad PD5 is separated from the guard ring GR (first portion GR1), so that such a singular point does not occur and it is possible to ensure the breakdown voltage of the semiconductor chip CHP3.

[0067] Third embodiment A semiconductor device according to a third embodiment will be described. The semiconductor device according to the second embodiment will be referred to as a semiconductor device DEV3. Here, differences from the semiconductor device DEV2 will be mainly described, and overlapping descriptions will not be repeated.

[0068] <Configuration of semiconductor device DEV3> The configuration of the semiconductor device DEV3 will be described below.

[0069] The semiconductor device DEV3 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV3 is common to the configuration of the semiconductor device DEV2.

[0070] Fig. 15 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV3. As shown in Fig. 15, in the semiconductor device DEV3, the semiconductor chip CHP3 does not have a pad PD6. From another perspective, in the semiconductor device DEV3, the shape of the receiving coil CL2 is different from the shape of the transmitting coil CL3 in a plan view. In this respect, the configuration of the semiconductor device DEV3 is different from the configuration of the semiconductor device DEV2.

[0071] <Effects of semiconductor device DEV3> The effects of the semiconductor device DEV3 will be described below.

[0072] In the semiconductor device DEV3, since the pad PD6 is not formed, the width of the transmitter coil CL3 is smaller than that of the semiconductor device DEV2. Therefore, according to the semiconductor device DEV3, it is possible to reduce the layout of the transmitter coil CL3.

[0073] (Additional Note) The above embodiment includes the following configurations.

[0074] <Appendix 1> A first semiconductor chip; A second semiconductor chip; a third semiconductor chip; the first semiconductor chip has a first receiving circuit; the second semiconductor chip has a first transmission circuit; the third semiconductor chip has a semiconductor substrate, a first receiving coil connected to the first receiving circuit, a first transmitting coil connected to the first transmitting circuit, a first lead, and an insulating layer; The first receiving coil includes a first coil and a second coil, the first transmitting coil includes a third coil and a fourth coil; the first lead wire is formed in the same layer as the first coil and the second coil on the semiconductor substrate, the first coil and the second coil are adjacent to each other via the first lead wire in a plan view and are electrically connected in series to each other via the first lead wire; the insulating layer covers the first coil, the second coil, and the first lead wire; the third coil is formed on the first coil so as to face the first coil via the insulating layer, the fourth coil is formed on the second coil so as to face the second coil via the insulating layer, the third coil and the fourth coil are adjacent to each other in a plan view and are electrically connected to each other, The first transmitting circuit transmits a signal to the first receiving circuit via the first transmitting coil and the second receiving coil.

[0075] <Appendix 2> 2. The semiconductor device according to claim 1, wherein, in a cross-sectional view, the distance between the first coil and the third coil or the distance between the second coil and the fourth coil is 6 μm or more and 10 μm or less.

[0076] <Appendix 3> 2. The semiconductor device according to claim 1, wherein, in a cross-sectional view, the distance between the first coil and the third coil or the distance between the second coil and the fourth coil is 10 μm or more and 14 μm or less.

[0077] <Appendix 4> the first coil and the third coil overlap each other in a plan view, 2. The semiconductor device according to claim 1, wherein the second coil and the fourth coil overlap each other in a planar view.

[0078] <Appendix 5> the first coil and the third coil are magnetically coupled to each other; 2. The semiconductor device according to claim 1, wherein the second coil and the fourth coil are magnetically coupled to each other.

[0079] <Appendix 6> 2. The semiconductor device according to claim 1, wherein the first lead line is connected to a reference potential.

[0080] <Appendix 7> In a plan view, between the third coil and the fourth coil, no other lead wire is formed in the same layer as the third coil and the fourth coil, 2. The semiconductor device according to claim 1, wherein the third coil and the fourth coil are directly adjacent to each other in a planar view.

[0081] <Appendix 8> the first semiconductor chip further includes a second transmission circuit; the second semiconductor chip further includes a second receiving circuit; the third semiconductor chip further includes a second transmitting coil connected to the second transmitting circuit, a second receiving coil connected to the second receiving circuit, and a second lead line; the second transmitting coil includes a fifth coil and a sixth coil, the second receiving coil includes a seventh coil and an eighth coil; the insulating layer further covers the fifth coil and the sixth coil, the seventh coil is formed on the fifth coil so as to face the fifth coil via the insulating layer, the eighth coil is formed on the sixth coil so as to face the sixth coil via the insulating layer, the seventh coil and the eighth coil are adjacent to each other via the second lead wire in a plan view and are electrically connected in series to each other via the second lead wire, 2. The semiconductor device according to claim 1, wherein the second transmission circuit transmits a signal to the second reception circuit via the second transmission coil and the second reception coil.

[0082] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0083] DEV1, DEV2, DEV3 semiconductor device, CHP1, CHP2, CHP3 semiconductor chip, CL1 transmitting coil, CL11, CL12 coil, CL2 receiving coil, CL21, CL22 coil, CL3 transmitting coil, CL31, CL32 coil, CL4 receiving coil, CL41, CL42 coil, DR driving circuit, GR guard ring, GR1 first part, GR2 second part, GR3 connection part, IF1, IF2 insulating film, IL insulating layer, PD1, PD2, PD3, PD4, PD5, PD6 pad, PF passivation film, PL1, PL2 lead wire, RX1, RX2 receiving circuit, S1 preparation step, S2 first insulating film forming step, S3 wiring forming step, S4 second insulating film forming step, S5 via plug forming step, S6 first coil forming step, S7 insulating layer forming step, S8 second coil forming step, S9 Passivation film formation process, SG1,SG2,SG3,SG4 signals, SUB semiconductor substrate, TR1,TR2 transformers, TX1,TX2 transmitting circuits, VP1,VP2,VP3,VP4,VP5,VP6,VP7,VP8 via plugs, WL1,WL2,WL3,WL4,WL5,WL6,WL7,WL8 wiring.

Claims

1. A semiconductor substrate; A first coil, a second coil, a third coil and a fourth coil; With pull-out line, an insulating layer; the lead wire is formed in the same layer as the first coil and the second coil on the semiconductor substrate, the first coil and the second coil are adjacent to each other via the lead wire in a plan view and are electrically connected in series to each other via the lead wire, the insulating layer covers the first coil, the second coil, and the lead wire; the third coil is formed on the first coil so as to face the first coil via the insulating layer, the fourth coil is formed on the second coil so as to face the second coil via the insulating layer, The semiconductor device, wherein the third coil and the fourth coil are adjacent to each other in a plan view and are electrically connected to each other.

2. 2 . The semiconductor device according to claim 1 , wherein in a cross-sectional view, a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is not less than 6 μm and not more than 10 μm.

3. 2 . The semiconductor device according to claim 1 , wherein in a cross-sectional view, a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is not less than 10 μm and not more than 14 μm.

4. the first coil and the third coil overlap each other in a plan view, The semiconductor device according to claim 1 , wherein the second coil and the fourth coil overlap each other in a plan view.

5. the first coil and the third coil are magnetically coupled to each other; The semiconductor device according to claim 1 , wherein the second coil and the fourth coil are magnetically coupled to each other.

6. The semiconductor device according to claim 1 , wherein said lead line is connected to a reference potential.

7. In a plan view, between the third coil and the fourth coil, no other lead wire is formed in the same layer as the third coil and the fourth coil, The semiconductor device according to claim 1 , wherein the third coil and the fourth coil are directly adjacent to each other in a plan view.

8. A semiconductor substrate; a first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil, and an eighth coil; A first lead line and a second lead line, an insulating layer; the first lead wire is formed in the same layer as the first coil, the second coil, the third coil, and the fourth coil on the semiconductor substrate; the first coil and the second coil are adjacent to each other via the first lead wire in a plan view and are electrically connected in series to each other via the first lead wire, the third coil and the fourth coil are adjacent to each other in a plan view and are electrically connected in series to each other, the insulating layer covers the first coil, the second coil, the third coil, the fourth coil, and the first lead wire, the fifth coil is formed on the first coil so as to face the first coil via the insulating layer, the sixth coil is formed on the second coil so as to face the second coil via the insulating layer, the seventh coil is formed on the third coil so as to face the third coil with the insulating layer interposed therebetween; the eighth coil is formed on the fourth coil so as to face the fourth coil via the insulating layer, the fifth coil and the sixth coil are adjacent to each other in a plan view and are electrically connected to each other, A semiconductor device, wherein the seventh coil and the eighth coil are adjacent to each other via the second lead-out line in a plan view and are electrically connected in series to each other via the second lead-out line.

9. In a plan view, no other lead wires are formed between the third coil and the fourth coil in the same layer as the first coil, the second coil, the third coil, and the fourth coil, the third coil and the fourth coil are directly adjacent to each other in a plan view, In a plan view, between the fifth coil and the sixth coil, no other lead wires are formed in the same layer as the fifth coil, the sixth coil, the seventh coil, and the eighth coil; The semiconductor device according to claim 8 , wherein the fifth coil and the sixth coil are directly adjacent to each other in a plan view.

10. A semiconductor substrate; a first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil, and an eighth coil; With pull-out line, a first pad, a second pad, a third pad, a fourth pad, and a fifth pad; an insulating layer; the lead wire is formed in the same layer as the first coil, the second coil, the third coil, and the fourth coil on the semiconductor substrate; the first coil and the second coil are adjacent to each other via the lead wire in a plan view and are electrically connected in series to each other via the lead wire, the third coil and the fourth coil are adjacent to each other in a plan view and are electrically connected in series to each other, the insulating layer covers the first coil, the second coil, the third coil, the fourth coil, and the lead wire, the fifth coil is formed on the first coil so as to face the first coil via the insulating layer, the sixth coil is formed on the second coil so as to face the second coil via the insulating layer, the seventh coil is formed on the third coil so as to face the third coil with the insulating layer interposed therebetween; the eighth coil is formed on the fourth coil so as to face the fourth coil via the insulating layer, the first pad, the second pad, the third pad, and the fourth pad are electrically connected to an innermost periphery of the fifth coil, an innermost periphery of the sixth coil, an innermost periphery of the seventh coil, and an innermost periphery of the eighth coil, respectively; the fifth coil and the sixth coil are adjacent to each other in a plan view and are electrically connected to each other, A semiconductor device, wherein the seventh coil and the eighth coil are adjacent to each other via the fifth pad in a plan view and are electrically connected in series to each other via the fifth pad.

11. A sixth pad; and a passivation film. the fifth coil and the sixth coil are adjacent to each other via the sixth pad in a plan view and are electrically connected in series to each other via the sixth pad, the passivation film covers the fifth coil, the sixth coil, the seventh coil, the eighth coil, the first pad, the second pad, the third pad, the fourth pad, the fifth pad, and the sixth pad, 11. The semiconductor device according to claim 10, wherein the passivation film has an opening for exposing the fifth pad and no opening for exposing the sixth pad.

12. 11. The semiconductor device of claim 10, wherein in a cross-sectional view, the distance between the first coil and the fifth coil, the distance between the second coil and the sixth coil, the distance between the third coil and the seventh coil, or the distance between the fourth coil and the eighth coil is 6 μm or more and 10 μm or less.

13. 11. The semiconductor device of claim 10, wherein in a cross-sectional view, the distance between the first coil and the fifth coil, the distance between the second coil and the sixth coil, the distance between the third coil and the seventh coil, or the distance between the fourth coil and the eighth coil is 10 μm or more and 14 μm or less.

14. the first coil and the fifth coil overlap each other in a plan view, the second coil and the sixth coil overlap each other in a plan view, the third coil and the seventh coil overlap each other in a plan view, The semiconductor device according to claim 10 , wherein the fourth coil and the eighth coil overlap each other in a plan view.

15. the first coil and the fifth coil are magnetically coupled to each other; the second coil and the sixth coil are magnetically coupled to each other, the third coil and the seventh coil are magnetically coupled to each other, The semiconductor device according to claim 10 , wherein the fourth coil and the eighth coil are magnetically coupled to each other.

16. The semiconductor device according to claim 10 , wherein the lead line and the fifth pad are connected to a reference potential.

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