Semiconductor device

Abstract

To provide a semiconductor device that can be miniaturized in a configuration in which a plurality of external terminals is arranged in parallel and facing each other.SOLUTION: A semiconductor device comprises: an insulating circuit board 1; semiconductor chips 4a, 4b, 4e, 4f on a top side of the insulating circuit board 1; a sealing resin 7 sealing semiconductor chips 4a, 4b, 4e, 4f; a first external terminal 24 electrically connected to semiconductor chips 4a, 4b, 4e, 4f and exposed from a first side surface of the sealing resin 7; a second external terminal 22 electrically connected to semiconductor chips 4a, 4b, 4e, 4f and having a portion above the first external terminal 24 and parallel and opposite to the first external terminal 24 and exposed from a top surface of the sealing resin 7; and a first insulating member 62 provided between the first external terminal 24 and the second external terminal 22.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device in which a socket is disposed inside an outer edge of a sealing member in a direction in which a semiconductor element and a metal member overlap each other, and which may be a three-level or multilevel power converter. Patent Document 2 discloses a semiconductor device in which a positive-side external connection terminal and a negative-side external connection terminal are exposed overlapping each other while being spaced apart from each other from the upper surface of the semiconductor device.

[0003] Patent Document 3 discloses a semiconductor device in which insulating paper is inserted between each electrode exposed on the top surface of the case. Patent Document 4 discloses a semiconductor device having side terminals and top terminals. Patent Document 5 discloses a three-level semiconductor module and a semiconductor device in which three main terminals are arranged in parallel within the module. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 054560 [Patent Document 2] JP 2007-234693 A [Patent Document 3] JP 2004-153243 A [Patent Document 4] Patent Publication No. 2022-67815 [Patent Document 5] JP 2017-118816 A Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional power semiconductor modules, in order to reduce wiring inductance, a configuration has been considered in which multiple external terminals are arranged closely parallel to each other and facing each other (laminate arrangement) and protrude from the side of the sealing resin. However, if the parts of the multiple external terminals protruding from the sealing resin are arranged in a stepped manner so that they can be connected to an external circuit, it is difficult to reduce the size.

[0006] In view of the above problems, an object of the present disclosure is to provide a semiconductor device that can be miniaturized in a configuration in which a plurality of external terminals are arranged in parallel to face each other. [Means for solving the problem]

[0007] One aspect of the present disclosure is a semiconductor device including an insulating circuit board, a semiconductor chip provided on an upper surface of the insulating circuit board, a sealing resin that seals the semiconductor chip, a first external terminal electrically connected to the semiconductor chip and exposed from a first side surface of the sealing resin, a second external terminal electrically connected to the semiconductor chip, having a portion above the first external terminal and facing in parallel to the first external terminal, and exposed from the upper surface of the sealing resin, and a first insulating member provided between the first external terminal and the second external terminal. Effect of the Invention

[0008] According to the present disclosure, it is possible to provide a semiconductor device that can be miniaturized in a configuration in which a plurality of external terminals are arranged parallel to and facing each other. [Brief description of the drawings]

[0009] [Figure 1] 1 is a circuit diagram illustrating an example of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view illustrating an example of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a side view illustrating an example of a semiconductor device according to a first embodiment. [Figure 4] 4 is another plan view showing the example of the semiconductor device according to the first embodiment. FIG. [Diagram 5]1 is a cross-sectional view showing an example of a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view showing an example of a semiconductor device and a mold according to a first embodiment. [Figure 7] FIG. 2 is a circuit diagram showing a semiconductor device according to a first comparative example. [Figure 8] FIG. 2 is a plan view showing a semiconductor device according to a first comparative example. [Figure 9] FIG. 2 is a side view showing a semiconductor device according to a first comparative example. [Figure 10] FIG. 11 is another plan view showing the semiconductor device according to the first comparative example. [Figure 11] 1 is a cross-sectional view showing a semiconductor device according to a first comparative example. [Figure 12] 1 is a cross-sectional view showing a semiconductor device and a mold according to a first comparative example. [Figure 13] FIG. 11 is a plan view showing a semiconductor device according to a second comparative example. [Figure 14] FIG. 11 is a side view showing a semiconductor device according to a second comparative example. [Figure 15] FIG. 11 is a cross-sectional view showing a semiconductor device according to a second comparative example. [Figure 16] FIG. 11 is a cross-sectional view showing an example of a semiconductor device according to a second embodiment. [Figure 17] FIG. 11 is a plan view illustrating an example of a semiconductor device according to a third embodiment. [Figure 18] FIG. 1 is a plan view showing a semiconductor device that configures a two-level circuit. [Figure 19] FIG. 11 is a cross-sectional view showing an example of a semiconductor device according to a fourth embodiment. [Figure 20] FIG. 13 is a cross-sectional view showing an example of a semiconductor device and a mold according to a fourth embodiment. [Figure 21] FIG. 13 is a cross-sectional view showing an example of a semiconductor device according to a fifth embodiment. [Figure 22] FIG. 13 is a cross-sectional view showing an example of a semiconductor device and a mold according to a fifth embodiment. [Figure 23] FIG. 13 is a cross-sectional view showing an example of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the first to sixth embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted with the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, the drawings may include parts with different dimensional relationships and ratios. In addition, the first to sixth embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present disclosure, and the technical idea of ​​the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below.

[0011] In addition, the definitions of directions such as up / down and left / right in the following description are merely for the convenience of explanation and do not limit the technical ideas of the present disclosure. For example, if an object is rotated 90 degrees and observed, up / down is converted to left / right and read, and if it is rotated 180 degrees and observed, up / down is of course read inverted.

[0012] In the following description, the "first main electrode" of a semiconductor chip means an electrode through which a main current flows into or out of the semiconductor chip. When the semiconductor chip is a field effect transistor (FET) or a static induction transistor (SIT), the "first main electrode" means either a source electrode or a drain electrode. When the semiconductor chip is an insulated gate bipolar transistor (IGBT), the "first main electrode" means either an emitter electrode or a collector electrode. When the semiconductor chip is a static induction (SI) thyristor or a gate turn-off (GTO) thyristor, the "first main electrode" means either an anode electrode or a cathode electrode. When the semiconductor chip is a FET or a SIT, the "second main electrode" of a semiconductor chip means either a source electrode or a drain electrode that is not the first main electrode. When the semiconductor chip is an IGBT, the "second main electrode" of a semiconductor chip means either an emitter electrode or a collector electrode that is not the first main electrode. When the semiconductor chip is an SI thyristor or a GTO thyristor, the "second main electrode" of a semiconductor chip means either an anode electrode or a cathode electrode that is not the first main electrode. That is, if the "first main electrode" of the semiconductor chip is the source electrode, the "second main electrode" means the drain electrode. If the "first main electrode" of the semiconductor chip is the emitter electrode, the "second main electrode" means the collector electrode. If the "first main electrode" of the semiconductor chip is the anode electrode, the "second main electrode" means the cathode electrode.

[0013] In addition, the "first external terminal" in the claims corresponds to any one of the positive terminal, negative terminal, intermediate terminal, and output terminal when the semiconductor device is three-level, and corresponds to any one of the positive terminal, negative terminal, and output terminal when the semiconductor device is two-level. The "second external terminal" corresponds to any one of the positive terminal, negative terminal, intermediate terminal, and output terminal other than the "first external terminal" when the semiconductor device is three-level, and corresponds to any one of the positive terminal, negative terminal, and output terminal other than the "first external terminal" when the semiconductor device is two-level. The "third external terminal" corresponds to any one of the positive terminal, negative terminal, intermediate terminal, and output terminal other than the "first external terminal" and "second external terminal" when the semiconductor device is three-level, and corresponds to any one of the positive terminal, negative terminal, and output terminal other than the "first external terminal" and "second external terminal" when the semiconductor device is two-level. When the semiconductor device is three-level, the "fourth external terminal" corresponds to any one of the positive terminal, negative terminal, intermediate terminal, and output terminal that is different from the "first external terminal" to the "third external terminal."

[0014] (First embodiment) <Circuit configuration of semiconductor device> As an example of the semiconductor device according to the first embodiment, a power semiconductor module constituting one phase circuit (three-level circuit) of a three-level power conversion device (three-level inverter) circuit is illustrated. Fig. 1 shows an example of an equivalent circuit of the semiconductor device according to the first embodiment. As shown in Fig. 1, the semiconductor device according to the first embodiment constitutes a three-level circuit and has a positive terminal P which is an input terminal, a negative terminal N which is an input terminal, an intermediate terminal M which is an input terminal, and an output terminal O.

[0015] The drain of the transistor T1 is connected to the positive terminal P. The source of the transistor T1 is connected to the output terminal O and the drain of the transistor T2. The source of the transistor T2 is connected to the negative terminal N.

[0016] The source of the transistor T3 is connected to the intermediate terminal M. The drain of the transistor T3 is connected to the drain of the transistor T4. The source of the transistor T4 is connected to the output terminal O, the source of the transistor T1, and the drain of the transistor T2.

[0017] The transistors T1 to T4 have built-in body diodes D1 to D4 connected in anti-parallel to function as free wheel diodes (FWD). A capacitor C1 is connected between the positive terminal P and the intermediate terminal M. A capacitor C2 is connected between the intermediate terminal M and the negative terminal N.

[0018] <Structure of Semiconductor Device> FIG. 2 is a plan view (top view) of the semiconductor device according to the first embodiment, and FIG. 3 is a side view of the semiconductor device according to the first embodiment.

[0019] 2 and 3, the semiconductor device according to the first embodiment includes a sealing resin 7 having a substantially rectangular parallelepiped shape, a positive terminal (external terminal) 21, a negative terminal (external terminal) 22, and an output terminal (external terminal) 23 exposed from the side surface of the sealing resin 7, an intermediate terminal (external terminal) 24 exposed from the upper surface of the sealing resin 7, and a cooling plate 8 provided on the lower surface side of the sealing resin 7. The positive terminal 21, the negative terminal 22, the output terminal 23, and the intermediate terminal 24 correspond to the positive terminal P, the negative terminal N, the output terminal O, and the intermediate terminal M shown in FIG.

[0020] The positive electrode terminal 21 protrudes from a side surface of the sealing resin 7 and extends in one direction. The positive electrode terminal 21 has a joining region 21a to which an external circuit such as the capacitor C1 shown in Fig. 1 can be joined by laser welding or the like. Note that a screw hole may be provided in the joining region 21a, and the positive electrode terminal 21 may be joined to an external circuit by screwing.

[0021] The negative electrode terminal 22 is provided on the positive electrode terminal 21 via a plate-shaped (sheet-shaped) insulating member (insulating sheet) 61. The negative electrode terminal 22 protrudes from the side surface of the sealing resin 7 from which the positive electrode terminal 21 protrudes, and extends approximately parallel to the extending direction of the positive electrode terminal 21. The negative electrode terminal 22 has a joining region 22a to which an external circuit such as the capacitor C2 shown in FIG. 1 can be joined by laser welding or the like. Note that a screw hole may be provided in the joining region 22a, and the negative electrode terminal 22 may be joined to an external circuit by screwing.

[0022] The intermediate terminal 24 is exposed from an opening 7a provided on the upper surface of the sealing resin 7. The intermediate terminal 24 has a joining area 24a to which an external circuit such as the capacitors C1 and C2 shown in Fig. 1 can be joined by laser welding or the like. Note that a screw hole may be provided in the joining area 24a, and the intermediate terminal 24 may be joined to an external circuit by screwing.

[0023] The output terminal 23 protrudes from a side surface of the sealing resin 7 opposite to the side surface from which the positive electrode terminal 21 and the negative electrode terminal 22 protrude, and extends in the opposite direction to the positive electrode terminal 21 and the negative electrode terminal 22. The output terminal 23 has a bonding area 23a, which is shown in a schematic manner by a dashed line. The bonding area 23a is an area to which an external circuit such as a load can be bonded by laser welding or the like. Note that a screw hole may be provided in the bonding area 23a, and the output terminal 23 may be bonded to an external circuit by screwing.

[0024] Fig. 4 is a plan view (top view) showing the internal structure of the sealing resin 7 shown in Fig. 1 and Fig. 2. In Fig. 4, the sealing resin 7 is shown typically by a broken line, and the negative electrode terminal 22, intermediate terminal 24, insulating member 61, and cooling plate 8 shown in Fig. 2 and Fig. 3 are omitted. Fig. 5 is a cross-sectional view seen from the AA direction in Fig. 4, and also shows the negative electrode terminal 22, intermediate terminal 24, insulating member 61, and cooling plate 8 shown in Fig. 2 and Fig. 3.

[0025] As shown in Figures 4 and 5, the semiconductor device according to the first embodiment includes a cooling plate (base) 8, an insulating circuit board 1 provided on the cooling plate 8, and semiconductor chips (power semiconductor chips) 4a to 4p which are semiconductor elements (power semiconductor elements) for generating electric power provided on the insulating circuit board 1.

[0026] The cooling plate 8 is joined to the lower surface of the insulating circuit board 1 via solder, a sintered material, a thermal compound, or the like. The cooling plate 8 is made of, for example, copper (Cu), aluminum (Al), a composite material of Al and silicon carbide (AlSiC), a composite material of magnesium (Mg) and silicon carbide (MgSiC), or the like. The cooling plate 8 may not be provided on the lower surface side of the insulating circuit board 1, and the lower surface of the insulating circuit board 1 may be exposed from the lower surface of the sealing resin 7. Also, instead of the cooling plate 8, a cooling fin may be provided on the lower surface side of the insulating circuit board 1.

[0027] The insulating circuit board 1 is formed of, for example, a direct copper bond (DCB) board or an active metal solder (AMD) board, etc. The insulating circuit board 1 includes an insulating plate 11, conductive plates (conductor foils) 12a to 12c provided on the upper surface side of the insulating plate 11, and a heat sink (conductor foil) 13 provided on the lower surface side of the insulating plate 11.

[0028] The insulating plate 11 may be a ceramic plate mainly made of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), or a resin insulating layer made of a polymer material. When a resin insulating layer is used as the insulating plate 11, the heat sink 13 on the lower surface side of the insulating plate 11 may be omitted. The conductive plates 12a to 12c and the heat sink 13 are made of, for example, copper (Cu), aluminum (Al), or the like. The planar pattern, number, arrangement position, and the like of the conductive plates 12a to 12c are not particularly limited.

[0029] The semiconductor chips 4a to 4d shown in Figures 4 and 5 correspond to the transistor T1 and body diode D1 shown in Figure 1. The semiconductor chips 4e to 4h shown in Figures 4 and 5 correspond to the transistor T2 and body diode D2 shown in Figure 1. The semiconductor chips 4i to 4l shown in Figures 4 and 5 correspond to the transistor T3 and body diode D3 shown in Figure 1. The semiconductor chips 4m to 4p shown in Figures 4 and 5 correspond to the transistor T4 and body diode D4 shown in Figure 1.

[0030] The semiconductor chips 4a to 4d are bonded onto the conductive plate 12a of the insulating circuit board 1 via a bonding material (not shown) such as solder or a sintered material. The semiconductor chips 4e to 4h and 4m to 4p are bonded onto the conductive plate 12b of the insulating circuit board 1 via a bonding material (not shown) such as solder or a sintered material. The semiconductor chips 4i to 4l are bonded onto the conductive plate 12c of the insulating circuit board 1 via a bonding material (not shown) such as solder or a sintered material.

[0031] In the first embodiment, the semiconductor chips 4a to 4p are configured as metal oxide semiconductor field effect transistors (MOSFETs). The semiconductor chips 4a to 4p may be insulated gate bipolar transistors (IGBTs), static induction (SI) thyristors or gate turn-off (GTO) thyristors, diodes, etc. The semiconductor chips 4a to 4p are configured with semiconductor substrates such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3). The arrangement positions and the number of the semiconductor chips 4a to 4p are not particularly limited.

[0032] 5, the semiconductor chip 4a has a first main electrode (drain electrode) 41a provided on the lower surface side, and a second main electrode (source electrode) 42a and a gate electrode (not shown) provided on the upper surface side. The semiconductor chip 4b has a drain electrode 41b provided on the lower surface side, and a source electrode 42b and a gate electrode (not shown) provided on the upper surface side.

[0033] The conductive plate 12a of the insulating circuit board 1 is joined to the drain electrodes 41a, 41b of the semiconductor chips 4a, 4b via a bonding material (not shown) such as solder or a sintered material. One end of the lead frame 26 is joined to the source electrodes 42a, 42b of the semiconductor chips 4a, 4b via a bonding material (not shown) such as solder or a sintered material. The conductive plate 12b of the insulating circuit board 1 is joined to the other end of the lead frame 26 via a bonding material (not shown) such as solder or a sintered material. A control terminal (not shown) is electrically connected to the gate electrodes of the semiconductor chips 4a, 4b via a bonding wire (not shown) or the like. A control signal is applied to the gate electrodes of the semiconductor chips 4a, 4b via the control terminal, and the on and off of the current flowing between the drain electrodes 41a, 41b and the source electrodes 42a, 42b of the semiconductor chips 4a, 4b is controlled.

[0034] The semiconductor chip 4e has a drain electrode 41e provided on the lower surface side, and a source electrode 42e and a gate electrode (not shown) provided on the upper surface side. The semiconductor chip 4f has a drain electrode 41f provided on the lower surface side, and a source electrode 42f and a gate electrode (not shown) provided on the upper surface side.

[0035] The conductive plate 12b of the insulating circuit board 1 is joined to the drain electrodes 41e, 41f of the semiconductor chips 4e, 4f via a joining material (not shown) such as solder or a sintered material. The intermediate terminal 24 is joined to the source electrodes 42e, 42f of the semiconductor chips 4e, 4f via a joining material (not shown) such as solder or a sintered material. A control terminal (not shown) is electrically connected to the gate electrodes of the semiconductor chips 4e, 4f via a bonding wire (not shown) or the like. A control signal is applied to the gate electrodes of the semiconductor chips 4e, 4f via the control terminal, and the on and off of a current flowing between the drain electrodes 41e, 41f and the source electrodes 42e, 42f of the semiconductor chips 4e, 4f is controlled.

[0036] The semiconductor chips 4c, 4d, 4g to 4p shown in FIG. 4 have a source electrode and a gate electrode on the upper surface side and a drain electrode on the lower surface side in the same configuration as the semiconductor chips 4a, 4b, 4e, and 4f shown in FIG.

[0037] The positive electrode terminal 21, the negative electrode terminal 22, the output terminal 23, and the intermediate terminal 24 shown in FIG. 4 and FIG. 5 are electrically connected to the semiconductor chips 4a to 4p. The materials for the positive electrode terminal 21, the negative electrode terminal 22, the output terminal 23, and the intermediate terminal 24 may be copper (Cu), a Cu alloy, aluminum (Al), an Al alloy, or the like. The thicknesses of the positive electrode terminal 21, the negative electrode terminal 22, the output terminal 23, and the intermediate terminal 24 depend on the rated current and the rated voltage, but are, for example, about 0.8 mm or more and 2 mm or less. The thicknesses of the positive electrode terminal 21, the negative electrode terminal 22, the output terminal 23, and the intermediate terminal 24 may be the same as each other or may be different from each other. The widths of the positive electrode terminal 21, the negative electrode terminal 22, the output terminal 23, and the intermediate terminal 24 may be the same as each other or may be different from each other.

[0038] The positive electrode terminal 21 has a flat plate shape. The positive electrode terminal 21 is joined to the conductive plate 12a of the insulating circuit board 1 by laser welding or the like. The positive electrode terminal 21 may be joined to the conductive plate 12a of the insulating circuit board 1 via a conductive member such as a copper block or a lead frame, or may be joined to the conductive plate 12a of the insulating circuit board 1 by having a bent portion bent in an L-shape or a Z-shape. The positive electrode terminal 21 is electrically connected to the drain electrodes 41a and 41b on the lower sides of the semiconductor chips 4a and 4b. The positive electrode terminal 21 is also electrically connected to the drain electrodes on the lower sides of the semiconductor chips 4c and 4d shown in FIG. 4. As shown in FIGS. 2 to 5, a part of the positive electrode terminal 21 protrudes from the side surface of the sealing resin 7 and extends in one direction.

[0039] In the cross-sectional view shown in Fig. 5, the negative electrode terminal 22 has a flat plate shape. The negative electrode terminal 22 is joined to the conductive plate 12c of the insulating circuit board 1 shown in Fig. 4 by laser welding or the like. The negative electrode terminal 22 may be joined to the conductive plate 12c of the insulating circuit board 1 via a conductive member such as a copper block or a lead frame, or may be joined to the conductive plate 12c of the insulating circuit board 1 by having a bent portion bent in an L-shape or a Z-shape. The negative electrode terminal 22 is electrically connected to the drain electrodes on the lower surface sides of the semiconductor chips 4i to 4l.

[0040] 2, 3, and 5, a part of the negative electrode terminal 22 protrudes from the side surface of the sealing resin 7 from which the positive electrode terminal 21 protrudes, and extends approximately parallel to the extending direction of the positive electrode terminal 21. The length of the part of the negative electrode terminal 22 protruding from the sealing resin 7 is shorter than the length of the part of the insulating member 61 protruding from the sealing resin 7. The length of the part of the insulating member 61 protruding from the sealing resin 7 is shorter than the length of the part of the positive electrode terminal 21 protruding from the sealing resin 7. The ends of the negative electrode terminal 22, the insulating member 61, and the positive electrode terminal 21 are provided in a stepped shape.

[0041] A large current exceeding several hundred amperes flows through the positive terminal 21, the negative terminal 22, the output terminal 23, and the intermediate terminal 24. When the current is turned on and off, a surge voltage (V=L×di / dt) occurs due to the influence of the wiring inductance (L). If this voltage exceeds the breakdown voltage of the semiconductor chips 4a to 4p, the semiconductor chips 4a to 4p will be destroyed. Therefore, it is necessary to suppress the surge voltage by reducing the wiring inductance. In order to reduce the inductance, it is effective to make the wiring thicker and shorter, or to branch the current path into multiple parallel paths, but in order to reduce the size, it is effective to arrange the current paths closely together (laminate arrangement) so that they run in opposite directions on the way there and back, thereby increasing the effect of mutual electromagnetic induction and reducing the apparent inductance.

[0042] 2, 3, and 5, a part of the positive electrode terminal 21 and a part of the negative electrode terminal 22 are arranged in close proximity (laminated arrangement) so as to overlap each other in parallel and face each other through an insulating member 61 from the inside to the outside of the sealing resin 7. The thickness of the insulating member 61 is constant, and a part of the positive electrode terminal 21 and a part of the negative electrode terminal 22 are arranged in parallel and spaced apart from each other by a predetermined distance. The thickness of the insulating member 61 does not have to be constant. In the overlapping portion of the positive electrode terminal 21 and the negative electrode terminal 22, currents flow in the opposite directions in the positive electrode terminal 21 and the negative electrode terminal 22 in the outgoing and returning directions of the current path, so that the wiring inductance between the positive electrode terminal 21 and the negative electrode terminal 22 can be reduced. In addition, by overlapping the positive electrode terminal 21, the intermediate terminal 24, and the negative electrode terminal 22 in this order, the wiring inductance between the positive electrode terminal 21 and the intermediate terminal 24 and the wiring inductance between the intermediate terminal 24 and the negative electrode terminal 22 can be reduced.

[0043] As shown in Fig. 5, the intermediate terminal 24 has a bent portion bent in a Z-shape and is joined to the source electrodes on the upper surfaces of the semiconductor chips 4e, 4f via a joining material such as solder or a sintered material. The intermediate terminal 24 may not have a bent portion and may be electrically connected to the source electrodes on the upper surfaces of the semiconductor chips 4e, 4f via a conductive member such as a copper block or a lead frame. The intermediate terminal 24 is also electrically connected to the source electrodes on the upper surfaces of the semiconductor chips 4g, 4h shown in Fig. 4.

[0044] 5, inside the sealing resin 7, a part of the negative electrode terminal 22 and a part of the intermediate terminal 24 are closely arranged (laminated) so as to overlap and face each other substantially parallel to each other via a plate-shaped (sheet-shaped) insulating member (insulating sheet) 62. The thickness of the insulating member 62 is constant, and the part of the negative electrode terminal 22 and the part of the intermediate terminal 24 are arranged substantially parallel to each other while being spaced apart from each other by a predetermined distance. The thickness of the insulating member 62 does not have to be constant. In the overlapping portion of the negative electrode terminal 22 and the intermediate terminal 24, currents flow in the negative electrode terminal 22 and the intermediate terminal 24 in the opposite directions in the outgoing and returning current paths, so that the wiring inductance can be reduced.

[0045] The insulating members 61, 62 may be made of insulating materials having high insulating properties and heat resistance, such as insulating paper, polyimide, or polyamide. The insulating members 61, 62 may be made of epoxy resin, polyphenylene sulfide (PPS) resin, or the like. When using a resin material for the insulating members 61, 62, a plate-shaped (sheet-shaped) resin material may be sandwiched between the insulating members 61, 62, or terminals such as the positive terminal 21, the negative terminal 22, and the intermediate terminal 24 may be fabricated as an integral part with the resin material by primary molding, and the integral part may be mounted on the semiconductor chips 4a to 4p. The thickness of the insulating members 61, 62 may be thinner than the thickness of the positive terminal 21, the negative terminal 22, the output terminal 23, and the intermediate terminal 24. The thickness of the insulating members 61, 62 is, for example, about 0.1 mm or more and 1.0 mm or less.

[0046] 2 and 5, a part of the intermediate terminal 24 is exposed from the opening 7a provided in the upper surface of the sealing resin 7. The upper surface of the intermediate terminal 24 exposed from the opening 7a is flush with the upper surface of the sealing resin 7. A thickness t11 of the portion where the upper surface of the intermediate terminal 24 is exposed is thicker than a thickness t12 of the portion where the intermediate terminal 24 is not exposed. Note that the intermediate terminal 24 may be bent in a Z-shape and exposed from the opening 7a, and the thickness of the portion where the upper surface of the intermediate terminal 24 is exposed may be approximately the same as the thickness of the portion where the intermediate terminal 24 is not exposed or may be thinner than the thickness of the portion where the intermediate terminal 24 is not exposed.

[0047] 2 to 5, output terminal 23 has a flat plate shape. Output terminal 23 is joined to conductive plate 12b of insulating circuit board 1 by laser welding or the like. Output terminal 23 may be joined to conductive plate 12b of insulating circuit board 1 via a conductive member such as a copper block or a lead frame, or may be joined to conductive plate 12b of insulating circuit board 1 by having a bent portion bent in an L-shape or Z-shape.

[0048] The output terminal 23 is electrically connected to the upper source electrodes 42a, 42b of the semiconductor chips 4a, 4b and the lower drain electrodes 41e, 41f of the semiconductor chips 4e, 4f. The output terminal 23 is also electrically connected to the upper source electrodes of the semiconductor chips 4c, 4d and the lower drain electrodes of the semiconductor chips 4g, 4h, 4m to 4p shown in Fig. 4. A part of the output terminal 23 protrudes from a side surface of the sealing resin 7 opposite to the side surface from which the negative electrode terminal 22 and the positive electrode terminal 21 protrude, and extends in the opposite direction to the negative electrode terminal 22 and the positive electrode terminal 21.

[0049] The sealing resin 7 seals the insulating circuit board 1 and the semiconductor chips 4a to 4p, etc. As the sealing resin 7, insulating sealing resins such as thermosetting silicone gel and epoxy resins can be used.

[0050] According to the semiconductor device of the first embodiment, in a configuration in which the three positive electrode terminals 21, the negative electrode terminal 22, and the intermediate terminal 24 are closely arranged (laminated) with the insulating members 61, 62 interposed therebetween, the two lower positive electrode terminals 21 and the negative electrode terminal 22 are caused to protrude from the side surface of the sealing resin 7, and the uppermost intermediate terminal 24 is exposed from the upper surface of the sealing resin 7. As a result, compared to a case in which the three positive electrode terminals 21, the negative electrode terminal 22, and the intermediate terminal 24 are caused to protrude from the side surface of the sealing resin 7, the distance d1 and the thickness t1 of the parts of the positive electrode terminal 21 and the negative electrode terminal 22 protruding from the sealing resin 7 can be made smaller, and miniaturization can be achieved.

[0051] <Method of Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0052] Heat sink 13 of insulating circuit board 1 is bonded onto cooling plate 8 shown in Figures 4 and 5 via a bonding material such as solder, a sintered material, or a thermal compound. Semiconductor chips 4a to 4p are bonded onto conductive plates 12a to 12c of insulating circuit board 1 shown in Figures 4 and 5 via a bonding material such as solder or a sintered material.

[0053] Next, the positive terminal 21, the negative terminal 22, the output terminal 23, the intermediate terminal 24, and the lead frame 26 are joined via a joining material such as solder or a sintered material onto the conductive plates 12a-12c and the semiconductor chips 4a-4p of the insulating circuit board 1. At this time, an insulating member 61 is sandwiched between the positive terminal 21 and the negative terminal 22 and disposed adjacent to them, and an insulating member 62 is sandwiched between the negative terminal 22 and the intermediate terminal 24 and disposed adjacent to them.

[0054] Next, the insulating circuit board 1, the semiconductor chips 4a to 4p, the positive electrode terminals 21, the negative electrode terminals 22, the output terminals 23, the intermediate terminals 24, the lead frame 26, the insulating member 61, etc. are fixed (chucked) from above and below by metal molds 91, 92 (see FIG. 6). At this time, the upper surface of the portion of the intermediate terminal 24 that is to be exposed from the sealing resin 7 contacts the metal mold 91. In this state, resin is injected inside the metal molds 91, 92 to perform transfer molding. As a result, the sealing resin 7 is formed as shown in FIG. 6, and the semiconductor device according to the first embodiment is completed.

[0055] <First Comparative Example> Fig. 7 shows an example of an equivalent circuit of the semiconductor device according to the first comparative example. As shown in Fig. 7, the semiconductor device according to the first comparative example differs from the semiconductor device according to the first embodiment, which constitutes a three-level circuit, shown in Fig. 1, in that it constitutes a two-level circuit. That is, the semiconductor device according to the first comparative example differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that it does not have an intermediate terminal M, does not have a capacitor C2 connected between the intermediate terminal M and the output terminal O, and does not have transistors T3, T4 and body diodes D3, D4 connected between the intermediate terminal M and the output terminal O.

[0056] Fig. 8 is a plan view (top view) of the semiconductor device according to the first comparative example, and Fig. 9 is a side view of the semiconductor device according to the first comparative example. As shown in Figs. 8 and 9, the semiconductor device according to the first comparative example is different from the semiconductor device according to the first embodiment shown in Figs. 2 and 3 in that the opening 7a is not provided on the upper surface of the sealing resin 7, the semiconductor device does not have an intermediate terminal 24, and the negative terminal 22 protrudes from the side surface of the sealing resin 7.

[0057] Fig. 10 is a plan view (top view) showing the internal structure of the sealing resin 7 shown in Fig. 8 and Fig. 9. In Fig. 10, the sealing resin 7 is shown typically by a broken line, and the positive electrode terminal 21, the insulating member 61, and the cooling plate 8 shown in Fig. 8 and Fig. 9 are omitted. Fig. 11 is a cross-sectional view seen from the AA direction in Fig. 10, and also shows the positive electrode terminal 21, the insulating member 61, and the cooling plate 8 shown in Fig. 8 and Fig. 9.

[0058] As shown in Figures 10 and 11, the semiconductor device according to the first embodiment differs from the semiconductor device according to the first embodiment shown in Figures 4 and 5 in that the conductive plate 12c and the semiconductor chips 4i to 4p are not provided on the upper surface side of the insulating circuit board 1, and that the positive electrode terminal 21 and the negative electrode terminal 22 are arranged adjacent to each other (laminated arrangement) with an insulating member 62 interposed therebetween.

[0059] In manufacturing the semiconductor device according to the first comparative example, as shown in FIG. 12, the sealing resin 7 is formed by transfer molding using dies 91 and 92. In contrast to this, in the semiconductor device according to the first embodiment, the distance d1 and thickness t1 of the parts of the positive terminal 21 and the negative terminal 22 protruding from the sealing resin 7 shown in FIG. 6 are adjusted to match the distance d2 and thickness t2 of the parts of the positive terminal 21 and the negative terminal 22 protruding from the sealing resin 7 of the semiconductor device according to the first comparative example shown in FIG. 12. As a result, the outer shape of the parts protruding from the sealing resin 7 of the semiconductor device according to the first embodiment and the outer shape of the parts protruding from the sealing resin 7 of the semiconductor device according to the first comparative example become similar. Therefore, the dies 91 and 92 used in the transfer molding of the semiconductor device according to the first embodiment shown in FIG. 6 can be used in common with the dies 91 and 92 used in the transfer molding of the semiconductor device according to the first comparative example shown in FIG. 12.

[0060] <Second Comparative Example> The semiconductor device according to the second comparative example is similar to the semiconductor device according to the first embodiment shown in FIG. 1 in that it constitutes a three-level circuit.

[0061] Fig. 13 is a plan view (top view) of the semiconductor device according to the second comparative example, Fig. 14 is a side view of the semiconductor device according to the second comparative example, and Fig. 15 is a cross-sectional view of the semiconductor device according to the second comparative example at a position corresponding to Fig. 5. As shown in Figs. 13 to 15, the semiconductor device according to the second comparative example differs from the semiconductor device according to the first embodiment in that the three positive electrode terminals 21, the negative electrode terminal 22, and the intermediate terminal 24 protrude from a common side surface of the sealing resin 7.

[0062] In the semiconductor device of the second comparative example, the three positive electrode terminals 21, the negative electrode terminal 22, and the intermediate terminal 24 protrude from a common side surface of the sealing resin 7, and therefore the distance d3 and thickness t3 of the portions where the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 protrude from the sealing resin 7 become large, making miniaturization difficult.

[0063] In addition, when realizing a two-level circuit or a three-level circuit, the manufacturing equipment can be standardized by molding the product with resin without changing the external size. However, in the semiconductor device according to the second comparative example, the distance d3 and thickness t3 of the protruding parts of the positive terminal 21, the negative terminal 22, and the intermediate terminal 24 from the sealing resin 7 increase due to the increase in the number of terminals, and they interfere with the molds 91 and 92 during transfer molding of the semiconductor device according to the first comparative example shown in FIG. 12, so it is necessary to change the shape of the mold.

[0064] In contrast, according to the semiconductor device of the first embodiment, the dies 91, 92 used during transfer molding of the semiconductor device of the first embodiment shown in Fig. 6 can be made common to the dies 91, 92 used during transfer molding of the semiconductor device of the first comparative example shown in Fig. 12. This makes it unnecessary to change the setup or replace the dies during production, thereby making it possible to suppress increases in die manufacturing costs and product costs.

[0065] Second embodiment The semiconductor device according to the second embodiment, like the semiconductor device according to the first comparative example shown in FIG. 7, constitutes a two-level circuit, which differs from the semiconductor device according to the first embodiment which constitutes a three-level circuit shown in FIG. 1.

[0066] A plan view (top view) of the semiconductor device according to the second embodiment is similar to the plan view (top view) of the semiconductor device according to the first comparative example shown in Fig. 10. Fig. 16 is a cross-sectional view of the semiconductor device according to the second embodiment at a position corresponding to Figs. 5 and 11.

[0067] 10 and 16, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that it does not have an intermediate terminal 24, that the conductive plate 12c and the semiconductor chips 4i-4p are not provided on the upper surface of the insulating circuit board 1, and that a part of the negative electrode terminal 22 is exposed from an opening 7a provided on the upper surface of the sealing resin 7. Other configurations of the semiconductor device according to the second embodiment are substantially similar to those of the semiconductor device according to the first embodiment, so duplicated explanations will be omitted.

[0068] According to the semiconductor device of the second embodiment, in a configuration in which a two-level circuit is formed and the positive electrode terminal 21 and the negative electrode terminal 22 are disposed adjacent to each other via an insulating member 61, the lower positive electrode terminal 21 of the two positive electrode terminals 21 and the negative electrode terminal 22 is caused to protrude from the side surface of the sealing resin 7, and the upper negative electrode terminal 22 is exposed from the upper surface of the sealing resin 7. As a result, compared to a case in which both the positive electrode terminal 21 and the negative electrode terminal 22 are caused to protrude from the side surface of the sealing resin 7, the distance d4 and the thickness t4 of the part of the positive electrode terminal 21 protruding from the side surface of the sealing resin 7 can be made smaller, and the size can be reduced.

[0069] Third embodiment Fig. 17 is a plan view (top view) of a semiconductor device according to a third embodiment. As shown in Fig. 17, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 2 in that the positive electrode terminal 21 and the intermediate terminal 24 protruding from the side surface of the sealing resin 7 are arranged side by side (horizontally) without overlapping each other. The negative electrode terminal 22 is exposed from the upper surface of the sealing resin 7 through an opening 7a provided in the upper surface of the sealing resin 7.

[0070] The cross section viewed from the AA direction in Fig. 17 is similar to that in Fig. 16. As shown in Fig. 16, inside the sealing resin 7, the positive electrode terminal 21 and the negative electrode terminal 22 are disposed adjacent to each other via an insulating sheet 61. Although not shown, inside the sealing resin 7, the intermediate terminal 24 and the negative electrode terminal 22 are also disposed adjacent to each other via an insulating sheet. Other configurations of the semiconductor device according to the third embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0071] According to the semiconductor device of the third embodiment, in a configuration in which the negative electrode terminal 22 is disposed adjacent to the positive electrode terminal 21 and the intermediate terminal 24 (laminated arrangement), the lower positive electrode terminal 21 and intermediate terminal 24 are caused to protrude from the side surface of the sealing resin 7, and the upper negative electrode terminal 22 is exposed from the upper surface of the sealing resin 7. As a result, compared to a case in which the three positive electrode terminals 21, the negative electrode terminal 22, and the intermediate terminal 24 are caused to protrude from the side surface of the sealing resin 7, the distance d4 and thickness t4 (see FIG. 16 ) of the parts of the positive electrode terminal 21 and the intermediate terminal 24 protruding from the side surface of the sealing resin 7 can be made smaller, and miniaturization can be achieved.

[0072] Furthermore, according to the semiconductor device according to the third embodiment, the external shape of the semiconductor device according to the first embodiment shown in FIG. 17 can be made the same as that of the semiconductor device constituting the two-level circuit shown in FIG. 18. In the semiconductor device constituting the two-level circuit shown in FIG. 18, the positive terminal 21 and the negative terminal 22 are arranged side by side (horizontally) without overlapping each other. Therefore, the mold used in the transfer molding of the semiconductor device according to the first embodiment shown in FIG. 17 can be shared with the mold used in the transfer molding of the semiconductor device constituting the two-level circuit shown in FIG. 18. This makes it unnecessary to change the setup or replace the mold during manufacturing, and can suppress increases in mold manufacturing costs and product costs.

[0073] (Fourth embodiment) Fig. 19 is a cross-sectional view of the semiconductor device according to the fourth embodiment, taken at a position corresponding to Fig. 5. As shown in Fig. 19, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 5 in that the upper surfaces of the intermediate terminals 24 exposed from the upper surface of the sealing resin 7 are not flush with the upper surface of the sealing resin 7, but are recessed from the upper surface of the sealing resin 7.

[0074] 20, a mold 91 having a protrusion 91a is used for transfer molding of the semiconductor device according to the fourth embodiment. The portions of the intermediate terminals 24 to be exposed from the upper surface of the sealing resin 7 are in contact with the protrusions 91a of the mold 91 when transfer molding is performed, thereby forming openings 7a in the sealing resin 7. Other configurations of the semiconductor device according to the fourth embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0075] According to the semiconductor device of the fourth embodiment, in a configuration in which three positive electrode terminals 21, negative electrode terminal 22, and intermediate terminal 24 are closely arranged (laminated arrangement) via insulating members 61 and 62, the two lower positive electrode terminals 21 and negative electrode terminal 22 are protruded from the side surface of the sealing resin 7, and the uppermost one intermediate terminal 24 is exposed from the upper surface of the sealing resin 7. As a result, compared to a case in which the three positive electrode terminals 21, negative electrode terminal 22, and intermediate terminal 24 are protruded from the side surface of the sealing resin 7, the distance d1 and thickness t1 of the protruding parts of the positive electrode terminal 21 and negative electrode terminal 22 from the sealing resin 7 can be made smaller, and miniaturization can be achieved. In addition, since the upper surface of the intermediate terminal 24 is recessed from the upper surface of the sealing resin 7, the conductive member (not shown) connected to the intermediate terminal 24 can be easily positioned by making it correspond to this recessed shape.

[0076] Fifth embodiment Fig. 21 is a cross-sectional view of the semiconductor device according to the fifth embodiment, taken at a position corresponding to Fig. 5. As shown in Fig. 21, the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 5 in that the upper surfaces of the intermediate terminals 24 exposed from the upper surface of the sealing resin 7 are not flush with the upper surface of the sealing resin 7, but protrude upward from the upper surface of the sealing resin 7 in a convex manner.

[0077] 22, a mold 91 is used in which recesses 91b corresponding to the protruding portions of the upper surfaces of the intermediate terminals 24 are provided. Other configurations of the semiconductor device according to the fifth embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0078] According to the semiconductor device of the fifth embodiment, in a configuration in which three positive electrode terminals 21, negative electrode terminals 22, and intermediate terminals 24 are closely arranged (laminated arrangement) via insulating members 61 and 62, the two lower positive electrode terminals 21 and negative electrode terminals 22 are protruded from the side surface of the sealing resin 7, and the uppermost intermediate terminal 24 is exposed from the upper surface of the sealing resin 7. As a result, compared to a case in which the three positive electrode terminals 21, negative electrode terminals 22, and intermediate terminals 24 are protruded from the side surface of the sealing resin 7, the distance d1 and thickness t1 of the protruding parts of the positive electrode terminals 21 and negative electrode terminals 22 from the sealing resin 7 can be made smaller, and miniaturization can be achieved. In addition, since the upper surface of the intermediate terminal 24 protrudes upwardly from the upper surface of the sealing resin 7, the intermediate terminal 24 can be made thick, and when the intermediate terminal 24 and a conductive member (not shown) are joined by a laser, a temperature rise of the insulating member 62 directly below the welding location can be suppressed.

[0079] Sixth embodiment Fig. 23 is a cross-sectional view of the semiconductor device according to the sixth embodiment at a position corresponding to Fig. 5. As shown in Fig. 23, the semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 5 in that an opening 7a in the upper surface of the sealing resin 7 is provided at an end of the upper surface of the sealing resin 7. The upper surface and side surface of the end of the intermediate terminal 24 are exposed in the opening 7a of the sealing resin 7. Other configurations of the semiconductor device according to the sixth embodiment are substantially similar to those of the semiconductor device according to the first embodiment, so duplicated explanations will be omitted.

[0080] According to the semiconductor device of the sixth embodiment, in a configuration in which the three positive electrode terminals 21, the negative electrode terminal 22, and the intermediate terminal 24 are closely arranged (laminated) with insulating members 61, 62 interposed therebetween, the two lower positive electrode terminals 21 and the negative electrode terminal 22 are caused to protrude from the side surface of the sealing resin 7, and the uppermost intermediate terminal 24 is exposed from the upper surface of the sealing resin 7. As a result, compared to a case in which the three positive electrode terminals 21, the negative electrode terminal 22, and the intermediate terminal 24 are caused to protrude from the side surface of the sealing resin 7, the distance d1 and the thickness t1 of the parts of the positive electrode terminal 21 and the negative electrode terminal 22 protruding from the sealing resin 7 can be made smaller, and miniaturization can be achieved.

[0081] (Other embodiments) As described above, the present disclosure has been described by the first to sixth embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0082] For example, in the first, fourth and sixth embodiments, a laminate wiring structure in which the positive electrode terminal 21, the negative electrode terminal 22 and the intermediate terminal 24 are arranged in this order from the bottom has been exemplified, but the order of the positive electrode terminal 21, the negative electrode terminal 22 and the intermediate terminal 24 is not limited to this and can be appropriately selected. For example, a laminate wiring structure in which the positive electrode terminal 21, the intermediate terminal 24 and the negative electrode terminal 22 are arranged in this order from the bottom may also be used. In addition, the position of any one of the positive electrode terminal 21, the negative electrode terminal 22 and the intermediate terminal 24 and the output terminal 23 may be interchanged.

[0083] In the second embodiment, a laminate wiring structure in which the positive terminal 21 and the negative terminal 22 are arranged in this order from the bottom is illustrated, but the order of the positive terminal 21 and the negative terminal 22 is not limited to this, and a laminate wiring structure in which the negative terminal 22 and the positive terminal 21 are arranged in this order from the bottom may also be used. In addition, the positions of either the positive terminal 21 or the negative terminal 22 and the output terminal 23 may be interchanged.

[0084] Furthermore, in the first to sixth embodiments, the semiconductor device constituting a two-level circuit or a three-level circuit has been exemplified, but the present invention is also applicable to a semiconductor device constituting a multi-level circuit such as a four-level circuit.

[0085] In addition, the configurations disclosed in the first to sixth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is determined only by the invention-specifying matters related to the claims that are appropriate from the above description. [Explanation of symbols]

[0086] 1...Insulated circuit board 4a~4p...Semiconductor chips 7…Sealing resin 7a...Opening 8…Cooling plate (base) 11...Insulating plate 12a~12c...Conductive plate 13...Heat sink 21...Positive terminal (external terminal) 21a...Joining area 22...Negative terminal (external terminal) 22a...Joining area 23...Output terminal (external terminal) 23a...Joining area 24...Intermediate terminal (external terminal) 24a...Joining area 26…Lead frame 41a, 41b, 41e, 41f...Drain electrodes 42a, 42b, 42e, 42f...Source electrodes 61, 62...Insulating member 91,92…Mold 91a…Convex part C1, C2: Capacitors D1~D4: Body diodes M…Intermediate terminal N...Negative terminal O: Output terminal P…Positive terminal T1~T4: Transistors d1~d4…distance t1~t4…Thickness

Claims

1. An insulating circuit board; a semiconductor chip provided on an upper surface side of the insulating circuit board; a sealing resin for sealing the semiconductor chip; a first external terminal electrically connected to the semiconductor chip and exposed from a first side surface of the sealing resin; a second external terminal that is electrically connected to the semiconductor chip, has a portion that faces the first external terminal in parallel on a side above the first external terminal, and is exposed from an upper surface of the sealing resin; a first insulating member provided between the first external terminal and the second external terminal; A semiconductor device comprising:

2. a third external terminal that is electrically connected to the semiconductor chip, has a portion that faces the first external terminal in parallel below the first external terminal, and is exposed from the first side surface of the sealing resin; a second insulating member provided between the first external terminal and the third external terminal; Further comprising The semiconductor device according to claim 1 .

3. a third external terminal that is electrically connected to the semiconductor chip, that is provided on a side of the first external terminal, that has a portion that faces the first external terminal in parallel, and that is exposed from the first side surface of the sealing resin; The semiconductor device according to claim 1 .

4. a third external terminal electrically connected to the semiconductor chip and exposed from a second side surface of the sealing resin opposite to the first side surface. The semiconductor device according to claim 1 .

5. a fourth external terminal electrically connected to the semiconductor chip and exposed from a second side surface of the sealing resin opposite to the first side surface. The semiconductor device according to claim 2 or 3.

6. The upper surface of the second external terminal exposed from the upper surface of the sealing resin is flush with the upper surface of the sealing resin. The semiconductor device according to claim 1 .

7. The upper surface of the second external terminal exposed from the upper surface of the sealing resin is recessed from the upper surface of the sealing resin. The semiconductor device according to claim 1 .

8. The upper surface of the second external terminal exposed from the upper surface of the sealing resin protrudes from the upper surface of the sealing resin. The semiconductor device according to claim 1 .

9. The second external terminal faces the first external terminal in parallel inside the sealing resin. The semiconductor device according to claim 1 .

10. The third external terminal is disposed in parallel to and faces the first external terminal from the inside to the outside of the sealing resin. The semiconductor device according to claim 2 .

11. A thickness of a portion of the second external terminal that is exposed from the upper surface of the sealing resin is greater than a thickness of a portion of the second external terminal that is not exposed from the upper surface of the sealing resin. The semiconductor device according to claim 1 .

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