Tool for supporting use of regular network topologies in generating network-on-chip topology

Abstract

To provide a tool for using a custom subnetwork description during generation and synthesis of a network, such as a network-on-chip (NoC).SOLUTION: A tool disclosed herein allows for incremental synthesis and transformation of a deadlock-free NoC. A NoC topology is transformed into an existing segment to reuse the existing segment in a new route and generate a deadlock-free NoC topology. The tool includes a machine learning model that is trained for synthesis and generation of the NoC and is capable of providing incremental synthesis. The model can also receive feedback from past or previous synthesis for further training of the model.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63 / 509,757, entitled "TOOL FOR SUPPORTING USE OF REGULAR NETWORK TOPOLOGIES IN GENERATING A NETWORK-ON-CHIP TOPOLOGY," filed on June 22, 2023 by Amir CHARIF et al., the entire disclosure of which is incorporated herein by reference.

[0002] Technical Field The present technology is in the field of system design, and more specifically, relates to topology generation for network-on-chip (NoC). [Background technology]

[0003] background Multiprocessor systems are implemented in systems-on-chip (SoCs) that communicate through networks-on-chip (NoCs). NoCs are an example for designing scalable communication architectures for SoCs. When using NoCs in design applications, it is more desirable to eliminate conditions that result in deadlocks in the network. Currently, it is known to route messages through an array of data processing nodes to facilitate multiple paths directed to a destination without causing messages to be delayed due to routing deadlocks. An important aspect in designing application-specific NoCs is more desirable deadlock-free operation with minimal power and area overhead. There are two main types of deadlocks that are known to occur in NoCs. The first type of deadlock is routing-dependent deadlock. The second type of deadlock is message-dependent deadlock.

[0004] The SoC contains an initiator intellectual property (IP) and a target IP. Transactions in the form of packets are sent from a master to one or more slaves using industry standard protocols. A master connected to a NoC sends a request transaction to a slave, using an address to select the slave. The NoC decodes the address and forwards the request from the master to the slave. The slave processes the transaction and sends a response transaction, which is sent back to the master by the NoC.

[0005] For a given set of performance requirements, such as connectivity and latency between source and destination, frequency of various elements, maximum area available for NoC logic, minimum throughput between source and destination, location on the floorplan of elements attached to the NoC, etc., it is a complex task to create an optimal NoC that meets all the requirements with a minimum amount of logic and wiring. This is usually the job of a chip architect or chip designer to create this optimal NoC, which is a difficult and time-consuming task. In addition to this being a difficult task, the design of the NoC is revised every time the requirements change, such as modifying the chip's floorplan or modifying the expected performance. As a result, this task needs to be reworked frequently over the design time of the chip. This process is time-consuming and results in fabrication delays. Therefore, what is needed is a system and method for efficiently generating a NoC from a set of constraints enumerated as requirements and a set of inputs. The system needs to fabricate a NoC with all its elements placed on the chip's floorplan. Summary of the Invention [Problem to be solved by the invention]

[0006] Current issues exist for supporting regular network topologies when performing NoC synthesis, especially when introducing new connections to an existing NoC. Thus, there is a need to have the ability to support regular network topologies while avoiding both routing-dependent and message-dependent deadlocks and allowing the synthesis of NoC topologies that are integrated with the topology synthesis phase of the NoC design flow. By considering the deadlock avoidance problem during topology synthesis, a more desirable NoC design can be achieved compared to traditional methods where the deadlock avoidance problem is managed separately. Furthermore, there is a need to add new connections without overwriting previous results. [Means for solving the problem]

[0007] overview According to various embodiments and aspects of the present invention, a tool is disclosed for generating a network-on-chip (NoC) using a set of constraints and a set of steps having inputs for fabricating or generating a NoC with all its elements while supporting a common network topology. The elements of the NoC are placed on a chip floor plan. An advantage of the present invention is the simplification of the design process and the work of the chip architect or designer. A NoC generation or synthesis method with incremental design, whereby a NoC is generated or synthesized one connection at a time. In particular, a set of source-destination pair nodes and each new connection are synthesized by taking as input a set of existing connections. New components, including but not limited to switches and / or links, may be created when synthesizing a new connection to define a network path from a source to a destination. It is within the scope of the present invention, including but not limited to, the destination being a list of components to be traversed. Furthermore, configuring the newly created components, including but not limited to clock and / or data width, is an important aspect when synthesizing a new connection.

[0008] According to various embodiments and aspects of the present invention, the tool can reuse existing segments of the generated topology even if the topology is highly irregular and tree-like. Therefore, in some designs, such as one subsystem of a design with complex connectivity, it is preferable to select a known regular topology, such as a mesh network, for its simplicity and efficiency in terms of implementation cost and bandwidth distribution. Thus, the tool can leverage the common format and add seamless support for regular topologies.

[0009] In one embodiment, the set of existing connections may be empty, so that the NoC is synthesized from the beginning of the process with no existing connections.

[0010] The order in which connections are implemented affects the quality of the topology. In one embodiment, the order may be determined based on multiple mathematical optimization techniques and / or heuristics. For example, the order may be determined by the area of ​​the floorplan that the connections span. In another example, the order may be a latency-based communication policy configured to measure the delay of arrival of packets to their destination and implement more sensitive connections with higher priority. It is within the scope of the present invention that the synthesis order is an input to a method for deterministic and incremental physically-aware NoC topology synthesis.

[0011] A system configured to automatically generate or synthesize a deadlock-free NoC from a specification includes a floorplan, which is a physical layout of a chip; technical parameters, including but not limited to wiring delays and / or logic density; floorplan areas, including but not limited to module and / or clock restrictions; clock domain crossings (CDCs), which are crossings of signals in a synchronous digital circuit from a first clock domain to a second clock domain; performance requirements; and components having configurations and positions on the floorplan, connectivity requirements between first components and second components, and communication policies between the first components and second components.

[0012] A method for transforming an existing deadlock-free network-on-chip (NoC) configuration, the existing deadlock-free network-on-chip configuration including a plurality of existing physical segments and a set of existing turns that are allowable between the segments, the plurality of existing physical segments and the set of existing turns forming a plurality of existing routes. The method includes generating a new NoC configuration by generating and / or merging at least a first new connection into the existing deadlock-free network-on-chip configuration, the first new connection having a source and a destination, the generating creating a first new deadlock-free route from the source to the destination, such that the new network-on-chip configuration is deadlock-free, and the generating of the first new deadlock-free route from the source to the destination preserves the existing route.

[0013] The generation includes, for each existing route, converting the route into segments and turns; identifying one or more new connections to be combined, where each of the multiple new connections has an undefined route, a source and a destination associated therewith, the one or more new connections being identified along with a combination order; and, for each of the one or more new connections, identifying multiple possible routes from the source to the destination for the new connection according to the sorting.

[0014] The possible routes include one or more of: a new ingress segment connecting the source to an existing deadlock-free NoC configuration; a new egress segment connecting the existing deadlock-free network-on-chip configuration to the destination; one or more new interior segments connecting existing segments of the existing deadlock-free network-on-chip configuration, whereby the one or more new interior segments connect the source to the destination, whereby the new interior segments create a cyclic dependency between the segments, whereby it is not considered whether a deadlock will occur; and only existing segments.

[0015] Filtering a plurality of possible routes based on one or more criteria, including: a communication policy criterion based on an acceptable latency of the route from the source to the destination of the new connection; any of a plurality of user-defined criteria; selecting one of a plurality of possible composite paths; and / or compositing the selected possible route into an existing deadlock-free network-on-chip configuration.

[0016] According to one or more embodiments of the present invention, the first new deadlock-free route includes at least one of an existing physical segment and a new physical segment.

[0017] According to one or more embodiments of the invention, generating a first new deadlock-free route from a source to a destination preserves all existing routes.

[0018] According to one or more embodiments of the present invention, the generation of new deadlock-free routes is repeated incrementally.

[0019] According to one or more embodiments of the present invention, identifying a composition order includes sorting the one or more new connections according to a heuristic.

[0020] In accordance with one or more embodiments of the present invention, at least some of the existing segments are physically unchanged.

[0021] According to one or more embodiments of the invention, at least some of the endpoints of the existing segments are switches. Switches are physically immutable.

[0022] In accordance with one or more embodiments of the present invention, any component is logically mutable, causing at least one existing component to reconfigure in response to a new resulting topology.

[0023] According to one or more embodiments of the present invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that maximizes use of an existing deadlock-free network-on-chip configuration, where the existing segments are left physically unchanged except for the ingress and egress segments, the switches are left physically unchanged, and at least one network element is left logically unchanged.

[0024] According to one or more embodiments of the present invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that minimizes a latency of the route.

[0025] According to one or more embodiments of the present invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that maximizes use of existing deadlock-free network-on-chip configurations, where existing segments are left physically unchanged, switches are enabled to have new connections, and existing network elements are left logically unchanged, including keeping clock frequencies and other attributes unchanged.

[0026] According to one or more embodiments of the invention, selecting one of multiple possible paths for synthesis includes selecting while existing segments are not physically altered, switches are allowed to have new connections, and existing network elements are reconfigurable.

[0027] A method for incremental synthesis and transformation of deadlock-free network-on-chip topologies includes receiving an input that is a network topology, the network topology being transformed into an existing segment; reusing the existing segment in a new route, the existing segment being formed by a path between a first node and a second node; recursively splitting the existing segment at any geographic point along the path between the first node and the second node to form a split segment; in response to the split, synthesizing a new route by adding a new segment and a new turn to the split segment; and generating a deadlock-free network-on-chip topology by routing packets from turns of the existing segment to the new segment, thereby avoiding deadlocks in the network.

[0028] According to one or more embodiments of the present invention, identifying a composition order includes sorting the one or more new connections according to a heuristic.

[0029] In accordance with one or more embodiments of the present invention, at least some of the existing segments are physically unchanged.

[0030] According to one or more embodiments of the invention, at least some of the endpoints of the existing segments are switches. Switches are physically immutable.

[0031] In accordance with one or more embodiments of the present invention, any component is logically mutable, causing at least one existing component to reconfigure in response to a new resulting topology.

[0032] A non-transitory computer-readable medium for storing code that, when executed by one or more processors, causes the processor to receive an input topology of a network-on-chip (NoC) and determine source-destination pairs and at least one existing connection to be selected for synthesis; transfer the source-destination pairs to a pair of segments; transfer the at least one existing connection to a pair of existing segments; determine whether the NoC is deadlock-free; in response to determining that the NoC is deadlock-free, extract segment pairs that do not have a defined route and sort them using a heuristic; input the segment pairs and the existing segment pairs to a configuration searcher, the configuration searcher using a communication policy to select source-destination pairs and at least one existing connection to be selected for synthesis. determining a configuration for routing from a source to a destination of a destination pair, the communication policy being configured to receive user-defined parameters associated with the source-destination pair, the communication policy being configured to communicate with a configuration filtering module being configured to output eligible configurations; selecting a final configuration to be implemented to connect the source-destination pair using the configuration selection module; splitting an existing segment pair that needs to be connected to the segment pair at a point indicated by the final configuration; creating a new segment indicated by the final configuration; activating a corresponding turn that connects the existing segment pair to the segment pair; and calculating a route from the source to the destination of the source-destination pair. [Brief description of the drawings]

[0033] [Figure 1A] 1 is a logical diagram of a network-on-chip (NoC), including the various elements that make up the NoC. [Figure 1B] FIG. 1 is a diagram showing a NoC with elements arranged on a network floorplan. [Figure 2A] FIG. 1 illustrates a method for generating a NoC description based on a set of constraints according to various aspects and embodiments of the present invention. [Figure 2B] FIG. 2 is a block diagram of a NoC synthesis tool in accordance with various aspects and embodiments of the present invention. [Diagram 3] FIG. 2 is a graphical representation of a chip floorplan having occlusion regions and locations of interfaces with a NoC in accordance with various aspects and embodiments of the present invention. [Figure 4] FIG. 2 illustrates a connectivity table for a NoC according to various aspects and embodiments of the present invention. [Diagram 5] FIG. 1 illustrates a scenario table with throughput definitions for read and write transactions in accordance with various aspects and embodiments of the present invention. [Figure 6] FIG. 1 illustrates the creation of a network with three traffic classes in accordance with various aspects and embodiments of the present invention. [Figure 7] FIG. 7 illustrates a decomposition of the network of FIG. 6 using mergers and splitters, in accordance with various aspects and embodiments of the present invention. [Figure 8] FIG. 7 illustrates a roadmap in a floorplan of one master of the network of FIG. 6, in accordance with various aspects and embodiments of the present invention. [Figure 9] FIG. 7 illustrates a roadmap in a floorplan of one slave of the network of FIG. 6, in accordance with various aspects and embodiments of the present invention. [Figure 10] FIG. 9 illustrates the decomposition of a main node splitter into a cascade of splitters physically distributed along the roadmap of FIG. 8 in accordance with various aspects and embodiments of the present invention. [Figure 11] FIG. 10 illustrates the decomposition of a main node merge into a cascade of physically distributed merges along the roadmap of FIG. 9 in accordance with various aspects and embodiments of the present invention. [Figure 12] FIG. 2 illustrates an example of two closely merged nodes in accordance with various aspects and embodiments of the present invention. [Figure 13] FIG. 2 illustrates a NoC topology on a floorplan having a deadlock-free network of segments and turns in accordance with various aspects and embodiments of the present invention. [Figure 14A] FIG. 2 illustrates a NoC topology on a floorplan having partitioned segments S to D in accordance with various aspects and embodiments of the present invention. [Figure 14B] FIG. 1 illustrates a NoC topology on a floorplan with a split segment S-D updated to use two new subsegments S-N and N-D in accordance with various aspects and embodiments of the present invention. [Figure 14C] FIG. 2 illustrates a NoC topology on a floorplan having sub-segments N and S that are merged into a split segment in accordance with various aspects and embodiments of the present invention. [Figure 14D] FIG. 2 illustrates a NoC topology on a floorplan having a sub-segment represented by a channel between node N and node S that is branched into a split segment in accordance with various aspects and embodiments of the present invention. [Figure 15] 1 is a flowchart illustrating a method for single-connection NoC topology synthesis processing in accordance with various aspects and embodiments of the present invention. [Figure 16A] 1 illustrates a NoC topology on a floorplan having a requirement to connect node S to node D in accordance with various aspects and embodiments of the present invention. [Figure 16B] FIG. 1 illustrates a NoC topology on a floorplan with incremental synthesis results of an S to D routing configuration with a new ingress segment, a new internal segment, and an existing egress segment in accordance with various aspects and embodiments of the present invention. [Figure 17A] FIG. 17 illustrates a NoC topology on a floorplan having a communication policy 1700 that optimizes wire length with best effort performance, in accordance with various aspects and embodiments of the present invention. [Figure 17B] FIG. 17 illustrates a NoC topology on a floorplan having a communication policy 1710 for low latency communication in accordance with various aspects and embodiments of the present invention. [Figure 18A] FIG. 18 illustrates an incremental combining mode 1800 for initial setup of a segment connected from node S to node D, in accordance with various aspects and embodiments of the present invention. [Figure 18B] FIG. 18 illustrates an incremental compositing mode 1810 for physical invariance of segments with minimally changed parameters, in accordance with various aspects and embodiments of the present invention. [Figure 18C] FIG. 18 illustrates an incremental synthesis mode 1820 for logical invariance of segments with parameters that optimize topology and preserve configuration, in accordance with various aspects and embodiments of the present invention. [Figure 18D] FIG. 18 illustrates an incremental combining mode 1830 for network element variability with topology optimization and configuration adaptation parameters in accordance with various aspects and embodiments of the present invention. [Figure 19] FIG. 1 illustrates a process of NoC synthesis based on a mesh custom sub-network description in accordance with various aspects and embodiments of the present invention. [Figure 20A] FIG. 1 illustrates a floorplan in which a tool can use a custom sub-network description, in accordance with various aspects and embodiments of the present invention. [Figure 20B] FIG. 20B illustrates the floorplan of FIG. 20A using a custom sub-network description, in accordance with various aspects and embodiments of the present invention. [Figure 21] FIG. 1 illustrates a process for incremental generation and synthesis of NoCs using custom sub-network descriptions in accordance with various aspects and embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Detailed Description Below, various examples of the present technology are described that illustrate various aspects and embodiments of the present invention. In general, the examples can use any combination of the described aspects. All statements herein that recite principles, aspects, and embodiments, as well as specific examples thereof, are intended to encompass both their structural and functional equivalents. Moreover, such equivalents are intended to include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0035] It should be noted that, as used herein, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Throughout this specification, reference to "one aspect," "aspect," "particular aspect," "various aspects," or similar language means that the particular aspect, feature, structure, or characteristic described in connection with any embodiment is included in at least one embodiment of the invention.

[0036] Throughout this specification, the appearance of the phrases "in one or more embodiments," "in one embodiment," "in at least one embodiment," "in an embodiment," "in a particular embodiment," and similar language may, but do not necessarily, all refer to the same or similar embodiments. Furthermore, the aspects and embodiments of the invention described herein are merely exemplary and should not be construed as limiting the scope or spirit of the invention as understood by those of ordinary skill in the art. The disclosed invention may be effectively made or used in any embodiment, including any novel aspects described herein. All statements herein reciting principles, aspects, and embodiments of the invention are intended to encompass both structural and functional equivalents thereof. Such equivalents are intended to include both currently known equivalents and equivalents developed in the future.

[0037] As used herein, "master" and "initiator" refer to similar intellectual property (IP) modules or units, and these terms are used interchangeably within the scope and embodiments of the present invention. As used herein, "slave" and "target" refer to similar IP modules or units, and these terms are used interchangeably within the scope and embodiments of the present invention. As used herein, a transaction may be a request transaction or a response transaction. Examples of request transactions include write requests and read requests.

[0038] As used herein, a node is defined as a distribution point and / or a communication endpoint that can create, receive, and / or transmit information over a communication path or channel. A node may refer to any one of a switch, a splitter, a merge, a buffer, and an adapter. As used herein, splitters and merges are switches, but not all switches are splitters or merges. As used herein, and in accordance with various aspects and embodiments of the invention, the term "splitter" refers to a switch with a single ingress port and multiple egress ports. As used herein, and in accordance with various aspects and embodiments of the invention, the term "merge" refers to a switch with a single egress port and multiple ingress ports.

[0039] 1A, a network-on-chip (NoC) 100 is shown according to various aspects and embodiments of the present invention. The NoC 100 is an example of a network. According to various aspects and embodiments of the present invention, the network includes a set of nodes and a set of edges, each of which has a model, and can be used in a synthesis center to perform and implement transformations on the network and converge to the best solution that meets the specified requirements. The NoC 100 uses basic network functions that include nodes and endpoints and are assembled, such as network interface units (NIUs) 102, 104, 106, 108, 110, 112, 130, 132, and 134, nodes / switches 114, 116, 118, 120, and 122; adapters, such as adapter 126; buffers, such as buffer 124. The NoC basic network functions use an internal transport protocol specific to the NoC 100 to communicate with each other, typically based on the transmission of packets. The NIU translates the protocols used by an attached system-on-chip (SoC) unit (not shown) to the transport protocols used within the NoC 100. The switches route traffic flows between sources and destinations. Buffers 124 are used to store packets to insert pipeline elements to span long distances or to handle rate adaptation between high speed transmitters and low speed receivers (or vice versa). Adapters 126 handle various conversions between data widths, clock domains, and power domains.

[0040] 1B, NoC 150 is shown having various elements such as NIUs, switches, and occlusion regions in a floorplan. NoC 150 includes various connection elements through various switches. According to one aspect of the invention, a set of constraints is used as input to a tool, which will be described in more detail below. According to some aspects of the invention, the tool executes a set of sub-steps to produce a description (synthesis) of the resulting NoC, such as NoC 150, with its configured elements and the location of each element on the floorplan. The generated description is used to actually implement the NoC hardware, using the physical information produced to provide guidance to the back-end implementation flow.

[0041] 2A, according to some aspects of the present invention, a set of constraints (210, 212, 214, 216, and scenarios) are provided to a synthesis tool 220. According to some embodiments and aspects of the present invention, the capabilities and capabilities of the tool 220 may include third-party ASIC implementation tools such as logic synthesis, place and route back-end tools. According to some aspects and embodiments of the present invention, the tool 220 includes machine learning models that aid in the design and automate the synthesis or generation process. A designer or user constructs a set of constraints that are provided to the tool 220. The constraints are captured in a machine-readable format, such as a computer file that uses a defined format to capture information that is understood and processed by the tool. According to one aspect of the present invention, the format is XML. According to another aspect of the present invention, the format is JSON. The scope of the present invention is not limited by the particular format used.

[0042] 2B, the tool reads a file containing a description of the constraints and executes a synthesis process. According to some aspects of the invention, the synthesis process is divided into multiple steps. A sequencer 250 is responsible for executing each step of the process. According to some aspects of the invention, a set of steps are executed by the sequencer 250 of the tool 220 in light of the constraints indicated by the user / designer. The scope of the invention is not limited by the number and type of steps that the sequencer 250 may call and execute.

[0043] Referring again to FIG. 2A in conjunction with FIG. 2B, according to various aspects of the invention, a network designer provides and defines a set of constraints, such as constraints 210, 212, 214, and 216. The sequencer 250 receives various inputs including: an input 251 including a global unified roadmap with connectivity between initiators and targets, including roadmap creation and information between each master and slave; an input 252 including traffic classification and main switch creation; an input 254 including main switch decomposition into merges and splitters; an input 258 including information regarding the physical distribution of splitters and merges in the roadmap; an input 259 including information regarding edge clustering; and an input 260 including information regarding performance-aware node clustering. According to one aspect of the invention, the sequencer 250 also receives an input 262 including information regarding optimization and network restructuring. According to one aspect of the invention, the sequencer 250 receives an input 264 including information regarding routing and justification. According to various aspects and embodiments of the invention, the sequencer 250 uses all the inputs 251-264 to generate the network. According to various aspects and embodiments of the invention, sequencer 250 uses a combination of inputs 251-264 to generate a network.

[0044] According to various aspects of the invention, the input 251 includes input for a global integration roadmap. The global integration roadmap includes an integration model that captures a global physical view of the connectivity of the free space of the floorplan as well as the connectivity between initiators and targets. The global integration roadmap is modeled by a graph of physical nodes and canonical segments that are used to position the nodes (splitters, mergers, switches, adapters) of the network being built. The global integration roadmap is used to anchor the computation. According to various aspects of the invention, the global integration roadmap is persistent, meaning that it is data that the system exports and re-consumes in incremental synthesis and subsequent runs.

[0045] According to some aspects of the invention, the input 259 includes information regarding edge clustering. Edge clustering aims to minimize resources and improve performance objectives through appropriate algorithms and techniques. According to some aspects of the invention, the edge clustering is applied in conjunction and cooperation with the input 260 node clustering. Edge clustering and node clustering can be used in combination by mixing, by being applied simultaneously, or by being applied in sequence. The advantage and goal is to expand the scope of the synthesis and span a larger solution space for the network.

[0046] According to various aspects of the invention, the input 262 includes information regarding the restructuring. The restructuring includes various transformations and capabilities. According to some aspects of the invention, the transformation is logical in that there is a change in the structure of the network. According to some aspects of the invention, the transformation is physical because there is a physical change in the network, such as moving a node to a new location. Other examples of restructuring include splitting a node into smaller nodes; changing parents between nodes; overlapping network subparts to avoid deadlocks and address congestion; physically rerouting links to avoid congested areas or to meet timing constraints.

[0047] 3, a floorplan 300 of a chip on which a NoC is implemented is shown, having locations of various initiator and target interfaces in accordance with various aspects of the present invention. Physical constraints 210 provide physical information for the design, including the size of the chip on which the NoC is implemented; various block areas on the floorplan, which are rectangles representing areas of the chip where NoC logic cannot exist or be placed; free space, which is areas of the chip where NoC logic can exist and is defined by areas not covered by occlusion; and locations of interfaces between SoC units and the NoC, which are locations of initiator and target interfaces such as NIUs.

[0048] According to various aspects of the invention, further constraints may include clock domain extensions and also provide power domain constraints 212. Domain constraints 212 include areas of the chip where logic belonging to a particular domain is allowed to be placed.

[0049] According to various aspects of the present invention, functionality of a logic library used to implement a NoC is provided, including the size of a reference logic gate and the time it takes a signal to cover a distance of 1 mm.

[0050] Referring again to FIG. 2A, in accordance with various aspects of the present invention, an SoC includes multiple clock domains and multiple power domains. A clock domain is defined by all logic fed by a given clock input. The clock input is characterized by its most critical parameter, the frequency of the clock. A power domain is defined by all logic powered from the same power supply. In accordance with various aspects of the present invention, the power supplies are gated, thus power domains can be turned on or off or isolated from other power domains. Thus, the designer provides a set of clock domain and power domain constraints 212 as part of the initial design.

[0051] According to various aspects of the invention, initiators and targets are communicatively connected to the NoC. Initiators are units that send requests, typically read and write commands. Targets are units that serve or respond to requests, typically read and write commands. Each initiator is attached or connected to the NoC via an NIU. An NIU attached to an initiator is called an Initiator Network Interface Unit (INIU). Furthermore, each target is attached to the NoC via an NIU. An NIU attached to a target is called a Target Network Interface Unit (TNIU). The main function of the NoC is to transport each request from an initiator to a desired destination target, and if the request requests or requires a response, the NoC transports each target's response to the corresponding requesting initiator. Initiators and targets have many different parameters that characterize them. According to various aspects of the invention, for each initiator and target, a clock domain and a power domain to which they belong are defined. The width of the data buses they use to send writes and receive read payloads is in bits. In accordance with various aspects of the invention, the width of the data buses for the connections (communication paths to and from the target) used to send write requests and receive write responses are also defined. Additionally, the clock and power domain definitions are references to the aforementioned clock and power domains present in the SoC as described herein.

[0052] 2A and 2B, and also with reference to FIG. 4, a connectivity table 400 is shown. According to various aspects of the present invention, the table 400 allows traffic to be defined by classification. The tool allows the use of a traffic class label for each connection between an initiator and a target. As shown in the table 400, there are three traffic classes: L1, L2, and L3. The traffic class labels are any labels selected by the user or designer. Any number of labels can be defined, and the scope of the present invention is not limited by the number of labels. Each label represents an independent network resource need. Each label is given a separate sub-network by the present invention, which can be physically distinct or use a virtual network if supported by the underlying NoC technology.

[0053] According to various aspects of the invention, an initiator does not need to be able to send requests to all targets or slaves connected to the NoC. The exact definition of targets that can receive requests from an initiator is outlined or described in a connectivity table, such as table 400. The connectivity and traffic class labeling information can be represented as a matrix. Each master has a row and each slave has a column. If a master must be able to send traffic to a slave, then a traffic class label must be present at the intersection between the master row and the slave column. If no label is present at the intersection, the tool does not require connectivity between that master and that slave. For example, Master 1 (M1) is in communication with Slave 1 (S1) using a defined label 1 (L1), but M1 does not communicate with S2, and therefore there is no label at the intersection of M1 and S2. According to various aspects of the invention, the actual format used to represent connectivity can vary, so long as each pair of initiator-slave combinations has a precise definition of its traffic class, or no classification label in the absence of connectivity.

[0054] Referring now to FIG. 5, a table 500 is shown according to various aspects of the present invention, including various scenarios of read (RD) and write (WR) transactions (shown in FIG. 2A). Table 500 includes information provided to a tool defining various throughput rates. The scenarios define the expected performance in terms of throughput of data between a master and a slave. Each scenario describes the expected required read bandwidth and the expected required write bandwidth between each initiator and each target. The throughput is defined in bytes per second (B / s). A typical SoC has multiple operating modes. As an example, an SoC for a smartphone may have a gaming operating mode, an audio call operating mode, an idle operating mode, etc. These define scenarios that depend on different throughput rates. Thus, the set of scenarios represents the different operating modes that the SoC supports, and correspondingly, the expected NoC minimum performance in terms of throughput between the master and the slave.

[0055] A scenario can be represented as two matrices, one defining the read throughput and one defining the write throughput. According to various aspects of the invention, the read throughput requirement is used to size the response network that handles data returning from the slave to the master. The write throughput requirement is used to size the request network that is data moving from the master to the slave, according to various aspects of the invention. An example of throughput requirements for various scenarios according to various aspects of the invention is shown in table 500. The actual format used to represent the scenarios can vary as long as each (master, slave) pair has a precise definition of the minimum throughput required for reads and writes. In table 500, a read transaction from M1 to S1 has a minimum performance throughput of 100MB / s. In table 500, a write transaction from M1 to S1 has a minimum throughput of 50MB / s.

[0056] According to some aspects of the invention, no tool scenario is defined, in which case the tool optimizes the NoC synthesis process for physical cost, such as lowest gate cost and / or lowest wiring cost.

[0057] 6 in conjunction with FIG 2B, an initial network 600 is created in accordance with various aspects of the present invention. Network 600 implements a connectivity matrix having the following defined parameters or components:

[0058] One Network Interface Unit per master, One Network Interface Unit per slave, One switch is created for each defined traffic class, called the main switch for the class. One switch after each initiator / master NIU that splits the traffic to the different main switches that this master needs to reach; One switch in front of each target / slave NIU that merges traffic from the different main switches sending traffic to that target.

[0059] The data width of each switch and the clock domain it belongs to are calculated using the data width of each attached interface and their clock domains as input to the tool. According to various aspects of the invention, each step of transforming a network that is part of a NoC also performs a calculation of the data width and clock domain of the newly created network element.

[0060] 7 and 2B, the network 600 of FIG. 6 is shown and a tool process transforms the network 600 according to various aspects of the invention. The sequencer 250 has an input 254 representing a main switch decomposition into merges and splitters. The tool decomposes each main switch of the network 600 into an equivalent implementation with splitters and merges. According to various aspects of the invention, some switches have a single ingress port and multiple egress ports. According to various aspects of the invention, some switches have multiple ingress ports and a single egress port. Each main switch ingress port is connected to a splitter and each main switch egress port is connected to a merge. For the main switches, the splitters and merges are connected to each other according to the connectivity table.

[0061] 8, a floorplan 800 according to various aspects of the present invention is shown. The sequencer 250 has an input 256 representing the creation of a roadmap between each master and slave. The floorplan 800 includes physical paths 802 calculated between a master interface (M0) on the floorplan and each of its connected slaves, e.g., slave S0, slave S1, slave S2, and slave S3. The paths 802 are referred to as the splitter roadmap of master M0. Although not shown, every master has a splitter roadmap. The tool uses any suitable algorithm to find paths between a source point and multiple destination points, including algorithms that minimize the length of the paths.

[0062] 9, the floor plan 800 has calculated physical paths 902 between the slave interfaces of slave S0 and each of its connected masters on the floor plan. The paths 902 are the merged roadmap of slave S0. As is evident, every slave has a merged roadmap. The tool uses any suitable algorithm to find paths between multiple source and destination points, including algorithms that minimize the path length. In accordance with various aspects of the present invention, the tool transforms the network to maintain its functionality and add location information to the network elements.

[0063] 10, a floorplan 800 having a path 1002 according to various aspects of the present invention is shown. The sequencer 250 has an input 258 that provides the physical distribution of splitters and merges on the roadmap. Using this tool, each switch is decomposed into merges and splitters. Using the tool, each splitter in the main switch is further decomposed into a cascade of splitters, and each splitter in the cascade is placed at a branch point on the splitter roadmap of the attached master. A branch point on the roadmap is defined by the fact that a path is split into two or more branches.

[0064] 11, a floorplan 800 with a path 1102 according to various aspects of the invention is shown. Using the tool, each switch of each merge in the main switch, the merge is further decomposed into a cascade of merges, and each merge in the cascade is placed at a branch point of the attached slave's merge roadmap. A branch point of the roadmap is defined by the fact that the path has been split into two or more branches. The process of decomposing a splitter in a cascade of splitters maintains the original splitter functionality, since the number of inputs to the cascade is still one, and the number of outputs of the cascade is identical to the number of outputs of the original splitter. The process of decomposing a merge in a cascade of merges maintains the original merge functionality, since the number of outputs of the cascade is still one, and the number of inputs to the cascade is identical to the number of inputs to the original merge. According to various aspects of the invention, the effect of this process is to obtain a set of basic switches, represented by merges and splitters, physically located near where the actual connections between the switches are required.

[0065] According to various aspects of the invention, the tool transforms the network to reduce the number of wires used between achievable switches while maintaining the performance defined in the scenario, which is a set of required minimum throughputs between masters and slaves. According to various aspects of the invention, switches are clustered for performance aware switching, and mergers and splitters distributed on the roadmap are treated like regular switches.

[0066] According to one aspect of the invention, the tool uses an iterative process to merge switches under conditions where performance is still met until no further switch merging can occur. The tool uses a process that is described as follows.

[0067] 1) Further switch fusion is not possible, but do the following: a) Select a candidate switch to merge with one of its neighbors. The selection process ensures that all switches in the network are eventually candidates.

[0068] b) Once a candidate is selected, search for neighbors to fuse. The neighbor criterion is based on the evaluation of a cost function. The cost function shall return the "best" switch to fuse with the candidate. The definition of "best" is implementation dependent, but the cost function shall be such that the potential fusion of two switches maximizes the gain in terms of at least one metric, including wire length, logic area, power, and performance.

[0069] c) Test whether the performance scenarios still meet all the minimum throughput requirements if a merge occurs. If not, these two switches cannot be merged. The process performed by the tool explores another neighbor until no more neighbors can be found (in which case all switches are left as is) or until one neighbor is found that can be merged with the candidate without violating the minimum throughput requirements of all scenarios (in which case the network is modified by merging the candidate switch with its neighbor).

[0070] According to various aspects of the invention, a process can prevent a switch from growing beyond a certain size (maximum number of ingress ports, maximum number of egress ports). If the combined switch exceeds a set threshold, a merge is prevented.

[0071] Referring now to FIG. 12, a candidate switch SW3 is shown next to switch SW4 for merging according to various aspects of the present invention. A sequencer 250 has an input 260 that provides performance-aware switching clustering. The tool executes a process to merge two switches. When the switches are merged, the wires that were coming out of different switches are simplified to one wire from each connected switch to the combined switch. According to various aspects of the present invention, switches SW3 and SW4 are merged. The connections between SW1, SW4, and SW3 are combined and replaced with a single connection between SW1 and SW3_4. Thus, long connections between distant switches are eliminated and reduced to a minimum, while connections between close switches are eliminated and made inside the switches themselves.

[0072] 2B, inputs 262 to sequencer 250 include various optimizations that may be performed to further reduce the number of wires used by the network, the area of ​​the network elements, and the power consumed by the network elements. Examples of such optimizations include finding links that are not being used and can be removed or traffic can be rerouted; reducing the width of a link if it is wider than required for the scenario; and performing wire length optimization by finding the optimal placement of all switch elements that minimizes the total wire length of the network, where the total wire length of the network is the sum of the distance spanned by each connection between network elements multiplied by the width of that connection.

[0073] 2B, inputs 264 to sequencer 250 include fabricating a legal NoC by modifying the location of network elements such that they fit into the allocated free space, do not overlap, and are within the limitations of corresponding clock and power domains. According to various aspects of the invention, the area occupied on the die by each network element is calculated using information provided regarding the capabilities of the technology, such as the area of ​​a reference logic gate. Each element is then tested for the correctness of its placement (there is enough free space for the element and other elements do not overlap). If the test fails, the element is moved until a suitable location is found where the test passes.

[0074] format 13, a floorplan 1300 illustrates a deadlock-free NoC that may be represented in terms of multiple segments and turns. A segment represents a directed channel between two components, e.g., “A” 1311 and “B” 1301, “B” 1301 and “C” 1302, “C” 1302 and D 1303, and / or D 1303 and “A” 1311. A first segment 1304 holds the physical path in the floorplan between “A” 1311 and “B” 1301, a second segment 1305 holds the physical path in the floorplan between “B” 1301 and “C” 1302, a third segment 1306 holds the physical path in the floorplan between “C” 1302 and D 1303, and a fourth segment 1307 holds the physical path in the floorplan between D 1303 and “A” 1311, which is represented by physical coordinates (x i , y i It is within the scope of the present invention that a segment may have one or more associated cost metrics that may be utilized during synthesis and / or generation to track the cost of a particular routine.

[0075] The turns, which are pairs of segments, may be utilized to avoid deadlocks in the network. Considering the allowed turns 1308, 1309, and 1310, the network remains deadlock-free as long as there are no cycles between the segments. According to another aspect or embodiment of the present invention, cycles may exist between nodes. Turns have dependencies between segments, which is the basic mechanism that ensures that the network is deadlock-free. It is within the scope of the present invention that cycles exist between nodes in order to reuse wiring without causing deadlocks, so that only necessary channels are allocated to prevent node cycles. As a result, this eliminates unnecessary channels and reduces the associated wiring costs associated therewith.

[0076] Referring again to FIG. 13, the presence of a first turn 1308 from the first segment 1304 to the second segment 1305 indicates that a packet may be routed from the first segment 1304 to the second segment 1305. The presence of a second turn 1309 from the second segment 1305 to the third segment 1306 indicates that a packet may be routed from the second segment 1305 to the third segment 1306. The presence of a third turn 1310 from the third segment 1306 to the fourth segment 1307 indicates that a packet may be routed from the third segment 1306 to the fourth segment 1307. With respect to segment division, the segments "S1" to "S2" may be divided into any point (x i , y i ), which can result in two new segments. Since there is no turn (D,A) that approaches (A,B), this network is deadlock-free.

[0077] 14A-14D, an embodiment of segment splitting on a NoC 1400 is shown. A segment 1403 (FIG. 14A) is defined by node "A" 1401 to node "B" 1402. The segment 1403 may be split 1404 (FIG. 14A) at any point (xi, yi) of its physical route into a new first segment 1409A (FIG. 14B-14D) and a new second segment 1409B (FIG. 14B-14D). FIGS. 14B-14D best show the result of this split 1404 (FIG. 14A) where a newly created node S 1408 (FIG. 14B-14D) is formed. A first turn 1405, a second turn 1406 (FIG. 14B-14D), and a third turn 1407 are shown.

[0078] FIG. 14B shows a segment split of a NoC topology with split segment "A" 1401-"B" 1402 updated to use two new subsegments "A" 1401-S1408 and S1408-"B" 1402. The newly created node S1408 is a new switch in the NoC. The set of turns that contain the split segment is updated to use the two new subsegments. A new turn 1406 is added while maintaining turn 1407.

[0079] Because the split segment resulted in a subsegment with a variable route, the split segment is no longer considered "as is". This recursive representation is essential for incrementality, as it ensures that a segment that is part of an existing route and may need to be split can still be recovered as a series of subsegments when reconstructing the existing route. Splitting a segment allows it to be connected to a new segment, which results in a new set of turns.

[0080] FIG. 14C shows a new segment 1411, represented by the channel between node N 1410 and node S 1408, which is merged into the split segment resulting in a new turn 1412.

[0081] 14D shows that a new segment 1413, represented by the channel between node N 1410 and node S 1408, is branched into a split segment resulting in a new turn 1414. The added node N 1410 may include, but is not limited to, an IP block and / or an initiator.

[0082] process According to one aspect and embodiment of the present invention, the system executes a generation and synthesis process, where all existing network routes are converted into segments and turns. In one embodiment, the entire NoC is described as a set of at least one segment, defined by the physical paths existing between two nodes (S, D), for example. According to various aspects and embodiments of the present invention, if the network is not deadlock-free, the system provides and returns a "fail" notification to the user. This is because, according to one or more embodiments of the present invention, the network or NoC must first be deadlock-free. The system also extracts a set of connections that do not have defined routes and / or connections that need to be synthesized. It sorts the extracted set of connections considering heuristics. According to various aspects and embodiments of the present invention, for each connection source S to destination D, the single connection synthesis process includes using a configuration explorer, a configuration filtering module, a configuration selection module, split, create and route computing. It configures each of the newly created components, switches and links such that the bandwidth requirements are met by assigning clock domains and data width settings.

[0083] 15' is a flow chart showing a method 1500 for a NoC generator using a topology synthesis process. The input 1503A to be synthesized may be a new connection 1501 and / or the input 1503B may be an existing segment 1502. The new connection 1501 includes creating new components such as switches and / or links, defining a network route from S to D. The existing segment 1502 may be re-represented as at least one segment and / or a pair of segments having at least one turn. The existing network has a set of turns that cannot be changed. When a new segment is added, a turn associated with the newly added segment is also added to complete the route from S to D. The added turn does not create a cycle and / or a deadlock with the existing turns.

[0084] The configuration searcher 1504 receives an input 1503A, which is a new connection 1501, and an input 1503B, which is an existing segment 1502. Since there are multiple ways to connect to segments S to D, the configuration searcher 1504 influences the best configuration based on the communication policy 1506 assigned to each segment. The configuration searcher 1504 searches various ways to connect S to D using a search for legal configurations 1505. The legal configurations 1505 are a list of described parameters. The configuration searcher 1504 is configured to traverse the segment and search and / or consider and analyze at least one configuration of location possibilities to split the segment from a list of meaningful configurations stored in memory. The configuration searcher 1504 may be a configuration with a new entrance segment for connecting S to some segment of the NoC. If S is already connected, it already has an entrance segment. The configuration searcher 1504 may have a configuration with a new exit segment for connecting.

[0085] The cost of a given path is updated at each step according to the communication policy 1506. In one example, depending on whether the communication policy 1506 prioritizes wire length and / or latency, traveling within an existing segment away from the destination may be more or less costly than creating a new segment that reaches the destination directly. It is within the scope of the present invention that established shortest path algorithms explore both concrete segments and identify potential future segments, using cost updates as a way to effectively enforce some communication policies.

[0086] The main configuration search process (configuration searcher 1504) may be designed as a specialized version of common shortest path algorithms, including but not limited to A* and / or Dijkstra. A given step in the shortest path algorithm considers different points that can be reached from the current point. The current point is at least one point along the physical path of an existing segment. The path from the current point to the next point in the current segment is considered.

[0087] In one embodiment, the path may proceed one step along the path of the current segment. In one embodiment, when the end of the path of a segment is reached, the path may proceed to the first point of any path of the next segment, such as a segment that is directly connected to the current segment and about which the current segment can "turn."

[0088] In one embodiment, if the destination is not connected, such as if no exit segment exists, the path may jump directly to the destination point, which corresponds to creating a new exit segment. The new exit segment and / or future exit segments are then added to the configuration.

[0089] In yet another embodiment, a path may jump to any point in any segment as long as no circular dependencies are created, the two segments have compatible communication policies, and the communication policies allow merging, which corresponds to creating a new internal segment that is added to the configuration.

[0090] Referring again to FIG. 15, the configuration filtering module 1507 has a predefined list that includes data including, but not limited to, which configurations are legal, which configurations result in deadlocks, and which configurations are suboptimal. The configuration filtering module 1507 filters the configurations given multiple criteria, including, but not limited to, communication policy 1506 based criteria and / or any custom criteria, and keeps only a subset. In an example of custom criteria, a user, such as a programmer, may base a parameter on low latency defined by a shorter length between routes from S to D. The user may define a maximum length of the path. The configuration filtering module 1507 of the communication policy 1506 removes routes if the length of the path exceeds a user-defined threshold. In another example, the parameter may be based on the use of a minimum number of extra wires. In another example, the parameter may be based on a cost function that prioritizes routes from S to D with the lowest cost. The configuration filtering module 1507 is customizable to user predefined parameters. Users may set their own filters and discard certain types of configurations.

[0091] The first criterion is a communication policy 1506 based criterion. The user may control how new segments are created. A communication policy 1506 is a set of parameters that may be associated with any given connection in the network. The system may have multiple communication policies defined, and each connection may be associated with one communication policy 1506. A communication policy 1506 has parameters and flags. In one example of a flag, low latency is when the connection should be implemented in a manner that minimizes the total path length from the source to the destination. In another example of a flag, enable serialization is when links included in the path from the source to the destination can use serialization to save wiring. Some configurations of a given connection may not be legal with respect to the communication policy 1506 that governs the connection. Eligible configurations 1508 are filtered versions of legal configurations. In one example, if a connection S to D is configured to have a low latency communication policy, restrictions on the total length of the route and the number of hops or components traversed must be applied, and candidate configurations that do not fall within these restrictions are discarded.

[0092] Referring again to FIG. 15, after filtering, the configuration filtering module 1507 outputs eligible configurations 1508. It is desirable to select one eligible configuration, which is performed by the configuration selection module 1509. Selecting the best configuration is accomplished using the configuration selection module 1509, which retains only one final configuration to be implemented as the final composition of connections S to D. The metric used to select the best configuration is configurable and may take into account several parameters, based on the community policy 1506. In one embodiment, the communication policy parameter is the total additional wire length. The length of the additionally created segments creates the wires needed to traverse the route. There is a cost associated with the wiring. A parameter that aims to minimize the total wire length to reduce the cost of the topology would be more desirable. In one embodiment, the communication policy parameter is the total route length. The total length of the route is the sum of the existing segments combined with the newly added segments. This parameter focuses on minimizing latency. In another embodiment, the communication policy parameter is based on the bandwidth distribution. This parameter optimizes performance by focusing on the traffic distribution on the segments and the associated congestion levels.

[0093] Once the best configuration 1510 is selected, the system implements 1511 the best configuration 1510 by splitting the segments involved, creating 1512 new segments and turns, and applying it to the network. It is within the scope of the invention that the best configuration is the final configuration. When a segment is split, it is split with all existing segments that need to be connected to the new segment at the point dictated by the selected configuration. For optimization, if the split point is within a certain distance from one of the segment's endpoints and the endpoint is a switch, the endpoint should be reused for the connection instead of creating a new switch. This can reduce the number of switches created. Creates 1512 the necessary new segments dictated by the selected configuration and actuates the corresponding turns. The newly created segments and turns 1512 are input to a routing tool 1513 that combines with the existing segments and turns 1502 to generate the final path 1514. A route is calculated from S to D taking into account the newly created segments. The route is stored in memory. The routing tool 1513 is routing connections on the geographic floor plan since the segments are defined in terms of geographic paths along the floor plan.

[0094] FIG. 16A shows a NoC topology 1600 on a floorplan having a source (S) 1601 to a destination (D) 1602. When an existing network exists and a change is requested, such as a request to add a new connection from a node at S 1601 to a node at D 1602, incremental synthesis must be performed. IP blocks are an example of a constraint on the floorplan that a route must navigate. Existing nodes are connected to each other. It is desirable to create a route for a new connection in the existing network without having to make changes to the existing structure.

[0095] 16B illustrates a NoC topology 1600 on a floorplan with an incremental synthesis result of routing configurations from S1601 to D1602 with a new ingress segment 1603 having a node at S1601, a nearby node 1606 having a new internal segment 1604, and an egress segment having a node 1605 near D1602, according to various aspects and embodiments of the present invention. The search for legal configurations 1505 is illustrated in the configuration illustrated in FIG. 16B, where an ingress segment 1603 is added if the node is not already connected to the NoC. In one embodiment, the new ingress segment 1603 can connect S1601 to a segment of the NoC. If S1601 is already connected to a segment of the NoC, it already has an ingress segment.

[0096] In the diagram of FIG. 16B, an exit segment 1605 existed because D 1602 was already connected to another node. Thus, if D 1602 is already connected, it already has an exit segment. A new exit segment may be a configuration option to connect some segments of the NoC to D 1602.

[0097] Referring again to FIG. 16B, it is within the scope of the present invention that there are any number of interior segments 1604. According to some aspects and embodiments of the present invention, the tool includes a machine learning model that can propose and generate new segments based on training of the model, which includes feedback from previous design generation. At least one and / or more new interior segments may connect existing segments such that the entrance segment reaches the exit segment. A connection between two existing segments is considered only if it does not create a cyclic dependency between the segments, ensuring that only deadlock-free configurations are considered. The composition may include calculating the network route without creating new switches and / or segments. This is the case when both S and D are connected to the network or NoC and the entrance segment can already reach the exit segment considering only existing turns. It is an important aspect of the present invention that no concrete segments are created in the topology during the exploration phase, including using a machine learning model with feedback capabilities for further training of the model, where configuration may define future segments.

[0098] In one embodiment, the system may pre-set some common communication policies to make the selection easy for the user. Instead of requiring the user to create a communication policy, it is more desirable for the user to select from a list of presets. Connections associated with different communication policies have a composite route that is physically separated. During composition, the configuration filtering module 1507 (FIG. 15) and the configuration selection module 1509 (FIG. 15) output the best configuration 1510 for implementing the route (1511) depending on the communication policy 1506 (FIG. 15).

[0099] FIG. 17A illustrates a NoC topology on a floorplan with a communication policy 1700 that optimizes wire length with best-effort performance, according to various aspects and embodiments of the present invention. FIG. 17A and FIG. 17B illustrate how the same connection can result in different implementations based on the selected communication policy. In the diagram of FIG. 17A, the focus is on connecting node S to node D, and the parameter of wire length is the main criterion for optimization according to various aspects and embodiments of the present invention. A configuration selection module, which may be controlled by a machine learning model, selects the implementation that creates the least amount of extra wiring. It is shown that having a short inlet segment 1703 and one turn 1704 actuated meets the parameter requirements.

[0100] 17B illustrates a NoC topology on a floorplan with a communication policy 1710 of low latency communication in accordance with various aspects and embodiments of the present invention. In this example, there is a preference for a direct connection 1713 between node S 1711 and node D 1712 rather than traversing several switches. One turn 1714 that is activated is near D. This configuration incurs more extra wiring and is more costly, but it is the user-selected path from S to D that has the shortest length.

[0101] The basic method for incrementally synthesizing new connections while reusing existing segments is best illustrated in Figures 1A-20B. This embodiment relies on spitting out existing segments and branching new segments. At the end of the process, only the newly created components, such as clock and / or data width, are configured, while the existing components remain unchanged. Referring again to Figure 15, existing segments 1502 and turns are modified by user control at an incremental level according to various aspects and embodiments of the invention. According to some aspects and embodiments of the invention, existing segments and turns are modified by machine learning models trained for the generation of networks-on-chips. The user (with or without input from the model) utilizes communication policies 1506 to control the creation and selection of new segments in the network as well as modify existing topologies or segments. In one example, reusing existing segments in new routes may not be desirable due to performance considerations or previous optimizations that the user may have performed and that rely on the segments remaining unchanged. If a segment is split, hops may be added to traverse multiple routes, which may not be the desired outcome. As a result, the system defines several incremental levels or modes based on the physical variability of segments, the physical variability of switches, and the logical variability of network elements.When synthesizing a new set of connections in the presence of an existing NoC topology, it is more desirable to capture the user's intent.

[0102] In an alternative embodiment, the incremental synthesis mode allows the user to customize how the existing topology is modified.

[0103] Regarding the physical mutability of a segment, a segment is mutable by default. A segment may be split to branch off a new segment. A user may make a segment immutable, for example if they do not want to add a switch to an existing route.

[0104] Referring to the physical mutability of a switch, a new segment may be connected to an existing endpoint of an immutable segment if the endpoint is a switch. If it is not desired to change the physical size of a switch, the switch may be immutable, so that a new segment cannot be connected to an immutable switch.

[0105] Referring now to logical mutability of network elements, as a default, existing network elements, including but not limited to data width and / or assigned clocks, are not reconfigured by the incremental synthesis process. Only newly created switches and adapters are configured. This may result in inefficient configurations such as insufficient bandwidth and / or too many clock domain crossings. Any component may be marked as logically mutable to allow existing components to be reconfigured into a given new resulting topology. In an example of how preset incremental synthesis modes can be defined within a system based on the aforementioned concepts, three preset modes are described.

[0106] 18A illustrates an incremental synthesis mode 1800 for initial setup of a segment connected from node S 1801 to node D 1802. A high bandwidth segment 1803 and a low bandwidth segment 1804 traverse an existing NoC topology route in accordance with various aspects and embodiments of the invention. During the initial setup, user parameters determine how the existing topology is modified to connect S 1801 to D 1802.

[0107] 18B illustrates an incremental synthesis mode 1810 for physical consistency of segments with minimally changed parameters, in accordance with various aspects and embodiments of the present invention. The segment splits at node 1811 and branches 1812 into a new segment, creating a U-turn in the deadlock-free network to connect S 1801 to D 1802 with minimal changes. The high-bandwidth segment 1803 is unchanged to prevent splitting, and the traversal of the low-bandwidth segment 1804 is routed around the existing NoC topology route.

[0108] It is more desirable to preserve the maximum amount of existing topology. All segments are made physically immutable, except for the ingress and egress segments, because ingress and egress segments are needed to implement new connections. All switches are physically immutable and all network elements are logically immutable. In one example, if one segment, from S1801 to D1802, is marked immutable, it prevents segment splits and facilitates routes around existing segments. As a result, the existing segment remains unchanged.

[0109] FIG. 18C illustrates an incremental synthesis mode 1820 for logical invariance of segments with parameters that have been identified to optimize the topology and preserve the configuration. The low bandwidth 1804 segment is split at 1821, a new segment 1822 is branched, and a new turn is created to connect S 1801 to D 1802. The high bandwidth is not fully utilized because it is connected to a lower bandwidth and the switches cannot be changed according to various aspects and embodiments of the present invention. It would be more desirable for some switches to be changed to adapt. This preset splits existing segments and allows the switches to have new connections for a more optimized topology. As a result, better cost (in terms of resources and wiring usage) by reusing existing elements can be achieved. Existing network elements may be made logically invariant to maintain, for example, clock frequencies, clocks assigned to switches, and / or other attributes that are not changed according to various aspects and embodiments of the present invention.

[0110] FIG. 18D illustrates an incremental synthesis mode 1830 for variability of network elements with parameters to optimize topology and adapt configuration. A segment of high bandwidth 1803 is split at node 1831, a new segment 1832 branches off, and a new turn is created to connect S 1801 to D 1802. The high bandwidth is fully utilized since the switch has been modified according to various aspects and embodiments of the present invention to connect to a higher bandwidth. All segments can be split, switches can be connected to new segments, and / or components can be reconfigured, and a more flexible synthesis process is achieved if reconfiguring them improves the results, e.g., changing the clock improves performance.

[0111] FIG. 19 illustrates the process of NoC 1900 synthesis based on a mesh custom sub-network description according to various aspects and embodiments of the present invention. First, mesh segments are generated and optimally placed physically in the requested space, which may be done using machine learning models trained on topology synthesis and network generation with feedback for further training. Second, new mesh segments that are considered existing segments by the incremental synthesis process are used expediently when appropriate to generate the final route. The result is a topology that mixes automatically generated regular mesh topology with optimally generated or synthesized new segments. In a fully connected system, the network on chip (NoC) 1900 connects each node 1901 to every other node. Regions 1902 are specified for a 3×3 mesh using an XY routing algorithm according to various aspects and embodiments of the present invention. This allows for the identification and selection of regions in the floor plan for placing the 3×3 mesh. As a result of the synthesis process 1903, the NoC 1905 uses the requested mesh segments and the newly synthesized segments. An automatically synthesized local tree 1904, which may be done using a machine learning model, is shown in accordance with various aspects and embodiments of the invention. A mesh is generated and optimally positioned within a specified region 1906 representing a 3x3 mesh.

[0112] According to another aspect of the invention, there is provided an extension of clock and power domains on the floorplan, where each element is tested to ensure that it is located within the boundaries of the specified clock and power domains. If the test fails, the element is moved until a suitable location is found where the test passes. Once a suitable placement is found for each element, each connection between the elements is routed. The routing process finds suitable paths for the set of wires that make the connections between the elements. After routing is done, distance spanning pipeline elements are inserted into the links as necessary using information provided about the capabilities of the technology based on the time it takes a signal to cover a distance of 1 mm.

[0113] According to some aspects and embodiments of the invention, the tool generates one or more computer files describing the generated NoC, the computer files including: A list of network elements and their configuration: data width, clock domain.

[0114] The location of each generated network element on the floor plan. A set of routes through network elements that implement connectivity.

[0115] According to an aspect of the invention, a route is an ordered list of network elements, one for each pair of (initiator, target) and one for each pair of (target, initiator). The route describes how traffic between the pairs flows and through which elements.

[0116] According to various aspects of the invention, tools are used to generate metrics for the generated NoC, such as a histogram of wire length distribution, number of switches, and a histogram of switches by size.

[0117] According to another aspect of the invention, the tool automatically inserts various adapters and buffers into the network. The tool inserts adapters based on the accommodation required between two elements having different data widths, different clock domains and power domains. The tool inserts buffers based on the scenario and the detected rate mismatch.

[0118] 20A and 20B illustrate floorplans for using a custom sub-network description. According to various embodiments and aspects of the invention, the tool can accept new input as part of the synthesis process, such as a custom sub-network description. According to various embodiments and aspects of the invention, a machine learning model of the tool analyzes the description to provide for generation of the NoC. The custom sub-network description describes the sub-network to be generated before the synthesis process begins. The custom sub-network description includes:

[0119] -Geographic Boundary: The rectangular area used to place this network within a floor plan.

[0120] Sub-network type: can be one of several predefined regular network types (mesh, torus, etc.).

[0121] Configuration: This is specific to each sub-network type. For example, for a mesh network, it is defined by the number of rows, the number of columns, and the routing algorithm (e.g., XY, North-Last, etc.).

[0122] Once the custom subnetwork descriptions have been established, a process is performed prior to beginning the synthesis process that involves analyzing or processing each custom subnetwork description as follows.

[0123] 1) According to various embodiments and aspects of the present invention, a subnetwork placement module is used to generate optimal node locations, such as for meshes, given geographic boundaries and type of subnetwork.

[0124] -The entire subnetwork occupies the maximum possible area within the boundary. -Straight line segments do not physically collide with floorplan obstacles.

[0125] -Segment sizes are as uniform as possible. 2) According to various embodiments and aspects of the invention, given a sub-network type, configuration, and previously generated node positions, a tool that may use trained machine learning models for generating networks (e.g., using a Regular Topology Generator) creates: A switch, b. An immutable internal segment; c. the corresponding turn of the routing algorithm, and d. Variable entry and exit segments for entering and leaving a regular sub-network.

[0126] When a new segment of a sub-network is registered, an incremental synthesis process can be invoked to implement the new connections, using the normal sub-network as much as possible.

[0127] Referring again to FIG. 21, a process is shown illustrating how a NoC is synthesized based on a mesh custom sub-network description in accordance with various aspects and embodiments of the present invention. In step 2110, mesh segments are generated and optimally placed physically on the requested space. In step 2112, new mesh segments that are considered by the incremental synthesis process as existing segments are advantageously used whenever appropriate. In step 2114, using the existing segments, the tool generates a final route. The result is a topology that mixes the automatically generated regular mesh topology with the new optimally synthesized segments.

[0128] According to some aspects and embodiments, the tool can be used to ensure that multiple iterations of synthesis are performed for incremental optimization of the NoC, including situations where one constraint provided to the tool is information about a previous run.

[0129] After the software performs the synthesis process, the results are produced in a machine-readable format, such as a computer file, that uses a well-defined format to capture the information. An example of such a format is XML, and another example of such a format is JSON. The scope of the present invention is not limited by any particular format.

[0130] Some aspects of the invention use an incremental approach to network synthesis. This incremental approach is useful in many situations. For example, in some embodiments, the incremental process begins with a specification and a brand new floorplan. These and other embodiments, some of which are discussed above.

[0131] According to some aspects and embodiments, a connection may have a communication policy that specifies, for example, the sensitivity of the connection to latency.

[0132] Certain methods according to various aspects of the present invention may be performed by instructions stored on a non-transitory computer-readable medium. The non-transitory computer-readable medium stores code including instructions that, when executed by one or more processors, cause a system or computer to perform steps of the methods described herein. Non-transitory computer-readable media include rotating magnetic disks, rotating optical disks, flash random access memory (RAM) chips, and other mechanically moving or solid-state storage media. Any type of computer-readable medium is suitable for storing code including instructions according to various examples.

[0133] Although specific examples have been described herein, it should be noted that different combinations of different components from different examples may be possible. Salient features have been presented to better explain the examples. However, it will be apparent that certain features may be added, modified and / or omitted without modifying the functional aspects of these examples as described.

[0134] Various examples are methods that use any or a combination of machine behaviors. The method examples are completed wherever in the world the most configuration steps are performed. For example, according to various aspects and embodiments of the present invention, an IP element or unit includes a processor (e.g., CPU or GPU), random access memory (RAM, e.g., off-chip dynamic RAM or DRAM), a network interface for wired or wireless connections, e.g., Ethernet, Wi-Fi, 3G, 4G long-term evolution (LTE), 5G, and other wireless interface standard radios. The IP may also include various I / O interface devices for various peripheral devices, such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices (such as keyboards and mice, among others), as needed. By executing instructions stored in the RAM device, the processor performs the steps of the methods described herein.

[0135] Some examples are one or more non-transitory computer-readable media configured to store such instructions for the methods described herein. Any machine that holds a non-transitory computer-readable medium containing any of the necessary code may perform the examples. Some examples may be implemented as a physical device such as a semiconductor chip, a hardware description language representation of the logical or functional behavior of such a device, and one or more non-transitory computer-readable media configured to store such a hardware description language representation. The descriptions herein that recite principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as coupled have a possible and operative relationship, either by direct connection or indirectly with one or more other intervening elements.

[0136] Those skilled in the art will recognize many modifications and variations. Modifications and variations include any relevant combination of the disclosed features. The descriptions herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as "coupled" or "communicatively coupled" have an effective relationship that can be achieved by a direct connection or an indirect connection using one or more other intervening elements. An embodiment described herein as "communicating" or "in communication with" another device, module, or element includes any form of communication or link and includes an effective relationship. For example, a communication link can be established using a wired connection, a wireless protocol, a near-field protocol, or RFID.

[0137] To the extent that the terms "including," "includes," "having," "has," "with," or variations thereof are used in any of the detailed description and claims, such terms are intended to be inclusive in the same manner as the term "comprising."

[0138] The scope of the present invention, therefore, is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of the present invention is embodied in the appended claims.

Claims

1. 1. A tool that uses a custom sub-network description to generate a deadlock-free network-on-chip (NoC), the tool, when executed by one or more processors of the tool, comprising: Identifying an area within a floorplan of the NoC; generating a sub-network that is optimally located within said region; generating a configuration for a new NoC by synthesizing the NoC including the sub-network; Using a configuration selection module to select a final configuration to be implemented for the new NoC. A tool comprising a non-transitory computer readable medium for storing code.

2. The tool of claim 1 , comprising a machine learning model trained to generate the final configuration.

3. The tool of claim 2 , wherein the machine learning model receives feedback for further training.

4. The tool of claim 1 , wherein the sub-network is a mesh network segment.

5. The tool of claim 4 , wherein the mesh network segments are optimally positioned with spaces identified within the region.

6. The tool of claim 1 , wherein the regions are selected based on a size of the sub-network.

7. The tool of claim 6 , wherein the sub-network is a mesh network segment.

8. 2. The tool of claim 1, wherein the tool is further adapted to check a location of the sub-network within the region to ensure that the sub-network is within the bounds of a specified clock domain.

9. The tool of claim 1 , wherein the tool is further adapted to check the location of the sub-network within a power domain to ensure that the sub-network is within a boundary of the domain.

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