Semiconductor device

Abstract

To reduce the area of one memory cell in view of the fact that a content addressable memory has many elements in one memory cell and thus the area of one memory cell tends to be large.SOLUTION: Charge can be held with the use of a channel capacitance in a reading transistor (capacitance between a gate electrode and a channel formation region). In other words, the reading transistor also serves as a charge storage transistor. One of a source and a drain of a charge supply transistor is electrically connected to a gate of the reading and charge storage transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technical field relates to a semiconductor device equipped with an associative memory. [Background technology]

[0002] Content Addressable Memory (CAM) can make a match or mismatch decision on a string of information called a data word. It is a memory.

[0003] In an associative memory, for example, a data word such as "10110" is judged to be a match or a mismatch. conduct.

[0004] Associative memories include binary associative memories (BCAM (Binary CAM)), ternary associative memories (TCAM (TCAM)), Examples include virtual memory (TCAM (Ternary CAM)).

[0005] In a binary associative memory, each memory has one of two values, "Low (0)" or "High (1)". It is stored in the resel.

[0006] In a ternary associative memory, "Low (0)", "High (1)", and "X(Don't Ca One of the three values, "re"), is stored in each memory cell of the memory circuit.

[0007] Note that "X (Don't Care)" indicates what value is input during the read operation. This value will be considered a match even if it is changed.

[0008] One example of an associative memory is an associative memory using a capacitive element described in Patent Document 1. be. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2003-272386 A Summary of the Invention [Problem to be solved by the invention]

[0010] Associative memories have a large number of elements in each memory cell, and the area of ​​each memory cell is large. Easy to use.

[0011] Therefore, the object is to reduce the area of ​​one memory cell. [Means for solving the problem]

[0012] The channel capacitance of the readout transistor (the capacitance between the gate electrode and the channel formation region) The charge is maintained using a capacitance (capacity).

[0013] In other words, the read transistor also serves as a charge holding transistor.

[0014] A charge supply transistor is connected to the gate of the readout and charge storage transistor. Either the source or the drain of the transistor is electrically connected.

[0015] Here, the semiconductor used for the readout and charge retention transistor is Therefore, it is preferable to use a semiconductor containing silicon. In order to achieve this, it is preferable that the semiconductor containing silicon has crystallinity.

[0016] On the other hand, if the leakage of the charge supply transistor is large, the read and charge storage transistor The channel capacitance of the transistor must be increased, and the read and charge storage In some cases, it may be necessary to increase the area of ​​the channel formation region of a transistor for use.

[0017] Therefore, an oxide semiconductor is preferably used for the charge supply transistor.

[0018] That is, the oxide semiconductor has a wider band gap than silicon.

[0019] The wider the band gap of the semiconductor used in the transistor, the greater the on-state current of the transistor. The current becomes smaller.

[0020] Therefore, a transistor using an oxide semiconductor at least in a channel formation region has a Compared with transistors using semiconductors containing silicon, the leakage between the source and drain The amount of capacitance (off-state current of the transistor) is extremely small.

[0021] Therefore, an oxide semiconductor is used as a semiconductor for a charge supply transistor. This reduces the area of ​​the channel formation region of the read and charge storage transistor. It is possible.

[0022] If the charge supply transistor leaks a lot, a refresh operation may be required. do.

[0023] However, transistors using oxide semiconductors have extremely low leakage current. By using transistors, the number of refresh operations can be reduced.

[0024] Furthermore, by reducing the number of refresh operations, power consumption can be reduced.

[0025] In other words, by using an oxide semiconductor for a charge supply transistor, This also has the secondary effect of reducing the number of loop operations and reducing power consumption.

[0026] The first wiring includes a first to a fourth transistor and a first to a fourth wiring. One of the source and drain of the first transistor and the source of the third transistor The second wiring is electrically connected to one of the source and drain of the first transistor. one of the source or drain of the first transistor and the source or drain of the fourth transistor The third wiring is electrically connected to the gate of the first transistor. and the gate of the second transistor are electrically connected to the fourth wiring. the other of the source or the drain of the third transistor and the source of the fourth transistor or the other of the drains is electrically connected to the gate of the third transistor. The other of the source and the drain of the first transistor is electrically connected, and the fourth transistor The gate of the first transistor is electrically connected to the other of the source and drain of the second transistor. The first and second transistors are connected to each other, and an oxide semiconductor layer is used as a semiconductor layer of the first and second transistors. The semiconductor layers of the third and fourth transistors are made of a silicon-containing semiconductor. It is possible to provide a semiconductor device characterized in that a conductor layer is used.

[0027] The semiconductor layer of the third transistor and the semiconductor layer of the fourth transistor are common to each other. It is possible to provide a semiconductor device having the above-mentioned features.

[0028] The semiconductor device further includes first to fifth transistors and first to fifth wirings, and the first wiring The line is connected to one of the source or drain of the first transistor and the third transistor. The second wiring is electrically connected to one of the source and drain of the second transistor. one of the source or drain of the first transistor and the source or drain of the fourth transistor The third wiring is electrically connected to one of the drains of the first transistor. The gate of the second transistor is electrically connected to the gate of the third transistor. one of the source and drain of the fifth transistor is electrically connected, The gate of the fifth transistor is electrically connected to the wiring, and the third transistor is The gate of the first transistor is electrically connected to the other of the source and drain of the first transistor. The gate of the fourth transistor is connected to the source or drain of the second transistor. the other of the inputs is electrically connected to the other of the source or drain of the fifth transistor the other of the source or drain of the third transistor and the fourth transistor The other of the source and the drain is electrically connected to the first and second transistors. an oxide semiconductor layer is used as a semiconductor layer of the third to fifth transistors; A semiconductor layer containing silicon is used as the semiconductor layer. A body device can be provided.

[0029] Moreover, the first transistor is provided above the third transistor, The second transistor is provided above the fourth transistor, and the third transistor The semiconductor layer of the first transistor, the semiconductor layer of the fourth transistor, and the semiconductor layer of the fifth transistor In this way, it is possible to provide a semiconductor device in which the semiconductor layer of the second insulating film is shared with the semiconductor layer of the first insulating film.

[0030] a semiconductor layer of the first transistor and a semiconductor layer of the third transistor overlap each other; The semiconductor layer of the second transistor and the semiconductor layer of the fourth transistor overlap each other. It is possible to provide a semiconductor device having the above features.

[0031] One end of the semiconductor layer of the first transistor and one end of the semiconductor layer of the third transistor is electrically connected to the first connection electrode via a first connection electrode, and The end of the fourth transistor is electrically connected to one end of the semiconductor layer of the fourth transistor via a second connection electrode. One end of a semiconductor layer of the first transistor is in contact with the first connection electrode, The other end of the semiconductor layer of the first transistor functions as the gate of the third transistor. One end of the semiconductor layer of the second transistor is in contact with the gate electrode of the second transistor. the other end of the semiconductor layer of the second transistor is in contact with the A gate electrode that functions as a gate is in contact with the first connection electrode, the second connection electrode, and the front The gate electrode of the third transistor and the gate electrode of the fourth transistor are formed in the same process. It is possible to provide a semiconductor device formed by the steps of:

[0032] The first to fourth transistors are included in a memory cell, and the memory cell includes the third transistor. The channel capacitance of the first transistor and the channel capacitance of the second transistor hold charge. It is possible to provide a semiconductor device that performs the above. Effect of the Invention

[0033] By using the channel capacitance of the readout transistor to hold the charge, The area of ​​each memory cell can be reduced.

[0034] The read and charge storage transistors are made of crystalline silicon-containing semiconductors. By using a semiconductor layer and an oxide semiconductor layer for a charge supply transistor, This makes it possible to improve the speed and reduce the area of ​​one memory cell. [Brief description of the drawings]

[0035] [Figure 1] 1 is an example of a semiconductor device. [Diagram 2] 1 is an example of a semiconductor device. [Diagram 3] 1 is an example of a semiconductor device. [Figure 4] 1 is an example of a semiconductor device. [Diagram 5] 1 is an example of a semiconductor device. [Figure 6] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 7] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 8] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 9] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 10] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 11] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 12] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 13] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 14] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 15] 1 illustrates an example of a method for manufacturing a semiconductor device. [Figure 16] Initial characteristics of the sample in Example 1. [Figure 17] BT test results of the sample in Example 1. [Figure 18] BT test results of the sample in Example 1. [Figure 19] Relationship between off-state current and substrate temperature during measurement. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The embodiments will be described in detail with reference to the drawings.

[0037] However, the form and details of the invention may be modified in various ways without departing from the spirit of the invention. This will be readily understood by those skilled in the art.

[0038] Therefore, the scope of the invention should not be construed as being limited to the description of the following embodiments. do not have.

[0039] In the configurations described below, the same parts or parts having similar functions are referred to as the same parts. Reference numerals are used commonly among different drawings, and repeated explanations will be omitted.

[0040] In addition, the following embodiments can be implemented in combination with one another.

[0041] (Embodiment 1) An example of a semiconductor device having an associative memory will be described with reference to FIGS.

[0042] FIG. 1 shows the memory cell in row i and column j of FIG. 2 (b in FIG. 2). ij The figure shows an example of In the figure, i, j, m, and n are natural numbers. Also, i is smaller than m and j is smaller than n.

[0043] In FIG. 1, one memory cell includes a transistor 11, a transistor 12, and a transistor A resistor 21, a transistor 22, a wiring 31, a wiring 32, a wiring 33, and a wiring 34 are arranged. It is being done.

[0044] The transistors 11 and 12 function as charge supply transistors. Yes.

[0045] The transistors 11 and 12 are made of an oxide semiconductor. Since the transistor uses an OSI (semiconductor) The symbols are given as follows.

[0046] The transistor 21 and the transistor 22 are a read transistor and a charge storage transistor. The transistor functions as follows.

[0047] In FIG. 1, transistor 11, transistor 12, transistor 21, and transistor 22 Although n-channel transistors are used, p-channel transistors can be used as necessary. It's fine if you're there.

[0048] In addition, when using a p-channel transistor, the input signal or input voltage may be Just reverse the polarity.

[0049] The wiring 31 and the wiring 32 function as search lines.

[0050] In addition, SL and / SL in the figure represent search lines.

[0051] Also, SL x (x is an arbitrary number), the server located in the xth column of the memory cell This means that it is line SL.

[0052] The wiring 33 functions as a word line.

[0053] In the figure, WL denotes a word line.

[0054] Also, W.L. y (y is an arbitrary number), the word arranged in the memory cell of the yth row This means that it is a WL line.

[0055] The wiring 34 functions as a match line.

[0056] In the figure, ML stands for match line.

[0057] Also, M.L. y (y is an arbitrary number), the map arranged in the memory cell in the yth row This means that it is a Chi line ML.

[0058] The wiring 31 is connected to one of the source and drain of the transistor 11 and the The source or the drain is electrically connected to the first electrode.

[0059] The wiring 32 is connected to one of the source and drain of the transistor 12 and the The source or the drain is electrically connected to the first electrode.

[0060] The wiring 33 electrically connects the gate of the transistor 11 and the gate of the transistor 12. is connected to

[0061] The gate of the transistor 11 and the gate of the transistor 12 are connected to different wirings. The input terminal may be electrically connected to the

[0062] However, the same signal is input to the gate of the transistor 11 and the gate of the transistor 12. In order to achieve this, the gates of the transistors 11 and 12 are connected to a common It is preferable to electrically connect to wiring.

[0063] The wiring 34 is connected to the other of the source and drain of the transistor 21 and the The other of the source and the drain is electrically connected.

[0064] The wiring 31 and the wiring 32 are provided in common to a group of memory cells arranged in the column direction. .

[0065] The wiring 33 and the wiring 34 are provided in common to a group of memory cells arranged in the row direction. .

[0066] The other of the source and drain of the transistor 11 is electrically connected to the gate of the transistor 21. are actively connected.

[0067] The other of the source and drain of the transistor 12 is electrically connected to the gate of the transistor 22. are actively connected.

[0068] In this specification, the term "connected directly" refers to an element that does not affect the operation of a circuit. The state in which the two devices are connected via a signal is called "electrically connected."

[0069] An element that does not affect circuit operation is an element that outputs the signal without changing its contents when the input is a signal. It is an element that outputs the voltage without changing its polarity when the input is a voltage. These include resistors, switches, diodes, etc. An example of a switch is a transistor. When the input is a voltage, it also includes a capacitance element, etc.

[0070] In addition, in FIG. xy ) are arranged in the row and column directions. do.

[0071] In addition, b xy If written as (x, y are arbitrary numbers), it is placed in the xth column and yth row. This means that the memory cell is

[0072] Also, in FIG. 2, a means for precharging each row ("High (1 The transistors through which the input and output of the row are input and output, and a buffer for adjusting the output of each row is provided. It is being done.

[0073] Also, the output G y is input to the judgment circuit, and the judgment circuit outputs G y (``High(1)'' also The match or mismatch is determined depending on whether the value is "Low (0)".

[0074] Here, each operation (write operation, read operation) will be explained.

[0075] The following description will be given taking the operation of the memory cell in row i, column j in FIG. 1 and FIG. 2 as an example. By repeating the same operation in the cells, the write operation and the read operation are performed in all memory cells. A read operation can be performed.

[0076] When a write operation is performed, first, the word line WL i Select the gate of transistor 11. The gate of the transistor 12 is set to an open state (the transistor is in an on state).

[0077] And the search line SL j and search line / SL j "High(1)" or "Low(0 )" and enter the voltage corresponding to "

[0078] Here, in the case of a ternary content addressable memory (TCAM), the search line SL j Input S j and search line / SL j Input / S j The combination of j is "High(1)" and / S j "Low The first state of "(0)", S j is "Low(0)" and / S j The second state of "High(1)" State, and Sj is "Low(0)" and / S j is the third state, "Low (0)".

[0079] Note that "High(1)" is the power supply voltage Vdd.

[0080] Also, "Low(0)" is the low power supply voltage Vss or the ground potential GND.

[0081] The low power supply voltage Vss is a voltage lower than the power supply voltage Vdd.

[0082] If the reference potential is not the ground potential GND, the power supply voltage that is paired with the power supply potential Vdd must be lowered. This is called the power supply voltage Vss.

[0083] The first and second states are S j and / S j and have opposite polarity.

[0084] And the first state is S j Since "High (1)" is input to memory cell b ij of The status is "High(1)".

[0085] Also, the second state is S j Since "Low (0)" is input to memory cell b ij Status is "Low(0)".

[0086] And the third state is S j and / S j "Low (0)" will be entered into both Resale b ij The status is "X (Don't Care)".

[0087] In addition, memory cell b ij Information b ij and information / b ij are stored respectively.

[0088] b ij is the information stored in the channel capacitance of transistor 21, and / b ij Tran This is information stored in the channel capacity of register 22.

[0089] "X (Don't Care)" indicates what value is input during a read operation. is also a value that is judged to match.

[0090] By carrying out the above-mentioned operations for each memory cell, writing to each memory cell is performed. conduct.

[0091] After the write operation is completed, the gates of transistors 11 and 12 are The gate is closed (the transistor is off).

[0092] Therefore, when a read operation is performed, the gate of transistor 11 and the gate of transistor 1 The gate of 2 is closed (the transistor is off).

[0093] When a read operation is performed, the match line ML i Precharge to "High(1)" .

[0094] Next, the search line SL j and search line / SL j "High(1)" or "Low(0) " Input the voltage corresponding to ".

[0095] In addition, during a read operation, the search line SL j Input S j and search line / SL j Input / S j and have opposite polarity.

[0096] b during read operation ij , / bij , S j , / S j , and M.L. i The relationship is shown in Table 1. show.

[0097] [Table 1]

[0098] As shown in Table 1, when a write operation to a memory cell is performed in the first state or the second state, In this case, the input S j is the b in the memory cell ij If it matches, match line ML i The potential of It will remain at "High(1)".

[0099] On the other hand, when a write operation to a memory cell is performed in the first state or the second state, Input S j is the b in the memory cell ij If it does not match, match line ML i The potential of "Low ( 0)".

[0100] In addition, when the write operation to the memory cell is in the third state ("X (Don't Care)"), If this is done, during a read operation, the gate of transistor 21 and the gate of transistor 22 Since the gate of is closed (the transistor is off), the search line SL j of Input S j and search line / SL j Input / S j Match line ML i is never supplied to

[0101] Therefore, the write operation to the memory cell is in the third state ("X (Don't Care) "), input S j and b in the memory cell ijRegardless of the agreement or disagreement , match line ML i The potential of remains at “High(1)”.

[0102] Here, the match line ML i Output of G i In the judgment circuit that judges i "High h(1)" is judged as a match and the output G i If it is "Low (0)", it is judged as a mismatch. do.

[0103] Therefore, when all the memory cells arranged in the row direction match, the match line ML i The potential of The result is "High (1)" and it is determined to be a match. In other words, all memory cells aligned in the row direction In the embodiment, a write operation is performed in a first state or a second state, and an input S j B j Matches If the write operation is performed in the third state, the match line ML i The potential of " High(1)" and is determined to be a match.

[0104] On the other hand, if even one of the memory cells arranged in the row direction does not match, the match line ML i Electric potential of Since the value is "Low (0)", it is judged as a mismatch. In other words, all the memory In the cell, a write operation is performed in the first state or in the second state, and the input S j Memo b in resell j If it does not match, match line ML i The potential of the is judged to be a mismatch.

[0105] As described above, in the associative memory, whether the data words match or not is judged for each row, and if they match, If there is even one line that matches, the entire associative memory is judged to match. If there is no matching line, If not, the associative memory as a whole judges it to be a mismatch.

[0106] For example, if the data word "10110" is entered as shown in Figure 3, the first line is the data The word "10100" is stored and matches the entered data word "10110" Therefore, the first line is judged to be a mismatch.

[0107] In addition, in FIG. 3, the data word "10110" is stored in the Lth row. Since the Lth line matches the entered data word “10110”, the Lth line is determined to be a match.

[0108] In FIG. 3, the data word "1011X" is stored in the Mth row, where X is the total number of bits. Since it matches the input data word "10110", the Mth row is is considered a match.

[0109] In FIG. 3, the data word "101XX" is stored in the Nth row, where X is the total number of characters. Since it matches the input data word "10110", the Nth line is considered a match.

[0110] Therefore, in the case of Figure 3, since there is a matching row, the associative memory as a whole is judged to match. .

[0111] On the other hand, if there is no matching row, the associative memory as a whole is determined to be inconsistent.

[0112] A part or all of the contents of this embodiment may be combined with any other embodiment or example. This can be implemented.

[0113] (Embodiment 2) In Fig. 1, Fig. 2, Fig. 4, and Fig. 5, "X (Don't Care)" is not stored. When only the first and second states are written, it becomes a binary content addressable memory (BCAM).

[0114] That is, FIG. 1, FIG. 2, FIG. 4, and FIG. 5 show a binary content addressable memory (BCAM) and a ternary content addressable memory (TCAM). (TCAM) can be used for both.

[0115] A part or all of the contents of this embodiment may be combined with any other embodiment or example. This can be implemented.

[0116] (Embodiment 3) In a binary content addressable memory (BCAM) or ternary content addressable memory (TCAM), each memory cell There may be cases where you want to check the contents of a memory after writing them.

[0117] In the case of a binary content addressable memory (BCAM), by repeating the read operation, Since the stored data words can be confirmed, the contents of each memory cell can be read by a read operation alone. can be confirmed.

[0118] However, as shown in the example in Figure 3, in a ternary content addressable memory (TCAM), multiple rows may match.

[0119] Therefore, if multiple lines match, the content of each matched line is checked to see if it contains "X". Therefore, even if the read operation is repeated, the contents of each memory cell cannot be determined. There may be cases where this is not possible.

[0120] Another method is to prepare a separate memory to store the written information.

[0121] However, the method of storing the data in a separate memory requires a large memory to be prepared and formed separately. Therefore, this is not a preferred method.

[0122] Therefore, in this embodiment, a configuration is provided in which the memory contents of each memory cell can be checked after writing. This will be explained with reference to Figs. 4 and 5.

[0123] The configuration of FIG. 4 is the same as that of FIG. 1 except that the other of the source and drain of the transistor 21 and the transistor Between the connection part of the transistor 22 with the other of the source or drain and the wiring 34 which is the match line. A transistor 23 is added to the above.

[0124] In FIG. 4, one of the source and drain of the transistor 23 is connected to the a connection portion between the other of the source or drain and the other of the source or drain of the transistor 22; are electrically connected.

[0125] In FIG. 4, the other of the source and the drain of the transistor 23 is electrically connected to the wiring 34. Connected.

[0126] In FIG. 4, the gate of the transistor 23 is electrically connected to a wiring 35 .

[0127] In this embodiment, the transistor 23 is an n-channel transistor. A channel type transistor may also be used.

[0128] When a p-channel transistor is used, the polarity of the input signal or input voltage is adjusted appropriately. That would be good.

[0129] The wiring 35 functions as a read selection line.

[0130] In the figure, RL denotes a read selection line.

[0131] Also, R.L. y (y is an arbitrary number), the readout data stored in the memory cell in the yth row is This means that the output selection line RL.

[0132] The wiring 35 is provided in common to a group of memory cells arranged in the row direction.

[0133] The configuration of FIG. 5 is the same as that of FIG. 2 except that a read selection line RL is added and Add a means (such as a transistor) to input "High (1)" or "Low (0)" and A configuration that adds a means (transistor, etc.) to input "Low (0)" to the match line ML It is.

[0134] In this embodiment, by adding the transistor 23 and the read selection line RL, In addition to write and read operations, a verify operation can be performed.

[0135] The operation of FIG. 4 and FIG. 5 will be described.

[0136] The following description will be given taking the operation of the memory cell in row i, column j in FIG. 4 and FIG. 5 as an example. By repeating the same operation on the cells, write and read operations can be performed on all memory cells. It is possible to perform a read operation and a check operation.

[0137] First, the write operation is the same as in FIGS.

[0138] During a write operation, transistor 23 may be in either an on or off state.

[0139] However, during a write operation, the match line ML i The electrical state of the search line SL j Does not affect In order to avoid this, it is preferable to turn off the transistor 23.

[0140] Therefore, even in the first embodiment in which the verification operation is not performed, the electrical state of the match line ML is A transistor 23 may be added so as not to affect the search line SL.

[0141] Next, the read operation is also the same as in FIG. 1 and FIG.

[0142] However, during a read operation, the match line ML i and the source or drain of transistor 21 The other of the inputs must be electrically connected to the other of the source or drain of the transistor 22. Therefore, the transistor 23 is turned on during the read operation.

[0143] Next, in the case of a confirmation operation, all the search lines S1 to S n and search line / S1~ / S n "L ow(0)".

[0144] When reading data in the i-th row, the match line ML i and the read selection line R.L. i is set to "High(1)" and the match lines ML1 to ML i-1 , M L i+1 ~ML m and the read selection lines RL1 to RL i-1 , R.L. i+1 ~RL m "Lo Let w(0) be the square root of the

[0145] At this time, the b ij Depending on S j The output of "High( 1)" or "Low(0)".

[0146] That is, b ij When the signal is "High(1)", transistor 21 is in the on state. Therefore, match line ML i The voltage "High(1)" is SL j is entered into S j As "H igh(1)" is output.

[0147] On the other hand, b ij When the signal is "Low (0)", the transistor 21 is in the off state. Match line ML i The voltage "High(1)" is SL j is not entered in S j Preacher The signal remains at the previously-set "Low(0)" level.

[0148] Also, the / b stored in the memory cell in the i-th row ij Depending on / S j The output of "High( 1)" or "Low(0)".

[0149] That is, / b ij When it is "High (1)", transistor 22 is on. Therefore, match line ML i The voltage "High(1)" is / SL j / S j year and "High(1)" is output.

[0150] On the other hand, / b ij When the signal is "Low (0)", the transistor 22 is in the off state. Therefore, match line ML i The voltage "High(1)" is / SL j / S j Happy It remains charged at "Low (0)".

[0151] As described above, by the confirmation operation, Sj From the output of b ij The contents of / S can be confirmed. j of Output from / b ij In other words, the contents of each memory cell can be confirmed by the confirmation operation. You can check the contents.

[0152] A part or all of the contents of this embodiment may be combined with any other embodiment or example. This can be implemented.

[0153] (Embodiment 4) In Figures 1 and 4, a channel capacitance is used to hold charge (store data), The area of ​​each memory cell is reduced.

[0154] On the other hand, one electrode of the first capacitance element is electrically connected to the gate of the transistor 21, and The other electrode of the first capacitance element is set to “Low (0)” and the gate of the transistor 22 is set to One electrode of the second capacitance element is electrically connected, and the other electrode of the second capacitance element is It can also be set to "Low(0)".

[0155] In the above configuration, it is necessary to provide a first capacitance element and a second capacitance element. Since an oxide semiconductor is used as the semiconductor of the first capacitor 11 and the transistor 12, Even if the areas of the capacitance element and the second capacitance element are reduced, the charge can still be held.

[0156] Therefore, even when the first capacitance element and the second capacitance element are provided, the first capacitance element Since the area of ​​the second capacitance element can be minimized, the area of ​​one memory cell can be reduced. can be made smaller.

[0157] A part or all of the contents of this embodiment may be combined with any other embodiment or example. This can be implemented.

[0158] (Embodiment 5) In FIG. 1 and FIG. 4, a readout and charge storage transistor (transistor 21 The semiconductor used in the transistor 22) is crystalline and made of silicon to improve the read speed. It is preferable to use a semiconductor containing silicon.

[0159] On the other hand, the leakage current of the charge supply transistors (transistor 11 and transistor 12) If the number of charges is large, the channel capacitance of the readout and charge storage transistors must be increased. Therefore, the area of ​​the channel formation region of the read and charge storage transistor is increased. Must.

[0160] Therefore, the charge supply transistors (transistor 11 and transistor 12) are made of oxide. It is preferable to use a semiconductor.

[0161] Oxide semiconductors have a wider band gap than silicon, and transistors using oxide semiconductors Compared to silicon transistors, the amount of leakage between the source and drain ( The off-state current of the transistor is extremely low.

[0162] Therefore, the transistors for supplying electric charge (transistor 11 and transistor 12) By using an oxide semiconductor as the semiconductor, a transistor for reading and storing electric charges can be obtained. The area of ​​the channel forming region of the transistor can be reduced.

[0163] In order to improve the read speed, a read and charge storage transistor (transistor 2 1. The transistor 22) quickly changes the potential precharged to the match line ML (wiring 34). It is necessary to make it a reality.

[0164] Therefore, the transistor for reading and storing electric charge (transistor 21, transistor It is preferable that the channel width of the capacitor 22 be made wider.

[0165] On the other hand, in order to reduce the off-state current, the charge supply transistor (transistor 11, It is preferable that the channel width of the transistor 12 be narrow.

[0166] Therefore, the read and charge storage transistors (transistor 21, transistor The channel width of the charge supply transistor (transistor 11, transistor 22) is It is preferable that the channel width is wider than that of the channel width of the first embodiment.

[0167] A part or all of the contents of this embodiment may be combined with any other embodiment or example. This can be implemented.

[0168] (Embodiment 6) In this embodiment, a semiconductor material will be described.

[0169] Semiconductors that are crystalline and contain silicon include silicon (Si), silicon gel, Examples include silicon germanium (SiGe).

[0170] Semiconductors containing silicon may have crystallinity, such as single crystal, polycrystal, or microcrystal. Any material may be used, but a single crystal is most preferable in terms of improving mobility.

[0171] The oxide semiconductor contains at least indium (In) or zinc (Zn). It is particularly preferable that the alloy contains In and Zn.

[0172] In addition, a stabilizer for reducing variations in the electrical characteristics of transistors using oxide semiconductors has been developed. In addition to these, gallium (Ga), tin (Sn), and hafnium (Hf) are used as risers. , aluminum (Al), or lanthanides. preferable.

[0173] Lanthanides include lanthanum (La), cerium (Ce), praseodymium (Pr), Neodymium (Nd), Samarium (Sm), Europium (Eu), Gadolinium (Gd) , terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (E r), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0174] For example, indium oxide, tin oxide, zinc oxide, etc. are used as oxide semiconductors of single-element metals. It can be used.

[0175] In addition, for example, as a binary metal oxide semiconductor, In-Zn oxide, Sn-Zn oxide, Oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides Oxides, In-Ga-based oxides, etc. can be used.

[0176] In addition, for example, In-Ga-Zn oxide (IGZ) is used as an oxide semiconductor of a ternary metal. O), In-Sn-Zn oxide, Sn-Ga-Zn oxide, In-Al -Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce- Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Z n-type oxides, In-Eu-Zn-type oxides, In-Gd-Zn-type oxides, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide Oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide Examples of materials that can be used include oxides of Al-Ga-Zn system, Sn-Al-Zn system oxides, and the like.

[0177] In addition, for example, as an oxide semiconductor of a quaternary metal, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide, etc. can be used.

[0178] In addition, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than Ga and Zn may be contained.

[0179] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In: In-Ga-Zn system with an atomic ratio of Ga:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) It is possible to use oxides having compositions close to those of the oxides.

[0180] Alternatively, In:Sn:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3), In:Sn :Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1: In-Sn-Zn oxide with an atomic ratio of 5 (=1 / 4:1 / 8:5 / 8) and its neighboring compositions Alternatively, an oxide of the above may be used.

[0181] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to set the degree, etc., appropriately.

[0182] The oxide semiconductor may be either single-crystal or non-single-crystal.

[0183] In the case of non-single crystal, it may be amorphous or polycrystalline. Also, a portion having crystallinity in an amorphous state may be In addition, since amorphous has many defects, non-amorphous is preferable. .

[0184] A part or all of the contents of this embodiment may be combined with any other embodiment or example. This can be implemented.

[0185] (Embodiment 7) An example of a method for manufacturing a semiconductor device using an associative memory will be described with reference to FIGS. do.

[0186] 10 to 13 are top views corresponding to FIGS. 1 and 2, and illustrate four memory cells. is doing.

[0187] 14 and 15 are top views corresponding to FIGS. 4 and 5, and illustrate one memory cell. is doing.

[0188] The cross-sectional views along the line AB in FIGS. 10 to 15 correspond to FIGS. 6 to 9.

[0189] The same parts or parts having similar functions are commonly designated by the same reference numerals in FIGS. 6 to 15. is doing.

[0190] First, a semiconductor device having an insulating layer 102 on a substrate 101 and a semiconductor layer 200 on the insulating layer 102 is A structure is prepared (Figure 6(A)).

[0191] The structure shown in FIG. 6(A) is an SOI (Semiconductor On In) substrate. A sulator, etc. can be used.

[0192] Alternatively, the insulating layer 102 and the semiconductor layer 200 are successively formed on the substrate 101, as shown in FIG. The structure (A) may be formed.

[0193] The substrate 101 may be a silicon wafer, a glass substrate, a quartz substrate, a metal substrate (stainless steel, Substrates, etc.) can be used, but are not limited to these.

[0194] Note that a transistor is formed using a silicon wafer instead of the structure shown in FIG. is also good.

[0195] As the insulating layer 102, any material can be used as long as it has insulating properties. For example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, a silicon nitride film containing oxygen, a nitrogen Examples of the film that can be used include an aluminum nitride film, an aluminum oxide film, and a hafnium oxide film. The insulating layer 102 may have a single layer structure or a multilayer structure.

[0196] The semiconductor layer 200 is preferably made of a semiconductor that has crystallinity and contains silicon. However, the present invention is not limited thereto. For example, a crystalline or amorphous oxide semiconductor may be used. Alternatively, a semiconductor containing amorphous silicon may be used.

[0197] Semiconductors containing silicon include silicon (Si), silicon germanium (Si Ge), etc.

[0198] Semiconductors containing silicon may have crystallinity, such as single crystal, polycrystal, or microcrystal. Any material may be used, but a single crystal is most preferable in terms of improving mobility.

[0199] Next, the semiconductor layer 200 is etched to form an island-shaped semiconductor layer 210, and the semiconductor layer A gate insulating layer 300 is formed on 210 (FIG. 6(B), FIG. 10(A), FIG. 14(A)). .

[0200] The gate insulating layer 300 can be made of any material that has insulating properties. For example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, a silicon nitride film containing oxygen, a nitrogen aluminium nitride film, aluminium oxide film, a film obtained by oxidizing or nitriding the semiconductor layer 210, halide oxide The gate insulating layer 300 may be a single layer, such as a fluorine film, but is not limited to these. It may have a layered structure or a laminated structure.

[0201] In FIG. 6B, a semiconductor layer used in the transistor 21 in FIG. The semiconductor layer used in 2 is shared (integrally formed).

[0202] As shown in FIG. 6B, a semiconductor layer used for the transistor 21 in FIG. By sharing the semiconductor layer used for the memory cell 22, As a result, the area of ​​one memory cell can be reduced.

[0203] Note that the semiconductor layer used for the transistor 21 and the semiconductor layer used for the transistor 22 are may be separated.

[0204] 10A shows a semiconductor layer used in the transistor 21 in FIG. 4 and a semiconductor layer used in the transistor 21 in FIG. The semiconductor layer used for the transistor 22 is shared with the semiconductor layer used for the transistor 23 in FIG. (Formed as one unit).

[0205] As shown in FIG. 10A, a semiconductor layer used for the transistor 21 in FIG. The semiconductor layer used for the transistor 22 in FIG. 4 is shared with the semiconductor layer used for the transistor 23 in FIG. By doing so, when fabricating the memory cell of FIG. 4, the area of ​​one memory cell can be reduced. It is possible.

[0206] Note that the semiconductor layer used for the transistor 21 and the semiconductor layer used for the transistor 22 are The semiconductor layer used for the transistor 23 in FIG. 4 may be separated.

[0207] Next, a plurality of openings are provided in the gate insulating layer 300 (FIG. 6(C)).

[0208] The openings are provided at positions that will become the source or drain of the transistor.

[0209] Next, the gate electrode on the gate insulating layer 300 is electrically connected to the semiconductor layer 210 through the opening. The gate electrode and the connection electrode are formed simultaneously. As a result, impurity elements are added to the gate electrode (FIG. 7(A), FIG. 10(B), FIG. 14(B)). Since the gate electrode and the connection electrode are formed at the same time in the same process, the gate electrode and the connection electrode are in the same layer. Since the gate electrode and the connection electrode are formed at the same time in the same process, It can be said that the electrode and the connection electrode are formed using the same starting film.

[0210] As impurity elements, donor elements (phosphorus, arsenic, etc.) or acceptor elements (boron, etc.) are used. There can be.

[0211] In order to reduce the resistance at the contact points between the connection electrodes and the semiconductor layer, the connection electrodes are An impurity element may be selectively added to the portion in contact with the connection electrode.

[0212] The electrodes 411, 412, and 413 correspond to gate electrodes.

[0213] Moreover, electrodes 421, 422, 423, and 424 correspond to connection electrodes.

[0214] Electrode 411 corresponds to the gate electrode of transistor 21 in FIGS.

[0215] 1 and 4. Electrode 412 corresponds to the gate electrode of transistor 22 in FIG.

[0216] 4. Also, the electrode 413 corresponds to the gate electrode of the transistor 23 in FIG.

[0217] The gate electrode and the connection electrode can be made of any material as long as it is conductive. For example, aluminum, titanium, molybdenum, tungsten, gold, silver, copper, conductive Silicon doped with impurities that give the material a conductive layer of various alloys and oxides (typically indium). However, the present invention is not limited to these. The pole may be of single layer or multilayer construction.

[0218] Next, after forming a sidewall insulating layer, the sidewall insulating layer is etched back. By this, sidewalls 510 are formed on the side surfaces of the gate electrode and the connection electrode. Then, impurity elements are added using the sidewalls, gate electrode, and connection electrode as a mask (FIG. 7). (B)).

[0219] When the sidewalls are formed, a part of the gate insulating layer 300 is also removed at the same time (FIG. 7(B) )).

[0220] Any material having insulating properties can be used as the sidewall insulating layer. For example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, a nitride film containing oxygen, etc. Silicon film, aluminum nitride film, aluminum oxide film, hafnium oxide film, etc. can be used. The insulating layer for the sidewall may have a single-layer structure or a multi-layer structure. good.

[0221] Next, an interlayer insulating film 600 is formed on the gate electrode and the connection electrode (FIG. 7(C)).

[0222] The interlayer insulating film 600 may be a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, Silicon nitride film containing oxygen, polyimide, acrylic, siloxane polymer, aluminum nitride Examples of the film that can be used include, but are not limited to, hafnium oxide, aluminum oxide, and hafnium oxide. The interlayer insulating film 600 may have a single layer structure or a multilayer structure.

[0223] Next, the interlayer insulating film 600 is etched back or polished (mechanical polishing, CMP (Chemical Polishing) By applying mechanical polishing, etc., the gate electrode and The upper surface (front surface) of the connection electrode is exposed (FIG. 8(A)).

[0224] By filling the interlayer insulating film 600, no contact holes are formed. Since the upper surface (front surface) of the gate electrode and the upper surface (front surface) of the connection electrode can be exposed, , the number of masks can be reduced.

[0225] The interlayer insulating film 600 exposing the upper surfaces (front surfaces) of the gate electrode and the connection electrode is and is embedded between the connection electrodes.

[0226] Therefore, the interlayer insulating film 600 exposing the upper surfaces (front surfaces) of the gate electrode and the connection electrode is filled with It can be said that this is an embedded insulating layer.

[0227] Note that when the oxide semiconductor layer to be formed later is to have crystallinity, It is preferable that the surface of the interlayer insulating film 600 on which the film is formed has a high flatness.

[0228] Therefore, the method for exposing the upper surfaces (surfaces) of the gate electrode and the connection electrode uses CMP. It is preferable.

[0229] Next, an oxide film is formed on the interlayer insulating film 600 (buried insulating layer), the connection electrode, and the gate electrode. A semiconductor layer 711 and an oxide semiconductor layer 712 are formed (FIG. 8(B), FIG. 11(A), FIG. 14 (C)).

[0230] Note that the oxide semiconductor layer 711 corresponds to the semiconductor layer of the transistor 11 in FIGS. .

[0231] The oxide semiconductor layer 712 corresponds to the semiconductor layer of the transistor 12 in FIGS. .

[0232] One end of the oxide semiconductor layer is in contact with a connection electrode, and the other end of the oxide semiconductor layer is in contact with a gate electrode. It is in contact with the ground electrode.

[0233] Furthermore, the oxide semiconductor layer is disposed at a position overlapping a region between the connection electrode and the gate electrode. The insulating layer is disposed at a position overlapping the underlying semiconductor layer.

[0234] By adopting the above-mentioned configuration, the area of ​​one memory cell can be reduced. do.

[0235] Here, the hydrogen element serves as a carrier (donor) in the oxide semiconductor layer.

[0236] Furthermore, hydrogen element has reducing properties and is an element that induces oxygen deficiency.

[0237] Therefore, since hydrogen has both of the factors that induce carriers, It can be said that the substance containing the oxide semiconductor layer is a substance that prevents the oxide semiconductor layer from being highly purified and brought closer to an i-type oxide semiconductor layer. do.

[0238] Note that substances containing a hydrogen element include hydrogen, moisture, hydroxides, hydrides, and the like.

[0239] On the other hand, when the interlayer insulating film 600 is formed by the plasma CVD method, the deposition gas contains hydrogen elements. Therefore, hydrogen is taken into the interlayer insulating film 600 and adversely affects the oxide semiconductor layer. .

[0240] In addition, resin films such as polyimide, acrylic, and siloxane polymer contain a large amount of moisture. In this case, moisture adversely affects the oxide semiconductor layer.

[0241] Therefore, the interlayer insulating film 600 in contact with the oxide semiconductor layer 711 and the oxide semiconductor layer 712 It is preferable that the film is formed by a sputtering method that does not contain hydrogen. A silicon oxide film or an aluminum oxide film formed on the insulating film is preferable.

[0242] Next, a gate insulating layer 800 is formed over the oxide semiconductor layer 711 and the oxide semiconductor layer 712. A gate electrode 811 (gate wiring) is formed on the gate insulating layer 800 (FIG. 8(C) , Figure 11(B), Figure 15(A).

[0243] The gate insulating layer 800 can be made of any material that has insulating properties. For example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, a silicon nitride film containing oxygen, a nitrogen Examples of the film that can be used include an aluminum nitride film, an aluminum oxide film, and a hafnium oxide film. The gate insulating layer 800 may have a single layer structure or a multilayer structure.

[0244] The gate electrode 811 can be made of any material as long as it is conductive. For example, aluminum, titanium, molybdenum, tungsten, gold, silver, copper, conductive Silicon with added impurities, various alloys, oxide conductive layers (typically indium tin oxide) The gate electrode (gate wiring) can be made of, but not limited to, The structure may be a single layer or a laminated structure.

[0245] The gate electrode 811 corresponds to the gate electrode of the transistor 11 and the gate electrode of the transistor 12 shown in FIG. These correspond to the gate electrodes and the wiring 33 (word lines WL).

[0246] Next, after forming a sidewall insulating layer, the sidewall insulating layer is etched back. As a result, sidewalls 910 are formed on the sides of the gate electrode (FIG. 9(A)).

[0247] When the sidewalls are formed, a part of the gate insulating layer 800 is also removed at the same time (FIG. 9(A) )).

[0248] Any material having insulating properties can be used as the sidewall insulating layer. For example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, a nitride film containing oxygen, etc. Silicon film, aluminum nitride film, aluminum oxide film, hafnium oxide film, etc. can be used. The insulating layer for the sidewall may have a single-layer structure or a multi-layer structure. good.

[0249] Next, the electrodes 1011 and 1021 on the oxide semiconductor layer 711 and the oxide semiconductor layer 7 12, the electrode 1012 and the electrode 1022, and the wiring on the electrode 423 and the interlayer insulating film 600. 1023 and are formed at the same time (FIG. 9(B), FIG. 12, FIG. 15(B)).

[0250] In addition, when forming the memory cell of FIG. 4, as shown in FIG. 15(B), The wiring 1024 on the interlayer insulating film 600, and the wiring on the electrode 424 and the interlayer insulating film 600 are The wire 1025 is also formed at the same time.

[0251] The electrodes and wiring in FIG. 9(B) can be made of any material as long as it is conductive. For example, aluminum, titanium, molybdenum, tungsten, gold, silver, copper, conductive Silicon with impurities added to give it properties, various alloys, and oxide conductive layers (typically indium However, it is not limited to these. The electrodes and wiring are It may have a layered structure or a laminated structure.

[0252] One of the electrodes 1011 and 1021 is the source electrode of the transistor 11 in FIG. 1 and 4, and the other corresponds to the drain electrode of transistor 11 in FIG.

[0253] One of the electrodes 1012 and 1022 is the source electrode of the transistor 12 in FIG. 1 and 4, and the other corresponds to the drain electrode of transistor 12 in FIG.

[0254] The wiring 1023 corresponds to the wiring 34 (match line ML) in FIG.

[0255] The wiring 1023 is connected between the transistor 23 in FIG. 4 and the transistor 21 in FIG. This serves as an auxiliary wiring for the wiring that electrically connects the transistor 22. Although the formation of the auxiliary wiring may be omitted, the supply of charge to the match line ML can be simplified by forming the auxiliary wiring. It is preferable to form the auxiliary wiring because this can be done quickly.

[0256] The wiring 1024 corresponds to the wiring 35 (read selection line RL) in FIG.

[0257] The wiring 1025 corresponds to the wiring 34 (match line ML) in FIG.

[0258] As shown in FIG. 9B, the source electrode or drain electrode (electrode 1011, electrode 102 1, electrode 1012, electrode 1022, etc.) so as to contact the gate electrode or connection electrode in the lower layer. As a result, poor contact between the oxide semiconductor layer and the underlying gate electrode or connection electrode is prevented. Even if this occurs, electrical connection between the oxide semiconductor layer and the underlying gate electrode or connection electrode is maintained. It will be possible to continue.

[0259] In addition, in a region where the oxide semiconductor layer 711 and the electrode 1011 overlap, a region where the oxide semiconductor layer 712 and the electrode 1012 overlap; The area where the conductor layer 712 and the electrode 1022 overlap is the source area or drain area of ​​the transistor. It can also be considered as a rain area.

[0260] The presence of the sidewall 510 prevents the channel formation region and the source A high resistance region (a portion of the oxide semiconductor layer overlapping with the sidewall) is provided between the drain region and the gate electrode. Since a thin film transistor (a thin film region) is formed, the off-state current of a transistor including an oxide semiconductor can be reduced. As a result, leakage current of a transistor including an oxide semiconductor can be reduced.

[0261] Next, an interlayer insulating film 1100 is formed on the gate electrode, and a contact is formed on the interlayer insulating film 1100. Holes are formed, and wiring 1211 and wiring 1212 are formed on the interlayer insulating film 1100 (FIG. 9(C), Fig. 13, Fig. 15(C).

[0262] The wiring 1211 is electrically connected to the electrode 1021 through a contact hole.

[0263] The wiring 1212 is electrically connected to the electrode 1022 through a contact hole.

[0264] The interlayer insulating film 1100 is a silicon oxide film, a silicon nitride film, or a silicon oxide film containing nitrogen. , silicon nitride film containing oxygen, polyimide, acrylic, siloxane polymer, aluminum nitride Examples of the film that can be used include, but are not limited to, a hafnium film, an aluminum oxide film, and a hafnium oxide film. The interlayer insulating film 1100 may have a single layer structure or a multilayer structure.

[0265] The wiring 1211 and the wiring 1212 can be made of any material as long as it is conductive. For example, aluminum, titanium, molybdenum, tungsten, gold, silver, copper, Silicon doped with impurities to give it electrical conductivity, various alloys, and oxide conductive layers (typically ITO) Indium tin oxide, etc. can be used, but are not limited to these. The wiring 1212 may have a single layer structure or a multilayer structure.

[0266] The wiring 1211 corresponds to the wiring 31 (search line SL) in FIGS.

[0267] The wiring 1212 corresponds to the wiring 32 (search line / SL) in FIGS.

[0268] By arranging and fabricating each layer as described above, the memory cell of FIG. 1 or FIG. 4 is fabricated. In this case, the area of ​​one memory cell can be reduced.

[0269] A part or all of the contents of this embodiment may be combined with any other embodiment or example. This can be implemented.

[0270] (Embodiment 8) In the seventh embodiment, a top-gate transistor is shown, but a bottom-gate transistor may be used. It may be a transistor or a fin type transistor.

[0271] A top-gate transistor having a structure different from that described in Embodiment Mode 7 may also be used.

[0272] That is, any transistor structure is applicable.

[0273] A part or all of the contents of this embodiment may be combined with any other embodiment or example. This can be implemented. EXAMPLES

[0274] The transistor using an oxide semiconductor containing In, Sn, and Zn is The substrate may be heated when the oxide semiconductor film is formed, or heat treatment may be performed after the oxide semiconductor film is formed. By carrying out this process, good characteristics can be obtained.

[0275] It is preferable that each of In, Sn, and Zn is contained in a composition ratio of 5 atomic % or more. It is nice.

[0276] By intentionally heating the substrate after the formation of an oxide semiconductor film containing In, Sn, and Zn, This makes it possible to improve the field effect mobility of the transistor.

[0277] In addition, the threshold voltage of an n-channel transistor can be shifted in the positive direction. .

[0278] By positively shifting the threshold voltage of an n-channel transistor, The absolute value of the voltage required to maintain the off-state of a transistor of a transistor type can be reduced. This enables low power consumption.

[0279] Furthermore, the threshold voltage of the n-channel transistor is shifted in the positive direction to If the voltage is set to 0V or higher, it is possible to form a normally-off transistor. .

[0280] The characteristics of a transistor using an oxide semiconductor containing In, Sn, and Zn are described below.

[0281] (Samples A to C common conditions) The composition ratio of the target was In:Sn:Zn=1:1:1, and the gas flow ratio was Ar / O2=6 / 9sccm, deposition pressure 0.4Pa, deposition power 100W, 15nm An oxide semiconductor layer was formed over a substrate so as to have a thickness of 100 nm.

[0282] Next, the oxide semiconductor layer was etched to have an island shape.

[0283] Then, a tungsten layer was formed on the oxide semiconductor layer to a thickness of 50 nm. This was etched to form a source electrode and a drain electrode.

[0284] Next, using the plasma CVD method, silane gas (SiH4) and dinitrogen monoxide (N2O) A silicon oxynitride film (SiON) was formed to a thickness of 100 nm using The velum was used.

[0285] Next, tantalum nitride is formed to a thickness of 15 nm, and then tantalum nitride is formed to a thickness of 135 nm. The tungsten was then formed as shown in FIG.

[0286] Furthermore, a silicon oxynitride film ( A polyimide film is then formed to a thickness of 1.5 μm, which acts as an interlayer insulating film. did.

[0287] Next, a contact hole is formed in the interlayer insulating film, and the first channel is formed to a thickness of 50 nm. A tin film is formed, an aluminum film is formed to a thickness of 100 nm, and a 50 nm thick film is formed. A second titanium film is formed so that the thickness of the first titanium film is smaller than that of the second titanium film. These are then etched to form the measurement pads. Formed.

[0288] In the manner described above, a semiconductor device having a transistor was formed.

[0289] (Sample A) In Sample A, the substrate was not intentionally heated during the formation of the oxide semiconductor layer.

[0290] In addition, sample A was obtained after the oxide semiconductor layer was formed and the oxide semiconductor layer was etched. No heat treatment was performed prior to construction.

[0291] (Sample B) For sample B, the oxide semiconductor layer was formed while the substrate was heated to 200° C. Ta.

[0292] In addition, sample B was obtained after the oxide semiconductor layer was formed and then etched. No heat treatment was performed prior to construction.

[0293] The reason for performing the deposition while the substrate was heated is to add hydrogen, which serves as a donor, to the oxide semiconductor layer. This is to get it out.

[0294] (Sample C) For sample C, the oxide semiconductor layer was formed while the substrate was heated to 200°C. Ta.

[0295] Furthermore, sample C is a sample after the oxide semiconductor layer is formed, and the oxide semiconductor layer is etched. Before processing, the specimens were heat-treated at 650°C for 1 hour in a nitrogen atmosphere, and then heated at 650°C for 1 hour in an oxygen atmosphere. Heat treatment was carried out between 100 and 200°C.

[0296] The reason for performing the heat treatment at 650°C for 1 hour in a nitrogen atmosphere is to form a donor in the oxide semiconductor layer. This is to expel hydrogen that is generated.

[0297] Here, oxygen is also removed by the heat treatment for expelling hydrogen, which serves as a donor in the oxide semiconductor layer. In addition, oxygen vacancies that serve as carriers are also generated in the oxide semiconductor layer.

[0298] Therefore, by performing a heat treatment at 650°C for 1 hour in an oxygen atmosphere, oxygen vacancies are reduced. The aim was to achieve this effect.

[0299] (Transistor characteristics of samples A to C) FIG. 16A shows the initial characteristics of the transistor of sample A.

[0300] FIG. 16B shows initial characteristics of the transistor of Sample B.

[0301] FIG. 16C shows the initial characteristics of the transistor of Sample C.

[0302] The field effect mobility of the transistor of sample A is 18.8 cm 2 / Vsec.

[0303] The field effect mobility of the transistor of sample B is 32.2 cm 2 / Vsec.

[0304] The field effect mobility of the transistor of sample C is 34.5 cm 2 / Vsec.

[0305] Here, a cross section of the oxide semiconductor layer formed by the same film formation method as in Samples A to C was observed using a transmission microscope. When observed with a TEM, Sample B and Sample C, which had been heated during film formation, Crystallinity was confirmed in the sample formed by the same film formation method.

[0306] Surprisingly, the sample in which the substrate was heated during deposition was found to have a crystalline and amorphous portion. The crystallinity was such that the crystalline portions were aligned along the c-axis.

[0307] In normal polycrystals, the crystalline parts are not aligned and point in different directions. The sample in which the substrate was heated during film formation has a new structure.

[0308] In addition, when comparing FIGS. 16(A) to 16(C), it is found that the substrate is heated during film formation, or By carrying out a heat treatment later, the donor hydrogen element can be expelled, so that n It can be seen that the threshold voltage of the channel type transistor can be shifted in the positive direction.

[0309] That is, the threshold voltage of sample B, in which the substrate was heated during film formation, was The threshold voltage of sample A is shifted in the positive direction compared to that of sample A which does not have a threshold voltage of 100 V.

[0310] In addition, when comparing sample B and sample C, in which the substrate was heated during film formation, Sample C, which was heat-treated, had a higher luminance than sample B, which was not heat-treated after deposition. It is clear that there is a positive shift.

[0311] In addition, light elements such as hydrogen are more likely to be desorbed at higher heat treatment temperatures. The higher the temperature, the easier it is for hydrogen to be released.

[0312] Therefore, if the temperature during or after film formation is increased, a larger positive shift is possible. I considered that there was.

[0313] (Gate BT stress test results for sample B and sample C) For sample B (not heat-treated after film formation) and sample C (heat-treated after film formation) A gate BT stress test was performed.

[0314] First, the substrate temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I ds Special The characteristics of the transistor were measured before heating and applying a positive high voltage. .

[0315] Next, the substrate temperature is set to 150°C and V ds was set to 0.1V.

[0316] Next, V is applied to the gate insulating film. gs A voltage of 20 V was applied to the electrode and the electrode was maintained for 1 hour.

[0317] Next, V gs was set to 0V.

[0318] Next, the substrate temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I ds measurement The characteristics of the transistor were measured after heating and application of a positive high voltage.

[0319] In this way, the characteristics of the transistor before and after heating and applying a positive high voltage were compared. This comparison is called the Plus BT test.

[0320] First, the substrate temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I d s The characteristics of the transistor were measured before heating and applying a negative high voltage. It was determined.

[0321] Next, the substrate temperature is set to 150°C and V ds was set to 0.1V.

[0322] Next, V is applied to the gate insulating film. gs A voltage of −20 V was applied to the electrode and the electrode was maintained for 1 hour.

[0323] Next, V gs was set to 0V.

[0324] Next, the substrate temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I ds measurement The characteristics of the transistor were measured after heating and application of a negative high voltage.

[0325] In this way, the characteristics of the transistor before and after heating and applying a negative high voltage were measured. This comparison is called a minus BT test.

[0326] Figure 17(A) shows the positive BT test results for sample B, and Figure 17(B) shows the positive BT test results for sample B. The BT test result was negative.

[0327] Figure 18(A) shows the positive BT test results for sample C, and Figure 18(B) shows the positive BT test results for sample C. The BT test result was negative.

[0328] The positive BT test and negative BT test are tests to determine the degree of deterioration of transistors. However, referring to FIG. 17(A) and FIG. 18(A), at least the process of the plus BT test is performed. It was found that the threshold voltage could be shifted in the positive direction by this.

[0329] In particular, in FIG. 17(A), the transistor is turned on by the plus BT test. It can be seen that it has become a Marie-off type.

[0330] Therefore, in addition to the heat treatment during the manufacture of the transistor, the process of the Plus BT test is performed. This promotes a positive shift in the threshold voltage, resulting in a normally-off transistor. was able to be formed.

[0331] Figure 19 shows the relationship between the off-state current of the transistor of sample A and the inverse of the substrate temperature (absolute temperature) at the time of measurement. This shows the relationship between:

[0332] Here, the horizontal axis shows the reciprocal of the substrate temperature during measurement multiplied by 1000 (1000 / T). is doing.

[0333] In addition, FIG. 19 shows the amount of off-state current per 1 μm of channel width.

[0334] When the substrate temperature is 125°C (1000 / T is approximately 2.51), the -19 A or below was.

[0335] When the substrate temperature is 85°C (1000 / T is approximately 2.79), the -20 A or below there was.

[0336] In other words, the off-state current is extremely low compared to that of a transistor using a silicon semiconductor. I realized that.

[0337] In addition, the lower the temperature, the lower the off-current, so at room temperature, the off-current is lower. It is clear that... [Explanation of symbols]

[0338] 11 Transistor 12 Transistor 21 Transistor 22 Transistor 23 Transistor 31 Wiring 32 Wiring 33 Wiring 34 Wiring 35 Wiring 101 Substrate 102 Insulating layer 200 Semiconductor layer 210 Semiconductor layer 300 Gate insulation layer 411 Electrode 412 Electrode 413 Electrode 421 Electrode 422 Electrode 423 Electrode 424 Electrode 510 Sidewall 600 Interlayer insulating film 711 Oxide semiconductor layer 712 Oxide semiconductor layer 800 Gate Insulator 811 Gate electrode 910 Sidewall 1011 Electrode 1012 Electrode 1021 Electrode 1022 Electrode 1023 Wiring 1024 Wiring 1025 Wiring 1100 Interlayer insulating film 1211 Wiring 1212 Wiring

Claims

1. A semiconductor device including first to fourth transistors, a first semiconductor layer having a first channel formation region of the first transistor and a second channel formation region of the second transistor; a first conductive layer having a region located above the first channel formation region and functioning as a gate of the first transistor; a second conductive layer having a region located above the second channel formation region and functioning as a gate of the second transistor; a third conductive layer having a region disposed above the first semiconductor layer and electrically connected to one of a source region or a drain region of the first transistor; a fourth conductive layer having a region disposed above the first semiconductor layer and electrically connected to one of a source region or a drain region of the second transistor; a fifth conductive layer having a region in contact with the first semiconductor layer and electrically connected to the first semiconductor layer; an insulating layer having a region disposed above the first semiconductor layer; a second semiconductor layer having a region disposed above the insulating layer and having a third channel formation region of the third transistor; a third semiconductor layer having a region disposed above the insulating layer and having a fourth channel formation region of the fourth transistor; a sixth conductive layer having a region disposed above the third channel formation region and a region disposed above the fourth channel formation region, the sixth conductive layer having a function as a gate of the third transistor and a function as a gate of the fourth transistor; a seventh conductive layer having a region disposed above the second semiconductor layer and electrically connected to one of the source and the drain of the third transistor; an eighth conductive layer having a region disposed above the third semiconductor layer and electrically connected to one of the source and the drain of the fourth transistor; having the other of the source and the drain of the third transistor is electrically connected to the third conductive layer; the other of the source and the drain of the fourth transistor is electrically connected to the fourth conductive layer; the third conductive layer and the fifth conductive layer are brought into a conductive state at least via a channel formation region of the first transistor in response to first data held in a gate of the first transistor; the fourth conductive layer and the fifth conductive layer are brought into a conductive state at least via a channel formation region of the second transistor in response to second data held in a gate of the second transistor; the seventh conductive layer has a region in contact with the second semiconductor layer and a region in contact with the first conductive layer; The eighth conductive layer has a region in contact with the third semiconductor layer, and also has a region in contact with the second conductive layer.

2. A semiconductor device including first to fourth transistors, a first semiconductor layer having a first channel formation region of the first transistor and a second channel formation region of the second transistor; a first conductive layer having a region located above the first channel formation region and functioning as a gate of the first transistor; a second conductive layer having a region located above the second channel formation region and functioning as a gate of the second transistor; a third conductive layer having a region disposed above the first semiconductor layer and electrically connected to one of a source region or a drain region of the first transistor; a fourth conductive layer having a region disposed above the first semiconductor layer and electrically connected to one of a source region or a drain region of the second transistor; a fifth conductive layer having a region in contact with the first semiconductor layer and electrically connected to the first semiconductor layer; an insulating layer having a region disposed above the first semiconductor layer; a second semiconductor layer having a region disposed above the insulating layer and having a third channel formation region of the third transistor; a third semiconductor layer having a region disposed above the insulating layer and having a fourth channel formation region of the fourth transistor; a sixth conductive layer having a region disposed above the third channel formation region and a region disposed above the fourth channel formation region, the sixth conductive layer having a function as a gate of the third transistor and a function as a gate of the fourth transistor; a seventh conductive layer having a region disposed above the second semiconductor layer and electrically connected to one of the source and the drain of the third transistor; an eighth conductive layer having a region disposed above the third semiconductor layer and electrically connected to one of the source and the drain of the fourth transistor; having the other of the source and the drain of the third transistor is electrically connected to the third conductive layer; the other of the source and the drain of the fourth transistor is electrically connected to the fourth conductive layer; the third conductive layer and the fifth conductive layer are brought into a conductive state at least via a channel formation region of the first transistor in response to first data held in a gate of the first transistor; the fourth conductive layer and the fifth conductive layer are brought into a conductive state at least via a channel formation region of the second transistor in response to second data held in a gate of the second transistor; the third conductive layer has a region in contact with the second semiconductor layer and a region in contact with the first semiconductor layer; the fourth conductive layer has a region in contact with the third semiconductor layer and a region in contact with the first semiconductor layer; the seventh conductive layer has a region in contact with the second semiconductor layer and a region in contact with the first conductive layer; The eighth conductive layer has a region in contact with the third semiconductor layer, and also has a region in contact with the second conductive layer.

3. A semiconductor device including first to fourth transistors, a first semiconductor layer having a first channel formation region of the first transistor and a second channel formation region of the second transistor; a first conductive layer having a region located above the first channel formation region and functioning as a gate of the first transistor; a second conductive layer having a region located above the second channel formation region and functioning as a gate of the second transistor; a third conductive layer having a region disposed above the first semiconductor layer and electrically connected to one of a source region or a drain region of the first transistor; a fourth conductive layer having a region disposed above the first semiconductor layer and electrically connected to one of a source region or a drain region of the second transistor; a fifth conductive layer having a region in contact with the first semiconductor layer and electrically connected to the first semiconductor layer; an insulating layer having a region disposed above the first semiconductor layer; a second semiconductor layer having a region disposed above the insulating layer and having a third channel formation region of the third transistor; a third semiconductor layer having a region disposed above the insulating layer and having a fourth channel formation region of the fourth transistor; a sixth conductive layer having a region disposed above the third channel formation region and a region disposed above the fourth channel formation region, the sixth conductive layer having a function as a gate of the third transistor and a function as a gate of the fourth transistor; a seventh conductive layer having a region disposed above the second semiconductor layer and electrically connected to one of the source and the drain of the third transistor; an eighth conductive layer having a region disposed above the third semiconductor layer and electrically connected to one of the source and the drain of the fourth transistor; having the other of the source and the drain of the third transistor is electrically connected to the third conductive layer; the other of the source and the drain of the fourth transistor is electrically connected to the fourth conductive layer; the third conductive layer and the fifth conductive layer are brought into a conductive state at least via a channel formation region of the first transistor in response to first data held in a gate of the first transistor; the fourth conductive layer and the fifth conductive layer are brought into a conductive state at least via a channel formation region of the second transistor in response to second data held in a gate of the second transistor; the first semiconductor layer comprises silicon; the second semiconductor layer includes an oxide semiconductor; the third semiconductor layer includes an oxide semiconductor; the seventh conductive layer has a region in contact with the second semiconductor layer and a region in contact with the first conductive layer; The eighth conductive layer has a region in contact with the third semiconductor layer, and also has a region in contact with the second conductive layer.

4. A semiconductor device including first to fourth transistors, a first semiconductor layer having a first channel formation region of the first transistor and a second channel formation region of the second transistor; a first conductive layer having a region located above the first channel formation region and functioning as a gate of the first transistor; a second conductive layer having a region located above the second channel formation region and functioning as a gate of the second transistor; a third conductive layer having a region disposed above the first semiconductor layer and electrically connected to one of a source region or a drain region of the first transistor; a fourth conductive layer having a region disposed above the first semiconductor layer and electrically connected to one of a source region or a drain region of the second transistor; a fifth conductive layer having a region in contact with the first semiconductor layer and electrically connected to the first semiconductor layer; an insulating layer having a region disposed above the first semiconductor layer; a second semiconductor layer having a region disposed above the insulating layer and having a third channel formation region of the third transistor; a third semiconductor layer having a region disposed above the insulating layer and having a fourth channel formation region of the fourth transistor; a sixth conductive layer having a region disposed above the third channel formation region and a region disposed above the fourth channel formation region, the sixth conductive layer having a function as a gate of the third transistor and a function as a gate of the fourth transistor; a seventh conductive layer having a region disposed above the second semiconductor layer and electrically connected to one of the source and the drain of the third transistor; an eighth conductive layer having a region disposed above the third semiconductor layer and electrically connected to one of the source and the drain of the fourth transistor; having the other of the source and the drain of the third transistor is electrically connected to the third conductive layer; the other of the source and the drain of the fourth transistor is electrically connected to the fourth conductive layer; the third conductive layer and the fifth conductive layer are brought into a conductive state at least via a channel formation region of the first transistor in response to first data held in a gate of the first transistor; the fourth conductive layer and the fifth conductive layer are brought into a conductive state at least via a channel formation region of the second transistor in response to second data held in a gate of the second transistor; the first semiconductor layer comprises silicon; the second semiconductor layer includes an oxide semiconductor; the third semiconductor layer includes an oxide semiconductor; the third conductive layer has a region in contact with the second semiconductor layer and a region in contact with the first semiconductor layer; the fourth conductive layer has a region in contact with the third semiconductor layer and a region in contact with the first semiconductor layer; the seventh conductive layer has a region in contact with the second semiconductor layer and a region in contact with the first conductive layer; The eighth conductive layer has a region in contact with the third semiconductor layer, and also has a region in contact with the second conductive layer.

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