Processing using compact arithmetic processing element

Abstract

To efficiently provide a calculation capacity in a programmable and / or a large scale parallel processor, or another device.SOLUTION: A processing element 400 includes a processing element which is designed to execute, to a numeric value of a low accuracy dynamic range (LPHDR arithmetic operation), an arithmetic operation, for example, but not necessarily, a process containing one or more of addition, multiplication, subtraction, and division. The number of LPHDR arithmetic operation elements n the processor or other devices far exceeds the number of arithmetic operation elements being designed to execute a high dynamic range arithmetic operation with a conventional accuracy, such as 32 bits or 64 bits floating point.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The ability to compute quickly has become crucial to humanity. Weather and climate forecasting, medical applications (e.g., drug design and tomography), national defense, geological exploration, financial modeling, Internet searches, network communications, scientific research in a wide variety of fields, and the design of new computer hardware all depend on the ability to process large amounts of calculations quickly. Advances in areas such as the computer-aided design of complex nanoscale systems and the development of consumer products that allow us to see, hear, and understand will likely require the economic deployment of ever more advanced computing power.

[0002] Gordon Moore predicts that computing power per dollar will double every two years The prediction that the computing power of silicon will continue to grow in some form or another has proven valid for 30 years and is likely to continue in some form or another for the foreseeable future. However, despite this rapid exponential progress, the reality is that the raw computing power available in silicon is growing much faster than the speed at which software can make it available. In other words, even though the theoretical computing power of computer hardware has grown exponentially, the interfaces that software needs to access the hardware limit the software's ability to use the hardware to perform computations at a rate approaching the hardware's theoretical maximum computing power.

[0003] Consider a modern silicon microprocessor chip that contains about one billion transistors and has a clock frequency of nearly 1 GHz. In one cycle, the chip performs approximately Deliver approximately one valid operation to the running software. For example, The numbers are transferred between the stars, another value is added, and the multiplication is complete. This is not dramatically different from what microprocessor chips did 30 years ago, even though clock speeds are about 1000 times faster today.

[0004] Real computers are constructed as physical devices, and the underlying physics on which computer machines are constructed often provides complex and fascinating behavior. For example, silicon metal oxide semiconductor field effect transistors (MOSFETs) The Sigma is a device capable of performing interesting nonlinear operations such as exponential processing. At the junction of the two wires the currents add up. If configured properly, Billions of transistors and wires are needed to make a circuit that is a few propagation delays away from the basic components (design If the entire project is a traditional digital design, it is called a "cycle" , which can perform a significant percentage of the billion operations involved in a computation. And today's CPU chips are software capable of performing a significant percentage of the billion possible operations. Instead, it uses a billion transistors simply to be able to perform a few of the above operations every cycle. Summary of the Invention [Problem to be solved by the invention]

[0005] Embodiments of the invention relate to processors or other devices, including programmable and / or massively parallel processors and other devices. and the processor or other device performs arithmetic operations (e.g., arithmetic operations that may include, but do not necessarily include, one or more additions, multiplications, subtractions, and divisions) that manipulate numbers in low precision high dynamic range (LPHDR arithmetic). The device includes a processing element designed to: Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR computing elements used in a processor or other device in some embodiments of the invention may be greater than or equal to conventional precision. High dynamic range calculations with 32-bit or 64-bit floating point calculations Such processor or other device is designed to perform operations such as The number of computational elements used in

[0006] In one embodiment, a "low precision" computing element has a frequency of at least 0.1% (one-tenth of 1%) This is a widely used method of computing a computer in a way that produces a result different from the correct result. This is significantly worse than the commonly used IEEE 754 single-precision floating-point standard. In an embodiment of the programmable processor of the present invention, programming is performed using an algorithm that functions properly even if an extraordinary number of such calculation errors occur. In some embodiments, the processing element processes the input and / or Both have the ability to output a range of outputs that spans from one part per million to one million. The processing elements have a "high dynamic range" in the sense that they have [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates the overall design of a SIMD processor according to one embodiment of the present invention. [Diagram 2] 2 illustrates an array of processing elements in a SIMD processor according to one embodiment of the present invention. [Diagram 3]1 illustrates one embodiment of the present invention, showing how a processing element in an array of processing elements of a processor communicates data with other parts of the processor. [Figure 4] 1 illustrates a processing element design according to one embodiment of the present invention. [Diagram 5] 1 illustrates an example of a word format of LPHDR data according to an embodiment of the present invention. [Figure 6] 1 illustrates an embodiment of the present invention, and illustrates a design of an LPHDR arithmetic unit. BEST MODE FOR CARRYING OUT THEINVENTION

[0008] As mentioned above, today's CPU chips do not use the transistors they contain efficiently. For example, a conventional CPU chip containing 1 billion transistors requires 10 ... This is highly inefficient, but those of ordinary skill in the art will appreciate that such an approach would reduce the CPU utilization for reasons that are widely accepted as valid. For example, the design approach described here meets the requirements for software conformance in early designs (which are often essential requirements), and also provides a very high degree of precision, typically with exact arithmetic using 32-bit or 64-bit integers, and fairly accurate, widely standardized arithmetic using 32-bit and 64-bit floating-point numbers. In many applications, this kind of precision is essential. As a result, traditional CPUs typically use on the order of a million transistors to perform the calculations. The system is essentially designed to provide the accuracy described above.

[0009] However, there are many economically important applications where the accuracy is not sensitive and where there is a very large gain in application performance per transistor. And a million transistors is not inherently This enormous gain is based on the ability to extract a significant percentage of the available computing power from the general purpose computer architecture, which is not currently capable of delivering this capability.

[0010] Due to the weaknesses of traditional computers such as typical microprocessors, other kinds of computers have been developed to achieve higher performance. These machines include the Single Instruction Stream / Multiple Data Stream (SIMD) design methodology, Multiple Instruction Stream / Multiple Data Stream (MSST) design methodology, and MIMD (Multiple Instruction Stream / Multiple Data Stream) design method, Reconfigurable architectures such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs), which when applied to general purpose computers, can be seen as a Single Instruction Stream / Multiple Thread (SIMT) design approach. This book contains design methods for Graphics Processing Units.

[0011] SIMD machines are designed to work with sequential programs that provide instructions to operate on collections of data. There are two main types of SIMD machines: vector processors and array processors. Vector processors stream data through processing elements (or small collections of processing elements). Each component of the data stream is processed in the same way. Vector machines use a sequential method of sending data to the processor, eliminating many instruction fetch / decode steps (bringing instructions from memory / decoding instructions) and allowing for faster clock speeds. By using the pipeline method, high speed is achieved.

[0012] Array processors distribute data across a grid of processing elements (PEs). Each processing element has its own memory. Instructions are sent sequentially from a central controller to the processing elements. Each processing element (PE) executes the instructions on its local data (often with the option to "idle" during certain cycles). Array processors use silicon efficiently, Achieving high speed: Array processors use only one instruction fetch / decode unit to run many smaller, simpler execution units in parallel.

[0013] Array processors can be implemented with a wide range of bit widths, e.g. 1, 4, 8 bits wide or more. Computers have been built using fixed-point arithmetic with bit widths up to 1000 MHz, and floating-point arithmetic. Smaller bit widths allow smaller processing elements, so most processing elements can fit inside a computer, but traditional arithmetic requires many operations to be performed in sequence. Wider bit widths allow traditional arithmetic operations to be completed in a single cycle. In fact, wider bit widths are desirable. Machines originally designed with small bit widths, such as the Connection Machine-1 and the Goodyear massively parallel processor, with 1-bit processing elements, have been developed with wider data paths to better support high-speed arithmetic, resulting in machines such as the Connection Machine-2 with 32-bit floating-point hardware and the massively parallel MasPar, which was a successor to the Goodyear machine and used 4-bit processing elements in the MasPar-1 and 32-bit processing elements in the MasPar-2.

[0014] Array processors are machines designed to provide an analog representation of numbers and use analog circuits to perform calculations. SCAMP is one such machine. These machines perform low-precision calculations, and the results of each process performed by these machines have an error of a few percent. Calculations cannot be repeated because this introduces noise. Furthermore, these machines only handle a narrow range of values, for example 8-bit fixed-point values, rather than offering the high dynamic range of 32- or 64-bit floating-point arithmetic. Due to these constraints, SCAMP is oriented towards general-purpose computers. It is designed and used for image processing and modeling of early biological visual processes. Such application areas do not require the full range of computational hardware. For example, SCAMP is Its design eliminates common division and multiplication operations.

[0015] In the 1980s, SIMD machines were popular, but as microprocessor price / performance improved, designers moved away from large collections of communications microprocessors. They began building machines consisting of a number of different types of processors. MIMD machines are fast and have price / performance characteristics comparable to the microprocessors that they are made of, but the MIMD machines are not very efficient. The computational performance per transistor is relatively low compared to the software used. It is as inefficient as its components in that it does not

[0016] Field Programmable Gate Arrays (FPGAs) are a large class of general purpose digital elements. It is an integrated circuit with a grid where the wiring between the digital elements is reconfigurable. The digital elements were originally single digital gates such as "AND" and "OR" gates. The FPGA was developed as a large element that can be programmed by Boolean functions, for example, into a 6-input, 1-output map. The architecture allows the FPGA to perform a wide variety of digital calculations from external sources. These calculations are then performed by the device acting as a co-processor to facilitate the CPU calculations. This enables the use of the However, integer and especially floating-point operations such as multiplication and division require many gates and use up a large portion of the FPGA's general-purpose resources. For this reason, modern FPGAs allocate a significant proportion of the FPGA's area to provide dozens or even hundreds of multiplication blocks that can be used instead of the general-purpose resources for calculations that require multiplication. These multiplication blocks typically perform integer multiplications of 18 bits or more in width and use many transistors. These multiplication blocks are equivalent to the multiplication circuits that function as part of a general-purpose CPU. It seems that.

[0017] Existing field programmable analog arrays (FPAAs) are similar to FPGAs, but the configurable elements of an FPAA perform analog processing. Such devices are intended to perform signal processing that aids in modeling neural circuits. FPAAs are relatively low precision and have a relatively low dynamic range. Noise is introduced into the calculation process. FPAAs can be used as general-purpose computers or They are not designed or intended for use in general purpose computers. For example, a person skilled in the art would understand that FPAAs are not intended for use in high performance digital It has never been seen as a machine capable of executing the many complex algorithms using floating-point arithmetic that are used on modern computers.

[0018] Finally, Graphic Processing Units (GPUs) are a variety of parallel processors developed to provide high-speed graphics capabilities for personal computers. GPUs provide standard floating-point computational capabilities that provide extremely high performance in certain tasks. The computational model of GPUs is often based on thousands of nearly identical computational threads (SIMT). In that regard, it is executed by a collection of SIMD-like internal computation engines, each of which is fed by a slower external DR. The AM memory provides data to perform the task, and then it routes or redirects the results. Like other machines that perform standard floating-point operations, GPUs use many transistors to perform those operations. GPUs are just as wasteful of these transistors as general-purpose CPUs in the sense described above.

[0019] Some GPUs support 16-bit floating point values ​​(often called "half" format). Current GPU manufacturers like NVIDIA and AMD / ATI use the usual 32-bit This ability is useful for rendering images with a higher dynamic range than the standard RGBA format, which uses 8-bit fixed-point data per color, and 32-bit floating-point data per color component. The High Dynamic Range (HDR) image file format was developed by Industrial Light & Magic (ILM) for use in computer imaging applications. Wikipedia (late 2008) states the following about 16-bit floating-point images: "The format includes OpenEXR, OpenGL, and D3DX. Used in some computer graphics environments. Its advantage over 8-bit or 16-bit binary integers is that it preserves more detail in highlights and shadows due to its expanded dynamic range. 32-bit single precision binary The advantage over the format is that it requires half the storage capacity and half the bandwidth."

[0020] When a graphics processor supports 16-bit floating point, it also supports 32-bit floating point and even 64-bit floating point. That is, the 16-bit floating point format is supported by applications that require it and is considered necessary for traditional graphics applications and so-called general-purpose GPU applications. Therefore, existing GPUs devote substantial resources to 32-bit (and even 64-bit) arithmetic, wasting transistors in the sense described above.

[0021] All of the various architectures mentioned above are attempts to squeeze more performance out of silicon than was available in traditional processor designs. However, traditional processor designers have struggled with the need to use vast numbers of transistors to increase the performance of their machines. These machines have historically and economically been unable to support existing large instruction sets, such as the Intel x86 instruction set. It is often necessary to double the number of transistors to achieve the same performance. This is a difficult problem because of the law of diminishing returns: you can't double One aspect of these designers' struggles has been to increase the precision of arithmetic operations, since transistors were plentiful and processors could natively support longer numbers (say, 64-bit numbers), resulting in noticeable speedups in some applications. With the increase in precision of decimal points, from 32 bits to 64 bits, and sometimes even 128 bits The increase in floating-point precision up to 8024 has forced programmers to think in terms of high precision and develop algorithms under the assumption that computer processors will provide such precision, since precision is something that is bound to change with each new generation of silicon chip.

[0022] The present invention is an efficient design method that uses a fundamentally different approach to the above-mentioned methods. In particular, embodiments of the present invention relate to computer processors or other devices that use low precision, high dynamic range (LPHDR) processing elements to perform calculations (e.g., arithmetic operations). .

[0023] One type of LPHDR calculation has an accuracy of about 0.1%, which represents values ​​from parts per million to parts per million. If these values ​​are represented and manipulated using floating-point arithmetic, these numbers will have a binary mantissa not exceeding 10 bits plus a sign bit, and a binary exponent of at least 5 bits plus a sign bit. However, multiplication and division of such floating-point numbers The circuits for performing the above operations are relatively large. One example of an alternative implementation is to use a logarithmic representation of floating-point numbers. In such an approach, the same number of bits are needed to represent the floating-point numbers, but multiplications and divisions are implemented as logarithmic additions and subtractions, respectively. Additions and subtractions can be performed efficiently, as explained below. As a result, the area of ​​the arithmetic circuits can be relatively small, and many computational elements can be placed in a given area on the silicon. This means that the machine can perform more operations per unit time or power. This, in turn, means that the machine can perform more operations per unit time or power, which, within the framework of LPHDR, is much faster. This means that we can enjoy the benefits of expressible computation.

[0024] Another embodiment utilizes analog representation and processing mechanisms. Analog implementations of LPHDR operations are superior to digital implementations. This is because analog computing seeks to exploit the inherent analog physical behavior of transistors and other physical devices, rather than exploiting only the digital aspects of the device's behavior. Thus, exploiting the entire inherent capabilities of the device is a major step forward in performing LPHDR operations. In recent years, analog techniques have been replaced by digital techniques in the field of silicon circuit technology, due to the ease of digital design compared to analog design. In addition, digital technology has continuously expanded at a faster rate than analog technology (Moore's In particular, in the deep submicron region, the large dimensions are Analog transistors no longer function like previous generations of transistors. These recent changes in well-known behavior make analog design even more challenging. However, digital transistors are actually analog transistors used in a digital way, and digital circuits are actually designed to switch transistors between fully "ON" and fully "OFF" states. As digital technology continues to expand, using transistors in this way will begin to face the reality of analog behavior. It is believed that the expansion of transistors in digital usage will either stall or that digital designers will need to recognize and deal with analog problems. For these reasons, digital implementation of LPHDR operations is no longer easy, reliable, and It is not scalable. And the analog implementation of the LPHDR calculation is It has the potential to become a dominant industrial architecture.

[0025] The LPHDR processing elements are relatively small and can be implemented using a single processor or other device. It can accommodate a very large number of LPHDR processing elements and operate in parallel with each other, and thereby constructing a massively parallel processing LPHDR processor or other device. Such processors and other devices have never been described or used by those of ordinary skill in the art as means for general purpose computation. There are at least two reasons for this. First, It was widely believed by those skilled in the art that LPHDR calculations, especially large LPHDR calculations, whether massively parallelized or not, were impractical on a circuit board for moderate general purpose computing. Secondly, it was widely believed by those skilled in the art that because large amounts of high precision calculations could be handled by compact computing units, it would not be useful to do large amounts of high precision calculations on a single chip or a single machine without increasing the bandwidth between the processing elements inside the machine, the inputs to the machine, and the outside of the machine, because the calculations would be limited by the wiring and could be assumed to be inexpensive to perform.

[0026] Despite the notion that doing large amounts of calculations on a single chip or on a massively parallel processing machine is not useful and that large amounts of LPHDR operations can actually lead to bad results, In the embodiments of the invention disclosed herein, massively parallel LPHDR designs are practically useful, at least Both have demonstrated that they can offer significant practical advantages in several applications.

[0027] In conclusion, modern digital computing systems can provide high precision arithmetic, but this precision comes at a high cost. A modern double precision floating point multiplier requires on the order of a million transistors, whereas a low precision multiplication requires only a few transistors to perform. Modern applications require high precision processing. Despite the widespread belief among those skilled in the art that precision is required, in reality some useful algorithms work adequately with much lower precision. As a result, such algorithms can be executed by a processor or other device incorporating embodiments of the present invention, which brings us closer to the goal of using only a few transistors for multiplication and wire contacts for addition. Moreover, this requires a relatively small amount of physical resources (a single silicon It is a technology that enables large-scale parallel computing by using a microcomputer (such as a microcomputer chip). While domain-specific tasks can function with lower precision, it is not self-evident, and in fact has been viewed as a clear misconception by those skilled in the art, that relatively general-purpose calculations, such as those typically performed today on general-purpose computers, can be performed with lower precision. However, in practice, certain useful and important algorithms can function adequately with less than 32-bit precision in the framework of massively parallel computing. Certain embodiments of the present invention support such algorithms, thus making efficient use of transistors. They offer improvements in speed, power consumption, and / or cost compared to conventional computers.

[0028] In the following, various computing devices to which embodiments of the present invention may be applied are described. Some of the embodiments described herein are illustrative of SIMD computer architectures, MIMD architectures, programmable array architectures (FPGAs and FPAAs), and other similar architectures. ), or other architectures such as GPU / SIMT architectures. The techniques disclosed herein may be implemented using a processor or other device with a pre-existing architecture, such as those described above, and the LPHDR computation unit used in any of the methods disclosed herein may be housed within the processor or other device. This can be done by replacing or augmenting some or all of the existing computational units. However, devices implemented in accordance with embodiments of the present invention need not necessarily start with an existing processor design, but may be modified to include an LPHDR computation unit within the architecture just described or any other architecture. A device implemented in accordance with an embodiment of the invention may be designed from scratch.

[0029] For example, embodiments of the invention may be implemented using array processor architectures, which are specialized SIMD computers. There are many types and special types of array processors disclosed in the scientific and commercial literature, including, by way of example, the Illiac 4, Connection Machine 1 and 2, Goodyear MPP, and MasPar computers.

[0030] However, embodiments of the present invention need not necessarily be implemented as SIMD computers. For example, embodiments of the present invention may be implemented as FPGAs, FPAAs, or related architectures that provide flexible connectivity to a group of processing elements. For example, embodiments of the present invention may be implemented as GPUs / SIMTs, MIMDs, and others. For example, embodiments of the present invention may be implemented as SIMD computers that require fewer resources (such as fewer transistors) than traditional architectures. In addition, the "processing element" referred to in the embodiments of the present invention may be implemented as any type of machine using LPHDR processing elements to perform calculations using a variety of parameters (such as volume, distance, and distance). Furthermore, the "processing element" referred to in the embodiments of the present invention may be implemented as any type of computational execution unit, whether or not it performs LPHDR processing. It should be interpreted generally.

[0031] An example of a SIMD computing system 100 is shown in Figure 1. The computing system includes a collection of multiple processing elements (PEs) 104. The computing system often includes a control unit (CU) 106, an I / O unit (IOU) 108, various peripheral devices 110, and a host computer 102. The collection of processing elements (PEs) 104 may be a two-dimensional arrangement, an array, a grid, or any other particular Although not necessarily depicted in the layout, this is referred to herein as a "Processing Element Array" (PEA) 104. Some machines include additional components, such as an additional memory system called "staging memory" in the Goodyear MPP. However, such additional components are not essential to the computer, nor are they necessary to understand embodiments of the present invention. Therefore, for clarity of illustration, such additional components are omitted herein. One embodiment of the present invention is a SIMD computing system as shown in FIG. As the terminology is used herein, one or more (eg, all) of the PEs in processing element array (PEA) 104 are LPHDR processing elements.

[0032] The host computer 102 is responsible for the overall control of the computing system 100. The host computer 102 is a conventional uniprocessor. Of course, the host computer 102 may have a more complex architecture that includes various kinds of parallel processing. Indeed, employing heterogeneous computing systems that combine multiple computing architectures in a single machine is a preferred use for embodiments of the present invention.

[0033] The purpose of the host computer 102 is to provide a processing element array (PEA) 104 with large, useful The host computer 102 causes the PEs to perform large amounts of calculations, typically by having each PE perform calculations in parallel with each other on data stored locally in each PE. For example, when there are many PEs, it is possible to perform many calculations per unit of time. A large amount of calculations are performed.

[0034] The PEs in the processing element array (PEA) 104 are capable of roughly performing individual calculations at a rate similar to the calculations performed by the host computer 102. This means that the calculations can be performed at a rate as fine as the minimum time step of the host computer 102 or the processing element array (PEA) 104. A host computer 102 controls a processing element array (PEA) 104 on a short time scale. This means that trying to achieve this minimum time step is inefficient. A step corresponds to a clock period in traditional digital design. To achieve this, a specialized Control Unit (CU) 106 is included in the architecture. The main task of the control unit (CU) 106 is to read and write data from the instruction memory. The main task of the processor is to retrieve and decode the instructions, which is conceptually called the Control Unit (CU). The role of the Control Unit (CU) 106 is to dispatch the partially decoded instruction to all PEs in the Processing Element Array (PEA) 104 (which may be viewed by the Control Unit (CU) 106 software as a nearly simultaneous event for all PEs), and It does not have to be literally synchronous. In fact, it is efficient to have a synchronous design where multiple instructions propagate to different stages of execution at the same time, like a wavefront propagating across the Processing Element Array (PEA) 104.

[0035] In designs that include a control unit (CU) 106, the host computer 102 typically loads instructions (programs) for the processing element arrays (PEAs) 104 into a control unit instruction memory (not shown in FIG. 1). The control unit (CU) 106 then decodes the programs and causes the processing element arrays (PEAs) 104 to perform the computations described in the programs. For example, the programs may be used to coordinate data movement within and between PEs, logical operations, arithmetic operations, etc., and control flow operations within the control unit (CU) 106. The control unit (CU) 106 may be similar to a general machine language program with other instructions to perform similar operations together. The processor is capable of executing a wide variety of programs, but also has the ability to issue massively parallel processing instructions to the processing element arrays (PEAs) 104.

[0036] Send data into the control unit (CU) 106 and the processing element array (PEA) 104 To receive and retrieve data from these, an I / O unit (IOU) 108 controls The processing unit (CU) 106 and the processing element array (PEA) 104 are connected to the host computer 102, the host computer memory (not shown in FIG. 1), an external storage device (e.g., a disk drive), a display device for visualizing the calculation results, and a special input device with a large bandwidth. Peripheral devices for computer systems such as sensors (e.g., vision sensors) 110 The host computer 102 may be configured to interface with the The ability of the Processing Element Array (PEA) 104 to process data much faster becomes useful to the I / O Unit (IOU) 108 to allow some portion of the data transfer to be performed bypassing the host computer 102. Additionally, the host computer 102 may have its own path for communicating with peripheral devices 110.

[0037] The particular embodiment shown in FIG. 1 is shown for illustrative purposes only and is not intended to limit the invention. For example, the control unit (CU) 106 The functions performed by the host computer may be omitted by omitting the control unit (CU) 106. The control unit (CU) 106 may be implemented by hardware separate from the processing element array (PEA) 104 (e.g., off-chip hardware). The control unit (CU) 106 may be implemented as a single piece of hardware, or the control unit (CU) 106 may be located near (e.g., on the same chip as) the processing element array (PEA) 104. I / O is routed through the control unit (CU) 106, omitting the I / O unit (IOU) 108. Alternatively, as shown in the figure, the signal may be sent via a separately provided I / O unit (IOU) 108. In addition, the host computer 102 is optional. For example, the control unit (CU) 106 may include a CPU or may have functions that can replace the functions that can be performed by the host computer 102. The peripheral device 110 shown in FIG. 1 is optional. The design shown in FIG. 1 uses the Goodyear MPP " It is possible to provide a special memory such as a "staging memory." For example, such a memory may be used to transfer memory from the processing elements (PEs) of the processing element array (PEA) 104. to the LPHDR chip using 3D assembly techniques for relatively fast parallel access to It is possible.

[0038] The Processing Element Array (PEA) 104 is connected to the Control Unit (CU) 106 and the I / O Unit (IOU) In addition to being able to communicate with the PEA 108, or other possible mechanisms, the PEA 104 itself includes a means for moving data within the array. For example, the PEA 104 can be driven to move data only from a processing element (PE) to its nearest neighbors; that is, there is no longer any distance for data transfer. Figures 2 and 3 show an embodiment of the invention that employs the approach described above. In this case, the nearest neighbors are the four adjacent processing elements (PEs), the north, east, west, and south processing elements. For example, Figure 2 shows a processing element array (PEA). A subset of processing elements (PEs) in 104, namely PE 202, PE 204, PE 206, PE 208, The control unit (CU) 106 receives a data transfer command and a PE 210. Upon issuing a command, all processing elements (PEs) access data from or send data to their nearest neighbors (PEs). For example, Every processing element (PE) accesses a particular data value in its neighboring processing element (PE) to the west and copies it into its own local storage. In some embodiments, such as analog processing embodiments, this type of data transfer can result in degradation of the copied value.

[0039] FIG. 3 shows a processing element (PE) 302 with a data connection to an I / O unit (IOU) 108. Processing element (PE) 302 is connected to processing element (PE) 304 on the north side, processing element (PE) 306 on the east side, processing element (PE) 308 on the south side, and processing element (PE) 310 on the west side. However, The driving signals going from inside the processing element array (PEA) 104 to the I / O unit (IOU) 108 are These typically require relatively large physical drive circuits or analog mechanisms. Providing such a system for every processing element (PE) would consume a large portion of the available resources (such as VLSI area) of the hardware implementation technology. Furthermore, providing an independent connection from every processing element (PE) to the I / O unit (IOU) 108 would be Providing a large number of connections means providing many connections and long connections, which also consumes a large portion of the available resources. For this reason, the connections between the processing elements (PEs) and the I / O unit (IOU) 108 may be limited to the processing elements (PEs) at the edge of the processing element array (PEA) 104. In this case, the IOU 108 is used to get data from the processing element array (PEA) 104 and to send data to the processing element array (PEA) 104. Data is written to and read from processing elements (PEs) at the edge of a processing element array (PEA) 104. , and the processing elements (PEs) at the edge of the processing element array (PEA) 104 and the processing element array (PEA) 104 The control unit is responsible for moving data between the processing elements (PEs) on the internal side of the In this design, the I / O unit (IOU) 108 routes data to any of the processing elements (PEs) inside the processing element array (PEA) 104 using a direct connection. The data is then transferred to the processing elements (PEs) at the edge of the processing element array (PEA) 104, where the data can be read in by the To send the data, the control unit (CU) 106 is used to read the data. That's fine too.

[0040] The connection between the control unit (CU) 106 and the processing element array (PEA) 104 is similar to There are variations in the design. In one design, instructions are delivered to all processing elements (PEs) almost simultaneously. Alternatively, an alternative approach would be to have instructions propagate gradually (e.g. , by shifting based on discrete time steps) to the processing element array (PEA) 104. The present invention is implemented in accordance with an embodiment of the present invention. In some SIMD designs, the OR-wiring of each processing element (PE) in the processing element array (PE) 104 The state or AND connection state is determined by the control unit (CU) 106 with a delay of approximately one instruction time. The facility is equipped with equipment that can read the information.

[0041] There are many well-researched papers on this topic, some of which are incorporated in the embodiments of the present invention. For example, interconnects such as 8-way local interconnects can be used. Local interconnects with various distance hops, such as distance 1, distance 4, and distance 16, can be used. At the outer edge, the interconnects can be connected using topologies such as a torus or twisted torus. More complex global interconnects, such as a hypercube design, can be used instead of or in addition to the local interconnect. Furthermore, the processing element array (PEA) 104 (e.g., chip) can be replicated (e.g., the circuit boards can be split) to create larger processing element arrays (PEAs) 104. The PEAs components can be physically implemented by The objects do not necessarily have to be in a grid arrangement, but can be replicated to form a simple grid or other arrangement.

[0042] FIG. 4 illustrates an example design of a processing element (PE) 400, which performs the functions of one or more of the processing elements (PEs) in the processing element array (PEA) 104. 400 stores local data. The storage capacity for this local data is based on the design This varies significantly from one chip to another, depending on the chip used to fabricate the processing element (PE) 400. It is highly dependent on implementation technology that can handle numbers that rarely change (constants). Constants (values) take up less space than numbers that change frequently (registers). And some designs provide more constants than resistors. For example, a single transistor cell (e.g., a flash memory) is used for the constants. A floating gate flash memory cell is used for the register. In digital implementations, there are many transistor cells (e.g., a 6-transistor SRAM cell). In analog implementations, the situation is often reversed. In this case, sufficient area for capacitance is required to ensure the long-term stability of the constants. Such implementations have many more registers than constants. Typically, the registers and constants in each processing element (PE) store tens or hundreds of calculations, and these storage capacities are often much larger than the total storage capacity. The amount can be adjusted by the designer. For example, some designs have register storage but no constant storage, and some designs store a large number of values ​​in each Processing Element (PE), possibly thousands or more. All of these variations are incorporated in the embodiments of the present invention.

[0043] Each processing element (PE) needs to process its local data. For this reason, inside the processing element (PE) 400, there are data paths 402a-i, routing mechanisms (such as multiplexers MUX 404), and a network for collecting the results of logical and arithmetic operations. components (such as logic unit 406 and LPHDR arithmetic unit 408) The LPHDR computation unit 408 performs the LPHDR computation, as that term is used herein. The inputs, outputs, and intermediate values ​​received by, output from, and processed by the processing element (PE) 400 may be, for example, numerical values. It takes the form of an electrical signal.

[0044] The processing element (PE) 400 may also include one or more masks, shown as masks 410 in FIG. The purpose of the mask 410 is to determine whether some processing is required. Enables the processor elements (PEs) to ignore commands issued by the control unit (CU) 106. To do this, certain mask bits are set in the processing elements (PEs). By this, the normal locking of all the processing elements (PEs) in the processing element array (PEA) 104 is performed. Variations in step operations can be created. For example, the control unit (CU) 106 can instruct each processing element (PE) to reset and set its mask 410 depending on whether a particular register in the processing element (PE) is positive or negative. A subsequent instruction, such as an arithmetic instruction, can have a bit that signifies that the instruction should only be executed by processing elements (PEs) that have the mask 410 reset. The combination has the effect of conditionally executing the arithmetic instruction in each processing element (PE) depending on whether the particular register in the processing element (PE) is negative. As with the compare instruction in a conventional computer, there are many design options for the mechanism to set and clear the mask.

[0045] Processing in the processing elements (PEs) is controlled by control signals 412a-d received from the control unit (CU) 106. Although four control signals are shown in FIG. 4, they are merely exemplary and are not meant to be limiting. Although the details of this mechanism are not shown, the control signals 412a-d may include register memory values, constant memory values, or other data to be sent to the data path within the processing elements (PEs) 400. Identify adjacent processing elements (PEs). Such processing may include logic units 406 and processors. The result is stored in a register. The control signals 412a-d are then used to determine the set and reset methods and masks 410. These are described in detail in the SIMD processor literature.

[0046] There are many variations in the design of the processing element (PE) 400 and the processing element array (PEA) 104. Many possibilities exist, all of which are within the scope of the present invention. Digital Processing Elements (PEs) may include shifters, look-up tables, and other devices such as those described in the above references. Many other mechanisms can be implemented. In analogue processing elements (PEs), The processing element array (PEA) 104 may include OR-based operators, filters, comparators with global broadcast signals, and many other mechanisms as described in the above references. For analog processing elements (PEs), it can have a SUM connection. Again, the digital and analog components can have a global mechanism such as AND connections. Many variations are detailed in the literature on computer architecture.

[0047] For example, LPHDR operations other than addition and multiplication and / or operations can be supported. For example, a machine that can only perform multiplication and the function (1-X) can also perform approximate addition and other operations. The set of LPHDR procedures can be used in the computational process. Using techniques well known to those skilled in the art, LPHDR operations such as addition, multiplication, subtraction and division are performed. Used to estimate processing.

[0048] One aspect of a unique embodiment of the present invention is the inclusion of an LPHDR computation mechanism within the Processing Elements (PEs), an embodiment of which is described below.

[0049] In one digital embodiment of the LPHDR calculation unit 408, The resulting numbers are then processed. In some digital implementations, these numbers are displayed logarithmically. Such a representation is called the logarithmic system (LNS) and is a system well known to those skilled in the art. .

[0050] In the Logarithmic System (LNS), numbers are represented by a sign and an exponent. In the Logarithmic System (LNS), there is an implicit base for logarithms, which is typically 2 when implemented with digital hardware. In this embodiment, the base of 2 is used as an example. As a result, number B is represented as the sign and logarithm of base 2, and number b is represented as its absolute value. For numbers with a maximum display error of 1%, the decimal part that can vary is the It is displayed with enough precision to correspond to about 1% change. If fractions are represented using 6 bits, If B is multiplied by 1, increasing or decreasing the decimal point by 1 will change the value of B to the 64th root of 2 (approximately 1.011). This corresponds to multiplying or dividing by (taking). This means that there is a possibility that the fractional part may be displayed with a multiplicative error of about 1%. Therefore, in this embodiment, 6 bits are allocated to display the fractional part.

[0051] Furthermore, the domain of values ​​processed in this embodiment has a high dynamic range. To represent absolute values ​​from one billionth to another billionth, the integer part of the logarithm is multiplied by 2. The logarithm must be long enough to represent both positive and negative numbers, whose logarithm is approximately 29.9. In this example, the integer part of the logarithmic representation is 5 bits long, which is sufficient to represent numbers from 0 to 31. An additional sign bit is required for the exponent. Negative logarithms are represented using two's complement representation.

[0052] In the logarithmic system (LNS), the value of 0 is negative infinity. To accurately represent this special value, one may choose a representation. However, to minimize the resources used by the computation circuitry (e.g., to minimize area), in this embodiment, 0 is represented as the negative infinity. It is represented by the largest number, -32, which corresponds to the two's complement bit representation "100000 000000", giving a value of approximately 2.33E-10.

[0053] When performing calculations, situations may arise where the process is unable to derive a reasonable value. For example, when multiplying or adding two very large numbers, or when dividing by zero (or a number close to zero), the number may be too large to be represented in the chosen word format. A common approach to solving such problems is to mark the resulting value as "Not A Number (NAN)" and check whether a problem has occurred somewhere along the way that resulted in a "NAN" or if any of the inputs are "NAN". In this embodiment, the approach described below is adopted.

[0054] 5 shows a word format 500 for expressing numerical values ​​used in this embodiment. This word format 500 includes one NAN bit 502a and a sign 502b for the value. It has one bit 502b that gives the logarithm, and 12 bits 502c-e that give the logarithm. The bits representing the logarithm have a 5-bit integer part 502d and a 6-bit fractional part 502e. To allow for the representation of negative logarithms, the bits representing the logarithm have a logarithm sign bit 502c, which is represented in two's complement format. The NAN bit 502a is set if there is a problem with the calculated value. The word format 500 shown in FIG. 5 is merely exemplary and does not limit the scope of the invention. Other variations than those described here can be used, as long as they have low precision and high dynamic range.

[0055] FIG. 6 shows an example of the LPHDR calculation unit 408 in a digital form corresponding to the display format shown in FIG. 5. The LPHDR calculation unit 408 receives two inputs A 602a and B 602b and outputs one output 602c. The inputs 602a-b and the output 602c may take the form of electrical signals representing numerical values ​​according to the display format shown in FIG. And the inputs 602a-b and the output 602c are real signals sent within the LPHDR calculation unit 408 by the components of the LPHDR calculation unit 408. Each of the inputs 602a-b and the output 602c consists of a numeric bit and a NAN bit. The LPHDR calculation unit 408 is controlled by control signals 412a-d sent from the control unit (CU) 106. The control signals 412a-d are then used to control the inputs 602a-b. In this embodiment, the inputs 602a-b All applicable arithmetic operations are performed in parallel on L by an adder / subtractor 604, a multiplier 606, and a divider 608. The adder / subtractor 604 performs LPHDR additions and subtractions, and the multiplier 606 performs L PHDR multiplication, and divider 608 performs LPHDR division.

[0056] The desired result is multiplexed (from the outputs of adder / subtractor 604, multiplier 606, and divider 608). The right multiplexer (MUX) 610b routes the desired value to output 602c. The left multiplexer (MUX) 610a routes the desired process to output 602c. The NAN bit information obtained from the process is sent to an OR gate 612, which outputs NAN if any of the inputs are NAN or if a NAN occurs during a particular calculation process. The literature on computer architecture discusses many variations that can be incorporated into the embodiment shown in FIG.

[0057] In the logarithmic system (LNS), multiplication (MUL) and division (DIV) are very easy. It has the enormous advantage of using fewer physical resources (less silicon area). The sign of the result is the exclusive OR of the signs of the operands. The logarithmic part of the output is the sum of the logarithmic parts of the operands in the case of multiplication (MUL) and the difference of the logarithmic parts of the operands in the case of division (DIV). The sum and difference of logarithms can overflow, resulting in NAN. Operations in the logarithm system (LNS) also make other operations easier. For example, taking a square root corresponds to dividing the logarithm by 1 / 2, which in the above representation is simply a shift of one bit to the right.

[0058] Thus, multiplier 606 and divider 608 in FIG. 6 will be implemented as circuits that simply add and subtract inputs that are binary complements (which happen to be logarithmic). If the number overflows, they will output 1 as NAN. There are.

[0059] To perform addition and subtraction in the logarithmic system (LNS), i.e., the adder / subtractor 604 in FIG. ,This is done following a common approach used in the literature on logarithmic systems (LNS). Consider addition: Consider two positive numbers B and C, whose logarithms are b and c. The sum of B and C is expressed as log(B+C). The approach to calculating this result is well known to those skilled in the art and is based on the following notation: Log(B+C)=log(B*(1+C / B))=log(B)+log(1+C / B)=b+F(cb) where F(x)=log(1+2^x) Thus, in this embodiment, using standard digital techniques well known to those skilled in the art, cb is calculated, substituted into F, and the result is added to b.

[0060] Much of the published literature on logarithm systems (LNS) is concerned with how to compute F(x), a special function for addition (ADD), and a similar function for subtraction (SUB). These two functions often share circuitry, and this is why Figure 6 shows This is why a single combined adder / subtractor 604 is used in the embodiment shown in There is a large body of published literature describing how to compute or approximate these functions, and how to handle the cases where the values ​​are less accurate. Any of these or other techniques can be used. In general, there are more suitable methods for performing massively parallel LPHDR computations. The approach minimizes the use of resources such as circuit area and is shown in the embodiment of FIG. The representations used in are low precision and the computations performed are deterministic. It does not have to be definitive (determined as one definitive), but it is best to use it in a low-precision display. Benefit from the fact that it need not return an exact answer, and therefore embodiments of the present invention may use circuitry that does not calculate the best answer, but rather selects from a limited set of options that are applicable to lower precision representations.

[0061] To allow conditional processing of selected processing elements (PEs), in this embodiment, the calculation result So that the mask flag 410 can be reset or set based on The mechanism for doing this is the control unit (CU) 106. To perform basic tests on values ​​coming into mask 410 through data path 402f. With this instruction, the flags of the mask 410 in each processing element (PE) are reset or set. 4. An instruction to copy the sign bit or NAN bit of the data coming in on data path 402f to mask bit 410 is issued and a flag is set. Example instructions provided below include an instruction to copy the sign bit or NAN bit of the data coming in on data path 402f to mask bit 410. Another example is to set mask bit 410 if the 12-bit numeric portion of the data on data path 402f is equal to binary zero. There are many additional and alternative ways to perform the above operations that are similar to compare instructions in conventional processors and are known to those skilled in the art.

[0062] The LPHDR operation is performed in a trivial manner using the logarithm system (LNS) processing described above, but programmers may consider converting selected numbers to 12-bit binary complement numbers. Multiplication (MUL) and division (DIV) are performed using the logarithm system (LNS) to determine the accuracy of the results. For this reason, such numbers can be used to add and subtract. The set mask command can compare these simple binary numbers. Thus, in addition to performing the LPHDR calculation, this digital implementation using the logarithm system (LNS) can also perform short signed integers. Simple binary arithmetic can be performed on numbers.

[0063] Some embodiments of the invention may provide analog representations and processing schemes. In such embodiments, LPHDR values ​​may be represented, for example, as charge, current, voltage, frequency, pulse width, pulse density, various forms of spikes, or other forms not characteristic of conventional digital implementations. Mechanisms for processing values ​​so represented may be provided. As with other implementations, such representations have been widely discussed in the literature. These implementations, called analog implementations, can be used to perform LPHDR operations on a wide range of architectures, such as the ones discussed here, e.g., SIMD, as an example. do.

[0064] An example of an analog SIMD architecture is Dudek's SCAMP design (and related designs), where numbers have low dynamic range and are accurate to within 1%. The numbers are represented by the charge on a capacitor. These capacitors are typically the gates of transistors. Each processing element (PE) contains several memory cells, similar to the registers shown in Figure 4. Addition is performed by turning on the pass transistors from the two operands, which transfer their charge to the analog bus and are summed together using the natural properties of charge and wiring. The two are summed up by a physical phenomenon, then transferred to another resistor by opening the circuit to charge the capacitor, and the sum of the two is displayed. While the exact mechanism would actually produce a negative sum, the basic concept is as described here, using an analog display and a simple processing mechanism to perform addition and subtraction in a straightforward manner.

[0065] Variations of the SCAMP design architecture have been produced and are relevant for image processing. In the field of imaging, low-precision, low-dynamic-range processing has been used. The SCAMP design architecture is The Dudek design architecture does not perform analog-based operations, nor does it provide any mechanism for multiplying or dividing values ​​stored in registers. This suggests the possibility of constructing a SIMD machine of this type. The following describes one embodiment of the present invention, which is a method for constructing an analog SIMD machine that executes LPHDR calculations. I will explain it below.

[0066] In one embodiment of the present invention, numbers are represented as a hybrid of analog and digital formats. In this embodiment, numbers are represented as low precision, normalized, floating point numbers with a minimum of 2. It is expressed as a point, with the mantissa being an analog value and the exponent being a binary digital value. The analog values ​​are accurate to about 1% and are based on the Dudek approach, where the accuracy is the same as that of the analog processing. This is well within the reasonable limits of science and technology. The exponent is 6 bits long. , or however long is necessary to provide the required high dynamic range.

[0067] To multiply numbers, the present embodiment works by analogy to conventional floating-point multiplication: the exponent, which is a digital value, is multiplied by the standard digital technique of binary arithmetic. These are summed using an adder. The mantissas, which are analog values, are multiplied. Since these represent normalized numbers between approximately 1 / 2 and 1, their product is a small number, approximately 1 / 4. The value of such a product must be renormalized to the range 1 / 2 to 1. In this embodiment, this is done using a threshold circuit that compares the analog value of the mantissa with an analog representation of 1 / 2. If the analog value of the mantissa is less than 1 / 2, The mantissa is doubled and one is subtracted from the exponent, which is a digital value. This subtraction is then a simple digital subtraction. Doubling the analog mantissa reduces the selected analog value. This is done in a way that corresponds to the log display. For example, it can be used to add two analog values. Whatever the means used, it can be used to double the mantissa by adding a copy of the mantissa to the mantissa. For example, if the mantissa is an analog value, If represented as currents, copies can be made using a current mirror or other suitable mechanism, and summation can be performed by providing current summing junctions.

[0068] The means by which the original analog value mantissa is multiplied depends on the representation chosen. For example, if the analog value mantissa is represented by charge according to SCAMP, In this case, methods known in the literature can be used to convert the charges to currents. For example, since the charge on a capacitor will determine the voltage on the capacitor, the conversion of the charge to current can be performed as a voltage to current conversion, and this technique is a basic technique well known to those skilled in the art of analog electronics. In either case, if the analog value mantissa is represented as a current or once the mantissa has been converted to a current, the multiplication of the mantissas can be performed using, for example, the Gilbert technique. The Gilbert multiplier creates a current representing the product and, if necessary, converts the current product to a charge (or whatever current is being used). The above can also be converted back to any representation that is acceptable. This is merely an example to show how the processing needs to be performed - the literature has extensively discussed this and analog circuits of this kind are well known to those skilled in the art.

[0069] Adding and subtracting numbers requires that the numbers be pre-normalized to have the same exponent, as is done in conventional digital floating point arithmetic. In this embodiment, normalization is performed by comparing the exponents and choosing the one with the smaller exponent. The smaller exponent is subtracted from the larger exponent using digital means. This difference is determined by how many times the mantissa of the number with the smaller exponent needs to be divided by 1 / 2. If the mantissa is expressed as a current (or converted to a current), If the ladder is specified by the difference in exponents calculated as above, Analog R-2R type to divide the current by 2 as many times as necessary, corresponding to the number of floors. A ladder of expressions can be used. The resulting scaled down current is added (or subtracted if this is an LPHDR subtraction operation) to the current corresponding to the mantissa of the number with the larger exponent to produce the output mantissa. The output exponent corresponding to the mantissa that is output is the larger exponent. At this point, a post-normalization step is required. If the output mantissa is greater than 1, The mantissa needs to be divided by 1 / 2 and the output exponent needs to be incremented by 1. If the output mantissa is less than 1 / 2, the mantissa needs to be multiplied by 2 as many times as necessary until it exceeds 1 / 2. The output exponent is then incremented by the corresponding The exponent of the binary digital form must be incremented or decremented by a number equal to the number of times the number was counted. This is accomplished by a series of threshold, doubling, and decrement circuits. and the corresponding doubling or halving of the analog mantissa current are simple processes well known to those skilled in the art.

[0070] In this embodiment, the exponent is represented in digital form as a binary number. The exponent can also be represented as an analog value. However, it is especially important that the exponent be represented in such a way that it does not introduce noise or error that would cause fluctuations in the number representing the exponent when stored and calculated. Such fluctuations in the exponent would result in a factor of two changes in the value of the stored number. One embodiment for storing the exponent is to store it at a relatively small level, e.g., 16 bits + sign. In this embodiment, the floating-point numbers can be quantized to 16 bit exponent bits. Any slight fluctuations introduced during processing into the analog representation of the exponent can be removed by circuitry that stores the numbers in a standardized quantization level of 16 bits. In order to obtain sufficient dynamic range in such an embodiment, the floating-point numbers are represented as For example, this means that the normalized mantissa is in the range 1 / 4 to 1. The addition, subtraction and multiplication operations described here can be done in just This results in small but simple fluctuations.

[0071] The above-mentioned embodiment using analog mixed signals is merely illustrative and is not intended to constitute a limitation of the present invention. Literature publications related to neuromorphic and analog mixed signal techniques have been described that may be implemented in LPHDR computations. The authors provide a wide variety of storage and processing techniques that allow the operation of the machine that performs the LPHDR calculation to be affected by assembly errors as well as by the number of steps required. Noise is also introduced. Although the results obtained in running software applications using the "fp+noise" algorithm, as described below, have a very "non-digital" quality, a machine built in this way is surprisingly usable.

[0072] Evidence that LPHDR arithmetic is useful in practice for several important computing applications Evidence exists that a wide variety of embodiments of the present invention are effective, but this effectiveness is not dependent on the details of the implementation.

[0073] For the purpose of illustrating the effectiveness of the LPHDR computation, a very general example of an LPHDR machine is chosen. A model of such a machine would provide at least the following capabilities: (1) massive parallelism, (2) the ability to provide potentially noisy LPHDR computations, (3) a small amount of local memory for each computational unit, and (4) a two-dimensional model with only local connections between units (connections that are not powerful, flexible, or sophisticated). (5) a machine with only limited bandwidth between the machine and a host machine; It should be noted that the model is illustrative only to demonstrate the validity of variations of the embodiments of the present invention, and is not intended to be limiting of the present invention. The model may be implemented in digital, analog, or a combination of both, with zero or no noise, with architectures such as FPGA, SIMD, MIMD, and architectures that conform to the model's assumptions, and may be implemented in general, such as shared memory designs, GPU-like designs, or other sophisticated designs. More advanced architectures incorporate the capabilities of this model, making LPHDR operations even more useful on these architectures. We show here that LPHDR operations are useful for a wide range of designs, but SIMD within a wide range of designs is shown as an example for the following discussion, with each unit referred to as a "processing element" or "PE", and each unit combining memory and computation.

[0074] Several applications are described below. For each application, we argue that (1) the results are valid when the calculations are performed in a noisy LPHDR operation, and (2) the calculations are organized in a two-dimensional physical layout with only local data exchange between each unit, limited to memory within each unit, and limited to data exchange with the host machine. This results in calculations that use machine resources (area, time, and power) efficiently. The first requirement is about "accuracy" and the second requirement is about "efficiency". Applications that satisfy these two requirements and run on this model are expected to function adequately on many types of LPHDR machines. Ming's machines can be put to a wide range of effective uses.

[0075] The application was tested by running two implementations of the machine. The first implementation performs exact floating point arithmetic, but multiplies the result of each operation by a uniformly chosen random number between 0.99 and 1.01. In the following discussion, this implementation will be denoted as "fp+noise". represents the result calculated by the machine according to an analog embodiment.

[0076] A second example uses logarithmic arithmetic, with the numbers in the format shown in FIG. The calculations are repeatable, i.e., noise-free, but due to the small size of the fraction, there is an error of up to about 1-2% in each step. In the following discussion, this embodiment will be denoted as "lns." This embodiment specifically represents the results calculated by a machine according to the digital embodiment.

[0077] To demonstrate the usefulness of the embodiments of the present invention, three computational tasks that can be performed by the embodiments of the present invention and that can have a variety of practical applications are described below. Two of the tasks are related to nearest neighbor search, and the remaining one is related to processing visual information. Below, we describe the tasks, then discuss their practical applications, and then demonstrate that each task can be computed using the general model described above and by applying the embodiments of the present invention. Application 1: Nearest Neighbor Search

[0078] We are given a large set of vectors, which we'll call "Examples". Let's call one vector "Test". The goal of the neural network (NN) is to find the “Example” that is closest to the “Test”, where the metric distance is the squared Euclidean distance (the sum of the squared distances between each component).

[0079] Neural networks are useful and widely used computations. One application is in the field of data compression, where it is called "vector quantization." In this application, we prepare a set of relatively long vectors in a "code book" that are associated with short "code words" (these are the Examples). We walk through the set of vectors to be compressed, and for each Test vector, we find the closest vector in the code book and output the corresponding code word. This results in a set of vectors that are The vectors are reduced to a short sequence of code words. Because the code words do not completely specify the original sequence of vectors, this approach is a lossy form of data compression. Other applications include audio compression and the MPEG standard.

[0080] Another application of NNs is to determine whether video fragmentation occurs in a large video database. Here, images from a video fragment are summarized into feature vectors using known techniques such as color histograms and scale-invariant feature extraction. Here, Examples are similar feature vectors extracted from the video database. We want to know if any vector from the video fragment was close to any vector from the video database, and NNs are useful in making such decisions.

[0081] In many applications of nearest neighbor searching, it is preferable to find the true nearest neighbor, but it is acceptable if most of the time you find the true nearest neighbor, and occasionally find another neighbor that is slightly further away. Thus, approximate solutions to the nearest neighbor problem are also useful, especially if they can be computed particularly quickly, or with low power, or have some other advantage over obtaining an exact solution.

[0082] In the following, we show that it is possible to apply an embodiment of the present invention to find approximate nearest neighbors in a way that satisfies the criteria for "accuracy" and "efficiency".

[0083] algorithm The following describes an algorithm that may be executed by a machine implemented in accordance with an embodiment of the present invention, and is implemented by executable software that includes instructions for carrying out the algorithm. The input to the algorithm is a set of The Examples and Test vectors are then used. The algorithm then finds the closest (or It finds the closest (or approximately closest) Example.

[0084] In the simplest version of the algorithm, the number of Examples is equal to the number of Processing Elements (PEs). The vector must not exceed 1, and each vector must be small enough to fit in the memory of a single processing element (PE). Examples are placed in the memory of the processing elements (PEs), with one Example placed in each processing element (PE). When a Test is given, it is designed to pass through all the processing elements (PEs) in order. Since the Test is designed to pass through the processing elements (PEs), by accompanying the Test, it is possible to determine which processing element (PE) (and therefore which Example) is the closest Example, and the distance from the Test to the closest Example. Each processing element (PE) has a relationship between Test and the Example stored in the memory of the processing element (PE). Calculate the distance of and forward the Test along with the distance and the passed indicator into this PE ( the distance calculated by this PE exceeds the distance passed to this PE), or , along with information indicating that this PE's Example is the closest. The distance calculated by this PE is forwarded to this PE along with the Test. distance). Thus, the algorithm results in simple, minimized processing as Test passes through a set of processing elements (PEs). When Test and associated information leave the last PE, the output contains an indication of which PE (and therefore which Example) is closest to Test, along with the distance between Example and Test.

[0085] In a more efficient variant of this algorithm, the Test is forwarded first, for example from the top row, and an efficient search is performed in parallel with the other columns, sending the Test and associated information downwards through all of the columns. Then, once the information reaches the bottom of the columns, it calculates the minimum distance of the Example for all columns being processed, as long as the information is propagated across the bottom of the columns. is the time required to process a Test, expressed as the number of processing elements (PEs) in a row and column. This means that it is proportional to (highly dependent on)

[0086] The enhancements to this algorithm are done as described above, but the enhanced algorithm adds information indicating both the nearest and second nearest Examples found. When this information leaves the array of processing elements (PEs), The digital processor managing the Processing Element (PE) array calculates (with high precision) the distance between Test and the two Examples represented by the Processing Element (PE) array, and the closest of the two is output as it appears to be the closest neighbor of Test.

[0087] accuracy It is coded in C and is implemented by the enhanced algorithm described above. This code calculates the nearest neighbors mentioned above, along with a weighted score as described below.

[0088] The C code represents the operations that would be performed in actually implementing the invention as implemented in hardware. The C code performs the same set of calculations, of the same order, using the same methods as the algorithms used in the present invention. Thus, the C code will produce the same results as the enhanced algorithms used in the implementation of the present invention. (In doing so, it is important to operate efficiently.) (How the algorithm is organized to achieve this is explained in the section discussing "efficiency".)

[0089] In particular, when calculating the distance between Test and each Example, the calculation required to calculate the sum of the squares of the distances between the vector components of Test and Example can result in a long sum of numbers, so the C code uses Kahan's method, as described below.

[0090] This C code contains several execution procedures for the calculations, as described above. When compiled with "#define fp", arithmetic is performed using IEEE standard floating point. If a command line argument is given to enable arithmetic in noise, random noise will be added to the result of each calculation. This is called "fp+noise". " style arithmetic. When compiled without "#define fp", the arithmetic is performed using low precision logarithmic arithmetic with a low of 2 and 6 bits of fraction. This is the "lns" style operation.

[0091] When this code is run, it produces output that shows the results of the calculations it performed. These outputs show that, depending on certain command line arguments, as explained below, the enhanced algorithm produces LPHDR nearest neighbor calculations. These results demonstrate the feasibility of this approach and are briefly discussed here.

[0092] The first result is for the "fp+noise" format. Ten distinct runs were performed. In each run, one million random example vectors were used. Example vectors of length 5 were generated by using the above formula. Each component of each vector was determined based on N(0, 1), where N(0, 1) is a Gaussian (normal) distribution. This means that the mean is zero and the standard deviation is one. Furthermore, for each run, 100 test vectors of length 5 were generated, and each component of each vector was determined based on the same N(0, 1). For each test, the nearest neighbor was calculated in two ways. One was using the enhanced algorithm described above, and the other was using the standard "nearest neighbor search method" with high precision and floating point arithmetic. The enhanced algorithm gave the same results as the standard floating point method. The results are shown below. % . / a.out 5 10 1000000 100 1 The representation format is floating point, and there is noise. Run 1: 100 tests were run, 100 (100.0%) conformance, 0.81% average score error Run 2: 100 tests were run, 100 (100.0%) conformance, 0.84% ​​average score error Run 3: 100 tests were run, 100 (100.0%) conformance, 0.98% average score error Run 4: 100 tests were run, 100 (100.0%) conformance, 0.81% average score error Run 5: 100 tests were run, 100 (100.0%) conformance, 0.94% average score error Run 6: 100 tests were run, 100 (100.0%) conformance, 0.82% average score error Run 7: 100 tests were run, 100 (100.0%) conformance, 0.78% average score error Run 8: 100 tests were run, 100 (100.0%) conformance, 0.86% average score error Run 9: 100 tests were run, 100 (100.0%) conformance, 0.85% average score error Run 10: 100 tests performed, 99 (99.0%) correct, 0.86% average score error Here, the average percentage of times that the LPHDR operation found the closest Example (finally, DP (corrected by) = 99.90% The average score error between LPHDR calculation and DP is 0.85%.

[0093] The value of the "average score error" will be explained in the discussion of "weighted scores" below. "what is appropriate" means

[0094] 10 calculations were performed, and only one of the tests was targeted for the calculation. The closest neighbors obtained by performing the calculations for the 100 tests were obtained by the conventional high-precision method. Therefore, the calculation of the "fp + noise" format The average percentage of conformance between the enhanced algorithm and the standard high-precision method was 99.9%.

[0095] A similar calculation was then performed using the "lns" style of operation, the results of which are shown below. vinegar. % . / a.out 5 10 1000000 100 0 The expression format is lns format, and it is noise-free. Run 1: 100 tests were run, 100 (100.0%) conformance, 0.15% average score error Run 2: 100 tests were run, 100 (100.0%) conformance, 0.07% average score error Run 3: 100 tests were run, 100 (100.0%) conformance, 0.08% average score error Run 4: 100 tests were run, 100 (100.0%) conformance, 0.09% average score error Run 5: 100 tests were run, 100 (100.0%) conformance, 0.11% average score error Run 6: 100 tests were run, 100 (100.0%) conformance, 0.16% average score error Run 7: 100 tests were run, 100 (100.0%) conformance, 0.07% average score error Run 8: 100 tests were run, 100 (100.0%) conformance, 0.13% average score error Run 9: 100 tests performed, 99 (99.0%) correct, 0.17% average score error Run 10: 100 tests performed, 98 (98.0%) conformance, 0.16% average score error Here, the average percentage of times that the LPHDR operation found the closest Example (finally, DP (corrected by) = 99.70% The average score error between LPHDR calculation and DP is 0.12%.

[0096] The results showed that the average percentage of conformance was 99.7%, slightly worse than the "fp+noise" format.

[0097] The accuracy shown by the improved algorithm for nearest neighbor search using two forms of LPHDR calculation was surprising. Performing many calculations in succession with 1% error and still achieving a final result with an error of less than 1% is unheard of based on past experience. Nevertheless, the LPHDR calculation proved to be efficient, The accuracy obtained was high enough to be useful in applications where computational methods for finding near-nearest neighbors are useful.

[0098] As an extreme case, we evaluated the “fp+noise” transformation method. In this case, the noise changes smoothly between +10% and -5%. Each calculation produces results ranging from 10% very large to 5% very small. The above-mentioned algorithm for nearest neighbor search was implemented. Here, 100,000 example vectors were generated for each calculation. As a result, Useful even in the extreme conditions of imprecise, noisy, non-zero mean LPHDR computation The surprising result was that such a result could be achieved. Run 1: 100 tests performed, 97 (97.0%) conformance Run 2: 100 tests performed, 100 (100.0%) conformance Run 3: 100 tests performed, 100 (100.0%) conformance Run 4: 100 tests performed, 98 (98.0%) conformance Run 5: 100 tests performed, 98 (98.0%) conformance Run 6: 100 tests performed, 99 (99.0%) conformance Run 7: 100 tests performed, 99 (99.0%) conformance Run 8: 100 tests performed, 99 (99.0%) conformance Run 9: 100 tests performed, 99 (99.0%) conformance Run 10: 100 tests performed, 99 (99.0%) conformance Here, the average percentage of times that the LPHDR operation found the closest Example (finally, DP (corrected by) = 98.80%

[0099] efficiency It will be apparent to those skilled in the art that the computational model presented here is efficient in implementing the enhanced algorithm for nearest neighbor search, with surprising accuracy results. The units are connected in a two-dimensional physical arrangement, using only local communication between the Processing Elements (PEs), but this means low bandwidth to the host machine, and is not intended to keep the machine busy doing useful work.

[0100] When computing the nearest neighbor search for a single Test, the Test passes through all the Processing Elements (PEs) in the array. As mentioned above, if the array is an MxM grid, then it takes at least O(M) steps for the Test to pass through the machine and return the result to the host machine. During this time, the machine takes O(MxM) steps to compute the distance between the nearest neighbors. However, at each step, the machine is capable of performing O(MxM) steps of computation, so the factor of O(M) steps is lost.

[0101] Compared to serial machines, such machines offer speedups, where a factor of O(M) steps becomes significant and useful, and more efficient. If we have to process a sufficiently large number of test vectors, so-called O(M) steps, or even more test vectors, they will flow into the machine and form a pipelined stream. The time to process an O(M) step test is still O(M) steps, the same as the time for a single test. But now the machine will perform distance calculations in O(M) x O(MxM) steps, and so will increase by a constant factor. However, all of the machine's computing power will be used.

[0102] A machine will be particularly efficient if it can process as many Test vectors as the square root of the number of Processing Elements (PEs). There are applications that are well suited to this form. Such applications include finding the closest match for each Example in a set of Examples. As well as problems of finding neighbours, there are problems with pattern recognition and compressing many independent tests (e.g. blocks of an image, parts of a file, independent stock price histories, etc.). What is being said here, as mentioned above, goes against the view of those skilled in the art that machines with a large number of processing elements on a single chip, or the like, are not useful. Application 2: Distance-weighted scoring

[0103] A related task to the nearest neighbor problem is distance weighted scoring. In this task, each Example has an associated score, which is a numerical value that characterizes the Example in some way. For example, if the Examples are a sample of the price history of a given stock, the score might be the history of the likelihood that the stock price is likely to go up or down. Given a Test vector, the task is to find a weighted sum of the scores of all the Examples, where the weights are a decreasing function of the distance from the Test to each of the Examples. For example, the weighted score might be treated as a prediction of the future price of the stock whose history is represented by the Test. Such application of embodiments of the present invention may support high speed trading of stocks, such as that performed by quantitative hedge funds, and this is contrary to the view held by those skilled in the art that low precision calculations are not valid for financial applications.

[0104] The C code above calculates the nearest neighbor search and also calculates the weighted score. The scores assigned to Examples in this computation are drawn from the range [0, 1]. The weight for each Example in this calculation is defined as the unnormalized weight for the Example divided by the sum of the unnormalized weights for all Examples. The unnormalized weight for each Example is defined as the inverse of the sum of the squared distance from the Example to the test vector plus 1. As mentioned above, the C code is Perform numerical calculations, derive many Examples and Tests for the calculations, and then use "fp+ Results calculated using the "noise" and "lns" formats compared to traditional floating-point calculations. The results were compared with the calculation results.

[0105] Looking again at the output results from the simulation above, the "fp+noise" format The average weighted scores for the LPHDR calculations using the 'lns' format were within 0.85% of the corrected value and did not exceed 1%. For the 'lns' format calculations, the error was very small. , the error on average was just 0.12%.

[0106] These results are surprising, as the weighted score calculation requires It indicates that the sum of the individual weighted scores involved is included. Since a million Examples are processed in each run, this means that the sum is over a million small positive values. A simplistic method of summing a million small values, with an error of about 1% on each addition, would produce a noisy result due to the rough estimate. However, this C code uses the same algorithm as Kahan (Kahan, William (January 1965), "Truncation "Notes on Reducing Errors" Communications of the ACM 8(1):40) and was invented by The summation is done using a method that has been known for some time, which allows for long summations that can be used in computing distance-weighted scores, or in financial engineering, such as for pricing derivative securities using Monte Carlo methods, or to perform deconvolution in image processing algorithms, as described next.

[0107] The efficiency of this algorithm is similar to that of the NN algorithm, as mentioned earlier: if many test vectors are processed at once, the machine performs the task particularly efficiently. Application 3: Removing motion blur in images

[0108] To gather enough light to form an image, cameras often keep the shutter open for long periods of time, which results in "blurring" caused by camera movement. Apart from moving cameras on satellites and aircraft, cheap consumer cameras as well as very expensive cameras can produce this "blurring" as a result of camera shake. If the camera's path is known (or can be calculated), If possible, the blur can be removed using various deblurring algorithms. By using a method that uses a set of algorithms, the noise generated by the inputs can be substantially eliminated. One such algorithm is the Richardson-Lucy method (referred to as the "RL method"). Here, we show that an embodiment of the present invention can implement an algorithm based on the Richardson-Lucy method and derive useful results. Following the description of the format of the algorithm above, we discuss criteria for accuracy and efficiency.

[0109] algorithm The Richardson-Lucy algorithm is well known and widely used. In this method, we assume that the image is blurred by a known kernel. In particular, we assume that this kernel is rectilinear, and that the image is oriented such that the "blurring" occurs purely horizontally. The Jth pixel in each column of the blurred image is A particular kernel for pixels is taken from the Jth to the J+31th pixels of the unblurred image. It is considered to be a uniformly weighted average of

[0110] accuracy A simple version of the RL method using the LPHDR algorithm in the C programming language. The calculations were performed using a program that loaded a test image, blurred it using the kernel as described above, and then deblurred it using either the "fp+noise" or "lns" style of algorithm. The sum was calculated using the RL algorithm as the kernel was convolved with the current approximation of the deblurred image. To perform the calculations, as mentioned at the beginning, Kahan's We used the method to calculate these sums. Figure 7 shows the original and The test image is a satellite image of the building used for Barack Obama's inauguration. Figure 8 shows the image that has been made extremely blurry by the kernel. In this image, it is not possible to distinguish any particular object. Figure 1 shows the result of deblurring using standard floating-point arithmetic. Figure 10 shows the result of deblurring using "fp+noise" style arithmetic. And Figure 11 shows the result of deblurring using the "lns" style operation. In all these cases, the images were resaved, with buildings, roads, parking lots, and cars being identifiable.

[0111] In addition to displaying the images for human eye judgment, we also calculated a numerical characteristic of the deblurring performance by calculating, for every pixel in the image, the average difference between the original pixel value (a grayscale value between 0 and 255) and the corresponding pixel value in the image reproduced by the RL method algorithm. The resulting numerical characteristic is shown in Table 1 below.

[0112] [Table 1]

[0113] These results, and the subjective but important human eye judgment, indicate that LPHDR calculation This shows that substantial and useful deblurring is possible compared to standard floating-point arithmetic. Furthermore, this example shows the visualization of deblurring using LPHDR arithmetic. We have chosen an extremely blurred image to better convey its impact and concept. With a more gentle, general kernel blurring, the resulting blurred image is closer to the original image than the image in this case, and the kernel length is reduced, so running the RL algorithm with LPHDR operation on such an image is much easier. This allows it to be seen as something more general.

[0114] efficiency The Richardson-Lucy method using local kernels performs only local calculations. It is obvious to those skilled in the art that the RL technique is a simple method of deblurring images. The image to be deblurred can be loaded into an array of processing elements (PEs), one or more pixels per PE can be stored, and the deconvolution process can be repeated tens or hundreds of times using the RL technique's algorithm. The deblurred image can then be loaded back into the host processor. As long as the iterations are long enough, the machine can be used efficiently.

[0115] An extreme form of image deblurring is computer tomography. There is an iterative reconstruction method used to reconstruct 3D stereoscopic images from 2D projected images. This is an extremely computationally intensive task. The method described above naturally generalizes to iterative restoration methods, which makes efficient use of machines.

[0116] Advantages of embodiments of the invention may include one or more of the following.

[0117] Processing elements (PEs) implemented according to certain embodiments of the present invention are relatively small as processing elements (PEs) capable of executing operations. This means that the unit resources (e.g., transistors) This means that there are many more Processing Elements (PEs) per unit of memory (star, area, volume, etc.), which means much more computational power per unit of resource. This allows larger problems to be solved for a given range of resources compared to traditional computer designs. For example, a digital embodiment of the present invention built as a large silicon chip assembled with modern technology could have up to 10 ... A conventional GPU can perform tens of thousands of operations per cycle, compared to hundreds per cycle for a conventional GPU and only a few operations per cycle for a conventional multi-core CPU. These operation ratios reflect the architectural advantages of embodiments of the present invention, which remain as building blocks of technology that are continually being improved, even as we reach nanotechnology and the art of performing calculations in digital and analog ways.

[0118] Generally speaking, performing operations with few resources, and as clearly shown in the embodiments, means that the power used for the operations is small. As a result, a machine implemented by the embodiments of the present invention can have a reasonable power usage (e.g., tens of watts). Either extremely high performance or low power consumption (e.g., a fraction of the power This means that the embodiment is a super This means that the system is suitable for the full range of computers, from mobile computers to desktop computers to mobile computers. Similarly, since cost is generally related to the amount of resources available, embodiments of the present invention are able to provide a relatively large amount of computing power per unit cost compared to traditional computing devices.

[0119] SIMD architectures are quite old and have been abandoned by most people in the art as a way of approaching computer design. However, SIMD architectures can be useful if they retain important features such as general computational power, and the processing elements of a SIMD machine can be made particularly small. The example presented here possesses exactly these qualities.

[0120] Despite the general view that large-scale LPHDR calculations are not useful, The discovery that the LPHDR algorithm is useful as a very general computational framework has been The implementation of SIMD machines is not limited to these, but can be effectively leveraged on any parallel processing machine (large or small). Large-scale LPHDR operations can be implemented on FPGAs, FPAAs, GPUs / SIMD machines, and other machines that use small resources (transistors, volume, etc.) to perform large amounts of computation. The present invention can be used in any kind of machine using compact processing elements for executing the above.

[0121] Another advantage of embodiments of the present invention is that they can be used to address a variety of practical problems that are generally not useful because they perform computations efficiently, but which would typically require high-precision computing elements. Even if embodiments of the present invention have only low-precision computing elements (or the majority of the computing elements are low-precision), Even if the accuracy is low, the above can be said. Although some examples have been described, and successful implementations of non-bonded force field calculations in molecular dynamics simulations and other tasks have been demonstrated, these are merely illustrative and do not limit the scope of practical problems that can be solved using embodiments of the present invention.

[0122] The disclosed embodiments are merely illustrative and not limiting of the invention, but rather, the embodiments of the invention can be practiced in a variety of other ways, such as:

[0123] For example, embodiments of the present invention may represent values ​​in any of a variety of ways, including using digital or analog representations, fixed point, logarithmic, or floating point representations, voltage, current, charge, pulse width, pulse density, frequency, probability, spikes, timing, or combinations thereof. Such inherent representations may be used individually or in combination to represent the value of LPHDR. The LPHDR computation circuitry may be implemented using a variety of digital formats (parallel or serial, pipelined or otherwise). among various methods such as digital, analog, or a combination of these. The calculation elements are the four nearest neighbors, the four nearest neighbors, There must be eight adjacent ones, various types of stepping stones, or triangles or grids. The computing elements may be connected using a variety of connection architectures, such as architectures that use parallel or serial, digital or analog, or a combination of these modes. Any method may be used to communicate between the computing elements, such as using parallel or serial, digital or analog, or a combination of these modes. The computing elements may operate synchronously or asynchronously, and may operate entirely simultaneously or not entirely simultaneously. The computing elements may be implemented on a single physical device, such as a silicon chip, or on multiple, dispersed devices. And embodiments built from multiple devices may have computing elements connected in a variety of ways, including, for example, in a grid, truss, hypercube, tree, or other manner. The computing elements may be connected to a host machine in a variety of ways, based on cost, bandwidth, if any, and other requirements for a particular embodiment. For example, there may be many host machines connected to a collection of computing elements.

[0124] Although certain embodiments of the present invention are described as being implemented in a SIMD architecture, this is by way of example only and is not intended to be limiting. For example, embodiments of the present invention may be implemented in a reconfigurable architecture, such as, but not limited to, a programmable logic device, a field programmable analog array, or a field programmable gate array architecture, including those designed to replace or supplement existing multiplier blocks in an FPGA with any of the types of LPHDR computational elements disclosed herein. or LPHDR computing elements are contained within new or existing reconfigurable devices. As another example, embodiments of the present invention may be implemented in a GPU or SIMT type architecture, which may include: Any type of LPHDR computation element disclosed herein may be incorporated. LPHDR elements can replace or complement conventional elements used in current or new graphic processing unit designs. In another example, embodiments of the present invention may be implemented as a MIMD type architecture incorporating any of the types of LPHDR computing elements disclosed herein. For example, current or new MIMD computers may be implemented as a MIMD type architecture. The LPHDR computational elements replace the traditional computational elements used in computer system design. Further, in another example, embodiments of the invention may be implemented as any type of machine, including a massively parallel processing machine. These massively parallel processing machines use compact computing elements to provide massive amounts of computing power using fewer resources (e.g., transistors, area, volume, etc.) than traditional architectures.

[0125] Although certain embodiments of the present invention are described herein as implementing software, this is by way of example only and is not intended to be limiting. For example, embodiments of the present invention may include a multi-threaded processor that implements a multi-threaded processor to control any of the types of LPHDR computing elements disclosed herein. For example, embodiments of the present invention may be implemented using a hardwired controller to control any of the types of LPHDR computing elements disclosed herein. , burned-in or pre-programmed controllers can be used to This can be done.

[0126] Although certain embodiments of the present invention have been described as being implemented using custom silicon as the hardware, this is by way of example only and is not intended to be limiting. For example, embodiments of the present invention may be implemented using FPGAs or other reconfigurable chips as the underlying hardware. The reconfigurable chip is configured to perform the LPHDR processing disclosed herein. As another example, embodiments of the present invention may be implemented using programmable, conventional digital or analog computing architectures, including those using high precision computing elements or other types of non-LPHDR hardware to perform LPHDR operations, as well as those that are massively parallel. This architecture is described here. The LPHDR processing is programmed with software to perform the LPHDR processing disclosed in. For example, , embodiments of the present invention may be implemented using a software emulator of the functions disclosed herein.

[0127] As yet another example, embodiments of the invention may be implemented using 3D fabrication techniques, whether based on silicon chips or other technologies. In some illustrative embodiments, a memory chip may be connected to a processor or another device. or several memory chips and / or processor chips, or Other device chips are stacked and connected to each other. The embodiment of the present invention using the 3D technology is highly useful because it is denser than the embodiment using the 2D technology and enables 3D information communication between processor units. Furthermore, the embodiment using this 3D technology is more efficient and allows advanced functions to be executed than the embodiment using the 2D technology. It is what makes the algorithm possible.

[0128] Although certain embodiments of the present invention have been described as being implemented using silicon chip fabrication techniques, this is by way of example only and is not intended to be limiting. Also, for example, embodiments of the present invention may be implemented using other types of conventional digital and analog computer processors and other devices. Examples of such technologies include various nanomechanical and nanoelectronic technologies, chemical-based technologies such as DNA computing, nanowires and nanotubes, and the like. Any number of technologies, including those based on transistors, optical technologies, mechanical technologies, biological technologies, and other technologies, whether or not based on transistors, may be capable of performing LPHDR operations of the type disclosed herein. It has the following features.

[0129] Certain embodiments of the present invention have been described as using "massively parallel" techniques. While some embodiments of the present invention may include thousands, millions, or more arithmetic units, embodiments of the present invention may also include only a few (or a very small number) of arithmetic units. For example, even embodiments including only a single LPHDR unit may be small, inexpensive, and To provide a large amount of LPHDR processing power for modern processors and other devices. The device can be used in a serial processing unit or other device for this purpose.

[0130] In some embodiments of the invention, even when performed exclusively using digital techniques, the computational process may not produce a result that is deterministic, repeatable, or the most accurate possible result in the selected low-precision representation. For example, for a particular input value, the computational process may produce a result that is not the closest value in the selected representation to the true computational result.

[0131] The degree of precision of a "low precision high dynamic range" element varies depending on the particular implementation. For example, in one embodiment, the LPHDR element produces results that include fractional numbers, i.e., numbers greater than 0 and less than 1. For example, in one embodiment, the LPHDR element produces results that are often (or always) more than 0.05% off the correct result (i.e., the absolute value of the difference between the result produced by the LPHDR element and the correct result is less than 0.05%). (The absolute value of the new result is not more than 1 / 20 of 1%.) As another example, the LPHDR computation element often (or always) produces results that are off by more than 0.1%. As another example, the LPHDR computation element often (or always) produces results that are off by more than 0.2%. Furthermore, as another example, the LPHDR computation element may often (or always) produce the correct result. produces results that are more than 0.5% off. Furthermore, as another example, the LPHDR computation element may often (or always) produce the correct result. produces results that are 1%, or 2%, or 5%, or 10%, or even 20% or more off.

[0132] The degree of accuracy can take various values, but in addition to these, the LPHDR calculation requirements The implementation of the LPHDR computation element varies depending on the dynamic range of the space of numbers the element operates on. For example, in one embodiment, the LPHDR computation element operates on numbers in a space of ranges having a range of approximately one part per million to one million. As another example, in one embodiment, the LPHDR computation element operates on The elements handle numbers in a range space that ranges from roughly one billionth to a billion. As yet another example, in one embodiment, the LPHDR calculation element processes numbers in a range space having a range of approximately 1 in 65,000 to 65,000. As yet another example, in one embodiment, the LPHDR calculation element processes numbers in a range space having a range of approximately 1 in 65,000 to 65,000. As yet another example, an LPHDR computation element in an alternative embodiment may operate on numbers in a range space that ranges from 0 to a particular value greater than 1. It is possible to process numbers in a space with a dynamic range that combines the ranges shown in the previous examples, for example, a range that ranges from roughly one part in a billion to tens of millions. In all of these exemplary embodiments of the present invention, as well as in the examples, the numerical values ​​discussed are signed, and the above discussion deals with the absolute nature of the numerical values ​​to which it refers.

[0133] The frequency of the LPHDR calculation elements, which can only produce an approximation to the correct result, is For example, the LPHDR calculation element may be one or more processes. In an embodiment, the LPHDR calculation element is capable of performing a number of operations (perhaps involving trigonometric functions, for example) in which each of the LPHDR calculation elements is taken from a range of valid values. It accepts a set of inputs and generates one or more LPHDR operators for a given set of input values. or more output values ​​(e.g., taking both the sine and cosine of an input value simultaneously) (such as computing a function with a certain set of input values) In the embodiment of such an example, we further consider the ratio F of the effective input to the relative error magnitude E. This causes the result calculated by the LPHDR calculation element to differ from the mathematically correct result. In one embodiment of the present invention, in each of the LPHDR computing elements, a permissible value for at least one operation that the LPHDR computing unit can perform is For at least a proportion F of valid inputs, at least one The statistical average of the output signals of the LPHDR arithmetic unit over the entire iteration of the operation, when the operation is performed on each input. The statistical average of the represented values ​​differs by at least E from the correct mathematical calculation result for the same input values, where F is 1% and E is 0.05%. In some alternative embodiments, F is not 1% but is either 2%, or 5%, or 10%, or 20%, or 50%. Each of these embodiments has some particular value for F, and a value for E is not 0.05% but is 0.1%, or 0.2%, or 0.5%, or 1%, or 2%. Other embodiments have E values ​​of 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, or 20%. These various examples are merely illustrative and do not limit the invention.

[0134] A device embodied in the present invention (such as a computer, processor, or the like) In some cases, such as other devices, the number of LPHDR computing elements within a device (e.g., a computer, processor, or other device) may be limited to conventional precision (i.e., up to 32 bits). High dynamic range (floating point arithmetic with word lengths of 100 or more bits) Let NL be the total number of LPHDR elements in the device, and NH be the number of LPHDR elements in the device that are designed to perform the high precision operation. The total number of computing elements in a device designed to perform the dynamic range computation, NL, exceeds T(NH), where T( ) denotes a function. Any of a variety of functions can be used as the function T( ). For example, in one embodiment, Then, T(NH) is 20+3xNH, and the number of LPHDR calculation elements in the device is If there were a computing element, the number would exceed 20 + 3 x [the number of computing elements in the device]. The device is designed to perform high dynamic range calculations with conventional accuracy. As another example, in one embodiment, the LPHDR calculation elements in the device The number is 50 + 5 x [number of computing elements in the device] if there are computing elements in the device. where the device is designed to perform high dynamic range calculations with conventional precision. As another example, in one embodiment, the number of LPHDR calculation elements in the device is greater than 100 + 5x [the number of calculation elements in the device], if there are calculation elements in the device, where the device is designed to perform high dynamic range calculations with conventional precision. As another example, in one embodiment, the number of LPHDR computing elements in a device may be increased by 1 if the device has more computing elements. If there was such a device, it would exceed 1000 + 5x [the number of computing elements in the device]. As another example, in one embodiment, the number of LPHDR computing elements in a device may be: If there are computing elements in the device, the number of computing elements in the device exceeds 5000 + 5 x [the number of computing elements in the device]. wherein the device is designed to perform high dynamic range calculations with conventional precision. Some embodiments of the present invention are adapted to be implemented within a single physical device, such as, but not limited to, a silicon chip, or stacked chips, or chip package, or circuit board. Then, the number of LPHDR calculation elements in the physical device, NL, and the number of conventional The number of computing elements, NH, designed to perform high dynamic range operations with precision is the sum of the individual computing elements in the physical device. Some embodiments of the invention are implemented in a computer system that includes one or more physical devices. Such physical devices include, but are not limited to, a collection of silicon chips, or stacked chips, or chip packages, or circuit boards, connected together and interconnected by various means (such as a bus, switch, or network of any kind). communicate with each other using a network connection or other means of communication In this case, the number of LPHDR calculation elements in the computer system is NL, and the number of conventional precision high dynamic range calculation elements in the computer system is NL. The number of computing elements, NH, designed to perform a computation is the sum of the individual computing elements in all these concatenated physical devices.

[0135] Some embodiments of the present invention may form a processor or a portion of a processor. The processor is a device capable of running software to perform calculations. Such a processor may include mechanisms for storing the software, using the software to determine which operations to perform, executing these operations, storing large amounts of data, modifying the data with the software to perform specific operations, and communicating with devices connected to the processor. The processor may be a reconfigurable device such as, but not limited to, a field programmable array. The processor may be a co-processor to assist a host machine or may have the ability to perform computations independent of an external host machine. Processors include CPUs, GPUs, FPGAs, and the like. It may be formed as a collection of various types of host processor and coprocessor components, such as other processors and other devices. This may be referred to as a heterogeneous processor design or a heterogeneous computer system, any or all of which components may be the same or variations of embodiments of the present invention.

[0136] However, embodiments of the invention may be implemented in devices in addition to a processor or in devices other than a processor. For example, a computer including a processor and other components (such as memory connected to the processor by a data path) is an example of an embodiment of the invention, where the processor includes components for performing LPHDR processing according to any of the methods disclosed herein. More generally, any device or combination of devices that performs the functions disclosed herein, whether or not falling within the scope of the term processor, constitutes an example of an embodiment of the invention.

[0137] More generally, any of the techniques disclosed herein may be implemented, for example, by hardware, software tangibly stored on a computer-readable medium, firmware, or a combination thereof. The techniques described herein may be implemented by one or more computer programs running on a programmable computer having a processor, a processor-readable storage medium (including, for example, volatile or non-volatile memory and / or storage elements), at least one input device, and at least one output device. The program code is entered using the input device to perform the functions described above and generate output. The output is provided to one or more output devices.

[0138] Each computer program within the scope of the claims below may be implemented in any programming language, such as assembly language, machine language, a high-level procedural programming language, or an object-oriented language, e.g., the programming language may be compiled or interpreted.

[0139] Each such computer program is implemented in the form of a computer program product tangibly embodied in a machine-readable storage device for execution by a computer processor. The techniques of the present invention are carried out by a computer processor which runs a program tangibly embodied in a computer-readable storage medium to perform the functions of the invention by processing input and producing output. Suitable processors include, by way of example, both general-purpose and special-purpose microprocessors. Typically, the processor receives instructions and data from a read-only memory and / or a random access memory. Suitable storage devices for reliably embodying computer program instructions include, for example, semiconductor memory devices, including EPROMs and EEPROMs, flash memory devices, and the like. Magnetic disks such as internal hard disks and removable disks, optical magnetic disks This includes all types of non-volatile memory, such as flash memory, flash drives, and CR-ROMs. All of these can be captured and executed by specially designed ASICs (Application-Specific Integrated Circuits) or FPGAs (Field-Programmable Gate Arrays). The computer also typically receives programs and data from a storage medium such as an internal hard disk (not shown) or a removable disk. These elements may be found in conventional desktop or workstation computers and other computers suitable for running computer programs that perform the methods described herein, and may be used in conjunction with digital print or marking engines, display monitors, and other raster output devices capable of outputting color or gray scale pixels onto paper, film, a display screen, or other output medium.

Claims

[Claim 1] a plurality of low precision high dynamic range (LPHDR) execution units; at least one high precision execution unit, wherein a precision of calculations performed by the at least one high precision execution unit is greater than a precision of calculations performed by the plurality of LPHDR execution units; and means for controlling the plurality of LPHDR execution units and the at least one high precision execution unit to perform a method, The method comprises: receiving as input a number of example vectors and a test vector; storing the plurality of example vectors; Using the plurality of LPHDR execution units, identifying a first example vector among the plurality of example vectors that is closest to the one test vector; storing an identifier of the first example vector; identifying a second example vector from the plurality of example vectors that is second closest to the one test vector; storing an identifier of the second example vector; using the at least one high precision execution unit, Calculating a first distance between the test vector and the first example vector; calculating a second distance between the test vector and the second example vector; identifying a smaller one of the first distance and the second distance; identifying an example vector from among the first example vector and the second example vector that is associated with a smaller one of the first distance and the second distance; and outputting the example vector associated with the smaller of the first distance and the second distance. device.

Images