Solid-state image capturing device and electronic apparatus

Abstract

To provide a photodetection device and an electronic apparatus capable of enhancing a degree of freedom in arranging elements in a photoelectric conversion region.SOLUTION: A solid-state imaging device 1A, which is a photodetection device includes a semiconductor layer 21, that has a first surface portion S1 and a second surface portion positioned on mutually opposite sides in a thickness direction Z and has a photoelectric conversion region 22 partitioned by a separation region 31 extending in the thickness direction. The photoelectric conversion region includes: an upper surface portion 22a positioned on the first surface portion side of the semiconductor layer; a side surface portion 22b positioned on the separation region side; a pixel transistor provided on the upper surface portion side; a floating diffusion region FD1, FD2 that is provided on the upper surface portion side and that holds a signal charge photoelectrically converted by a photoelectric conversion unit; and a capacitive element Cp connected to the floating diffusion region. The capacitive element includes a first electrode 47c provided in the separation region adjacent to the side surface portion of the photoelectric conversion region with a dielectric film interposed therebetween, and a second electrode 52c provided inside the side surface portion of the photoelectric conversion region so as to be adjacent to the first electrode.SELECTED DRAWING: Figure 6B

Description

[Technical field]

[0001] The present technology (technology related to the present disclosure) relates to a photodetection device and electronic device, and in particular to a technology that is effective when applied to a photodetection device having a capacitive element electrically connected to a floating diffusion region and an electronic device using the same. [Background technology]

[0002] Photodetection devices such as solid-state imaging devices and photodetectors include a transfer transistor that transfers photoelectrically converted signal charges to a floating diffusion region, and a readout circuit (pixel circuit) that outputs a pixel signal based on the signal charges accumulated (held) in the floating diffusion region.

[0003] Patent Document 1 discloses a solid-state imaging device in which a floating diffusion region, a transfer transistor, a pixel transistor included in a readout circuit, etc. are provided in a photoelectric conversion region of a semiconductor layer. Patent Document 1 also discloses a photoelectric conversion region partitioned by a trench-type isolation region.

[0004] On the other hand, Patent Document 2 discloses a technique in which a capacitive element electrically connected to a floating diffusion region is provided in a photoelectric conversion region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-101491 [Patent Document 2] WO2020 / 105634 issue Summary of the Invention [Problem to be solved by the invention]

[0006] Incidentally, in recent years, there has been a demand in the market for high-resolution image sensors, and the development of image sensors with reduced pixel sizes is underway.

[0007] However, as the pixel size is reduced, the degree of freedom in arranging elements such as transfer transistors, pixel transistors, and capacitive elements in the photoelectric conversion region is reduced.

[0008] An object of the present technology is to provide a technology that can increase the degree of freedom in arranging elements in a photoelectric conversion region. [Means for solving the problem]

[0009] (1) A photodetector according to one aspect of the present disclosure, The semiconductor layer has a first surface portion and a second surface portion located opposite each other in the thickness direction, and has a photoelectric conversion region partitioned by a separation region extending in the thickness direction. The photoelectric conversion region is an upper surface portion of the semiconductor layer located on the first surface portion side; A side portion located on the separation region side; a floating diffusion region provided on the upper surface side and configured to hold signal charges photoelectrically converted by the photoelectric conversion portion; a capacitance element connected to the floating diffusion region; It is equipped with: The capacitance element is a first electrode provided on the outer side of the side surface of the photoelectric conversion region with a dielectric film interposed therebetween; a second electrode provided adjacent to the first electrode on the inner side of the side surface of the photoelectric conversion region; has.

[0010] (2) An electronic device according to another aspect of the present technology includes: The photodetector; an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device; a signal processing circuit for processing a signal output from the photodetector; It is equipped with: [Brief description of the drawings]

[0011] [Figure 1]1 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. [Diagram 2] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present technology. [Diagram 3] 2 is an equivalent circuit diagram showing a configuration example of a readout circuit according to the first embodiment of the present technology. [Figure 4A] 2 is a plan view illustrating a schematic configuration example of four pixels included in the pixel array unit of FIG. 1. [Figure 4B] 4B is an enlarged plan view of a main part of one pixel in FIG. 4A. FIG. [Figure 5A] 5 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a4-a4 cutting line in FIG. 4. [Figure 5B] FIG. 5B is a schematic enlarged longitudinal sectional view of a portion of FIG. 5A. [Figure 6A] 5 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the b4-b4 cutting line in FIG. 4. [Figure 6B] FIG. 6B is a schematic enlarged longitudinal sectional view of a portion of FIG. 6A. [Figure 7A] 1A to 1C are longitudinal cross-sectional views illustrating schematic steps of a method for manufacturing a solid-state imaging device according to a first embodiment of the present technology. [Figure 7B] FIG. 7B is a vertical cross-sectional view showing a schematic diagram of a step subsequent to FIG. 7A. [Figure 7C] FIG. 7C is a vertical cross-sectional view illustrating a process subsequent to FIG. 7B. [Figure 7D] FIG. 7D is a vertical cross-sectional view illustrating a process following FIG. 7C. [Figure 7E] FIG. 7B is a vertical cross-sectional view illustrating a process subsequent to FIG. 7D. [Figure 7F] FIG. 7B is a vertical cross-sectional view illustrating a process subsequent to FIG. 7E. [Figure 7G] FIG. 7B is a vertical cross-sectional view illustrating a process following FIG. 7F. [Figure 8] FIG. 11 is a longitudinal sectional view of a main part, which is a schematic view showing a modified example 1-1 of the first embodiment. [Figure 9] FIG. 11 is a longitudinal sectional view of a main portion, which is a schematic view showing a modified example 1-2 of the first embodiment. [Figure 10]13 is a plan view illustrating a schematic configuration example of four pixels in a solid-state imaging device according to a second embodiment of the present technology. FIG. [Figure 11] 11 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a10-a10 cutting line in FIG. [Figure 12] 11 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the b10-b10 cutting line in FIG. 10. [Figure 13] 13 is a plan view illustrating a schematic configuration example of four pixels in a solid-state imaging device according to a third embodiment of the present technology. FIG. [Figure 14] 14 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a13-a13 cutting line in FIG. 13. [Figure 15] 14 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the b13-b13 cutting line in FIG. 13. [Figure 16] 13 is an equivalent circuit diagram showing a configuration example of a readout circuit in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. [Figure 17] 13 is a plan view illustrating a schematic configuration example of two pixels in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. [Figure 18] 18 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a17-a17 cutting line in FIG. 17. [Figure 19] FIG. 13 is a diagram showing a configuration example of an electronic device according to a fifth embodiment of the present technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. In the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description.

[0013] In addition, the drawings may of course include parts with different dimensional relationships and ratios. In addition, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0014] In addition, the following embodiments are merely examples of devices and methods for embodying the technical ideas of the present technology, and are not intended to limit the configurations to those described below. In other words, the technical ideas of the present technology can be modified in various ways within the technical scope described in the claims.

[0015] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read.

[0016] In the following embodiment, among the three mutually orthogonal directions in space, a first direction and a second direction mutually orthogonal in the same plane are defined as an X direction and a Y direction, respectively, and a third direction perpendicular to each of the first direction and the second direction is defined as a Z direction. In the following embodiment, the thickness direction of a semiconductor layer 21 described later is described as the Z direction.

[0017] [First embodiment] In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described. In addition, in this first embodiment, a readout circuit having a capacitive element connected to a floating diffusion region will be described.

[0018] <Overall configuration of solid-state imaging device> First, the overall configuration of the solid-state imaging device 1A will be described.

[0019] As shown in Fig. 1, a solid-state imaging device 1A according to a first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. As shown in Fig. 19, this solid-state imaging device 1A (101) takes in image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 focused on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0020] As shown in Fig. 1, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes a square pixel array section 2A provided in the center in a two-dimensional plane including mutually orthogonal X-direction and Y-direction, and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A. The semiconductor chip 2 is formed in a manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 described below into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally similar in a wafer state before the semiconductor wafer is diced. That is, the present technology is applicable in a semiconductor chip state and a semiconductor wafer state.

[0021] The pixel array section 2A is a light receiving surface that receives light collected by, for example, an optical lens (optical system) 102 shown in Fig. 19. In the pixel array section 2A, a plurality of pixels 3 (sensor pixels) are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other on the two-dimensional plane.

[0022] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 functions as an input / output terminal that electrically connects the semiconductor chip 2 to an external device.

[0023] <Logic circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0024] The vertical drive circuit 4 shown in Fig. 2 is formed of, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A in the vertical direction row by row, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section of each pixel 3 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 11.

[0025] 2 is arranged for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion for removing fixed pattern noise specific to each pixel.

[0026] 2 is configured with, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5 to select each of the column signal processing circuits 5 in turn, and causes each of the column signal processing circuits 5 to output a pixel signal that has been subjected to signal processing to a horizontal signal line 12.

[0027] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12, and outputs the processed signals. For example, the signal processing may include buffering, black level adjustment, column variation correction, various types of digital signal processing, and the like.

[0028] 2 generates clock signals and control signals that serve as a reference for the operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0029] <Photoelectric conversion circuit and readout circuit> The semiconductor chip 2 includes a photoelectric conversion circuit 15 and a readout circuit (pixel circuit) 16 shown in FIG. The photoelectric conversion circuit 15 includes, for example, but not limited to, a photoelectric conversion unit 25, a charge holding unit 26 that holds (accumulates) signal charge photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR that transfers the signal charge photoelectrically converted by the photoelectric conversion unit 25 to the charge holding unit 26. The photoelectric conversion circuit 15 is provided for each pixel 3. Although not limited thereto, the readout circuit 16 includes, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG as pixel transistors Q. That is, the readout circuit 16 of the first embodiment has a four-transistor configuration.

[0030] Here, in the first embodiment, as an example, a circuit configuration is shown in which one readout circuit 16 is assigned to each pixel 3, but the present invention is not limited to this first embodiment. For example, a circuit configuration may be used in which one readout circuit 16 is assigned to two pixels 3 as one unit, or a circuit configuration may be used in which one readout circuit 16 is assigned to three or more pixels 3 as one unit.

[0031] <Photoelectric conversion circuit> (Photoelectric conversion section) 3 is composed of, for example, a pn junction type photodiode (PD), and generates a signal charge according to the amount of received light. The photoelectric conversion unit 25 also temporarily holds (accumulates) the generated signal charge. The cathode side of the photoelectric conversion unit 25 is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground).

[0032] (transfer transistor) 3 transfers the signal charge photoelectrically converted by the photoelectric conversion unit 25 to the charge holding unit 26. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the charge holding unit 26. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor driving line of the pixel driving line 10 shown in FIG.

[0033] (Charge holding part) Although not limited thereto, for example, as shown in FIG. 3, the charge holding unit 26 has two floating diffusion regions FD1 and FD2 and a capacitance element Cp. The floating diffusion region FD1 is connected between the transfer transistor TR and the switching transistor FDG. The floating diffusion region FD2 is connected between the switching transistor FDG and the reset transistor RST. The capacitance element Cp is connected to the floating diffusion region FD2.

[0034] The floating diffusion region FD1 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR. The floating diffusion region FD2 and the capacitance element Cp temporarily accumulate and hold the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR when the switching transistor FDG is in a conductive state (ON state).

[0035] <Readout circuit> As shown in Fig. 3, the input stage of the readout circuit 16 is electrically connected to the floating diffusion region FD1 of the charge holding unit 26. When the switching transistor FDG is in a non-conductive state (OFF state), the readout circuit 16 reads out the signal charge held in the floating diffusion region FD of the charge holding unit 26, and when the switching transistor FDG is in a conductive state (ON state), the readout circuit 16 reads out the signal charge held in the floating diffusion regions FD1 and FD2 and the capacitance element Cp of the charge holding unit 26. The readout circuit 16 outputs a pixel signal based on the read signal charge. In other words, the readout circuit 16 converts the signal charge photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charge and outputs it.

[0036] The pixel transistors Q (AMP, RST, SEL, FDG) included in the readout circuit 16 and the transfer transistor TR included in the photoelectric conversion circuit 15 are configured as insulated gate type field effect transistors, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) whose gate insulating film is made of a silicon oxide (SiO2) film. In addition, the pixel transistors Q and the transfer transistors TR may be MISFETs (Metal Insulator Semiconductor FETs) whose gate insulating film is made of a silicon nitride (Si3N4) film or a laminated film of a silicon nitride film and a silicon oxide film.

[0037] Of the pixel transistors Q (AMP, RST, SEL, FDG) included in the readout circuit 16, the selection transistor SEL, the reset transistor RST, and the switching transistor FDG mainly function as switching elements, while the remaining amplification transistor AMP mainly functions as an amplification element.

[0038] 3, the source region of the amplifier transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line VDD and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to the floating diffusion region FD1 of the charge holding unit 26, the drain region of the transfer transistor TR, and the source region of the switching transistor FDG.

[0039] 3, the source region of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain region is electrically connected to the source region of the amplification transistor AMP. The gate electrode of the selection transistor SEL is electrically connected to the selection transistor driving line of the pixel driving line 10 shown in FIG.

[0040] 3, the source region of the reset transistor RST is electrically connected to the floating diffusion region FD2 of the charge holding unit 26 and the drain region of the switching transistor FDG, and the drain region is electrically connected to the power supply line VDD and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG.

[0041] 3, the source region is electrically connected to the floating diffusion region FD1 of the charge holding unit 26, the drain region of the transfer transistor TR, and the gate electrode of the amplification transistor AMP, and the drain region is electrically connected to the floating diffusion region FD2 of the charge holding unit 26 and the drain region of the reset transistor RST. The gate electrode of the switching transistor FDG is electrically connected to the switching transistor drive line of the pixel drive line 10 shown in FIG.

[0042] The transfer transistor TR shown in FIG. 3 transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the charge holding unit 26 when the transfer transistor TR is turned on.

[0043] When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the charge holding unit 26 (FD1, FD2, Cp) to the potential of the power supply line VDD. The selection transistor SEL shown in FIG.

[0044] 3 generates, as a pixel signal, a signal whose voltage corresponds to the level of the signal charge held in the charge holding unit 26. The amplifying transistor AMP constitutes a source-follower type amplifier, and outputs a pixel signal whose voltage corresponds to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of the charge holding unit 26, and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0045] The switching transistor FDG shown in FIG. 3 controls charge retention by the charge retention unit 26, and adjusts the image magnification of the voltage according to the potential amplified by the amplification transistor AMP.

[0046] The switching transistor FDG is used when switching the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, if the FD capacitance C (floating diffusion capacitance C) of the charge holding unit 26 is large when performing charge-voltage conversion, the voltage V when converted to a voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal is large, so if the FD capacitance C of the charge holding unit 26 is not large, the charge holding unit 26 cannot receive the charge of the photoelectric conversion unit 25 (photodiode PD). Furthermore, the FD capacitance C of the charge holding unit 26 needs to be large so that the voltage V when converted to a voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). In consideration of this, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, so that the overall FD capacitance C becomes large. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the switching transistor FDG on / off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0047] During operation of the solid-state imaging device 1A according to the first embodiment, the signal charge generated in the photoelectric conversion unit 25 of the pixel 3 is held (accumulated) in the charge holding unit 26 via the transfer transistor TR of the pixel 3. Then, the signal charge held in the charge holding unit 26 is read out by the readout circuit 16 and applied to the gate electrode of the amplification transistor AMP of the readout circuit 16. A selection control signal for a horizontal line is provided to the gate electrode of the selection transistor SEL of the readout circuit 16 from the vertical shift register. Then, by setting the selection control signal to a high (H) level, the selection transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor AMP flows in the vertical signal line 11. Also, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the readout circuit 16 to a high (H) level, the reset transistor RST becomes conductive, and the signal charge accumulated in the floating diffusion region FD is reset.

[0048] Each of the photoelectric conversion unit 25, the transfer transistor TR, the floating diffusion regions FD1 and FD2, and the capacitance element Cp shown in Fig. 3 is mounted on a semiconductor layer 21 (see Figs. 5A and 6A) described later. In addition, although not limited thereto, the pixel transistor Q (AMP, RST, SEL) included in the readout circuit 16 in Fig. 3 is also mounted on the semiconductor layer 21, for example.

[0049] <<Specific configuration of solid-state imaging device>> Next, a specific configuration of the semiconductor chip 2 (solid-state imaging device 1A) will be described with reference to FIGS. 4A to 6B.

[0050] In order to make the drawing easier to see, a multilayer wiring layer 55, which will be described later, is omitted in Fig. 4A, and layers above a first wiring layer 57 included in the multilayer wiring layer 55 are omitted in Fig. 5A and Fig. 6A. Also, Fig. 1 illustrates the light incident surface side of the semiconductor chip 2, but Fig. 4A is a plan view seen from the opposite side (the multilayer wiring layer side) to the light incident surface side of the semiconductor chip 2. Also, Fig. 6A omits illustration of a planarization film 61, an optical filter 63, and a microlens 64 shown in Fig. 5A.

[0051] As shown in Figure 5A, the semiconductor chip 2 comprises a semiconductor layer 21 having a first surface portion S1 and a second surface portion S2 located opposite each other in a thickness direction which is one direction (Z direction), an inter-pixel isolation region 31 as an isolation region extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 provided in the semiconductor layer 21 and partitioned by the inter-pixel isolation region 31.

[0052] As shown in FIG. 5A, the semiconductor chip 2 further includes a multi-layer wiring layer 55 provided on the first surface S1 side of the semiconductor layer 21. Moreover, the semiconductor chip 2 further includes, on the second surface S2 side of the semiconductor layer 21, a planarization film 61, an optical filter 63, and a microlens (on-chip lens) 64, which are provided in this order from the second surface S2 side.

[0053] Here, the first surface S1 of the semiconductor layer 21 may be referred to as a main surface or an element forming surface, and the second surface S2 may be referred to as a back surface. In the solid-state imaging device 1A according to the first embodiment, incident light incident from the second surface S2 side of the semiconductor layer 21 is photoelectrically converted by a photoelectric conversion section 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 may be referred to as a light incident surface.

[0054] In the first embodiment, the inter-pixel isolation region 31 corresponds to a specific but not limitative example of "isolation region" of the present technology.

[0055] <Planarization films, optical filters and microlenses> The planarization film 61 shown in FIG. 5A is provided on the second surface S2 side of the semiconductor layer 21 so as to cover the second surface S2 of the semiconductor layer 21 and planarize the second surface S2 side of the semiconductor layer 21.

[0056] 5A is provided for each pixel 3 (photoelectric conversion region 22). The optical filter 63 separates the color of the incident light incident from the light incident surface side (second surface portion S2 side) of the semiconductor chip 2. The microlens 64 collects the irradiated light and allows the collected light to efficiently enter the pixel 3 (photoelectric conversion region 22).

[0057] <Semiconductor layer> 5A, the semiconductor layer 21 includes an inter-pixel isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 partitioned by the inter-pixel isolation region 31. The photoelectric conversion region 22 is provided for each pixel 3. The semiconductor layer 21 may be a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, although not limited thereto, a p-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 21.

[0058] <Pixel isolation region> (Plane shape) 4A, the inter-pixel isolation region 31 includes a first planar portion 31x extending in the X direction in a plan view and a second planar portion 31y extending in the Y direction. The inter-pixel isolation region 31 further includes an intersection portion (intersection portion) where the first planar portion 31x and the second planar portion 31y intersect with each other on the same plane. In the first embodiment, the first planar portion 31x and the second planar portion 31y are, for example, perpendicular to each other.

[0059] The first planar portions 31x are repeatedly arranged at predetermined intervals in the Y direction. The second planar portions 31y are repeatedly arranged at predetermined intervals in the X direction. That is, the inter-pixel isolation region 31 has a lattice-like planar pattern in plan view.

[0060] 4A, the inter-pixel isolation region 31 corresponding to one photoelectric conversion region 22 has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds one photoelectric conversion region 22. The inter-pixel isolation region 31 corresponding to the pixel array unit 2A in which a plurality of pixels 3 are arranged has a composite planar pattern having a lattice-shaped planar pattern within the rectangular annular planar pattern.

[0061] (Cross-sectional shape) 5A, the inter-pixel isolation region 31 extends in the thickness direction (Z direction) of the semiconductor layer 21, and electrically and optically isolates two adjacent photoelectric conversion regions 22 in a plan view. The inter-pixel isolation region 31 is, for example, a carved type, a so-called trench type, in which a carved portion 33 is formed in the semiconductor layer 21 to partition and isolate the photoelectric conversion regions 22.

[0062] The inter-pixel isolation region 31 includes, for example, but not limited to, a recessed portion 33 extending across the first surface S1 and the second surface S2 of the semiconductor layer 21, and an isolation insulating film 34 provided in the recessed portion 33. That is, the inter-pixel isolation region 31 extends across the first surface S1 and the second surface S2 of the semiconductor layer 21. The isolation insulating film 34 may be, for example, a silicon oxide film. In the first embodiment, the recessed portion 33 is filled with, for example, the isolation insulating film 34.

[0063] <Photoelectric conversion area> 4A and 4B, the photoelectric conversion region 22 is surrounded by the inter-pixel isolation region 31 in a plan view, and has a rectangular planar shape. Specifically, the photoelectric conversion region 22 is surrounded by two first planar portions 31x extending in the X direction and spaced apart in the Y direction, and two second planar portions 31y extending in the Y direction and spaced apart in the X direction, in the inter-pixel isolation region 31. The photoelectric conversion region 22 is partitioned by the first planar portion 31x and the second planar portion 31y, and is separated from other photoelectric conversion regions 22.

[0064] As shown in Figures 5A to 6B, the photoelectric conversion region 22 has an upper surface portion 22a located on the first surface portion S1 side of the semiconductor layer 21, and a side surface portion (outer wall surface portion) 22b located on the inter-pixel isolation region 31 side. Moreover, the photoelectric conversion region 22 further includes the above-mentioned photoelectric conversion unit 25, a transfer transistor TR, floating diffusion regions FD1 and FD2, and a capacitance element Cp. As shown in Figures 4A to 6B, the photoelectric conversion region 22 further includes an inter-element isolation region (field isolation region) 41 provided on the upper surface portion 22a side, and an island-shaped element formation region (active region) 43 partitioned by the inter-element isolation region 41 and the inter-pixel isolation region 31 and provided on the upper surface portion 22a side (the first surface portion S1 side of the semiconductor layer 21). Moreover, the photoelectric conversion region 22 further includes, as the pixel transistors Q included in the readout circuit 16 described above, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG. Moreover, the photoelectric conversion region 22 further includes a p-type semiconductor region (well region) 23, an n-type semiconductor region 24, and a p-type power supply contact region WC (see FIGS. 4A and 4B).

[0065] (p-type semiconductor region and n-type semiconductor region) 5A and 5B, the p-type semiconductor region 23 is provided over a wide area in the photoelectric conversion region 22, extending across the first face portion S1 side and the second face portion S2 side of the semiconductor layer 21. The p-type semiconductor region 23 contacts the inter-pixel isolation region 31 along the depth direction (Z direction) of the semiconductor layer 21.

[0066] 5A and 5B, the n-type semiconductor region 24 is provided in the p-type semiconductor region 23 in the photoelectric conversion region 22. That is, six sides of the n-type semiconductor region 24, including the top surface, bottom surface, and four side surfaces, are surrounded by the p-type semiconductor region 23. The n-type semiconductor region 24 is separated from the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21 and the inter-pixel isolation region 31.

[0067] (Photoelectric conversion section) 5A and 5B includes a p-type semiconductor region 23 and an n-type semiconductor region 24 in the photoelectric conversion region 22. The photoelectric conversion unit 25 is configured as a pn junction type photodiode (PD) including a pn junction between the p-type semiconductor region 23 and the n-type semiconductor region 24.

[0068] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface portion S2 side of the semiconductor layer 21 into a signal charge in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charge at the pn junction between the p-type semiconductor region 23 and the n-type semiconductor region 24.

[0069] (Isolation region and element formation region) 5A to 6B, the element isolation region 41 is provided in a surface layer portion on the upper surface portion 22a side of the photoelectric conversion region 22, i.e., a surface layer portion on the first surface portion S1 side of the semiconductor layer 21. The element isolation region 41 has, for example, but is not limited to, an STI (Shallow Trench Isolation) structure in which an isolation insulating film 42b is embedded inside a shallow groove portion 42a recessed from the first surface portion S1 to the second surface portion S2 side of the semiconductor layer 21.

[0070] As shown in FIG. 4B, the inter-element isolation region 41 has an island-like planar pattern separated from the inter-pixel isolation region 31 except for a part in a plan view, and defines an element formation region 43 together with the inter-pixel isolation region 31.

[0071] 5A to 6B, the element formation region 43 is provided in a surface layer portion on the upper surface portion 22a side of the photoelectric conversion region 22, i.e., a surface layer portion on the first surface portion S1 side of the semiconductor layer 21. Then, as shown in Fig. 4B, the element formation region 43 is partitioned by the inter-element isolation region 41 and the inter-pixel isolation region 31, and has a planar pattern extending in a ribbon shape along the four sides of the photoelectric conversion region 22 in a planar view. The planar pattern of the element formation region 43 is, but is not limited to, the same for each pixel 3 (each photoelectric conversion region 22), for example.

[0072] (p-type power supply contact area) As shown in FIG. 4B and FIG. 6B, the p-type power supply contact region WC is provided on the corner side between two sides of the photoelectric conversion region 22 in a plan view. The p-type power supply contact region WC is provided on the surface layer portion on the upper surface portion 22a side of the photoelectric conversion region 22, i.e., on the surface layer portion on the first surface portion S1 side of the semiconductor layer 21. The p-type power supply contact region WC is provided in an island-shaped power supply region partitioned by the inter-element isolation region 41 and the inter-pixel isolation region 31 on the upper surface portion 22a side of the photoelectric conversion region 22. The p-type power supply contact region WC is composed of a p-type semiconductor region having a higher impurity concentration than the p-type semiconductor region 23. The p-type power supply contact region WC is connected to the p-type semiconductor region 23 and is electrically conductive.

[0073] A first reference potential of, for example, 0V is applied to this p-type power supply contact region WC as a reference potential within the semiconductor chip 2 (within the solid-state imaging device 1A) during operation, and the potential is fixed to this first reference potential.

[0074] (Floating diffusion region) 4A, 6A, and 6B, each of the floating diffusion regions FD1 and FD2 included in the charge holding portion 26 described above is provided in a p-type semiconductor region 23 in the element formation region 43 on the upper surface portion 22a side of the photoelectric conversion region 22, and forms a pn junction with the p-type semiconductor region 23. The floating diffusion regions FD1 and FD2 are also used as main electrode regions 52f, 52r of the switching transistor FDG described later, and are formed of an n-type semiconductor region. Furthermore, the floating diffusion region FD2 is also used as the second electrode 52c of the capacitance element Cp included in the charge holding portion 26.

[0075] (transfer transistor) As shown in FIG. 4B and FIG. 5B, the transfer transistor TR is provided on the first surface portion S1 side of the semiconductor layer 21, that is, on the upper surface portion 22a side of the photoelectric conversion region 22. The transfer transistor TR has a gate electrode 47t provided on the upper surface portion 22a side of the photoelectric conversion region 22 across the inside and outside of the photoelectric conversion region 22, and a gate insulating film 46 provided between the gate electrode 47t and the semiconductor layer 21. The transfer transistor TR further has an n-type semiconductor region 24 functioning as a source region, an n-type floating diffusion region FD1 functioning as a drain region, and a p-type semiconductor region 23 functioning as a channel formation portion. The transfer transistor TR is, for example, configured as a vertical type, but is not limited thereto.

[0076] 5B, the gate electrode 47t of the transfer transistor TR has a head 47t1 provided on the outside of the first surface portion S1 of the semiconductor layer 21 with the gate insulating film 46 interposed therebetween, and a leg portion 47r2 protruding from the head 47t1 into the semiconductor layer 21 and adjacent to the semiconductor layer 21 with the gate insulating film 46 interposed therebetween. The gate electrode 47t of the first embodiment is configured, for example, to have a T-shaped cross-sectional shape in which the width of the leg portion 47t2 is narrower than the width of the head portion 47t1, although this is not limited thereto.

[0077] The leg portion 47t2 of the gate electrode 47t is provided in a recessed portion of the semiconductor layer 21 with the gate insulating film 46 interposed therebetween, and the tip of the leg portion 47t2 extends into the n-type semiconductor region 24 while being insulated and isolated.

[0078] <Pixel transistor> 4B and 5B, a plurality of pixel transistors Q (AMP, SEL, RST, FDG) included in the readout circuit 16 are provided in the element formation region 43. Each of the plurality of pixel transistors Q is configured as, for example, a planar type.

[0079] (Reset transistor) As shown in FIG. 4B and FIG. 5B, the reset transistor RST has a gate electrode 47r provided on the upper surface portion 22a side of the photoelectric conversion region 22 (the first surface portion S1 side of the semiconductor layer 21) so as to overlap with the element formation region 43 (semiconductor layer 21) in a planar view, and a gate insulating film 46 interposed between the gate electrode 47r and the element formation region 43. The reset transistor RST further has a pair of main electrode regions 52r and 52ar provided in the element formation region 43 on both sides in the gate length direction of the gate electrode 47r and functioning as a source region and a drain region. The reset transistor RST further has a channel formation portion 53r provided in the element formation region 43 so as to overlap with the gate electrode 47r in a planar view. The pair of main electrode regions 52r and 52ar are spaced apart from each other via the channel formation portion 53r. The pair of main electrode regions 52r and 52ar are formed of n-type semiconductor regions provided in the element formation region 43, and the channel formation portion 53r is formed of a p-type semiconductor region 23 provided in the element formation region 43.

[0080] (selection transistor) As shown in Fig. 4B and Fig. 5B, the selection transistor SEL has a gate electrode 47s provided on the upper surface portion 22a side of the photoelectric conversion region 22 (the first surface portion S1 side of the semiconductor layer 21) so as to overlap with the element formation region 43 (semiconductor layer 21) in a planar view, and a gate insulating film 46 interposed between the gate electrode 47s and the element formation region 43. The selection transistor SEL further has a pair of main electrode regions 52s and 52as provided in the element formation region 43 on both sides in the gate length direction of the gate electrode 47s and functioning as a source region and a drain region. The selection transistor SEL further has a channel formation portion 53s provided in the element formation region 43 so as to overlap with the gate electrode 47s in a planar view. The pair of main electrode regions 52s and 52as are spaced apart from each other via the channel formation portion 53s. The pair of main electrode regions 52s and 52as are formed of n-type semiconductor regions provided in the element formation region 43, and the channel formation portion 53s is formed of a p-type semiconductor region 23 provided in the element formation region 43.

[0081] (Amplification transistor) Although not shown in detail, the amplifier transistor AMP has the same configuration as the reset transistor RST and the selection transistor SEL. That is, referring to FIG. 4B and FIG. 5B, the amplifier transistor AMP has a gate electrode 47a provided on the upper surface portion 22a side (the first surface portion S1 side of the semiconductor layer 21) of the photoelectric conversion region 22 so as to overlap with the element formation region 43 (the semiconductor layer 21) in a planar view, and a gate insulating film interposed between the gate electrode 47a and the element formation region 43. The amplifier transistor AMP further has a pair of main electrode regions 52as and 52ar provided in the element formation region 43 on both sides in the gate length direction of the gate electrode 47a and functioning as a source region and a drain region. The amplifier transistor AMP further has a channel formation portion provided in the element formation region 43 overlapping with the gate electrode 47a in a planar view. The pair of main electrode regions 52as and 52ar are spaced apart from each other via the channel formation portion. The pair of main electrode regions 52as and 52ar are formed of n-type semiconductor regions provided in the element formation region 43, and the channel formation portion is formed of a p-type semiconductor region 23 provided in the element formation region 43.

[0082] (switching transistor) As shown in FIG. 4B and FIG. 6B, the switching transistor FDG has a gate electrode 47f provided on the upper surface portion 22a side of the photoelectric conversion region 22 (the first surface portion S1 side of the semiconductor layer 21) so as to overlap with the element formation region 43 (semiconductor layer 21) in a planar view, and a gate insulating film 46 interposed between the gate electrode 47f and the element formation region 43. The switching transistor FDG further has a pair of main electrode regions 52f and 52r provided in the element formation region 43 on both sides in the gate length direction of the gate electrode 47f and functioning as a source region and a drain region. The switching transistor FDG further has a channel formation portion 53f provided in the element formation region 43 so as to overlap with the gate electrode 47f in a planar view. The pair of main electrode regions 52f and 52r are spaced apart from each other via the channel formation portion 53f. The pair of main electrode regions 52f and 52r are formed of n-type semiconductor regions provided in the element formation region 43, and the channel formation portion 53f is formed of a p-type semiconductor region 23 provided in the element formation region 43.

[0083] (Sharing of main electrode area) As shown in FIG. 4B, the amplifier transistor AMP and the select transistor SEL share a main electrode region 52as of the amplifier transistor AMP and a main electrode region 52as of the select transistor SEL, and are provided in the element formation region 43 in series connection. As shown in FIG. 4B, the amplifier transistor AMP and the reset transistor SRT share a main electrode region 52ar of the amplifier transistor AMP and a main electrode region 52ar of the reset transistor RST, and are provided in the element formation region 43 in series connection.

[0084] 4B, the switching transistor FDG and the transfer transistor TR share a main electrode region 52f of the switching transistor FDG and a main electrode region 52f of the transfer transistor TR, and are provided in series connection in the element formation region 43. The main electrode region 52f of each of the switching transistor FDG and the transfer transistor TR is also used as the floating diffusion region FD1.

[0085] 4B, the switching transistor FDG and the reset transistor RST share a main electrode region 52r of the switching transistor FDG and a main electrode region 52r of the reset transistor RST, and are provided in series connection in the element formation region 43. The main electrode region 52r of each of the switching transistor FDG and the reset transistor RST is also used as the floating diffusion region FD2.

[0086] (Gate insulating film and gate electrode materials) The gate insulating film 46 of each of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, the switching transistor FDG, and the transfer transistor TR is made of, for example, a silicon oxide (SiO2) film. The gate electrodes 47a, 47s, 47r, 47f, and 47t of each of these transistors AMP, SEL, RST, FDG, and TR are made of, for example, a polycrystalline silicon film (doped polysilicon film) into which an impurity that reduces the resistance value is introduced.

[0087] (Enhancement type) Each of the pixel transistors Q (AMP, SEL, RST, FDG) included in the readout circuit 16 can be configured as an enhancement type (normally off type) in which a drain current flows by applying a gate voltage equal to or higher than a threshold voltage to the gate electrodes 47a, 47s, 47r, 47f. Also, each of the pixel transistors Q (AMP, SEL, RST, FDG) included in the readout circuit 16 can be configured as a depletion type (normally on type) in which a drain current flows even if no voltage is applied to the gate electrodes 47a, 47s, 47r, 47f. In this first embodiment, the transistors are configured as, for example, an enhancement type, although not limited thereto. In the case of the enhancement type, in each of the pixel transistors Q (AMP, SEL, RST, FDG), a channel (inversion layer) electrically connecting a pair of main electrode regions is formed (induced) in the channel formation portion by a voltage applied to the gate electrodes 47a, 47s, 47r, 47f, and a current (drain current) flows from the drain region side through the channel in the channel formation portion to the source region side.

[0088] Like the pixel transistor Q, the transfer transistor TR is also configured as, for example, an enhancement type.

[0089] <Capacitor element Cp> 4B, 6A, and 6B, the capacitance element Cp has a dielectric film 46c provided on the side surface portion 22b of the photoelectric conversion region 22, a first electrode 47c provided in the inter-pixel isolation region 31 adjacent to (facing) the side surface portion 22b of the photoelectric conversion region 22 with the dielectric film 46c interposed therebetween, and a second electrode 52c provided adjacent to the first electrode 47c on the inner side of the side surface portion 22b of the photoelectric conversion region 22. The dielectric film 46c is made of, for example, a silicon oxide film.

[0090] 6B, although not limited thereto, for example, a part of the first electrode 47c is provided inside the inter-pixel isolation region 31, and another part is provided outside the inter-pixel isolation region 31. That is, the first electrode 47c in the first embodiment is provided across the inside and outside of the inter-pixel isolation region 31 in the thickness direction (Z direction) of the semiconductor layer 21.

[0091] The first electrode 47c is made of, for example, a polycrystalline silicon film (doped polysilicon film) into which an impurity that reduces a resistance value is introduced. The first electrode 47c can be formed in the same process as the gate electrode 47f of the switching transistor FDG.

[0092] The second electrode 52c is composed of a semiconductor region provided in the element formation region 43. The second electrode 52c in the first embodiment is used both as the main electrode region 52r of each of the switching transistor FDG and the reset transistor RST, and also as the floating diffusion region FD2. That is, the capacitance element Cp is composed of a MOS structure.

[0093] 6B, the floating diffusion region FD2 is provided across the upper surface portion 22a and the side surface portion 22b of the photoelectric conversion region 22. Specifically, the floating diffusion region FD2 includes a first portion 52c1 provided on the upper surface portion 22a of the photoelectric conversion region 22, and a second portion 52c2 extending from the first portion 52c1 along the side surface portion 22b of the photoelectric conversion region 22 to the side opposite to the first surface portion S1 of the semiconductor layer 21. That is, the second electrode 52c has an L-shaped vertical cross section along the thickness direction (Z direction) of the semiconductor layer 21.

[0094] 4A, in two photoelectric conversion regions 22 (22Xa, 22Xb) arranged side by side in the Y direction in a plan view, the first electrode 47c of the capacitance element Cp in one photoelectric conversion region 22Xa is electrically connected to the main electrode region 52ar of the amplification transistor AMP and the reset transistor RST in the other photoelectric conversion region 22Xb via a wiring 58z. This wiring 58z is electrically connected to the above-mentioned power supply line VDD, although not shown.

[0095] ≪Multilayer wiring layer≫ As shown in FIG. 5A to FIG. 6B, the multi-layer wiring layer 55 is provided on the first surface S1 side of the semiconductor layer 21. The multi-layer wiring layer 55 includes an interlayer insulating film 56 provided on the first surface S1 side of the semiconductor layer 21 so as to cover the inter-element isolation region 41 and the element formation region 43, contact electrodes 57c, 57f, 57r, 57s, 57t, and 57w provided in the interlayer insulating film 56, and a first-layer wiring layer 58 provided on the opposite side of the interlayer insulating film 56 to the semiconductor layer 21 side. The first-layer wiring layer 58 includes wirings 58c, 58r, 58s, 58t, and 58w. For example, tungsten (W), a high-melting point metal, can be used as the material of the contact electrodes 57c, 57f, 57r, 57s, 57t, and 57w. The first wiring layer 58 may be made of a metal material such as aluminum (Al) or copper (Cu), or an alloy material mainly containing Al or Cu. The interlayer insulating film 56 may be made of a silicon oxide film. The gate electrode 47t of the transfer transistor TR and the gate electrodes (47a, 47s, 47r, 47f) of the pixel transistors Q (AMP, SEL, RST, FDG) are covered with the interlayer insulating film 56.

[0096] <Contact electrodes and wiring> As shown in FIG. 5B, the gate electrode 47t of the transfer transistor TR is electrically connected to a wiring 58t provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57t provided in the interlayer insulating film 56.

[0097] As shown in FIG. 5B, the gate electrode 47r of the reset transistor RST is electrically connected to a wiring 58r provided in the wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57r provided in the interlayer insulating film 56.

[0098] As shown in FIG. 5B, the gate electrode 47s of the selection transistor SEL is electrically connected to a wiring 58s provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57s provided in the interlayer insulating film 56.

[0099] As shown in FIG. 6B, the gate electrode 47f of the switching transistor FDG is electrically connected to a wiring 58f provided in the wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57f provided in the interlayer insulating film 56.

[0100] As shown in FIG. 6B, the first electrode 47c of the capacitance element Cp is electrically connected to a wiring 58c provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57c provided in the interlayer insulating film 56.

[0101] Although not shown, the gate electrode 47a of the amplification transistor AMP is electrically connected to a wiring provided in the wiring layer 58 on the interlayer insulating film 56 via a contact electrode provided in the interlayer insulating film 56.

[0102] <Method for manufacturing solid-state imaging device> Next, a method for manufacturing the solid-state imaging device 1A according to the first embodiment of the present technology will be described with reference to FIGS. 7A to 7H. In this first embodiment, the description will be focused on the manufacture of the capacitance element Cp, which is included in the manufacturing method of the solid-state imaging device 1A.

[0103] First, as shown in FIG. 7A, a photoelectric conversion region 22, a p-type semiconductor region 23, an n-type semiconductor region 24, a photoelectric conversion section 25, an inter-pixel isolation region 31, an inter-element isolation region 41, an element formation region 43, etc. are formed in a semiconductor layer 21. The inter-pixel isolation region 31 can be formed by forming a recessed portion 33 in the semiconductor layer 21, extending in the thickness direction (Z direction) of the semiconductor layer 21, and then selectively filling this recessed portion 33 with an isolation insulating film . The element isolation region 41 can be formed by forming a shallow groove portion 42a on the first surface portion S1 side of the semiconductor layer 21, and then selectively filling this shallow groove portion 42a with an isolation insulating film 42b. Then, by forming the inter-pixel isolation region 31 and the inter-element isolation region 41, a photoelectric conversion region 22 is formed, which is partitioned by the inter-pixel isolation region 31 and the inter-element isolation region 41 and has an upper surface portion 22a and a side surface portion 22b. In addition, an element formation region 43 partitioned by the inter-element isolation region 41 is formed on the upper surface portion 22a side of the photoelectric conversion region 22.

[0104] 7B, a recessed portion 35 extending in the thickness direction (Z direction) of the semiconductor layer 21 along the side surface portion 22b of the photoelectric conversion region 22 is formed in the inter-pixel isolation region 31. The recessed portion 35 can be formed, for example, by forming a mask M1 on the first surface portion S1 of the semiconductor layer 21 by a well-known photolithography technique, and then selectively etching the inter-pixel isolation region 31 exposed from the opening of the mask M1 by anisotropic dry etching technique.

[0105] 7C, a first portion 52c1 made of an n-type semiconductor region extending from the upper surface portion 22a side of the photoelectric conversion region 22 along the side surface portion 22b to the opposite side to the upper surface portion 22a side is formed inside the side surface portion 22b of the photoelectric conversion region 22. The first portion 52c1 can be formed, for example, by ion-implanting an impurity into the side surface portion 22b of the photoelectric conversion region 22 through the opening and the recessed portion 35 of the mask M1, and then performing a heat treatment to activate the ion-implanted impurity.

[0106] Next, the mask M1 is selectively removed, and the native oxide film and excess insulating film on the upper surface portion 22a and the side portion 22b of the photoelectric conversion region 22 on the first surface portion S1 side of the semiconductor layer 21 are removed, for example by wet etching, to expose the semiconductor layer 21 on the upper surface portion 22a and the side portion 22b of the photoelectric conversion region 22.

[0107] Next, after exposing the semiconductor layer 21 on the upper surface portion 22a and the side surface portion 22b of the photoelectric conversion region 22, a gate insulating film 46 is formed on the semiconductor layer 21 on the upper surface portion 22a of the photoelectric conversion region 22, and a dielectric film 46c adjacent to the first portion 52c1 is formed on the semiconductor layer 21 on the side surface portion 22b of the photoelectric conversion region 22, as shown in FIG. 7D. The gate insulating film 46 and the dielectric film 46c may be, for example, a silicon oxide film. The silicon oxide film may be formed by thermal oxidation or deposition, but in this first embodiment, the silicon oxide film is formed by thermal oxidation as the gate insulating film 46 and the dielectric film 46c. The thermal oxidation method can form a silicon oxide film with better film quality than the deposition method. In this step, the dielectric film 46c and the gate insulating film 46 are formed in the same step.

[0108] 7E, a conductive film 47 is formed. The conductive film 47 is formed on the first surface S1 side of the semiconductor layer 21 so as to fill the inside of the dug portion 35. As the conductive film 47, a polycrystalline silicon film that can be formed by a CVD method can be used.

[0109] Next, the conductive film 47 is patterned to form a gate electrode 47f and a first electrode 47c, as shown in Fig. 7F. In Fig. 7F, the gate electrode 47f of the switching transistor FDG is illustrated, but in this process, the gate electrodes of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the transfer transistor TR are also formed.

[0110] In this process, the first electrode 47c is formed so as to be adjacent to each of the side portions 22b and the first portion 52c1 of the photoelectric conversion region 22 via the dielectric film 46c, and to extend from inside to outside the inter-pixel isolation region 31 in the thickness direction (Z direction) of the semiconductor layer 21. In this step, the gate electrode 47f and each of the other gate electrodes are formed in the element formation region 43 of the photoelectric conversion region 22 with the gate insulating film 46 interposed therebetween. In this step, the first electrode 47c and the gate electrode of the pixel transistor Q are formed in the same step.

[0111] 7G, a second portion 52c2 made of an n-type semiconductor region is formed on the upper surface portion 22a of the element formation region 43 of the photoelectric conversion region 22, and a floating diffusion region FD1 made of an n-type semiconductor region is also formed. Each of the second portion 52c2 and the floating diffusion region FD1 can be formed, for example, by selectively ion-implanting an impurity into the element formation region 43 of the photoelectric conversion region 22, and then performing a heat treatment to activate the ion-implanted impurity.

[0112] In this step, a floating diffusion region FD2 including the first portion 52c1 and the second portion 52c2 is formed, and a second electrode 52c that also serves as the floating diffusion region FD2 is formed. In this step, a capacitance element Cp is formed which includes the first electrode 47c, the dielectric film 46c, and the second electrode 52c and is electrically connected to the floating diffusion region FD2.

[0113] In this step, a main electrode region 52f that also serves as the floating diffusion region FD1 is formed, and a main electrode region 52r that also serves as the floating diffusion region FD2 is formed. In this step, a channel forming portion 53r is formed in the element forming region 43 which overlaps with the gate electrode 47f in a plan view and is sandwiched between the main electrode region 52f and the main electrode region 52r. In this step, a switching transistor FDG is formed as the pixel transistor Q, the switching transistor FDG having the gate insulating film 46, the gate electrode 47f, a pair of main electrode regions 52f and 52r, and a channel forming portion 53f.

[0114] Although not shown in the figure, in this process, other pixel transistors Q, such as an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST, are also formed in the element formation region 43 of the photoelectric conversion region 22, and a transfer transistor TR is also formed in the element formation region 43 of the photoelectric conversion region 22.

[0115] <<Main Effects of the First Embodiment>> Next, the main effects of the first embodiment will be described. 3, the solid-state imaging device 1A according to the first embodiment includes a capacitance element Cp connected to the floating diffusion region FD2. As shown in FIGS. 4B and 6B, the capacitance element Cp includes a first electrode 47c provided in the inter-pixel isolation region 31 adjacent to the side surface portion 22b of the photoelectric conversion region 22 with a dielectric film 46c interposed therebetween, and a second electrode 52c provided inside the side surface portion 22b of the photoelectric conversion region 22 adjacent to the first electrode 47c.

[0116] Therefore, compared with the case where each of the first electrode 47c and the second electrode 52c of the capacitance element Cp is disposed in the photoelectric conversion region 22, the area occupied by the capacitance element Cp in the photoelectric conversion region 22 can be made smaller, and the degree of freedom in arranging elements such as the capacitance element Cp, the pixel transistors Q (AMP, RST, SEL, FDG), and the transfer transistors TR in the photoelectric conversion region 22 (degree of freedom in layout) can be increased. Therefore, according to the solid-state imaging device 1A according to the first embodiment, the degree of freedom in arranging elements in the photoelectric conversion region 22 can be increased.

[0117] Furthermore, since the area occupied by the capacitance element Cp in the photoelectric conversion region 22 can be reduced, the photoelectric conversion region 22 can be miniaturized without miniaturizing the pixel transistors Q (AMP, SEL, RST, FDG) and the transfer transistors TR provided in the photoelectric conversion region 22. This makes it possible to miniaturize the photoelectric conversion region 22, i.e., miniaturize the pixels 3, while suppressing the deterioration of characteristics associated with the miniaturization of the pixel transistors Q (AMP, SEL, RST, FDG) and the transfer transistors TR provided in the photoelectric conversion region 22.

[0118] Moreover, the first electrode 47c and the second electrode 52c of the capacitance element Cp are provided adjacent to each other with the dielectric film 46c interposed therebetween on the side surface portion 22b of the photoelectric conversion region 22. This makes it possible to increase the area of ​​each of the first electrode 47c and the second electrode 52c in the thickness direction (Z direction) of the semiconductor layer 21, thereby making it possible to increase the capacitance without expanding the planar size of the capacitance element Cp.

[0119] In addition, the second electrode 52c of the capacitance element Cp is also used as the floating diffusion region FD2. This allows the planar size of the photoelectric conversion region 22 to be reduced, and the number of pixels in the pixel array section 1A to be increased without increasing the planar size of the pixel array section 1A. In recent years, there has been a demand in the market for image sensors capable of high resolution, and this can contribute to increasing the resolution of image sensors.

[0120] In addition, since the second electrode 52c of the capacitance element Cp is also used as the floating diffusion region FD2, the wiring electrically connecting the second electrode 52c and the floating diffusion region FD2 can be omitted, and the wiring density of the multilayer wiring layer 55 overlapping with the photoelectric conversion region 22 in a plan view can be reduced. This increases the degree of freedom in routing the wiring connecting to the pixel transistors Q (AMP, SEL, RST, FDG) of the photoelectric conversion region 22, and alleviates restrictions on the arrangement of the pixel transistors Q caused by the routing of the wiring.

[0121] Typically, in an image sensor, in order to expand the dynamic range and improve low-illumination characteristics, a transistor for switching conversion efficiency (switching transistor FDG) is provided, and the sensor is often operated with high conversion efficiency at low illuminance and low conversion efficiency at high illuminance.

[0122] In high illuminance regions, the charge storage unit 26 receives signal charges (transfer charges) from the photoelectric conversion unit 25, so the diffusion capacitance in the floating diffusion regions FD1 and FD2 alone is insufficient, and capacitance is often added. Therefore, in order to increase the capacitance, a wiring capacitance, a MOS capacitance, an MIM capacitance, etc. may be connected.

[0123] Since the dynamic range performance is determined by the FD capacitance in this charge holding unit 26, the larger the FD capacitance, the better, especially when performing overflow driving (LOFIC).

[0124] From the standpoint of reliability, the wiring capacitance cannot be made that large, and forming an MIM section in the photoelectric conversion region 22 has disadvantages in terms of cost and structure, so MOS capacitance has been widely used.

[0125] However, because conventional MOS capacitors have electrodes formed on the silicon surface with an insulating film between them, increasing the capacitance required a larger area, which required reducing the size of the pixel transistor Q. However, reducing the size of the pixel transistor Q resulted in poorer variation in transistor characteristics and affected characteristics such as random noise.

[0126] In contrast, the capacitance element Cp of this technology can increase its capacitance without expanding its planar size, making it useful for expanding the dynamic range and improving low-light characteristics without affecting characteristics such as worsening the variation in transistor characteristics or random noise.

[0127] <Modification of the First Embodiment> <Variation 1-1> In the above-described first embodiment, a case has been described in which the first electrode 47c of the capacitance element Cp is provided across the inside and outside of the inter-pixel isolation region 31 in the thickness direction (Z direction) of the semiconductor layer 21, but the present technology is not limited to the above-described first embodiment.

[0128] 8, the first electrode 47c may be embedded in the inter-pixel isolation region 31. In this modification 1-1 as well, the same effects as those of the first embodiment described above can be obtained.

[0129] <Variation 1-2> In addition, in the above-described first embodiment, a case has been described in which a silicon oxide film is used as the dielectric film 46c of the capacitance element Cp, but the present technology is not limited to the above-described first embodiment.

[0130] 9, the dielectric film 46c of the capacitance element Cp may include a film 46c1 having a higher dielectric constant than the isolation insulating film of the pixel isolation region. In this modification 1-2, the same effects as those of the first embodiment can be obtained. Moreover, in comparison with the first embodiment, this modification 1-2 can increase the capacitance at the same size.

[0131] Second Embodiment Next, a solid-state imaging device 1B according to a second embodiment of the present technology will be described with reference to FIGS. FIG. 10 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to the second embodiment of the present technology. FIG. 11 is a longitudinal sectional view that typically shows a longitudinal sectional structure taken along the a10-a10 cutting line in FIG. FIG. 12 is a vertical cross-sectional view that typically shows a vertical cross-sectional structure taken along the b10-b10 line in FIG.

[0132] A solid-state imaging device 1B according to a second embodiment of the present technology includes a pixel block 17B shown in Fig. 10. The pixel block 17B according to the second embodiment includes, as one unit, two pixels 3 (3c, 3d) that are adjacent to each other and aligned in the X direction in a plan view. Fig. 10 illustrates two pixel blocks 17B aligned in the Y direction in a plan view.

[0133] 10, each of two pixels 3 (3c, 3d) included in one pixel block 17B includes a photoelectric conversion region 22 (22Xc, 22Xd) partitioned by an inter-pixel isolation region 31. The photoelectric conversion region 22 (22Xc, 22Xd) of the second embodiment basically has the same configuration as the photoelectric conversion region 22 of the first embodiment described above, with the following differences.

[0134] That is, in the pixel block 17B of the second embodiment, in each photoelectric conversion region 22 (22Xc, 22Xd) of two pixels 3 (3c, 3d), the planar pattern of the element formation region 43 in one photoelectric conversion region 22Xc and the planar pattern of the element formation region 43 in the other photoelectric conversion region 22Xd are inverted around the boundary between pixels 3c and 3d arranged in the X direction.

[0135] In each of the photoelectric conversion regions 22 (22Xc, 22Xd) of the two pixels 3 (3c, 3d), the first electrode 47c is shared by the capacitance element Cp of one photoelectric conversion region 22Xc and the capacitance element Cp of the other photoelectric conversion region 22Xd.

[0136] Specifically, as shown in FIG. 11, the first electrode 47c is shared by two adjacent photoelectric conversion regions 22 (22Xc, 22Xd) that are arranged with the inter-pixel isolation region 31 interposed therebetween in a planar view, and is adjacent to (facing) each of the second electrodes 52c (floating diffusion regions FD2) on the side portions 22b of each of the two photoelectric conversion regions 22 (22Xc, 22Xd) with a dielectric film 46c interposed therebetween.

[0137] 10, in two pixel blocks 17B aligned in the Y direction in a plan view, the first electrode 47c of one pixel block 17B is extended to the other pixel block 17B across the inter-pixel isolation region 31. As shown in FIG. 12, the first electrode 47c of one pixel block 17B is electrically and mechanically connected to each main electrode region 52ar of the amplification transistor AMP provided in each of the two photoelectric conversion regions 22 (22Xc, 22Xd) included in the other pixel block 17B at each side portion 22b of the two photoelectric conversion regions 22 (22Xc, 22Xd). Although not shown, the first electrode 47c is electrically connected to a power supply wiring line VDD.

[0138] The solid-state imaging device 1B according to the second embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0139] In the second embodiment, in each of the photoelectric conversion regions 22 (22Xc, 22Xd) of two pixels 3 (3c, 3d) included in one pixel block 17B, the capacitance element Cp of one photoelectric conversion region 22Xc and the capacitance element Cp of the other photoelectric conversion region 22Xd share the first electrode 47c. Therefore, the contact electrodes and wirings connected to the first electrode 47c can also be shared, and the wiring density of the multilayer wiring layer 55 overlapping the pixel block 17B in a plan view can be reduced. This increases the degree of freedom in routing the wirings connected to the pixel transistors Q of the photoelectric conversion region 22, and reduces the constraints on the arrangement of the pixel transistors Q caused by the routing of the wirings. Therefore, according to the solid-state imaging device 1B according to the second embodiment, the degree of freedom in the arrangement of the pixel transistors Q in the photoelectric conversion region 22 can be further increased compared to the solid-state imaging device 1A according to the first embodiment described above.

[0140] In the second embodiment, in two pixel blocks 17B arranged in the Y direction in a plan view, the first electrode 47c of one pixel block 17B is extended to the other pixel block 17B across the inter-pixel separation region 31. The first electrode 47c of one pixel block 17B is electrically and mechanically connected to each main electrode region 52ar of the amplification transistor AMP provided in each of the two photoelectric conversion regions 22 (22Xc, 22Xd) included in the other pixel block 17B at the side portion 22b of each of the two photoelectric conversion regions 22 (22Xc, 22Xd). The power supply wiring VDD is electrically connected to the first electrode 47c. This allows the contact electrode and wiring connected to the main electrode region 52ar of the amplification transistor AMP to be shared with the contact electrode and wiring connected to the first electrode 47c, so that the degree of freedom in arranging the pixel transistor Q in the photoelectric conversion region 22 can be further increased compared to the solid-state imaging device 1A according to the first embodiment described above.

[0141] In addition, in this second embodiment, the capacitance element Cp sharing the first electrode 47c is described as two capacitance elements Cp, but the two capacitance elements Cp sharing the first electrode 47c can also be regarded as one capacitance element Cp.

[0142] Third Embodiment Next, a solid-state imaging device 1C according to a third embodiment of the present technology will be described with reference to FIGS. FIG. 13 is a plan view illustrating a schematic configuration example of two pixel blocks in a solid-state imaging device according to a third embodiment of the present technology. FIG. 14 is a longitudinal sectional view that typically shows a longitudinal sectional structure taken along the a13-a13 cutting line in FIG. As shown in Figures 13 and 14, the solid-state imaging device 1C of the third embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1B of the second embodiment described above, except for the configuration of the first electrode 47c of the capacitance element Cp. That is, as shown in FIGS. 13 and 14, a first electrode 47c in the third embodiment is provided across the upper surface portion 22a and the side surface portion 22b of the photoelectric conversion region 22 with a dielectric film 46c interposed therebetween.

[0143] In the third embodiment, the second electrode 52c (free diffusion region FD2) is provided across the upper surface portion 22a and the side surface portion 22b of the photoelectric conversion region 22. Therefore, the first electrode 47c in the third embodiment is adjacent to (faces) the second electrode 52c across the upper surface portion 22a and the side surface portion 22b of the photoelectric conversion region 22 with the dielectric film 46c interposed therebetween.

[0144] In the third embodiment, the first electrode 47c is shared by the capacitance elements Cp of the two photoelectric conversion regions 22 aligned in the X direction in a plan view. Therefore, the first electrode 47c in the third embodiment is provided across the upper surface portion 22a and the side surface portion 22b of each of the two photoelectric conversion regions 22 aligned in the X direction in a plan view, and is adjacent to the second electrodes 52c of each of the two photoelectric conversion regions 22 with the dielectric film 46c interposed therebetween.

[0145] The first electrode 47c of this third embodiment extends across the photoelectric conversion region 22 and the inter-pixel isolation region 31 in a planar view outside the first surface portion S1 of the semiconductor layer 21, and has a head with a dielectric film 46c interposed therebetween on the upper surface portion 22a of the photoelectric conversion region 22, and a leg portion that protrudes from this head toward the inter-pixel isolation region 31 and is adjacent to the second electrode 52c (floating diffusion region FD2) on the side portion 22b of the photoelectric conversion region 22 with the dielectric film 46c interposed therebetween.

[0146] The solid-state imaging device 1C according to the third embodiment also provides the same effects as the solid-state imaging device 1B according to the second embodiment.

[0147] Furthermore, since the capacitive element Cp of the third embodiment has the first electrode 47c and the second electrode 52c each extending across the upper surface 22a and the side surface 22b of the photoelectric conversion region 22, the capacitance can be increased compared to the capacitive elements Cp of the first and second embodiments described above.

[0148] The configuration in which the first electrode 47c of the capacitance element Cp is provided across the upper surface portion 22a and the side surface portion 22b of the photoelectric conversion region 22 can also be applied to the capacitance element Cp of the above-mentioned first embodiment.

[0149] <Modification of the third embodiment> <Variation 3-1> In the above-described third embodiment, the first electrode 47c of the capacitance element Cp is provided across the upper surface portion 22a and the side surface portion 22b of the photoelectric conversion region 22 with a dielectric film 46c interposed therebetween, but the present technology is not limited to the above-described first embodiment.

[0150] 15, the first electrode 47c of the capacitance element Cp may be provided across the upper surface portion 22a and the two side surface portions 22b, 22c of the photoelectric conversion region 22 with a dielectric film 46c interposed therebetween. In the case of this modification 3-1, the second electrode 52c (floating diffusion region FD2) is also provided across the upper surface portion 22a and the two side surface portions 22b, 22c of the photoelectric conversion region 22. The first electrode 47c of the capacitance element Cp is adjacent to the second electrode 52c (floating diffusion region FD2) across the upper surface portion 22a and the two side surface portions 22b, 22c of the photoelectric conversion region 22 with a dielectric film 46c interposed therebetween. The side surface portion (inner side surface portion) 22c of the photoelectric conversion region 22 is located on the opposite side to the side surface portion (outer side surface portion) 22b of the photoelectric conversion region 22 in a plan view, and is adjacent to the inter-element isolation region 41.

[0151] In this modified example 3-1 as well, the same effects as those of the above-described third embodiment can be obtained. Furthermore, since the capacitive element Cp of this modified example 3-1 has the first electrode 47c and the second electrode 52c each extending across the upper surface portion 22a and the two side surface portions 22b, 22c of the photoelectric conversion region 22, the capacitance can be made larger than that of the capacitive element Cp of the third embodiment described above.

[0152] [Fourth embodiment] Next, a solid-state imaging device 1D according to a fourth embodiment of the present technology will be described with reference to FIGS. FIG. 16 is an equivalent circuit diagram showing a configuration example of a readout circuit in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 17 is a plan view illustrating a schematic configuration example of two pixels in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 18 is a longitudinal sectional view that illustrates a schematic longitudinal sectional structure taken along the a17-a17 cutting line in FIG.

[0153] As shown in Figures 16 to 18, the solid-state imaging device 1D of the fourth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A of the first embodiment described above, with the following differences.

[0154] That is, the solid-state imaging device 1D of the fourth embodiment includes a photoelectric conversion circuit 15D and a readout circuit 16D shown in Fig. 16, instead of the photoelectric conversion circuit 15 and the readout circuit 16 of the first embodiment shown in Fig. 3. In the fourth embodiment, the transistor layout of the photoelectric conversion region 22 is slightly different from that of the first embodiment. The other configurations are generally similar to those of the first embodiment.

[0155] <Photoelectric conversion circuit and readout circuit> 16, the photoelectric conversion circuit 15D includes, for example but not limited to, a photoelectric conversion unit 25, a charge holding unit 26 that holds (accumulates) signal charge photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR that transfers the signal charge photoelectrically converted by the photoelectric conversion unit 25 to the charge holding unit 26D. The photoelectric conversion circuit 15D is provided for each pixel 3. Although not limited thereto, the readout circuit 16D includes, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and two switching transistors FCG and FDG as pixel transistors Q. That is, the readout circuit 16D of the fourth embodiment has a five-transistor configuration.

[0156] Here, in the fourth embodiment, as an example, a circuit configuration is shown in which one readout circuit 16D is assigned to each pixel 3, but the present invention is not limited to this fourth embodiment. For example, a circuit configuration may be used in which one readout circuit 16D is assigned to two pixels 3 as one unit, or a circuit configuration may be used in which one readout circuit 16D is assigned to three or more pixels 3 as one unit.

[0157] <Photoelectric conversion circuit> (Photoelectric conversion section and transfer transistor) The photoelectric conversion unit 25 and the transfer transistor TR shown in FIG. 16 have the same configuration as the photoelectric conversion unit 25 and the transfer transistor TR in the above-described first embodiment, and therefore a description thereof will be omitted in this fourth embodiment.

[0158] (Charge holding part) Unlike the charge holding unit 26 of the first embodiment described above, the charge holding unit 26D has three floating diffusion regions FD1, FD2, and FD3, and, as capacitive elements, a capacitive element Cp having a MOS structure and a capacitive element Cpm having a MIM (Metal Insulator Metal) structure.

[0159] The floating diffusion region FD1 is connected between the transfer transistor TR and the switching transistor FDG, as in the first embodiment described above. The floating diffusion region FD2 is connected between the switching transistors FDG and FCG. The floating diffusion region FD3 is connected between the switching transistor FCG and the reset transistor RST. The capacitance element Cp is connected to the floating diffusion region FD2 as in the first embodiment described above, and the capacitance element Cpm is connected to the floating diffusion region FD3.

[0160] The floating diffusion region FD1 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR. The floating diffusion region FD2 and the capacitance element Cp temporarily accumulate and hold the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR when the switching transistor FDG is in a conductive state (ON state). The floating diffusion region FD3 and the capacitance element Cpm temporarily accumulate and hold the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR when each of the switching transistors FDG and FCG is in a conductive state (ON state).

[0161] <Readout circuit> As shown in FIG. 16, the input stage of the readout circuit 16D is electrically connected to the floating diffusion region FD1 of the charge holding unit 26D. When the switching transistor FDG is in a non-conductive state (OFF state), the readout circuit 16D reads out the signal charge held in the floating diffusion region FD1 of the charge holding unit 26. When the switching transistor FDG is in a conductive state (ON state) and the switching transistor FCG is in a non-conductive state (OFF state), the readout circuit 16D reads out the signal charge held in the floating diffusion regions FD1, FD2 and FD3 of the charge holding unit 26 and the capacitance elements Cp and Cpm. When each of the switching transistors FDG and FCG is in a conductive state (ON state), the readout circuit 16D reads out the signal charge held in the floating diffusion regions FD1, FD2 and FD3 of the charge holding unit 26 and the capacitance elements Cp and Cpm. The readout circuit 16D then outputs a pixel signal based on the read-out signal charge. In other words, the readout circuit 16D converts the signal charge photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on this signal charge and outputs it.

[0162] The pixel transistors Q (AMP, RST, SEL, FCG, FDG) included in the readout circuit 16D and the transfer transistors TR included in the photoelectric conversion circuit 15D are configured as insulated gate type field effect transistors, for example, MOSFETs. Moreover, these pixel transistors Q and transfer transistors TR may be MISFETs.

[0163] The amplification transistor AMP and the selection transistor SEL shown in FIG. 16 are connected in the same manner as in the first embodiment described above, and therefore a description thereof will be omitted in this fourth embodiment.

[0164] 16, the source region of the reset transistor RST is electrically connected to the floating diffusion region FD3 of the charge holding unit 26D and the drain region of the switching transistor FCG, and the drain region is electrically connected to the power supply line VDD and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG.

[0165] 16, the source region of the switching transistor FCG is electrically connected to the floating diffusion region FD2 of the charge holding unit 26D and the drain region of the switching transistor FDG, and the drain region of the switching transistor FCG is electrically connected to the floating diffusion region FD3 of the charge holding unit 26D and the drain region of the reset transistor RST. The gate electrode of the switching transistor FCG is electrically connected to the second switching transistor driving line of the pixel driving line 10 shown in FIG.

[0166] 16, the source region of the switching transistor FDG is electrically connected to the floating diffusion region FD1 of the charge holding unit 26D, the drain region of the transfer transistor TR, and the gate electrode of the amplification transistor AMP, and the drain region of the switching transistor FCG is electrically connected to the floating diffusion region FD2 of the charge holding unit 26 and the drain region of the switching transistor FCG. The gate electrode of the switching transistor FDG is electrically connected to the first switching transistor driving line of the pixel driving line 10 shown in FIG.

[0167] When the transfer transistor TR shown in FIG. 16 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the charge holding unit 26D.

[0168] When the reset transistor RST shown in FIG. 16 is turned on, it resets the potential (signal charge) of the charge holding unit 26D (FD1, FD2, FD3, Cp, Cpm) to the potential of the power supply line VDD. The selection transistor SEL shown in FIG.

[0169] 16 generates a pixel signal having a voltage corresponding to the level of the signal charge held in the charge holding unit 26D. The amplifier transistor AMP constitutes a source-follower type amplifier, and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the charge holding unit 26D and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0170] 16, like the switching transistor FDG of the first embodiment described above, controls charge retention by the floating diffusion regions FD1, FD2, and FD3, and adjusts the voltage multiplication factor according to the potential amplified by the amplification transistor AMP. Then, by switching on / off each of these two switching transistors FCG and FDG, like the readout circuit 16 of the first embodiment described above, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0171] 17, the switching transistor FCG has a gate electrode 47f provided in the element formation region 43 of the photoelectric conversion region 22 with a gate insulating film interposed therebetween, and a pair of main electrode regions 52fc and 52r provided in the element formation region 43 of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47f in a plan view and functioning as a source region and a drain region. The switching transistor FCG further has a channel formation portion provided in the element formation region 43 (semiconductor layer 21) overlapping with the gate electrode 47f in a plan view. The pair of main electrode regions 52f and 52r are formed of n-type semiconductor regions, and the channel formation portion is formed of a p-type semiconductor region 23.

[0172] 17, the switching transistor FDG has a gate electrode 47f provided in the element formation region 43 of the photoelectric conversion region 22 with a gate insulating film interposed therebetween, and a pair of main electrode regions 52f and 52fc provided in the element formation region 43 of the photoelectric conversion region 22 spaced apart from each other in the gate length direction of the gate electrode 47f in a plan view and functioning as a source region and a drain region. The switching transistor FDG further has a channel formation portion provided in the element formation region 43 (semiconductor layer 21) overlapping with the gate electrode 47f in a plan view. The pair of main electrode regions 52f and 52fc are formed of n-type semiconductor regions, and the channel formation portion is formed of a p-type semiconductor region 23.

[0173] In the fourth embodiment, the reset transistor RST and the switching transistor FCG share a main electrode region 52r of the reset transistor RST and a main electrode region 52r of the switching transistor FCG, and are connected in series. Also, the switching transistor FCG and the switching transistor FDG share a main electrode region 52fc of the switching transistor FCG and a main electrode region 52fc of the switching transistor FDG, and are connected in series. That is, the reset transistor RST and the two switching transistors FCG and FDG are provided in the element formation region 43 of the photoelectric conversion region 22 in a state of being directly connected to each other.

[0174] In the fourth embodiment, the floating diffusion region FD1 also serves as the main electrode region 52f of the switching transistor FDG. The floating diffusion region FD2 also serves as the main electrode region 52fc of the switching transistors FDG and FCG. The floating diffusion region FD3 also serves as the main electrode region 52r of the switching transistor FCDG and the reset transistor RST.

[0175] <Capacitor element Cp> As shown in Figure 18, the capacitance element Cp of this fourth embodiment, similar to the first embodiment described above, has a dielectric film 46c provided on the side portion 22b of the photoelectric conversion region 22, a first electrode 47c provided in the inter-pixel isolation region 31 adjacent to (facing) the side portion 22b of the photoelectric conversion region 22 with the dielectric film 46c interposed therebetween, and a second electrode 52c provided adjacent to the first electrode 47c on the inside of the side portion 22b of the photoelectric conversion region 22.

[0176] The capacitance element Cp of the fourth embodiment differs from that of the first embodiment in the configuration of the second electrode 52c. That is, the second electrode 52c of the first embodiment is also used as the main electrode region 52r of the switching transistor FDG as shown in Fig. 6B. In contrast, the capacitance element Cp of the fourth embodiment is also used as the main electrode region 52ar of the recess transistor RST and the amplification transistor AMP as shown in Fig. 18.

[0177] 18, in two photoelectric conversion regions 22 (22Xe, 22Xf) arranged adjacent to each other in the X direction in a plan view, a first electrode 47c of a capacitance element Cp having a second electrode 52c provided in one photoelectric conversion region 22Xe is electrically connected to a wiring 58c provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 57c provided in the interlayer insulating film 56. The wiring 58c is electrically connected to a main electrode region 47fc of a switching transistor FCG provided in the other photoelectric conversion region 22 via a contact electrode 57fc provided in the interlayer insulating film 56.

[0178] <Capacitor element Cpm> Although not shown, the capacitive element Cpm of the MIM structure is provided, for example, in the multilayer wiring layer 55. This capacitive element Cpm of the MIM structure can be configured with two wiring layers and one interlayer insulating film in the multilayer wiring layer 55, and can achieve large capacitance.

[0179] <<Main Effects of the Fourth Embodiment>> The solid-state imaging device 1D according to the fourth embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0180] In the fourth embodiment, the capacitive element Cpm of the MIM structure is connected to the floating diffusion region FD3, which is effective when the high capacitance due to the wiring capacitance or the capacitive element Cpm of the MIM structure is not required in the floating diffusion region FD2.

[0181] Fifth embodiment <Applications to electronic devices> The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions. FIG. 19 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a fourth embodiment of the present technology.

[0182] 19, the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 illustrates an embodiment in which the solid-state imaging devices 1A to 1D according to the first to fourth embodiments of the present technology are used as the solid-state imaging device 101 in an electronic device (e.g., a camera).

[0183] The optical lens 102 focuses image light (incident light 106) from a subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 transfer charges in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 101. The video signals that have undergone signal processing are stored in a storage medium such as a memory, or output to a monitor.

[0184] With this configuration, the pixels 3 are miniaturized in the solid-state imaging device 101, and therefore the image quality performance of the electronic device 100 of the eleventh embodiment can be improved.

[0185] The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0186] In addition, the present technology can be applied to light detection devices in general, including distance measuring sensors that measure distance, called ToF (Time of Flight) sensors, in addition to the solid-state imaging devices as image sensors described above. Distance measuring sensors emit light toward an object, detect the light reflected back from the surface of the object, and calculate the distance to the object based on the flight time from when the light is emitted to when the reflected light is received. The pixel transistor described above can also be used in these distance measuring sensors.

[0187] The present technology may be configured as follows. (1) The semiconductor layer has a first surface portion and a second surface portion located opposite each other in a thickness direction, and has a photoelectric conversion region partitioned by a separation region extending in the thickness direction, The photoelectric conversion region is an upper surface portion of the semiconductor layer located on the first surface portion side; A side portion located on the separation region side; A pixel transistor provided on the upper surface side; a floating diffusion region provided on the upper surface side and configured to hold signal charges photoelectrically converted by the photoelectric conversion portion; a capacitance element connected to the floating diffusion region; having The capacitive element is a first electrode provided in the isolation region adjacent to the side surface portion of the photoelectric conversion region with a dielectric film interposed therebetween; a second electrode provided adjacent to the first electrode on the inner side of the side surface of the photoelectric conversion region; (2) the floating diffusion region is provided across the top surface portion and the side surface portion of the photoelectric conversion region, The photodetector according to (1) above, wherein the second electrode also serves as the floating diffusion region. (3) The photodetector according to (1) or (2) above, wherein the first electrode is provided across the inside and outside of the separation region. (4) The photodetector according to (1) or (2) above, wherein the first electrode is embedded in the isolation region. (5) The photodetector according to (1) or (2) above, wherein the first electrode is provided along the top surface and the side surface of the photoelectric conversion region with the dielectric film interposed therebetween. (6) A photodetection device described in any of (1) to (5) above, wherein the first electrode is shared by two of the photoelectric conversion regions adjacent to each other in a planar view via the separation region, and is adjacent to the second electrodes of each of the two photoelectric conversion regions via the dielectric film. (7) A photodetection device described in any of (1) to (5) above, wherein in two photoelectric conversion regions adjacent to each other via the separation region in a planar view, the first electrode adjacent to the second electrode of one of the photoelectric conversion regions is connected to a main electrode region of the pixel transistor provided in the other photoelectric conversion region at the side portion of the other photoelectric conversion region. (8) the isolation region has a recessed portion provided in the semiconductor layer and an isolation insulating film embedded in the recessed portion, The photodetector according to any one of (1) to (7) above, wherein the dielectric film includes a film having a higher dielectric constant than the isolation insulating film. (9) A photodetector; an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device; a signal processing circuit for processing a signal output from the photodetector; Equipped with The light detection device includes: The semiconductor layer has a first surface portion and a second surface portion located opposite each other in a thickness direction, and has a photoelectric conversion region partitioned by a separation region extending in the thickness direction, The photoelectric conversion region is an upper surface portion of the semiconductor layer located on the first surface portion side; A side portion located on the separation region side; A pixel transistor provided on the upper surface side; a floating diffusion region provided on the upper surface side and configured to hold signal charges photoelectrically converted by the photoelectric conversion portion; a capacitance element connected to the floating diffusion region; Equipped with The capacitive element is a first electrode provided in the isolation region adjacent to the side surface portion of the photoelectric conversion region with a dielectric film interposed therebetween; the second electrode being provided adjacent to the first electrode on the inner side of the side surface of the photoelectric conversion region.

[0188] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve the same effect as the intended purpose of the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features. [Explanation of symbols]

[0189] 1A, 1B, 1C, 1D...Solid-state imaging device 2. Semiconductor chip 2A: Pixel array section 2B: Periphery 3...Pixels 4. Vertical drive circuit 5...Column signal processing circuit 6...Horizontal drive circuit 7. Output circuit 8...Control circuit 10...Pixel drive line 11...Vertical signal line 12...Horizontal signal line 13...Logic circuit 14…Bonding pad 15...Photoelectric conversion circuit 16...Readout circuit (pixel circuit) 21...Semiconductor layer 22...Photoelectric conversion area 22a...Top part 22b…Side part 23...p-type semiconductor region 24...n-type semiconductor region 25...Photoelectric conversion section 26...Charge holding part 31...Inter-pixel isolation region (isolation region) 31b1…First vertical section 31b2…Second vertical section 31bz…Step 31x…1st plane part 31y…Second plane part 31z1…First vertical section 31z2…Second vertical section 33…Dug-in section 34...Isolation insulating film 41...Element isolation region (field isolation region) 42a...Shallow groove part 42b...Isolation insulating film 43...Element formation region (active region) 46...Gate insulating film 46c...Dielectric film 47...electrode film 47a, 47r, 47s, 47t...gate electrode 47t1…Head 47t2…Leg 47c...1st electrode 51…Dug-in section 52as,52as,52r,52s…Main electrode area 52c…Second electrode 52c1…Part 1 52c2…Second part 53f, 53r, 53s...Channel forming section 55...Multilayer wiring layer 56...Interlayer insulating film 57…First wiring layer 57a, 57f, 57r, 57s, 57t...Contact electrodes 58a, 58r, 58s, 58t...Wiring 61...Planarization film 63...Optical filter 64...Micro lens 100...Electronic equipment 101...Solid-state imaging device 102...Optical lens (optical system) 103...Shutter device 104...Drive circuit 105...Signal processing circuit AMP: Amplification transistor FD1, FD2...n-type floating diffusion regions FCG, FDG…switching transistor Q: Pixel transistor RST: Reset transistor SEL...Select transistor S1 …1 surface S2: Second surface TR: Transfer transistor WC: Power supply contact area

Claims

1. a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in a thickness direction, and having a photoelectric conversion region partitioned by a separation region extending in the thickness direction; The photoelectric conversion region is an upper surface portion of the semiconductor layer located on the first surface portion side; A side portion located on the separation region side; A pixel transistor provided on the upper surface side; a floating diffusion region provided on the upper surface portion and configured to hold signal charges photoelectrically converted by the photoelectric conversion portion; a capacitance element connected to the floating diffusion region; having The capacitive element is a first electrode provided in the isolation region adjacent to the side surface portion of the photoelectric conversion region with a dielectric film interposed therebetween; a second electrode provided adjacent to the first electrode on the inner side of the side portion of the photoelectric conversion region;

2. the floating diffusion region is provided across the top surface portion and the side surface portion of the photoelectric conversion region, The photodetector according to claim 1 , wherein the second electrode also serves as the floating diffusion region.

3. The photodetector according to claim 1 , wherein the first electrode is provided across the inside and outside of the isolation region.

4. The photodetector device of claim 1 , wherein the first electrode is embedded in the isolation region.

5. The photodetector according to claim 1 , wherein the first electrode is provided along the top surface and the side surface of the photoelectric conversion region with the dielectric film interposed therebetween.

6. 2. The photodetection device of claim 1, wherein the first electrode is shared by two of the photoelectric conversion regions adjacent to each other in a planar view via the isolation region, and is adjacent to the second electrode of each of the two photoelectric conversion regions via the dielectric film.

7. 2. The photodetection device of claim 1, wherein in two photoelectric conversion regions adjacent to each other in a planar view via the separation region, the first electrode adjacent to the second electrode of one of the photoelectric conversion regions is connected to a main electrode region of the pixel transistor provided in the other of the photoelectric conversion regions at the side portion of the other of the photoelectric conversion regions.

8. the isolation region has a recessed portion provided in the semiconductor layer and an isolation insulating film embedded in the recessed portion, The photodetector according to claim 1 , wherein the dielectric film includes a film having a higher dielectric constant than the isolation insulating film.

9. A photodetector; an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device; a signal processing circuit for processing a signal output from the photodetector; Equipped with The light detection device includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in a thickness direction, and having a photoelectric conversion region partitioned by a separation region extending in the thickness direction; The photoelectric conversion region is an upper surface portion of the semiconductor layer located on the first surface portion side; A side portion located on the separation region side; A pixel transistor provided on the upper surface side; a floating diffusion region provided on the upper surface portion and configured to hold signal charges photoelectrically converted by the photoelectric conversion portion; a capacitance element connected to the floating diffusion region; Equipped with The capacitive element is a first electrode provided in the isolation region adjacent to the side surface portion of the photoelectric conversion region with a dielectric film interposed therebetween; and a second electrode provided adjacent to the first electrode on the inner side of the side portion of the photoelectric conversion region.

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