Semiconductor device and method or manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of suppressing occurrence of a void at an end part of a bonding pad and deterioration in EM resistance and SM resistance, etc.SOLUTION: A semiconductor device 1 of an embodiment comprise a first device configuration part including a metal pad 5 provided on a first semiconductor substrate and a first circuit connected to at least a part of the first metal pad 5, and a second device configuration part bonded to the first device configuration part, provided so as to correspond to the first metal pad 5, and including a second metal pad 8 joined to the first metal part 5 and a second circuit connected to at least a part of the second metal pad 8. In the semiconductor device of the embodiment, at least one of the first metal pad 5 and the second metal pad 8 includes a recess provided on a bonding surface between the first device configuration part and the second device configuration part, and a carbon film filled in the recess.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In order to increase the density of semiconductor devices and to effectively utilize the device area, a lamination process is applied in which, for example, a semiconductor substrate having a memory cell and a semiconductor substrate having a peripheral circuit such as a CMOS are laminated together while bonding metal pads provided on each semiconductor substrate. In a semiconductor device having a laminated substrate to which a lamination process is applied, there is a concern that voids are formed at the end of the laminated metal pad (lamination pad), which deteriorates EM (Electromigration) resistance and SM (Stress Migration) resistance. Therefore, there is a demand for suppressing the generation of voids at the end of the lamination pad. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-092197 A [Patent Document 2] US Patent Publication No. 2021 / 0217716 [Patent Document 3] JP 2020-092146 A Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that suppresses the occurrence of voids at the end of a bonding pad and makes it possible to prevent deterioration of EM resistance, SM resistance, etc. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a first device component including a first metal pad provided on a first semiconductor substrate and a first circuit connected to at least a portion of the first metal pad, and a second device component attached to the first device component, the second device component including a second metal pad provided to correspond to the first metal pad and joined to the first metal pad, and a second circuit connected to at least a portion of the second metal pad. In the semiconductor device according to an embodiment, at least one of the first metal pad and the second metal pad has a recess provided on a bonding surface between the first device component and the second device component, and a carbon film filled in the recess. [Brief description of the drawings]

[0006] [Figure 1] 4 is a cross-sectional view showing a structure of the semiconductor device of the embodiment at a stage prior to thinning a second semiconductor substrate. FIG. [Diagram 2] 4 is a cross-sectional view showing a structure of the semiconductor device of the embodiment at a stage after the second semiconductor substrate has been thinned. FIG. [Diagram 3] 2 is an enlarged cross-sectional view showing a bonded body of a metal pad in the semiconductor device shown in FIG. 1. [Figure 4] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG. [Diagram 5] 1A to 1C are cross-sectional views showing a conventional manufacturing process for a semiconductor device. [Figure 6] 4 is an enlarged cross-sectional view showing a modified example of the bonded body of the metal pad shown in FIG. [Figure 7] 1 is a cross-sectional view showing a configuration example of a semiconductor chip manufactured using the semiconductor device of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the semiconductor device and the manufacturing method thereof according to the embodiment will be described with reference to the drawings. In each embodiment, the same reference numerals are used for substantially the same components, and the description thereof may be omitted. The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each part, etc. may differ from the actual ones. Terms indicating directions such as up and down in the description indicate relative directions in the case where the surface on which the metal pads of the first semiconductor substrate described later are formed is considered to be up, unless otherwise specified, and may differ from the actual directions based on the direction of gravitational acceleration.

[0008] 1 and 2 are cross-sectional views showing a semiconductor device 1 according to an embodiment, and Fig. 3 is an enlarged cross-sectional view showing a bonded body of metal pads in the semiconductor device 1 according to an embodiment. Fig. 1 shows the semiconductor device 1 in a stage before one of the two semiconductor substrates constituting a bonded substrate is thinned by back grinding or chemical treatment, and Fig. 2 shows the semiconductor device 1 in a stage after one of the semiconductor substrates has been thinned by back grinding or chemical treatment.

[0009] The semiconductor device 1 shown in FIG. 1 includes a first semiconductor substrate 2 and a second semiconductor substrate 3. The first semiconductor substrate 2 and the second semiconductor substrate 3 are bonded together to form a bonded substrate 4. That is, the semiconductor device 1 includes the bonded substrate 4. Reference symbol S indicates a bonding surface between the first semiconductor substrate 2 and the second semiconductor substrate 3. The bonding surface S is shown for convenience, and since the first semiconductor substrate 2 and the second semiconductor substrate 3 are integrated, there may be no visible bonding interface. However, by analyzing a cross section of the bonded substrate 4, it can be determined that the first semiconductor substrate 2 and the second semiconductor substrate 3 are bonded together.

[0010] The first semiconductor substrate 2 has a plurality of first metal pads 5. A first wiring layer 6 is connected to at least a portion of the first metal pads 5. The first metal pads 5 and the first wiring layer 6 are embedded in a first insulating layer 7 as an interlayer insulating film. The first metal pads 5 are arranged so that their surfaces are exposed to the surface of the first insulating layer 7. The second semiconductor substrate 3 has a plurality of second metal pads 8. A second wiring layer 9 is connected to at least a portion of the second metal pads 8. The second metal pads 8 and the second wiring layer 9 are embedded in a second insulating layer 10 as an interlayer insulating film. The second metal pads 8 are arranged so that their surfaces are exposed to the surface of the second insulating layer 10. In FIG. 1 and FIG. 2, a state in which the first and second metal pads 5 and 8 are connected to the first and second wiring layers 6 and 9 is shown. That is, FIG. 1 and FIG. 2 show the first and second metal pads 5 and 8 to which the first and second wiring layers 6 and 9 are connected. Some of the first and second metal pads 5, 8 may be dummy pads that are not connected to the wiring layers. Furthermore, the first and second wiring layers 6, 9 may include via plugs or the like as described later.

[0011] The first semiconductor substrate 2 has a first circuit region 12 in which a first circuit (not shown) including peripheral circuits (not shown) such as CMOS transistors and passive elements, and a wiring layer connecting the peripheral circuits to at least a part of the first metal pad 5, is provided. The first circuit region 12 is provided on a semiconductor substrate body 11 of the first semiconductor substrate 2. The second semiconductor substrate 3 has a second circuit region 14 in which a second circuit (not shown) including a pixel array including a plurality of image sensor pixels, a memory cell array including a plurality of memory cells, a source line, a plurality of bit lines, a wiring layer connected to at least a part of the second metal pad 8, and the like is provided. The second circuit region 14 is provided below (above in the manufacturing process of the semiconductor device) the semiconductor substrate body 13 of the second semiconductor substrate 3. The first semiconductor substrate 2 constitutes, for example, a control circuit chip, and the second semiconductor substrate 3 constitutes, for example, an array chip.

[0012] As shown in FIG. 2, the second semiconductor substrate 3 may be thinned by performing back grinding or chemical treatment on the laminated substrate 4 so that at least the second circuit region 14 remains. In this case, the semiconductor substrate body 13 of the second semiconductor substrate 3 may or may not remain. In the semiconductor device 1 shown in FIG. 2, the first semiconductor substrate 2 having the first metal pads 5 and the first circuit region 12 becomes the first device component. The second semiconductor substrate 3 having the second metal pads 8 and the second circuit region 14 and from which the semiconductor substrate body 13 has been removed, in other words, the remaining portion of the second semiconductor substrate 3 from which the semiconductor substrate body 13 has been removed, becomes the second device component. Furthermore, the first semiconductor substrate 2 and the second semiconductor substrate 3, which have a wafer shape when laminated, respectively correspond to a first chip component member and a second chip component member including a plurality of constituent units of a chip to be fabricated using them.

[0013] As shown in FIG. 3, the first metal pad 5 and the second metal pad 8 are embedded in the first wiring layer 7 and the second wiring layer 10 via the barrier metal layers 15 and 16, respectively. As the barrier metal layers 15 and 16, Ti, Ti alloy, TiN, Ta, Ta alloy, TaN, etc. are generally used. As shown in FIG. 3, the first metal pad 5 and the second metal pad 8 are bonded (bonded) by a bonding process described later to form a bonded body 17. Although not shown in FIG. 3, the first semiconductor substrate 2 includes the first wiring layer 6 connected to at least a part of the first metal pad 5 as described above, and the first circuit region 12 including a first circuit including a peripheral circuit such as a transistor such as a CMOS or a passive element, a wiring layer, etc. The second semiconductor substrate 3 includes the second wiring layer 9 connected to at least a part of the second metal pad 8 as described above, and the second circuit region 14 including a second circuit including a pixel array, a memory cell array, a wiring layer, etc.

[0014] The first metal pad 5 and the second metal pad 8 are arranged so as to be exposed on the surfaces of the first insulating layer 7 and the second insulating layer 10, and contribute to bonding the first semiconductor substrate 2 and the second semiconductor substrate 3. The first insulating layer 7 and the second insulating layer 10 also contribute to bonding the first semiconductor substrate 2 and the second semiconductor substrate 3. The first and second insulating layers 7 and 10 are made of inorganic insulating materials such as silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), and nitrogen-containing silicon carbide (SiCN), but may be made of other insulating materials. The first and second insulating layers 7 and 10 may have a structure in which one or more materials are laminated. The first and second metal pads 5 and 8 are made of metal materials having a higher thermal expansion coefficient than the inorganic insulating materials used for the first and second insulating layers 7 and 10, such as copper and copper alloys, but may be made of other metal materials.

[0015] The surface of the first metal pad 5 exposed on the bonding surface of the first semiconductor substrate 2 and the surface of the second metal pad 8 exposed on the bonding surface of the second semiconductor substrate 3 are directly bonded by element diffusion between metals, van der Waals force, metallic bonding due to volume expansion (thermal expansion), etc. Furthermore, the surface of the first insulating layer 7 exposed on the bonding surface of the first semiconductor substrate 2 and the surface of the second insulating layer 10 exposed on the bonding surface of the second semiconductor substrate 3 are directly bonded by element diffusion between insulators, van der Waals force, chemical reactions such as dehydration condensation and polymerization, etc. In this way, the first semiconductor substrate 2 and the second semiconductor substrate 3 are bonded together.

[0016] For example, when a SiO2 film or the like is applied to the first and second insulating layers 7, 10, the surfaces of the first and second insulating layers 7, 10 are activated by plasma of nitrogen (N2), oxygen (O2), argon (Ar), or the like. Next, the surfaces of the first and second insulating layers 7, 10 are washed with deionized water or the like, and OH groups (Si-OH bonds) are added to the surfaces. Next, the first semiconductor substrate 2 and the second semiconductor substrate 3 are aligned and laminated. At this time, the first semiconductor substrate 2 and the second semiconductor substrate 3 are bonded by hydrogen bonds between the surfaces of the first insulating layer 7 and the second insulating layer 10. After this, for example, an annealing treatment is performed at a temperature of about 300 to 400°C for about several hours, whereby the copper pads are metal-bonded by thermal expansion of copper, and the SiO2 films are covalently bonded by dehydration condensation. As a result, the first semiconductor substrate 2 and the second semiconductor substrate 3 can be firmly bonded to each other.

[0017] In the bonded body 17 of the first metal pad 5 and the second metal pad 8, at least one of the first metal pad 5 and the second metal pad 8 has recesses 18 (18A, 18B), 20 (20A, 20B) provided on the bonding surface S between the first semiconductor substrate 2 and the second semiconductor substrate 3, and carbon films 19 (19A, 19B), 21 (21A, 21B) filled in the recesses 18, 20. By filling the carbon films 19, 21 in the recesses 18, 20 provided on the bonding surface S between the first semiconductor substrate 2 and the second semiconductor substrate 3 and eliminating the spaces caused by the recesses 18, 20, it is possible to prevent deterioration of the EM resistance and SM resistance of the semiconductor device 1. In this case, by filling the recesses 18, 20 with the carbon films 19, 21, it is possible to improve the EM resistance and SM resistance by eliminating the spaces without causing deterioration of the electrical characteristics of the semiconductor device 1 or deterioration of the characteristics due to foreign matter such as metal. In Figure 3, the depression on the bonding surface S and the carbon film filling it are shown to be provided on both the first metal pad 5 and the second metal pad 8, but it is sufficient that the carbon film is provided on at least one of the first metal pad 5 and the second metal pad 8.

[0018] The depressions 18, 20 provided on the bonding surface S will be described in detail below. In the bonded body 17 of the first metal pad 5 and the second metal pad 8, the first metal pad 5 has a first depression 18A in at least a part of the area separated from the bonded second metal pad 8, and the second metal pad 8 has a first depression 18B in at least a part of the area separated from the bonded first metal pad 5. The bonded body 17 has first carbon films 19A, 19B filled in such first depressions 18A, 18B. That is, the first metal pad 5 and the second metal pad 8 have first carbon films 19A, 19B filled in the first depressions 18A, 18B provided in at least a part of the area separated from the bonded metal pads 8, 5.

[0019] Furthermore, in the bonded body 17 of the first metal pad 5 and the second metal pad 8, the first metal pad 5 has a second recess 20A in at least a part of the area facing the second metal pad 8, which is the bonded counterpart, and the second metal pad 8 has a second recess 20B in at least a part of the area facing the first metal pad 5, which is the bonded counterpart. The bonded body 17 has second carbon films 21A, 21B filled in such second recesses 20A, 20B. That is, the first metal pad 5 and the second metal pad 8 have second carbon films 21A, 21B filled in the second recesses 20A, 20B provided in at least a part of the area facing the metal pads 8, 5, which are the bonded counterparts.

[0020] As described above, the first carbon films 19A, 19B are filled in the first recesses 18A, 18B provided in at least a part of the region outside the metal pads 8, 5 to be joined of the first metal pad 5 and the second metal pad 8, and the space due to the first recesses 18A, 18B is eliminated, so that it is possible to prevent deterioration of the EM resistance and SM resistance of the semiconductor device 1. Furthermore, in addition to eliminating the space due to the recesses 18A, 18B provided in the region outside the metal pads 8, 5 to be joined of the metal pads 5, 8, the second carbon films 21A, 21B are filled in the second recesses 20A, 20B provided in at least a part of the region facing the metal pads 8, 5 to be joined of the first metal pad 5 and the second metal pad 8, and the space due to the second recesses 20A, 20B is eliminated, so that it is possible to further prevent deterioration of the EM resistance and SM resistance of the semiconductor device 1. In order to improve EM resistance and SM resistance, it is particularly effective to fill the second recesses 20A, 20B provided in at least a part of the region facing the metal pads 8, 5 to be joined with the second carbon films 21A, 21B. It is difficult to fill the second recess 20 provided in the region facing the metal pads 5, 8 with another material after bonding, but by filling the second recess 20 with the carbon film 21 during the bonding process, the second recess 20 can be reliably removed. This makes it possible to improve EM resistance and SM resistance.

[0021] Here, in the bonded body 17 of the first metal pad 5 and the second metal pad 8, the copper of the first metal pad 5 and the copper of the second metal pad 8 may be integrated, making it difficult to confirm the boundary between the copper. However, the bonding can be confirmed by the distortion of the bonded shape of the metal pad 5 and the metal pad 8 due to the misalignment of the bonding position, and the misalignment of the barrier metal layers 15 and 16 (the occurrence of discontinuous parts on the side surface). In addition, when the metal pad 5 and the metal pad 8 are formed by the damascene method, each side surface has a tapered shape. Therefore, the side wall of the vertical cross section of the bonded portion of the metal pad 5 and the metal pad 8 is not linear, but is non-rectangular. Furthermore, when the metal pad 5 and the metal pad 8 are bonded together, the bottom surface, side surface, and top surface of the copper forming them are covered with a barrier metal. In contrast, in a general wiring layer using copper, an insulating layer (SiN, SiCN, etc.) having a function of preventing oxidation of copper is provided on the top surface of the copper, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a general wiring layer.

[0022] In the first and second metal pads 5, 8, the first recess 18 provided in the area away from the metal pads 8, 5 to be joined and the second recess 20 provided in the area facing the metal pads 8, 5 to be joined are generated according to the bonding process of the first semiconductor substrate 2 and the second semiconductor substrate 3. FIG. 4 shows the manufacturing process (bonding process) of the semiconductor device 1 of the embodiment, and FIG. 5 shows the manufacturing process (bonding process) of a conventional semiconductor device in comparison with the first semiconductor substrate 1. As a pre-process of the bonding process of the first semiconductor substrate 2 and the second semiconductor substrate 3, in order to smooth the surfaces of the first and second metal pads 5, 8, the surfaces of the first and second semiconductor substrates 2, 3 before bonding are processed and smoothed by, for example, CMP (Chemical Mechanical Polishing). At this time, as shown in FIG. 5(A), the surfaces of the metal pads 5, 8 are recessed by about 3 nm on one side, so that a recess R is formed on the surfaces of the metal pads 5, 8. Although FIG. 5(A) shows only the metal pad 5, the same is true for the metal pad 8.

[0023] After aligning the metal pads 5, 8 whose surfaces are recessed by about 3 nm on one side, annealing at a temperature of about 300 to 400 ° C., the metal pads 5, 8 made of, for example, Cu expand thermally, and bonding occurs from the vicinity of the center of the upper and lower metal pads 5, 8, as shown in FIG. 5 (B). When the metal pads 5, 8 are bonded near the center, the end sides of the metal pads 5, 8 are deformed so as to drop. As the lamination process by annealing progresses further, the bonding near the center of the metal pads 5, 8 progresses, and the bonding area near the center of the metal pads 5, 8 gradually expands toward the end side. However, it is difficult to completely bond the metal pads 5, 8 to the end, and as shown in FIG. 5 (B), a recess R is likely to remain at the outer peripheral end of the metal pads 5, 8.

[0024] Even if the bonding area of ​​the metal pads 5, 8 is expanded to the end side, it is difficult to completely eliminate the recess R at the outer peripheral end of the metal pads 5, 8. For this reason, as shown in FIG. 5(C), a first recess 18 remains in the outer peripheral area of ​​each of the first metal pad 5 and the second metal pad 8 in an area away from the metal pads 8, 5 to be bonded thereto. Similarly, a second recess 20 remains in the outer peripheral area of ​​each of the first metal pad 5 and the second metal pad 8 in an area facing the metal pads 8, 5 to be bonded thereto. As described above, if such recesses 18, 20 remain, the EM resistance and SM resistance of the semiconductor device 1 will be deteriorated. Note that the recess on the bonding surface S is not limited to the outer peripheral area of ​​the metal pads 5, 8, and may be formed near the center of the metal pads 5, 8 depending on the bonding state, etc.

[0025] Therefore, in the manufacturing process of the semiconductor device 1 of the embodiment, as shown in FIG. 4(A), a carbon film 22 is formed in the recess R on the surface of the metal pad 5 formed by CMP processing. An organic film mainly made of carbon may be applied instead of the carbon film 22. The organic film used here is not limited to the organic film formed on the metal pad 5, but may be an organic film remaining in a cleaning process after CMP. The carbon film (or organic film) 22 is formed in the recess R on the surface of the metal pad 5. Although only the first metal pad 5 and the first insulating layer 7 provided on the first semiconductor substrate 2 are shown in FIG. 4(A), the second metal pad 8 and the second insulating layer 10 provided on the second semiconductor substrate 3 are actually arranged so as to face the first metal pad 5. Therefore, the carbon film (or organic film) 22 may be formed in the recess R on the surface of the second metal pad 8. The carbon film (or organic film) 22 may be formed in the recess R on the surface of at least one of the first metal pad 5 and the second metal pad 8.

[0026] Next, as shown in FIG. 4(B) and FIG. 4(C), the first metal pad 5 and the second metal pad 8 are aligned via a carbon film (or an organic film) 22 formed on at least one of the surfaces thereof, and then the first semiconductor substrate 2 on which the first metal pad 5 and the first insulating layer 7 are exposed and the second semiconductor substrate 3 on which the second metal pad 8 and the second insulating layer 10 are exposed are bonded together. The bonding process is carried out under conventionally known conditions. For example, the first semiconductor substrate 2 and the second semiconductor substrate 3 are bonded together by mechanical pressure. As a result, the first insulating layer 7 and the second insulating layer 10 are bonded together and integrated together. Next, the first semiconductor substrate 2 and the second semiconductor substrate 3 are annealed for several hours at a temperature of, for example, 300 to 400° C. As a result, the first metal pad 5 and the second metal pad 8 are bonded together, and the first and second metal pads 5 and 8 are electrically connected together and integrated together.

[0027] At this time, as shown in Fig. 4(B), by joining the metal pads 5, 8 near their centers, a carbon film (or organic film) 22 formed on the surface of at least one of the first metal pad 5 and the second metal pad 8 is present on the outer periphery of the central joint. Of these, the carbon film 22 formed on the pad surface remains as the carbon film 22 in the recess on the outer periphery of the central joint. In addition, the organic film formed on the pad surface decomposes at the annealing temperature, and after decomposition, remains as the carbon film 22 in the recess on the outer periphery of the central joint. Hydrogen, oxygen, etc. produced by decomposition of the organic film are vaporized by the annealing temperature, and do not adversely affect the semiconductor device 1.

[0028] After that, as shown in FIG. 4(C), a first carbon film 19 is filled in a first recess 18 provided in at least a part of the region away from the metal pads 8, 5 to be bonded to the metal pads 5, 8. Similarly, a second carbon film 21 is filled in a second recess 20 provided in at least a part of the region facing the metal pads 8, 5 to be bonded to the metal pads 5, 8. In this manner, a bonded substrate 4 constituting the semiconductor device 1 of the embodiment, that is, a bonded substrate 4 composed of a first semiconductor substrate 2 and a second semiconductor substrate 3, is produced. Since the first carbon film 19 and the second carbon film 21 occupy the space defined by the first recess 18 and the second recess 20, it is possible to prevent deterioration of EM resistance and SM resistance due to the presence of a space in the vicinity of the bonding surface S between the first semiconductor substrate 2 and the second semiconductor substrate 3. In other words, it is possible to provide a semiconductor device 1 including a bonded substrate 4 having excellent EM resistance and SM resistance.

[0029] FIG. 3 illustrates a case where the first metal pad 5 and the second metal pad 8 have substantially the same shape and area. In such a case, it is difficult to completely align the positions of the first metal pad 5 and the second metal pad 8 when bonding, and they are generally bonded with a slight deviation in center line as shown in FIG. 3. For this reason, when the first metal pad 5 and the second metal pad 8 have substantially the same shape, first carbon films 19A and 19B are filled in first recesses 18A and 18B provided in at least a part of the area of ​​the metal pads 5 and 8 that is not adjacent to the metal pads 8 and 5 that are bonded to the metal pads 5 and 8, as shown in FIG. 3. Furthermore, second carbon films 21A and 21B are filled in second recesses 20A and 20B provided in at least a part of the area of ​​the metal pads 5 and 8 that is opposite to the metal pads 8 and 5 that are bonded to the metal pads 5 and 8.

[0030] However, depending on the difference in area and shape between the first metal pad 5 and the second metal pad 8, and further the degree of overlap between the first metal pad 5 and the second metal pad 8, the first recess 18 and the second recess 20 may be formed only in one of the first metal pad 5 and the second metal pad 8. Therefore, the first recess 18 and the first carbon film 19 filled therein may be provided in at least a part of the region outside the metal pads 8, 5 to be joined with at least one of the first metal pad 5 and the second metal pad 8. Similarly, the second recess 20 and the second carbon film 21 filled therein may be provided in at least a part of the region facing the metal pads 8, 5 to be joined with at least one of the first metal pad 5 and the second metal pad 8.

[0031] Furthermore, when the first metal pad 5 has a larger area than the second metal pad 8, or vice versa, the second metal pad 8 may overlap with the first metal pad 5 so that the entirety of the second metal pad 8 is located inside the first metal pad 5, as shown in FIG. 6. FIG. 6 is an enlarged cross-sectional view showing a modified example of a bonded body of metal pads. In the bonded body shown in FIG. 6, only the first metal pad 5 has a first recess 18 provided in at least a part of the area away from the bonded metal pad 8 and a first carbon film 19 filled therein. Similarly, only the second metal pad 8 has a second recess 20 provided in at least a part of the area facing the bonded metal pad 5 and a second carbon film 21 filled therein. In such a case, for example, a carbon film or an organic film (reference numeral 22 in FIG. 4) may be formed only on the surface of the second metal pad 8 having a smaller area in FIG. 6, and the step of filling the second recess 20 with the second carbon film 21 may be preferentially performed. In this way, various combinations of the first depression 18 and the first carbon film 19 and the second depression 20 and the second carbon film 21 can be applied depending on the area and shape of the first metal pad 5 and the second metal pad 8, and further on the degree of overlap between the first metal pad 5 and the second metal pad 8, etc.

[0032] Next, an example of a semiconductor chip manufactured using the semiconductor device 1 of the above-mentioned embodiment will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view showing an example of the configuration of such a semiconductor chip. The semiconductor chip 31 shown in Fig. 7 includes a control circuit chip 32 made of a part of a first semiconductor substrate 2 having a first circuit region, and an array chip 33 made of a part of a second semiconductor substrate 3 having a second circuit region. Such a semiconductor chip 31 is manufactured by cutting the semiconductor device 1 of the embodiment along each chip region and dividing it into individual pieces. The control circuit chip 32 and the array chip 33 are bonded together.

[0033] The array chip 33 includes a memory cell array 34 including a plurality of memory cells, an insulating film 35 on the memory cell array 34, and an interlayer insulating film 36 below the memory cell array 34. The control circuit chip 32 is provided below the array chip 33. Symbol S indicates the bonding surface between the array chip 33 and the control circuit chip 32. The control circuit chip 32 includes an interlayer insulating film 37 and a substrate 38 below the interlayer insulating film 37. The substrate 38 is a semiconductor substrate such as a silicon substrate. The insulating films 35, 36, and 37 are, for example, silicon oxide films, silicon nitride films, silicon oxynitride films, etc., and may have a structure in which one or more materials are mixed or laminated.

[0034] 7 shows the X and Y directions parallel to and perpendicular to the surface of the substrate 38, and the Z direction perpendicular to the surface of the substrate 38. Here, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. For example, in the array chip 33, the memory cell array 34 functioning as the second circuit region is located above the substrate 38, and the substrate 38 is located below the memory cell array 34. The -Z direction may or may not coincide with the direction of gravity.

[0035] The array chip 33 includes a plurality of word lines WL and select gate lines (not shown) as electrode layers in a memory cell array 34. The central portion in the X direction of Fig. 7 shows a staircase structure portion of the memory cell array 34. One end of a columnar portion CL penetrating the word line WL is electrically connected to a source line BG and the other end is electrically connected to a bit line BL, and a memory cell is formed at the intersection of the columnar portion CL and the word line WL.

[0036] The control circuit chip 32 includes a plurality of transistors 39 that function as a part of the first circuit region. Each of the transistors 39 includes a gate electrode 40 provided on the substrate 38 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 38. The control circuit chip 32 further includes a plurality of plugs 41 provided on the source diffusion layer or drain diffusion layer or the gate electrode 40 of each of the transistors 39, a wiring layer 42 provided on the plugs 41 and including a plurality of wirings, and a wiring layer 43 provided on the wiring layer 42 and including a plurality of wirings. The control circuit chip 32 further includes a plurality of via plugs 44 provided on the wiring layer 43, and a plurality of metal pads 5 provided on the via plugs 44 in the insulating film 37. The control circuit chip 22 as described above functions as a control circuit (logic circuit) that controls the array chip 23.

[0037] The array chip 33 includes a plurality of metal pads 8 provided on the metal pads 5 in the insulating film 36, a plurality of via plugs 45 provided on the metal pads 8, and a wiring layer 46 including a plurality of wirings provided on the via plugs 45. Each word line WL and each bit line BL are electrically connected to a corresponding wiring in the wiring layer 46. The array chip 33 further includes via plugs 47 provided in the insulating film 36 or the insulating film 35 and provided on the wiring layer 46, and metal pads 48 provided on the insulating film 35 or the via plugs 47.

[0038] 7, and can be connected to a mounting board or other devices via bonding wires, solder balls, metal bumps, etc. The array chip 33 further includes a passivation film 49 formed on the insulating film 35 and the metal pads 48. The passivation film 49 has an opening P that exposes the upper surface of the metal pad 48, and the opening P is used, for example, to connect a bonding wire or the like to the metal pad 48.

[0039] The configurations of the above-mentioned embodiments can be applied in combination with each other, and some of them can be replaced. Although several embodiments of the present invention have been described here, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0040] Reference Signs List 1...semiconductor device, 2...first semiconductor substrate, 3...second semiconductor substrate, 4...laminate substrate, 5...first metal pad, 6...first wiring layer, 7...first insulating layer, 8...second metal pad, 9...second wiring layer, 10...second insulating layer, 11, 13...semiconductor substrate main body, 12...first circuit region, 14...second circuit region, 17...bonded body, 18...first recess, 19...first carbon film, 20...second recess, 21...second carbon film, 22...carbon film (or organic film).

Claims

1. a first device component including a first metal pad provided on a first semiconductor substrate and a first circuit connected to at least a portion of the first metal pad; a second device component including a second metal pad provided to correspond to the first metal pad and joined to the first metal pad, and a second circuit connected to at least a portion of the second metal pad, and bonded to the first device component; A semiconductor device, wherein at least one of the first metal pad and the second metal pad has a recess provided on a bonding surface between the first device component and the second device component, and a carbon film filled in the recess.

2. 2. The semiconductor device according to claim 1, wherein at least one of the first metal pad and the second metal pad has a first recess provided in at least a portion of an area separated from a mating metal pad, and a first carbon film filled in the first recess.

3. 2. The semiconductor device according to claim 1, wherein at least one of the first metal pad and the second metal pad has a second recess provided in at least a portion of an area facing a mating metal pad, and a second carbon film filled in the second recess.

4. providing a first chip component having a first semiconductor substrate, first metal pads disposed on the first semiconductor substrate, and a first circuit connected to at least a portion of the first metal pads; and a second chip component having a second semiconductor substrate, second metal pads disposed on the second semiconductor substrate, and a second circuit connected to at least a portion of the second metal pads; forming a carbon film or an organic film on a surface of at least one of the first metal pad and the second metal pad; a step of arranging the first chip component and the second chip component such that the first metal pad and the second metal pad face each other with the carbon film or the organic film interposed therebetween; a step of bonding the first chip component and the second chip component to each other by bonding the first metal pad and the second metal pad via the carbon film or the organic film to produce a bonded substrate; A method for manufacturing a semiconductor device comprising the steps of:

5. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising filling a recess provided on a bonding surface between the first chip component and the second chip component of at least one of the first metal pad and the second metal pad with carbon derived from the carbon film or the organic film to form a carbon film.

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