Sensor network

Abstract

To provide a sensor network capable of identifying relationship between a sensor detection signal and a sensor.SOLUTION: A sensor network includes an annular serial connection structure with N pieces of sensor units connected starting from a branch unit and returning to the branch unit. The sensor network includes first and second signal lines which transfer in first and second directions. Each of the N pieces of sensor units includes first and second changeover parts for detecting whether disconnection of the first and the second signal lines exist or not. The N pieces of sensor units include a first set having a first identification signal generation part and a first sensor, and a second set having a second identification signal generation part and a second sensor. The blanch unit outputs a pulse signal in which L pieces of the first identification signals and first sensor detection signals generated by L pieces of the first sets, and M pieces of the second identification signals and second sensor detection signals generated by M pieces of the second sets are included.SELECTED DRAWING: Figure 18

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a sensor network. [Background technology]

[0002] Patent Document 1 discloses a sensor system including a sensor array having a plurality of sensors arranged in a two-dimensional array and an XY decoder. The sensor array is scanned by the XY decoder, whereby the plurality of sensors can be read out. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-258018 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a sensor network that serially outputs detection signals from multiple sensors using a single signal line, there are cases where the network topology (network connection form) is changed. In this case, the output order of the multiple sensors changes, and there is a risk that it will become impossible to identify the correspondence between the multiple output data and the multiple sensors. [Means for solving the problem]

[0005] One aspect of the sensor network disclosed in this specification is a sensor network including N (N is a natural number of 2 or more) sensor units and a branching unit. The sensor network includes a serial connection structure in which the first to Nth sensor units are connected starting from the branching unit and then return to the branching unit. The sensor network includes a first signal line for transmitting a pulse signal that is transmitted from the branching unit in a first direction and returns to the branching unit, and a second signal line for transmitting a pulse signal that is transmitted from the branching unit in a second direction opposite to the first direction and returns to the branching unit. Each of the N sensor units includes a first input terminal, a first output terminal, a second input terminal, and a second output terminal. The first input terminal of the Kth (K is a natural number of 2 or more and N-1 or less) sensor unit is connected to the first output terminal of the K-1th sensor unit via the first signal line. The first output terminal of the Kth sensor unit is connected to the first input terminal of the K+1th sensor unit via the first signal line. The second input terminal of the K-th sensor unit is connected to the second output terminal of the K+1-th sensor unit via a second signal line. The second output terminal of the K-th sensor unit is connected to the second input terminal of the K-1-th sensor unit via a second signal line. Each of the N sensor units further includes a first switching unit that detects the presence or absence of a break in the first signal line connecting the first input terminal and the first output terminal of the K-1-th sensor unit, and a second switching unit that detects the presence or absence of a break in the second signal line connecting the second input terminal and the second output terminal of the K+1-th sensor unit. When no break is detected by the first switching unit and the second switching unit, each of the N sensor units transmits a pulse signal input to the first input terminal to the first output terminal and transmits a pulse signal input to the second input terminal to the second output terminal. When a break is detected by the first switching unit, each of the N sensor units transmits a pulse signal input to the second input terminal to the first output terminal. When a break is detected by the second switching section, each of the N sensor units transmits the pulse signal input to the first input terminal to the second output terminal.Each of the N sensor units includes at least one of a first set including a first identification signal generating unit and a first sensor arranged in series on a transmission path of a pulse signal from a first input terminal to a first output terminal, and a second set including a second identification signal generating unit and a second sensor arranged in series on a transmission path of a pulse signal from a second input terminal to a second output terminal. The first identification signal generating unit is a circuit that generates a first identification signal for identifying the first sensor constituting the first set in response to a pulse signal being input from the first input terminal, adds the generated first identification signal to the pulse signal, and outputs the signal to the first sensor. The first sensor is a circuit that starts a detection operation in response to a pulse signal to which the first identification signal has been added being input from the first identification signal generating unit, and adds a first sensor detection signal detected by the first sensor to the first identification signal, and outputs the signal to the first output terminal. The second identification signal generating unit is a circuit that generates a second identification signal for identifying the second sensor constituting the second set in response to a pulse signal being input from the second input terminal, adds the generated second identification signal to the pulse signal, and outputs the result to the second sensor. The second sensor is a circuit that starts a detection operation in response to the pulse signal to which the second identification signal has been added being input from the second identification signal generating unit, adds a second sensor detection signal detected by the second sensor to the second identification signal, and outputs the result to the second output terminal. The branching unit outputs a pulse signal including L first identification signals and first sensor detection signals generated by the L first set (L is a natural number between 0 and N) of N sensor units, and M second identification signals and second sensor detection signals generated by the M second set (M is a natural number between 0 and N) of N sensor units.

[0006] According to the above configuration, it is possible to continuously output the first identification signal and the first sensor detection signal detected by the first sensor identified by the first identification signal. Also, it is possible to continuously output the second identification signal and the second sensor detection signal detected by the second sensor identified by the second identification signal. Even if the output order of the multiple sensors changes, it is possible to identify the correspondence between the multiple sensor detection signals and the multiple sensors.

[0007] The first identification signal may be a single pulse having a unique first pulse width for identifying the first sensor. The second identification signal may be a single pulse having a unique second pulse width for identifying the second sensor. The L first identification signals generated by the L first identification signal generators and the M second identification signals generated by the M second identification signal generators may all have different pulse widths.

[0008] The first identification signal and the second identification signal may be pulse signals having Q consecutive pulses with P different pulse widths. P and Q may be natural numbers between 2 and N-1. The first identification signal and the second identification signal may be configured to be capable of generating P×Q bit patterns. The L first identification signals generated by the L first identification signal generators and the M second identification signals generated by the M second identification signal generators may all have different bit patterns.

[0009] The first set may further include a first dummy signal generating unit arranged on a transmission path of the pulse signal from the first input terminal to the first identification signal generating unit. The second set may further include a second dummy signal generating unit arranged on a transmission path of the pulse signal from the second input terminal to the second identification signal generating unit. The first dummy signal generating unit may be a circuit that generates a first dummy signal of one pulse in response to a pulse signal being input from the first input terminal, adds the generated first dummy signal to the pulse signal, and outputs the result to the first identification signal generating unit. The second dummy signal generating unit may be a circuit that generates a second dummy signal of one pulse in response to a pulse signal being input from the second input terminal, adds the generated second dummy signal to the pulse signal, and outputs the result to the second identification signal generating unit.

[0010] The pulse signal may be a signal whose voltage transitions between a first level and a second level different from the first level. The first set may output a first pulse train to which a first dummy signal, a first identification signal, and a first sensor detection signal are added from a first output terminal in response to a transition of a voltage inputted from a first input terminal from the first level to the second level. The number of pulses in the first pulse train may be such that the voltage at the completion of outputting the first pulse train is the first level. The second set may output a second pulse train to which a second dummy signal, a second identification signal, and a second sensor detection signal are added from a second output terminal in response to a transition of a voltage inputted from a second input terminal from the first level to the second level. The number of pulses in the second pulse train may be such that the voltage at the completion of outputting the second pulse train is the first level.

[0011] The branching unit may include a third input terminal, a third output terminal, a fourth input terminal, and a fourth output terminal. The third output terminal may be connected to a first input terminal of the first sensor unit via a first signal line. The third input terminal may be connected to a first output terminal of the Nth sensor unit via a first signal line. The fourth output terminal may be connected to a second input terminal of the Nth sensor unit via a second signal line. The fourth input terminal may be connected to a second output terminal of the first sensor unit via a second signal line. The branching unit may include a third switching unit. The third switching unit may be configured to be switchable between a first state in which a pulse signal is output from the third output terminal and a pulse signal input to the fourth input terminal is transmitted to the fourth output terminal, and a second state in which a pulse signal is output from the fourth output terminal and the third output terminal is put into a high impedance state. The third switching unit may maintain the first state when the pulse signal output from the third output terminal is input to the fourth input terminal during the period from when the pulse signal is output from the third output terminal to when the pulse signal transmitted through the sensor network and returned is input to the third input terminal. The third switching unit may switch to the second state when the pulse signal is input to the third input terminal without being input to the fourth input terminal after the pulse signal is output from the third output terminal.

[0012] One aspect of the sensor network disclosed in this specification is a sensor network including N (N is a natural number of 2 or more) sensor units and a branching unit. The sensor network includes a serial connection structure in which the first to Nth sensor units are connected starting from the branching unit and then return to the branching unit. The sensor network includes a first signal line for transmitting a pulse signal that is transmitted from the branching unit in a first direction and returns to the branching unit, and a second signal line for transmitting a pulse signal that is transmitted from the branching unit in a second direction opposite to the first direction and returns to the branching unit. Each of the N sensor units includes a first input terminal, a first output terminal, a second input terminal, and a second output terminal. The first input terminal of the Kth (K is a natural number of 2 or more and N-1 or less) sensor unit is connected to the first output terminal of the K-1th sensor unit via the first signal line. The first output terminal of the Kth sensor unit is connected to the first input terminal of the K+1th sensor unit via the first signal line. The second input terminal of the Kth sensor unit is connected to the second output terminal of the K+1th sensor unit via the second signal line. The second output terminal of the Kth sensor unit is connected to the second input terminal of the K-1th sensor unit via the second signal line. The branch unit includes a third input terminal, a third output terminal, a fourth input terminal, and a fourth output terminal. The third output terminal is connected to the first input terminal of the first sensor unit via the first signal line. The third input terminal is connected to the first output terminal of the Nth sensor unit via the first signal line. The fourth output terminal is connected to the second input terminal of the Nth sensor unit via the second signal line. The fourth input terminal is connected to the second output terminal of the first sensor unit via the second signal line. The branch unit includes a third switching unit. The third switching unit is configured to be switchable between a first state in which a pulse signal is output from the third output terminal and a pulse signal input to the fourth input terminal is transmitted to the fourth output terminal, and a second state in which a pulse signal is output from the fourth output terminal and the third output terminal is put into a high impedance state.The third switching unit maintains the first state when the pulse signal output from the third output terminal is input to the fourth input terminal during the period from when the pulse signal is output from the third output terminal to when the pulse signal that has been transmitted through the sensor network and returned is input to the third input terminal. The third switching unit switches to the second state when the pulse signal is input to the third input terminal without being input to the fourth input terminal after the pulse signal is output from the third output terminal. Each of the N sensor units includes at least one of a first set including a first identification signal generator and a first sensor that are arranged in series on a transmission path of the pulse signal from the first input terminal to the first output terminal, and a second set including a second identification signal generator and a second sensor that are arranged in series on a transmission path of the pulse signal from the second input terminal to the second output terminal. The first identification signal generating unit is a circuit that generates a first identification signal for identifying a first sensor constituting a first set in response to a pulse signal being input from a first input terminal, adds the generated first identification signal to the pulse signal, and outputs the result to the first sensor. The first sensor is a circuit that starts a detection operation in response to a pulse signal to which the first identification signal has been added being input from the first identification signal generating unit, adds a first sensor detection signal detected by the first sensor to the first identification signal, and outputs the result to a first output terminal. The second identification signal generating unit is a circuit that generates a second identification signal for identifying a second sensor constituting a second set in response to a pulse signal being input from a second input terminal, adds the generated second identification signal to the pulse signal, and outputs the result to the second sensor. The second sensor is a circuit that starts a detection operation in response to a pulse signal to which the second identification signal has been added being input from the second identification signal generating unit, and adds a second sensor detection signal detected by the second sensor to the second identification signal, and outputs the result to a second output terminal. The branching unit outputs a pulse signal including L first identification signals and first sensor detection signals generated by a first set of L (L is a natural number greater than or equal to 0 and less than or equal to N) sensor units and M second identification signals and second sensor detection signals generated by a second set of M (M is a natural number greater than or equal to 0 and less than or equal to N) sensor units. [Brief description of the drawings]

[0013] [Figure 1] 1 is a block diagram showing an outline of a sensor network 1. FIG. [Diagram 2] 4 is an example waveform of the control circuit CC. [Diagram 3] FIG. 2 is a diagram showing an embodiment of the sensor unit SU(N). [Figure 4] 6A to 6C are waveform diagrams illustrating the operation of the first sensor SE1. [Diagram 5] 11 is a waveform diagram illustrating the operation of the switching unit SW1. FIG. [Figure 6] FIG. 2 is a diagram showing an example of the configuration of a branching unit BU. [Figure 7] FIG. 2 is a diagram for explaining the internal configuration of a switching circuit RCC1. [Figure 8] FIG. 13 is a diagram showing an example in which there is no loop wiring LW. [Figure 9] FIG. 13 is a diagram showing an example in which a loop line LW is present. [Figure 10] FIG. 11 is a diagram illustrating a second state. [Figure 11] 11 is an operation waveform diagram of the switching circuit RCC2 when there is no loop wiring LW. FIG. [Figure 12] 13 is an operation waveform diagram of the switching circuit RCC2 when a loop line LW is present. FIG. [Figure 13] FIG. 2 is a diagram showing the sensor network 1 in a second state. [Figure 14] 11 is an operational waveform diagram of the sensor network 1 when there is no disconnection fault. FIG. [Figure 15] 11 is an operational waveform diagram of the sensor network 1 when a disconnection fault occurs. FIG. [Figure 16] FIG. 13 is a diagram showing a configuration example of a branching unit BUa of a modified example. [Figure 17] FIG. 13 is a diagram for explaining the internal configuration of a switching circuit RCC1a of a modified example. [Figure 18] FIG. 11 is a diagram showing a circuit configuration of a first set SS1 in the second embodiment. [Figure 19] FIG. 11 is a waveform diagram illustrating the operation of the first set SS1. [Figure 20] FIG. 2 is a diagram illustrating a sensor network 201. [Figure 21] FIG. 2 is a diagram illustrating a sensor network 201. [Figure 22] FIG. 2 is a diagram illustrating a sensor network 201. [Figure 23] FIG. 2 is a diagram illustrating the operation of the sensor network 201. [Figure 24] FIG. 2 is a diagram illustrating the operation of the sensor network 201. [Diagram 25] FIG. 11 is a diagram showing a circuit configuration of a first set SS1m in a third embodiment. [Figure 26] FIG. 11 is a waveform diagram illustrating the operation of the first set SS1m. [Figure 27] 11 is a table showing an example of setting the pulse widths of identification pulses IP1a and IP1b. [Figure 28] FIG. 2 is a diagram illustrating the operation of the sensor network 201. [Figure 29] FIG. 2 is a diagram illustrating the operation of the sensor network 201. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS EXAMPLES

[0014] (Configuration of sensor network 1) 1 shows a sensor network 1 of this embodiment. The sensor network 1 includes an input / output unit IOU, a branching unit BU with three branches, and three sensor units SU(1) to SU(3).

[0015] The sensor units SU(1) to SU(3) are connected by a first signal line LA, a second signal line LB, and an inspection signal line LL. Specifically, the sensor units SU(1) to SU(3) have a circular serial connection structure in which the sensor units are connected in order starting from the branching unit BU and then return to the branching unit BU. The first signal line LA is a signal line for transmitting a signal that is transmitted from the branching unit BU in a counterclockwise direction and returns to the branching unit BU. That is, the first signal line LA transmits an A-series pair of signals (a drive signal DRA and a detection signal DEA). The second signal line LB is a signal line for transmitting a signal that is transmitted from the branching unit in a clockwise direction and returns to the branching unit. That is, the second signal line LB transmits a B-series pair of signals (a drive signal DRB and a detection signal DEB).

[0016] The first signal line LA includes a first detection signal line LA_DE that transmits the detection signal DEA, and a first drive signal line LA_DR that transmits the drive signal DRA. The second signal line LB includes a second detection signal line LB_DE that transmits the detection signal DEB, and a second drive signal line that transmits the drive signal. The inspection signal line LL inputs an inspection signal CK to the sensor units SU(1) to SU(3). The inspection signal line LL is a signal line that applies a high-level inspection signal CK to each of the sensor units SU(1) to SU(3) during a disconnection inspection, which will be described later.

[0017] Each of the sensor units SU(1) to SU(3) has ports PT1 and PT2. The port PT1 has first input terminals DRI_1 and DEI_1, and second output terminals DRO_2 and DEO_2. The port PT2 has first output terminals DRO_1 and DEO_1, and second input terminals DRI_2 and DEI_2. The first input terminals DRI_1 and DEI_1 of the Kth (K is a natural number between 2 and N-1) sensor unit SU(K) are connected to the first output terminals DRO_1 and DEO_1 of the K-1th sensor unit SU(K-1) via a first signal line LA. The first output terminals DRO_1 and DEO_1 of the sensor unit SU(K) are connected to the first input terminals DRI_1 and DEI_1 of the sensor unit SU(K+1) via a first signal line LA. The second input terminals DRI_2 and DEI_2 of the sensor unit SU(K) are connected to the second output terminals DRO_2 and DEO_2 of the sensor unit SU(K+1) via the second signal line LB. The second output terminals of the sensor unit SU(K) are connected to the second input terminals DRI_2 and DEI_2 of the sensor unit SU(K-1) via the second signal line LB.

[0018] The branching unit BU includes ports PT1 to PT3. The port PT2 includes third output terminals DRO_3 and DEO_3, fourth input terminals DRI_4 and DEI_4, and a terminal CK. The port PT3 includes third input terminals DRI_3 and DEI_3, fourth output terminals DRO_4 and DEO_4, and a terminal CK. The third output terminals DRO_3 and DEO_3 are connected to the first input terminals DRI_1 and DEI_1 of the sensor unit SU(1) via the first signal line LA. The third input terminals DRI_3 and DEI_3 are connected to the first output terminals DRO_1 and DEO_1 of the sensor unit SU(3) via the first signal line LA. The fourth output terminals DRO_4 and DEO_4 are connected to the second input terminals DRI_2 and DEI_2 of the sensor unit SU(3) via the second signal line LB. The fourth input terminals DRI_4 and DEI_4 are connected to the second output terminals DRO_2 and DEO_2 of the sensor unit SU(1) via a second signal line LB. An inspection signal CK is output from a terminal CK of the ports PT2 and PT3.

[0019] The port PT1 of the branching unit BU has input terminals DRI_1, DEI_1, CK, and output terminals DRO_1, DEO_1. The input / output unit IOU has a built-in control circuit CC. The control circuit CC receives a sensor control signal EN from the outside and a drive signal DRB(U) from the branching unit BU. The control circuit CC outputs an inspection signal CK, a drive signal DRA(I), and a detection signal DEA(I), which are input to the port PT1 of the branching unit BU. The detection signal DEB(U) output from the branching unit BU is output from the input / output unit IOU as a serial output signal SOUT.

[0020] FIG. 2 shows an example waveform of the control circuit CC. Before time t0, the sensor control signal EN is 0, the inspection signal CK is 0, and the drive signal DRA(I) and the detection signal DEA(I) are 1. When the sensor control signal EN rises at time t0, the inspection signal CK also rises, and the inspection signal CK returns to 0 after a desired time has passed. The detection signal DEA(I) falls when the sensor control signal EN rises, and rises after the inspection signal CK falls. The sensor control signal EN falls until time t1. The drive signal DRA(I) falls after the inspection signal CK falls. As will be described later, the fall of the drive signal DRA(I) propagates around the entire sensor network 1. Then, at time t1, when the signal propagation returns to the input / output unit IOU, the drive signal DRB(U) falls and the drive signal DRA(I) rises.

[0021] (Configuration of sensor unit SU(N)) FIG. 3 shows an embodiment of the sensor unit SU(N). The sensor unit SU(N) includes ports PT1 and PT2 that can be connected to other units, a first sensor SE1 and a second sensor SE2, and switching units SW1 and SW2. The sensor unit SU(N) does not need to include both the first sensor SE1 and the second sensor SE2, and may include at least one of the two. The switching units SW1 and SW2 have the same circuit configuration. The switching unit SW1 includes input terminals DRI, DEI, DRD, DED, and CK. A drive input signal DRI, a detection input signal DEI, a drive bypass signal DRD, a detection bypass signal DED, and an inspection signal CK are input to each input terminal. The switching unit SW1 also includes output terminals DRS and DES. A drive selection signal DRS and a detection selection signal DES are output from each output terminal. In this specification, the terminal symbols and the signals input to and output from the terminals are the same for convenience.

[0022] The first input terminals DRI_1 and DEI_1 of the port PT1 are connected to the input terminals DRI and DEI of the switching unit SW1. The output terminals DRO and DEO of the second sensor SE2 are connected to the second output terminals DRO_2 and DEO_2 of the port PT1 and are connected to the input terminals DRD and DED of the switching unit SW1. The output terminals DRS and DES of the switching unit SW1 are connected to the input terminals DRI and DEI of the first sensor SE1. The output terminals DRO and DEO of the first sensor SE1 are connected to the first output terminals DRO_1 and DEO_1 of the port PT2 and are connected to the input terminals DRD and DED of the switching unit SW2. The connection structure between the switching unit SW2 and the second sensor SE2 is the same as the connection structure between the switching unit SW1 and the first sensor SE1 described above, so a description thereof will be omitted.

[0023] The switching unit SW1 includes a D latch DL, a pull-down resistor RI, and 2-1 multiplexers MUX1 and MUX2. An input terminal DRI is connected to one terminal of the pull-down resistor RI, a D terminal of the D latch DL, and one input terminal of the multiplexer MUX1. The other terminal of the pull-down resistor RI is connected to a reference voltage site GND. It is desirable for the pull-down resistor RI to be a high resistance (e.g., 1 MΩ or more).

[0024] The pull-down resistor RI of the switching unit SW1 is a part that detects the presence or absence of a break in the first signal line LA that connects the first input terminal DRI of the sensor unit SU(N) and the first output terminal DRO of the sensor unit SU(N-1). The switching unit SW1 detects the break when the voltage of the first input terminal DRI_1 is 0 during a break inspection. Similarly, the pull-down resistor RI of the switching unit SW2 is a part that detects the presence or absence of a break in the second signal line LB that connects the second input terminal DRI of the sensor unit SU(N) and the second output terminal DRO of the sensor unit SU(N+1). The switching unit SW2 detects the break when the voltage of the second input terminal DRI_2 is 0 during a break inspection.

[0025] The CK terminal of the D latch DL is connected to the inspection signal terminal CK. The output signal SR output from the Q terminal of the D latch DL is connected to the select terminals (S terminals) of the multiplexers MUX1 and MUX2. The 1 input terminals of the multiplexers MUX1 and MUX2 are connected to the input terminals DRI and DEI, respectively. The 0 input terminals of the multiplexers MUX1 and MUX2 are connected to the input terminals DRD and DED, respectively.

[0026] (Configuration of the first sensor SE1 and the second sensor SE2) The first sensor SE1 and the second sensor SE2 are elements that measure various physical quantities. The first sensor SE1 starts a detection operation in response to the drive input signal DRI being input from the first input terminal DRI_1 of the port PT1. Then, the first sensor SE1 generates a detection output signal DEO by adding the detected sensor detection signal to the detection input signal DEI, and outputs the detection output signal DEO to the first output terminal DRO_1 of the port PT2. The second sensor SE2 starts a detection operation in response to the drive input signal DRI being input from the second input terminal DRI_2 of the port PT2. Then, the second sensor SE2 generates a detection output signal DEO by adding the detected sensor detection signal to the detection input signal DEI, and outputs the detection output signal DEO to the second output terminal DRO_2 of the port PT1.

[0027] The circuit configuration of the first sensor SE1 will be described. The first sensor SE1 includes a NAND circuit ND, a detection element TH, a capacitor CT, and inverters INV1, INV2, and INV_OD. For convenience, the terminals of the first sensor SE1 are designated by the same reference numerals as the signals input to and output from the terminals. A drive input signal DRI is input to the inverters INV1 and INV_OD. A drive output signal DRO is output from the inverter INV2. A detection input signal DEI and a drive output signal DRO are input to the NAND circuit ND, and a detection output signal DEO is output. Since the first sensor SE1 and the second sensor SE2 have the same structure, a description of the second sensor SE2 will be omitted.

[0028] The operation of the first sensor SE1 will be described using the waveform diagram in Figure 4. At time t1, the drive input signal DRI falls, and the time constant measurement of the sensing element TH begins. At time t2, when a time proportional to the resistance value of the sensing element TH has elapsed, the drive output signal DRO falls, and the time constant measurement ends. The time T(N+1) from time t1 to t2 is the output of the first sensor SE1.

[0029] The detection input signal DEI includes the time constant serial output up to the previous stage sensor. That is, in the detection input signal DEI, N times from time T(1) to T(N) are output continuously. The NAND circuit ND logically combines the detection input signal DEI and the drive output signal DRO. Therefore, it is possible to generate a detection output signal DEO by adding the time T(N+1), which is the time constant output of the sensor, to the detection input signal DEI. Note that a plurality of first sensors SE1 may be cascaded to form a sensor array.

[0030] (Switch SW1 operation) The operation of the switching unit SW1 will be explained using the operation explanatory diagram of Figure 5. The switching unit SW1 is a circuit that determines the presence or absence of a disconnection based on the value of the drive input signal DRI when the inspection signal CK is 1, and switches the path. As an example, a case where a disconnection occurs between times t2 and t3 will be explained.

[0031] Between time t1 and time t2, the inspection signal CK becomes 1, and a disconnection determination and path switching are performed. At this time, the drive input signal DRI is 1 (region R11), so that a disconnection is not detected. Therefore, the drive input signal DRI is output as the drive selection signal DRS (arrow Y1 in FIG. 3), and the detection input signal DEI is output as the detection selection signal DES (arrow Y2). That is, the drive signal DRA input to the first input terminal DRI_1 of port PT1 is transmitted to the first output terminal DRO_1 of port PT2. Also, the detection signal DEA input to the first input terminal DEI_1 of port PT1 is transmitted to the first output terminal DEO_1 of port PT2.

[0032] Between times t2 and t3, the path is maintained because the inspection signal CK is 0. Here, a case will be described where a break occurs in the wiring connected to the first input terminal DRI_1 of the port PT1 between times t2 and t3.

[0033] Between time t3 and time t4, the inspection signal CK becomes 1 again, and a disconnection determination and a path switching are performed. Since there is a disconnection fault in the wiring connected to the first input terminal DRI_1 of the port PT1, the drive input signal DRI of the switching unit SW1 is fixed to 0 by the pull-down resistor RI (region R12). In this case, when the inspection signal CK is 1, the output signal SR of the D latch DL becomes 0 (arrow Y3). The multiplexers MUX1 and MUX2 switch the path. Then, the drive bypass signal DRD is output as the drive selection signal DRS (arrow Y4 in FIG. 3), and the detection bypass signal DED is output as the detection selection signal DES (arrow Y5). That is, the drive signal DRB input to the second input terminal DRI_2 of the port PT2 is folded back and transmitted to the first output terminal DRO_1 of the port PT2. Also, the detection signal DEB input to the second input terminal DEI_2 of the port PT2 is folded back and transmitted to the first output terminal DEO_1 of the port PT2. After time t4, this connection state is maintained until the inspection signal CK becomes 1.

[0034] (Configuration of branch unit BU) 6 shows an example of the configuration of the branching unit BU. The branching unit BU has three ports PT1 to PT3 that can be connected to other units. Each of the ports PT1 to PT3 has a switching circuit RCC1 to RCC3. The switching circuits RCC1 to RCC3 have input terminals DRI, DEI, DRD, DED, CKI, and LC, and output terminals DRS, DES, and DRO.

[0035] The internal configuration of the switching circuit RCC1 will be described with reference to FIG. 7. The configurations of the switching circuits RCC2 and RCC3 are the same as that of the switching circuit RCC1, and therefore will not be described. The switching circuit RCC1 has a configuration in which a loop switching circuit LS is further provided in addition to the circuit configuration of the switching units SW1 and SW2 in FIG. 3. Components common to the switching units SW1 and SW2 are given common reference numerals and will not be described. The loop switching circuit LS includes an AND circuit AD, a loop detection circuit LD, and a tri-state buffer TB.

[0036] Input terminals DRI, DRD, and LC are connected to the loop detection circuit LD. An output signal SR2 is output from the D flip-flop DF of the loop detection circuit LD. The output signal SR2 and the drive input signal DRI are input to the AND circuit AD. The output signal of the AND circuit AD is input to the D terminal of the D latch DL. The drive bypass signal DRD and the output signal SR2 are input to the tri-state buffer TB. The tri-state buffer TB outputs a drive output signal DRO. When the input output signal SR2 is 1, the tri-state buffer TB functions as a standard buffer, and when it is 0, the output becomes high impedance.

[0037] The loop detection circuit LD normally sets the output signal SR2 to 1. When the loop inspection signal LC falls from 1 to 0, if 0 is input to the input terminal DRD and 1 is input to the input terminal DRI, the loop detection circuit LD sets the output signal SR2 to 0. The circuit configuration of the loop detection circuit LD is not limited to the configuration in FIG. 7. Any circuit configuration can be used as long as it is a circuit that can perform the above-mentioned operations.

[0038] (Explanation of loop wiring LW) The loop wiring LW will be described with reference to Fig. 8 and Fig. 9. The loop wiring LW is a closed wiring path through which signals are not transmitted. Fig. 8 shows an example in which there is no loop wiring LW, and Fig. 9 shows an example in which there is a loop wiring LW.

[0039] In FIG. 8, the signal path PP1, which is output from the first output terminal DRO_1 of the input / output unit IOU and returns to the first input terminal DRI_1, is a single-stroke path. That is, the signal path PP1 reaches the branching unit BU from the input / output unit IOU. It reaches the sensor unit SU(1) via the first signal line LA, turns back at the sensor unit SU(1), and returns to the branching unit BU via the second signal line LB. Next, it reaches the sensor unit SU(2) from the branching unit BU via the sensor unit SU(3) via the second signal line LB. After turning back at the sensor unit SU(2), it reaches the branching unit BU via the sensor unit SU(3) via the first signal line LA. Finally, it reaches the input / output unit IOU from the branching unit BU. Since the signal path PP1 is a single-stroke path, it can pass through all the first sensors SE1 and the second sensors SE2. It is possible to read out the outputs of all the sensors.

[0040] On the other hand, in FIG. 9, the second signal line LB is a closed loop line LW. Therefore, the loop line LW cannot transmit signals between the input / output unit IOU. In this case, the second sensor SE2 connected to the loop line LW cannot be read and becomes an indefinite value. Therefore, it is not preferable to form the loop line LW.

[0041] (Operation of branch unit BU) The branching unit BU is configured to be switchable between a first state and a second state by the switching circuits RCC1 to RCC3. By appropriately switching between the first state and the second state, it is possible to remove the loop line LW, as described later.

[0042] The first state will be described with reference to Fig. 6. In the first state, the drive signal DRA(I) input from the input / output unit IOU to the first input terminal DRI_1 of the port PT1 is transmitted to the third output terminal DRO_3 of the port PT2 (arrow Y21). The drive signal DRB(1) input to the fourth input terminal DRI_4 of the port PT2 is transmitted to the fourth output terminal DRO_4 of the port PT3 (arrow Y22). In addition, the detection signal DEB(1) input to the fourth input terminal DEI_4 of the port PT2 is transmitted to the fourth output terminal DEO_4 of the port PT3 (arrow Y23).

[0043] The second state will be described with reference to Fig. 10. In the second state, the drive signal DRA(I) input from the input / output unit IOU to the first input terminal DRI_1 of the port PT1 is transmitted to the fourth output terminal DRO_4 of the port PT3 (arrow Y24). Also, the detection signal DEA(I) input to the first input terminal DEI_1 of the port PT1 is transmitted to the fourth output terminal DEO_4 of the port PT3 (arrow Y25). Also, the third output terminal DRO_3 is set to a high impedance state (pseudo-disconnection state).

[0044] Using FIG. 11, the operation of the switching circuit RCC2 in the case where there is no loop wiring LW (FIG. 8) will be described. The initial values ​​of the output signals SR2 and SR in the switching circuits RCC1 to RCC3 are set to 1. Therefore, the branching unit BU is in the first state. The drive signal DRA(I) propagated from the input / output unit IOU is input from the input terminal DRI_1 of the port PT1. The drive signal DRA(I) propagates to the drive bypass signal DRD of the switching circuit RCC2 of the port PT2 at time t0 via the switching circuit RCC1 of the port PT1. Since the initial values ​​of the output signals SR2 and SR in the switching circuit RCC2 are set to 1 and the first state is in effect, the drive signal DRA(I) propagates to the third output terminal DRO_3 of the port PT1 and is output as the drive signal DRA(0) (FIG. 6, arrow Y21).

[0045] After that, the drive signal is returned by the sensor unit SU(1) and input to the fourth input terminal DRI_4 of the port PT2 as the drive signal DRB(1) at time t1. This causes the drive input signal DRI to become 0. Therefore, it is stored that the drive signal output from the port PT2 by the first signal line LA has returned to the port PT2 by the second signal line LB (see area R11).

[0046] The drive signal DRB(1) that has returned to port PT2 is propagated to the input terminal DRD of the switching circuit RCC3 of port PT3. Since the initial values ​​of the output signals SR2 and SR in the switching circuit RCC3 are set to 1, the drive signal DRB(1) is propagated to the fourth output terminal DRO_4 of port PT3 and output as the drive signal DRB(0) (arrow Y22 in FIG. 6). The drive signal then propagates to the sensor unit SU(2) via the sensor unit SU(3), is folded back by the sensor unit SU(2), and returns to the sensor unit SU(3). Then, at time t2, it is input as the drive signal DRA(3) to the third input terminal DRI_3 of port PT3.

[0047] The drive signal DRA(3) input to port PT3 is input as a loop inspection signal LC to the input terminal LC of the switching circuit RCC2 of port PT2. Thus, at time t2, a loop inspection is performed at the falling edge of the loop inspection signal LC. At this time, the drive input signal DRI=0, and it is stored that a path is formed for the drive signal output from port PT2 to return to port PT2. Therefore, it is determined that the loop wiring LW does not exist (see FIG. 8). Therefore, the output signal SR2 is held at 1 (arrow Y11). That is, the first state is maintained.

[0048] The operation waveforms of the switching circuit RCC2 when the loop wiring LW is present (FIG. 9) will be described with reference to Fig. 12. The operation up to time t0 is the same as that described with reference to Fig. 11.

[0049] The drive signal DRA(0) output from the third output terminal DRO_3 of the port PT1 propagates through the sensor units SU(1), SU(2), and SU(3). Then, at time t3, it is input to the third input terminal DRI_3 of the port PT3 as the drive signal DRA(3). The drive signal DRA(3) is input to the switching circuit RCC2 as the loop inspection signal LC. Thus, at time t3, the loop inspection is performed. At this time, the drive input signal DRI=1, and it is stored that the drive signal output from the port PT2 does not return to the port PT2, and a path leading to the port PT3 is formed. That is, it is determined that the drive signal output from the port PT2 by the first signal line LA returns to the port PT3 by the first signal line LA. Then, it is determined that the loop wiring LW formed by the second signal line LB exists (see FIG. 9). Therefore, the output signal SR2 transitions to 0 (arrow Y12).

[0050] When the output signal SR2 transitions to 0, the tri-state buffer TB becomes high impedance. Then, as described above, the disconnection switching function can be operated in the adjacent sensor unit SU(1). Therefore, as shown in FIG. 13, a return path can be formed (region R21). Also, while the inspection signal CK=1, the output signal of the D latch DL becomes 0, so that the multiplexers MUX1 and MUX2 are switched. As a result, as shown in FIG. 13, the branching unit BU switches from the first state to the second state. Therefore, the drive signal DRA(I) transmitted from the input / output unit IOU is returned and output from the fourth output terminal DRO_4. As a result, a new one-stroke path can be established that reaches the sensor unit SU(1) using the second signal line LB, returns at the sensor unit SU(1), and returns to the branching unit BU using the first signal line LA.

[0051] As described above, by providing the switching circuits RCC1 to RCC3 corresponding to the ports PT1 to PT3 of the branching unit, it is possible to detect when the serial detection path has a loop wiring LW and switch the path. Since the branch start point of the loop wiring LW can be cut off, the loop wiring LW can be removed. Therefore, a path for serially driving and detecting all sensors is secured by self-organization, and it becomes possible to read out the outputs of all sensors.

[0052] (Example of operation when there is no open circuit fault) The operation of the sensor network 1 shown in FIG. 1 when no disconnection occurs will be described with reference to the operation explanatory diagram of FIG.

[0053] Before time t0, 0 is input to the sensor control signal EN. The control circuit CC of the input / output unit IOU outputs 0 to the inspection signal CK and 1 to the drive signal DRA(I) and detection signal DEA(I) (area R40). Also, 1 is output from the D latch DL of the switching parts SW1 and SW2 in the sensor units SU(1) to SU(3). Also, the output signal SR2 of the switching circuits RCC1 to RCC3 in the branching unit BU is set to 1 (area R41). At this time, the drive signal propagates through the branching unit BU and the sensor units SU(1) to SU(3) without inverting the logic, so the drive signal DRA(I)=1 output from the input / output unit IOU propagates to all the drive signals, and all the drive signals are set to 1 (area R42). On the other hand, as shown in FIG. 3, the detection output signal DEO of the first sensor SE1 and the second sensor SE2 is generated by logically combining the detection input signal DEI (detection output signal of the previous stage) and the drive output signal DRO (detection output signal of this stage) in the NAND circuit ND. Since the initial values ​​of all the drive signals are 1, the detection signal DEA is inverted every time it passes through the sensor units SU(1) to SU(3). Since the detection signal DEA(I) is 1, the initial values ​​of DEA(2), DEA(4), and DEB(0) are 0, and the initial values ​​of DEA(1), DEA(3), and DEB(0) are 1 (area R43). Note that the B series detection signals (DEB(1), DEB(2), DEB(3), and DEB(0)) are loop wiring LW, and the initial values ​​are undefined (area R44).

[0054] When the sensor control signal EN rises at time t0, the inspection signal CK becomes 1 for a desired period of time, and a check for disconnection is performed in the switching units SW1 and SW2 and the switching circuits RCC1 to RCC3. Since all the drive input signals are 1, it is determined that there is no disconnection, and the path is maintained.

[0055] When the drive signal DRA(I) falls at time t1 after the inspection signal CK falls, the falling edge of the drive signal DRA(I) propagates from port PT1 to port PT2 of the branching unit BU, and driving and detection begins from the first sensor SE1 of series A of the sensor unit SU(1).

[0056] The falling edge of the drive signal DRA(I) propagates through DRA(0), DRA(1), DRA(2), and DRA(3) in that order, and is input to the port PT3 of the branching unit BU at time t4. The drive signal DRA(3) is input to the switching circuit RCC2 as a loop inspection signal LC in the branching unit BU (arrow Y40). Thus, at time t4, a loop inspection is performed. At this time, the drive bypass signal DRD of the switching circuit RCC2 is connected to the drive signal DRA(I) and is 0. Also, the drive input signal DRI of the switching circuit RCC2 is connected to DRB(1) and is 1. From this result, it is determined that there is a loop path between the port PT2 and the port PT3, and the output signal SR2 of the switching circuit RCC2 becomes 0 (arrow Y41). At the same time, the drive signal DRA(0) output from the switching circuit RCC2 becomes high impedance.

[0057] When the sensor control signal EN rises again at time t5, the inspection signal CK becomes 1 for a desired time, and the switching units SW1 and SW2 and the switching circuits RCC1 to RCC3 perform a disconnection check and route switching. At this time, the output signal SR2 of the switching circuit RCC2 is 0, so the output signal SR becomes 0 (arrow Y42). Therefore, as explained with the arrows Y24 and Y25 in FIG. 10, the port PT2 of the branching unit BU is cut off, and the route is switched to output the drive signal and detection signal input from the port PT1 to the port PT3. Also, since the drive signal DRA(0) is 0 at high impedance (area R45), the switching unit SW1 in the sensor unit SU(1) judges that there is a disconnection. The output signal SR of the disconnection switching circuit 1 becomes 0, and the port PT1 of the sensor unit 1 is cut off. Therefore, the route is switched to the return route (see FIG. 13, area R21).

[0058] After the inspection signal CK falls, when the drive signal DRA(I) falls at time t6, the falling edge of the drive signal DRA(I) propagates from port PT1 to port PT3 of the branching unit BU, and drive detection is started from the B series sensor (second sensor SE2) of the sensor unit SU(3) (see Figure 13).

[0059] The falling edge of the drive signal DRA(I) is propagated in the order of DRB(0), the second sensor SE2 (series B sensor) of the sensor unit SU(3), DRB(3), the second sensor SE2 (series B sensor) of the sensor unit SU(2), DRB(2), and the second sensor SE2 (series B sensor) of the sensor unit SU(1) (arrows Y43 and Y44).Then, it is turned back just before the port PT1 of the sensor unit SU(1), and propagates in the order of the first sensor SE1 (series A sensor) of the sensor unit SU(1), DRA(1), the first sensor SE1 (series A sensor) of the sensor unit SU(2), DRA(2), the first sensor SE1 (series A sensor) of the sensor unit SU(3), DRA(3), and DRB(U), before returning to the input / output unit IOU (arrows Y45 and Y46). The serial output signal SOUT outputs time constant output pulses of the sensors in the order of TB3, TB2, TB1, TA1, TA2, and TA3.

[0060] In the example of Fig. 14, detection of loop wiring LW is performed at the first drive detection (time t0 to t5). At the start of the second drive detection (time t5 to t6), a disconnection inspection and loop wiring removal are performed. At the second and subsequent drive detections (time t6 onwards), a route for drive detection of all sensors in one stroke is established, and the time constant output series of all sensors on the sensor network 1 can be read out continuously.

[0061] (Example of operation when there is a wire break) Next, the operation when a disconnection fault occurs between the sensor units SU(1) and SU(2) will be described with reference to the operation explanatory diagram of FIG.

[0062] Before time t0, as in Fig. 14, 0 is input to the sensor control signal EN. 0 is output to the inspection signal CK, and 1 is output to the drive signal DRA(I) and the detection signal DEA(I) (area R50). Also, 1 is output from the D latches DL of the switching parts SW1 and SW2 in the sensor units SU(1) to SU(3). The output signals SR of the sensor units SU(1) and SU(2) are set to 1 (area R51). Also, the output signal SR2 of the branching unit BU is set to 1.

[0063] For the A-series drive signal, the drive signal DRA(I)=1 output from the input / output unit IOU propagates to ports PT1 and PT2 of the sensor unit SU(1) via ports PT1 and PT2 of the branching unit BU. Therefore, the drive signals DRA(0) and DRA(1) become 1 (area R52). The drive input signal DRI at port PT1 of the sensor unit SU(2) is set to 0 by the pull-down resistor RI in the switching section SW1. This propagates to the input / output unit IOU via port PT2 of the sensor unit SU(2), ports PT1 and PT2 of the sensor unit SU(3), port PT3 of the branching unit BU, and port PT1 in that order. Therefore, the drive signals DRA(2), DRA(3), and DRB(U) are 0 (area R53).

[0064] The B-series drive signal is a drive input signal DRI at port PT2 of sensor unit 1 due to a break in the input section of port PT2 of sensor unit 1. This propagates through port PT1 of sensor unit SU(1) to port PT2 of the branch unit, port PT3, ports PT2 and PT1 of sensor unit SU(3), and ports PT2 and PT1 of sensor unit SU(2) in that order, so the drive signals DRB(1), DRB(0), DRB(3), and DRB(2) are 0 (area R54). On the other hand, the detection signal is detection signal DEA(I)=1, so detection signal DEA(0)=1 and DEA(1)=0. The other detection signals are undefined values ​​due to the high impedance of the detection input signals at the ports of the sensor units that are broken due to the break (area R55).

[0065] When the sensor control signal EN rises at time t0, the inspection signal CK becomes 1 for a desired time, and a disconnection check is performed in the switching units SW1 and SW2 and the switching circuits RCC1 to RCC3. At this time, due to a disconnection between the sensor units SU(1) and SU(2), the output signal SR of the switching unit SW2 of the sensor unit SU(1) becomes 0, and the output signal SR of the switching unit SW1 of the sensor unit SU(2) becomes 0. Therefore, as shown in FIG. 8, the path is switched to one that is folded back just before the port where the disconnection occurs. This path switching propagates the drive signal DRA(I)=1 to all drive signals, so that all drive signals that were 0 before time t0 become 1 (area R56). In addition, the value of the detection signal, which was an indefinite value, is also determined (area R57).

[0066] After the inspection signal CK falls, when the drive signal DRA(I) falls at time t1, the falling edge of the drive signal DRA(I) propagates from port PT1 to port PT2 of the branching unit BU, and driving and detection begins from the A-series sensor of the sensor unit SU(1).

[0067] The falling edge of the drive signal DRA(I) is propagated in the order of DRA(0), the first sensor SE1 (A-series sensor) of the sensor unit SU(1), the second sensor SE2 (B-series sensor) of the sensor unit SU(1), DRB(1), and returns to the branch unit BU (arrow Y51). It is further propagated in the order of DRB(0), the second sensor SE2 (B-series sensor) of the sensor unit SU(3), DRB(3), the second sensor SE2 (B-series sensor) of the sensor unit SU(2), the first sensor SE1 (A-series sensor) of the sensor unit SU(2), DRA(2), the first sensor SE1 (A-series sensor) of the sensor unit SU(3), DRA(3), and DRB(U), and returns to the input / output unit IOU (arrow Y52). The serial output signal SOUT outputs the time constant output pulses of the sensors in the order of TA1, TB1, TB3, TB2, TA2, and TA3.

[0068] (effect) In the sensor network 1 of this embodiment, a port where a disconnection failure has occurred or a port that is not connected to an adjacent unit can be detected, and the port can be automatically switched to a detour route without using the port (see time t0 in FIG. 15, FIG. 8, etc.). In addition, the branching unit BU can detect the presence or absence of a loop line LW from the order in which the drive signal propagates through the ports (see arrow Y41 in FIG. 14, etc.). Then, the loop line LW can be removed by automatically switching to a detour route without using the port that is the starting point of the loop line LW (see FIG. 13). With this disconnection detour function and loop line removal function, a one-stroke route that drives and detects all sensors by self-organization can be established for a sensor network in which the sensor units SU and branching units BU are freely connected. Therefore, it becomes possible to read out the serial output of all sensors.

[0069] The sensor unit SU and the branching unit BU are equipped with the basic principle described in this specification. Therefore, when there are many loop wires LW, the route is switched the same number of times as the number of loop wires LW, and finally, a transmission route that passes through all the sensors in one stroke can be established. This makes it possible to further increase robustness.

[0070] The sensor network 1 of this embodiment has a self-organizing capability. Therefore, the number of ports of the branching unit BU and the shape of the serial connection of the sensor units SU can be freely expanded. For example, the branching unit BU may have four or more ports. Also, two or more groups of serially connected sensor units SU may be provided in one branching unit BU. The shape of the serial connection of the sensor units SU may be more complicated than a ring (e.g., a figure-of-eight shape). Also, it may have self-similarity in that another branching unit BU is connected to the serial connection path of the sensor units SU extending from a certain branching unit BU.

[0071] (Modification of the first embodiment) FIG. 16 shows a configuration example of a branching unit BUa having four ports PT1 to PT4. Each of the ports PT1 to PT4 is provided with a switching circuit RCC1a to RCC4a. The switching circuits RCC1a to RCC4a of the modified example (FIG. 16) are provided with input terminals LC1 and LC2 instead of the input terminal LC provided in the switching circuits RCC1 to RCC3 (FIG. 6) of the embodiment. The other configurations are the same as those of the switching circuits RCC1 to RCC3 of the embodiment, so their explanations are omitted. The internal configuration of the switching circuit RCC1a will be described with reference to FIG. 17. The switching circuit RCC1a of the modified example (FIG. 17) is provided with a loop switching circuit LSa and a loop detection circuit LDa instead of the loop switching circuit LS and the loop detection circuit LD provided in the switching circuit RCC1 (FIG. 7) of the embodiment. The other configurations are the same as those of the switching circuit RCC1 of the embodiment, so their explanations are omitted. 16 and 17, even when four ports PT1 to PT4 are provided, it is possible to detect when the serial detection path has a loop wiring LW and perform path switching. Note that the operation of the branching unit BUa of the modified example is similar to that of the branching unit BU of the embodiment, so a detailed description will be omitted. In addition, by using the circuit configuration shown in Figs. 16 and 17 that increases the number of ports from three to four, it is also possible to further expand the number of ports to five or more. EXAMPLES

[0072] (Configuration of the first set SS1 and the second set SS2) FIG. 18 shows a circuit configuration of the first set SS1 of the second embodiment. The first set SS1 is a circuit arranged in place of the first sensor SE1 of the sensor unit SU(N) (FIG. 3). The first set SS1 includes a first dummy signal generator DC1, a first identification signal generator IC1, and a first sensor SE1. The first dummy signal generator DC1, the first identification signal generator IC1, and the first sensor SE1 are connected in series between the input terminals DRI and DEI and the output terminals DRO and DEO. In other words, the first dummy signal generator DC1, the first identification signal generator IC1, and the first sensor SE1 are arranged in series on the transmission path of the pulse signal from the first input terminals DRI_1 and DEI_1 of the port PT1 to the first output terminals DRO_1 and DEO_1 of the port PT2.

[0073] The first dummy signal generating section DC1 includes a delay circuit DY1 and a NAND circuit ND1. The drive input signal DRI is input to the delay circuit DY1. The delay circuit DY1 is a circuit that adds a delay time t_d0 only to the falling edge. The delay circuit DY1 outputs a drive dummy signal DR_d. The detection input signal DEI and the drive dummy signal DR_d are input to the NAND circuit ND1, and the detection dummy signal DE_d is output.

[0074] The first identification signal generating unit IC1 includes a delay circuit DY2 and a NAND circuit ND2. The drive dummy signal DR_d is input to the delay circuit DY2. The delay circuit DY2 is a circuit that adds a delay time t_id1 only to the falling edge. The delay circuit DY2 outputs a drive identification signal DR_id. The detection dummy signal DE_d and the drive identification signal DR_id are input to the NAND circuit ND2, and the detection identification signal DE_id is output.

[0075] The circuit configuration of the first sensor SE1 (FIG. 18) of the first set SS1 is the same as the circuit configuration of the first sensor SE1 (FIG. 3) of the sensor unit SU(N), and therefore a description thereof will be omitted.

[0076] In the second embodiment, the second set SS2 is disposed in place of the second sensor SE2 (FIG. 3) of the sensor unit SU(N). The second set SS2 includes a second dummy signal generator DC2, a second identification signal generator IC2, and a second sensor SE2. The circuit configurations of the second dummy signal generator DC2, the second identification signal generator IC2, and the second sensor SE2 are the same as the circuit configurations of the first dummy signal generator DC1, the first identification signal generator IC1, and the first sensor SE1, and therefore detailed description thereof will be omitted.

[0077] The operation of the first set SS1 will be described using the waveform diagram of FIG. 19. At time t1, the drive input signal DRI falls. The drive input signal DRI is a signal input from the first input terminal DRI_1 (FIG. 3). At time t1_1, the delay circuit DY1 outputs a drive dummy signal DR_d obtained by adding a delay time t_d0 to the falling edge of the drive input signal DRI. The NAND circuit ND1 generates a detection dummy signal DE_d of one pulse based on the drive input signal DRI and the drive dummy signal DR_d (arrow 61). The detection dummy signal DE_d is added to the detection output signal DEO as a dummy pulse DP1 (arrow Y62).

[0078] At time t1_2, the delay circuit DY2 outputs the drive identification signal DR_id. The drive identification signal DR_id is a signal obtained by adding a delay time t_id1 to the falling edge of the drive dummy signal DR_d. The NAND circuit ND2 generates the detection identification signal DE_id based on the detection dummy signal DE_d and the drive identification signal DR_id (arrow 63). The detection identification signal DE_id is a signal for identifying the first sensor SE1 constituting the first set SS1. Therefore, the pulse width Wid of the detection identification signal DE_id is a pulse width specific to the first sensor SE1 constituting the first set SS1. That is, the detection identification signals DE_id generated in each of all the first sets SS1 and the second sets SS2 included in the sensor network all have different pulse widths. The detection identification signal DE_id is added to the detection output signal DEO as an identification pulse IP1 (arrow Y64).

[0079] In response to the drive identification signal DR_id falling at time t1_2, time constant measurement is started in the detection element TH of the first sensor SE1. At time t2, when a time proportional to the resistance value of the detection element TH has elapsed, the drive output signal DRO falls and the time constant measurement ends. The time T(N+1) from time t1_2 to time t4 is the sensor detection signal of the first sensor SE1. The sensor detection signal is added to the detection output signal DEO as a sensor detection pulse SP1 (arrow Y65).

[0080] As a result, the first set SS1 generates a pulse train PU1 in response to the falling edge of the drive input signal DRI, and outputs a detection output signal DEO including the pulse train PU1 to the first output terminal DEO_1 (FIG. 3).

[0081] (Description of the problem in Example 2) The problem of the second embodiment will be explained using Fig. 20 to Fig. 22. Fig. 20 shows a sensor network 201, which is an example of a sensor network for explaining the problem. The sensor network 201 includes an input / output unit IOU, a branching unit BUa (see Fig. 16) with four branches, two sensor units SU(1) and SU(2), and a branching unit BU (see Fig. 10) with three branches. The sensor units SU(1) and SU(2) are connected by a first signal line LA and a second signal line LB. In Fig. 20, the signal lines are indicated by dotted lines.

[0082] Each of the sensor units SU(1) and SU(2) includes at least one of the first set SS1 and the second set SS2. Also, each of the branching units BUa and BU includes at least one of the first set SS1 and the second set SS2. In the example of FIG. 20, the sensor unit SU(1) includes the second set SS2_2. The sensor unit SU(2) includes the first set SS1_3. The branching unit BUa includes the first set SS1_1. The branching unit BU includes the first set SS1_4. That is, in the example of FIG. 20, three first sets SS1 and one second set SS2 are included. Here, the number at the end of the symbol of each set is a consecutive number for identifying each of the sets.

[0083] FIG. 20 shows the initial state of the sensor network 201. The initial state is a state in which the above-mentioned switching operation is not performed, for example, immediately after power is turned on. In the initial state, the second signal line LB is the above-mentioned loop wiring LW1 and LW2. As described above with reference to FIG. 14, the first driving detection detects the loop wiring LW1 and LW2. The second driving detection removes the first loop wiring. The third driving detection removes the second loop wiring. This makes it possible to remove the loop wiring LW1 and LW2. As a result, as shown by the solid line in FIG. 21, a serial connection path CP1 is formed that serially drives and detects all the sensors. In the serial connection path CP1, the sensor outputs are read out in the order of the first set SS1_1, the second set SS2_2, the first set SS1_3, and the first set SS1_4.

[0084] On the other hand, consider a case where disconnection faults DIS1 and DIS2 occur in the initial state of the sensor network 201 (see FIG. 22). The disconnection fault DIS1 occurs on the path between the sensor unit SU(1) and the branching unit BUa. The disconnection fault DIS2 occurs on the path between the sensor unit SU(2) and the branching unit BU. In this case, as described above with reference to FIG. 15, a disconnection check is performed, and the path can be automatically switched to a detour path. As a result, as shown by the solid line in FIG. 22, a serial connection path CP2 is formed that serially drives and detects all the sensors. This makes it possible to detour the disconnection faults DIS1 and DIS2. In the serial connection path CP2, the sensor outputs are read out in the order of the first set SS1_1, the first set SS1_3, the first set SS1_4, and the second set SS2_2.

[0085] The serial connection paths CP1 and CP2 have different sensor output read orders. That is, in the sensor network 201, the sensor output read order changes when the network is freely rearranged or when a disconnection occurs. This causes a problem that it may become impossible to determine which sensor each of the sensor outputs (time constant output pulses) that are continuously output to the serial output signal SOUT belongs to.

[0086] (Effect of discrimination pulse IP) FIG. 23 is an explanatory diagram of the operation of the sensor network 201 (FIG. 21) in which the serial connection path CP1 is formed. FIG. 24 is an explanatory diagram of the operation of the sensor network 201 (FIG. 22) in which the serial connection path CP2 is formed. When the sensor control signal EN rises at time t0 and the drive signal DRA(I) falls at time t1, output of the serial output signal SOUT is started. As shown in FIG. 23, in the case of the serial connection path CP1, pulse trains are output in the order of pulse trains PU1, PU2, PU3, and PU4 in the serial output signal SOUT. On the other hand, as shown in FIG. 24, in the case of the serial connection path CP2, pulse trains are output in the order of pulse trains PU1, PU3, PU4, and PU2 in the serial output signal SOUT.

[0087] The pulse train PU1 is a signal output from the first set SS1_1 of the branching unit BUa. The pulse train PU1 has already been described with reference to FIG. 19. The pulse train PU2 is a signal output from the second set SS2_2 of the sensor unit SU(1). The pulse train PU2 is composed of a dummy pulse DP2, an identification pulse IP2, and a sensor detection pulse SP2. The contents of the pulse train PU2 are the same as the contents of the pulse train PU1 described above. The pulse train PU3 is a signal output from the first set SS1_3 of the sensor unit SU(2). The pulse train PU3 is composed of a dummy pulse DP3, an identification pulse IP3, and a sensor detection pulse SP3. The contents of the pulse train PU3 are the same as the contents of the pulse train PU1 described above. The pulse train PU4 is a signal output from the first set SS1_4 of the branching unit BU. The pulse train PU4 is composed of a dummy pulse DP4, an identification pulse IP4, and a sensor detection pulse SP4. The contents of the pulse train PU4 are the same as the contents of the pulse train PU1 described above.

[0088] The pulse widths of the identification pulses IP1 to IP4 correspond to the delay times t_id1 to t_id4. As described above, the pulse widths of the identification pulses IP1 to IP4 are different from each other. In this embodiment, the delay time t_id1=100 nsec, the delay time t_id2=200 nsec, the delay time t_id3=300 nsec, and the delay time t_id4=400 nsec. It is preferable that the difference in pulse width between the identification pulses IP1 to IP4 is designed with a margin. This makes it possible to identify each of the identification pulses IP1 to IP4 even when there is manufacturing variation. In this embodiment, the difference in pulse width is 100 nsec.

[0089] Furthermore, the pulse width of each of the dummy pulses DP1 to DP4 is not particularly limited and can be determined appropriately. In this embodiment, the pulse width of each of the dummy pulses DP1 to DP4 is set to the same 150 nsec.

[0090] In each of the pulse trains PU1 to PU4, the first dummy pulse DP is negligible data. The second identification pulse IP can identify the sensor by its pulse width. Therefore, by detecting the pulse width of the second pulse in each pulse train, it is possible to identify which sensor output the next third pulse, the sensor detection pulse SP.

[0091] For example, in FIG. 24, the identification pulse of the first pulse train (times t1 to t2) is about 100 nsec, so the subsequent sensor detection pulse can be identified as the output of the first set SS1_1. Similarly, the identification pulse of the second pulse train (times t2 to t3) is about 300 nsec, so the subsequent sensor detection pulse can be identified as the output of the first set SS1_3. Similarly, the identification pulse of the third pulse train (times t3 to t4) is about 400 nsec, so the subsequent sensor detection pulse can be identified as the output of the first set SS1_4. Similarly, the identification pulse of the fourth pulse train (times t4 to t5) is about 200 nsec, so the subsequent sensor detection pulse can be identified as the output of the second set SS2_2.

[0092] As described above, even if the readout order of the multiple sensor outputs (i.e., the output order of the pulse train) changes, it is possible to identify the correspondence between the multiple sensor outputs and the multiple sensors by using the identification pulse IP. This makes it possible to determine which sensor each of the sensor outputs (time constant output pulses) that are continuously output to the serial output signal SOUT belongs to.

[0093] (Effect of Dummy Pulse DP) The problem will be explained. Due to the scale of the sensor network, differences in detection paths, and the like, the signal propagation time between sensor units and between a sensor unit and a branching unit may become too long to be ignored. Here, consider a case where the signal propagation time between the connection paths between the jth set and the j+1th set becomes long. In this case, the pulse width of the leading pulse of the j+1th pulse train PU(j+1) increases by the amount of the signal propagation time.

[0094] Therefore, in the technology of this embodiment, a dummy pulse DP is placed at the beginning of each pulse train PU. This allows the dummy pulse DP to absorb the increase in pulse width due to the signal propagation time. It is possible to suppress the influence of the signal propagation time on the identification pulse IP and the sensor detection pulse SP that are output following the dummy pulse DP. As a result, it is possible to improve the accuracy of data readout. EXAMPLES

[0095] (First set SS1m configuration) Fig. 25 shows the circuit configuration of the first set SS1m of Example 3. The first set SS1m of Example 3 (Fig. 25) differs from the first set SS1 of Example 2 (Fig. 18) in that it includes a first identification signal generator IC1m. Components common to the first set SS1m of Example 3 and the first set SS1 of Example 2 are given the same reference numerals and will not be described.

[0096] The first identification signal generator IC1m includes delay circuits DY2m and DY3m, and NAND circuits ND2m and ND3m. The drive dummy signal DR_d is input to the delay circuit DY2m. The delay circuit DY2m is a circuit that adds a delay time t_ida only to the falling edge. The method of setting the delay time t_ida will be described later. The delay circuit DY2m outputs a drive identification signal DR_ida. The detection dummy signal DE_d and the drive identification signal DR_ida are input to the NAND circuit ND2m, and the detection identification signal DE_ida is output.

[0097] The drive identification signal DR_ida is input to the delay circuit DY3m. The delay circuit DY3m is a circuit that adds a delay time t_idb only to the falling edge. The method of setting the delay time t_idb will be described later. The delay circuit DY3m outputs the drive identification signal DR_idb. The detection identification signal DE_ida and the drive identification signal DR_idb are input to the NAND circuit ND3m, and the detection identification signal DE_idb is output.

[0098] The operation of the first set SS1m will be described using the waveform diagram of FIG. 26. Only the parts that are different from the waveform diagram (FIG. 19) of the first set SS1 of the second embodiment will be described. At time t1_2, the delay circuit DY2m outputs the drive identification signal DR_ida. The drive identification signal DR_ida is a signal obtained by adding a delay time t_ida to the falling edge of the drive dummy signal DR_d. The NAND circuit ND2m generates the detection identification signal DE_ida based on the detection dummy signal DE_d and the drive identification signal DR_ida (arrow 71). The detection identification signal DE_ida is added to the detection output signal DEO as an identification pulse IP1a (arrow Y72). The pulse width of the detection identification signal DE_ida and the identification pulse IP1a is the delay time t_ida.

[0099] At time t1_3, the delay circuit DY3m outputs the drive identification signal DR_idb. The drive identification signal DR_idb is a signal obtained by adding a delay time t_idb to the falling edge of the drive identification signal DR_ida. The NAND circuit ND3m generates the detection identification signal DE_idb based on the detection identification signal DE_ida and the drive identification signal DR_idb (arrow 73). The detection identification signal DE_idb is added to the detection output signal DEO as an identification pulse IP1b (arrow Y74). The pulse width of the detection identification signal DE_idb and the identification pulse IP1b is the delay time t_idb.

[0100] (Configuration of Identification Pulses IP1a and IP1b) Figure 27 shows an example of setting the pulse width of the identification pulses IP1a and IP1b. The identification pulses IP1a and IP1b have two pulse widths, 100 nsec and 200 nsec. A 100 nsec pulse corresponds to the binary number "0." A 200 nsec pulse corresponds to the binary number "1." Therefore, by combining the identification pulses IP1a and IP1b, it is possible to generate four bit patterns: "00," "01," "10," and "11."

[0101] A different bit pattern is assigned to each of the first set SS1_1, the second set SS2_2, the first set SS1_3, and the first set SS1_4. This makes it possible to identify each of the four sensors by a combination of the identification pulses IP1a and IP1b.

[0102] (Effect of discrimination pulses IP1a and IP1b) Fig. 28 is a diagram illustrating the operation of the sensor network 201 (Fig. 21) in which the serial connection path CP1 is formed, and Fig. 29 is a diagram illustrating the operation of the sensor network 201 (Fig. 22) in which the serial connection path CP2 is formed.

[0103] 28, in the case of the serial connection path CP1, pulse trains PU1, PU2, PU3, and PU4 are output to the serial output signal SOUT in this order. At this time, the bit patterns represented by the combination of the identification pulses IP1a and IP1b are output in the order of "00," "01," "10," and "11." This makes it possible to identify, based on the settings in FIG. 27, that the sensor outputs have been read out in the order of the first set SS1_1, the second set SS2_2, the first set SS1_3, and the first set SS1_4.

[0104] 24, in the case of the serial connection path CP2, the pulse trains PU1, PU3, PU4, and PU2 are output to the serial output signal SOUT in this order. At this time, the bit patterns represented by the combination of the identification pulses IP1a and IP1b are output in the order of "00," "10," "11," and "01." This makes it possible to identify, based on the settings in FIG. 27, that the sensor outputs have been read out in the order of the first set SS1_1, the first set SS1_3, the first set SS1_4, and the second set SS2_2.

[0105] (Other effects) The problem of the first set SS1 (FIG. 18) of the second embodiment will be described. In the first set SS1 of the second embodiment, each of the pulse trains PU is composed of three pulses (a dummy pulse DP, an identification pulse IP, and a sensor detection pulse SP), which are an odd number. Then, the detection input signal DEI input to the first set SS1 is inverted and output as the detection output signal DEO. For example, in the example of FIG. 19, when a high-level detection input signal DEI is input at time t1 (see region R61), a low-level detection output signal DEO is output at time t2 (see region R62). That is, when the pulse train PU is composed of an odd number of pulses, each of the first set SS1 and the second set SS2 functions as a kind of inverter.

[0106] Also, the sensor network has a period in which it is in an initial state. The initial state is a state in which the above-mentioned switching operation is not performed. For example, in FIG. 23 and FIG. 24, the period from when the power is turned on to when the sensor control signal EN rises at time t0 is the initial state period. When the sensor network is in the initial state, as described above, multiple closed loop paths are formed. If an odd number of first sets SS1 and second sets SS2 functioning as inverters are arranged on these closed loop paths, an unintended ring oscillator is formed. As a result, the closed loop path goes into an oscillating state, which causes a problem of wasting power consumption.

[0107] For example, in the example of Fig. 20, the outer peripheral closed loop is arranged with three elements, namely, the first set SS1_1, the first set SS1_3, and the first set SS1_4. Also, the loop wire LW1 is arranged with one element, namely, the second set SS2_2. Therefore, the outer peripheral closed loop and the loop wire LW1 oscillate.

[0108] Therefore, in the technology of the third embodiment, each of the pulse trains PU is composed of four pulses (a dummy pulse DP, an identification pulse IPa, an identification pulse IPb, and a sensor detection pulse SP), which is an even number. As a result, the detection input signal DEI input to the first set SS1m is output as the detection output signal DEO without being inverted. For example, in the example of FIG. 26, when a high-level detection input signal DEI is input at time t1 (see region R71), a high-level detection output signal DEO is output at time t2 (see region R72). Therefore, a ring oscillator is not formed on the closed loop path. Since it is possible to prevent the closed loop path from oscillating during the period when the sensor network is in the initial state, it is possible to suppress power consumption.

[0109] (Modification of the third embodiment) There may be various combinations of the identification pulses IP. For example, there may be a combination of Q consecutive identification pulses having P different pulse widths. This makes it possible to generate P×Q bit patterns.

[0110] The pulse train PU may have various combinations of pulses. For example, the first set SS1 may include two or more sensors, so that the pulse train PU may include two or more sensor detection pulses SP. Also, the pulse train PU may include three or more identification pulses IP. This allows the pulse train PU to be composed of an even number of pulses, six, including one dummy pulse, three identification pulses, and two sensor detection pulses.

[0111] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

[0112] (Modification) A D flip-flop with a preset whose hold value can be set externally may be used as the D flip-flop DF provided in the loop detection circuit LD of the switching circuit RCC1 (Fig. 7). Also, a D latch with a preset whose hold value can be set externally may be used as the D latch DL of the switching circuit RCC1 and the D latch DL of the switching parts SW1 and SW2 (Fig. 3). By presetting when the power is turned on, the initial values ​​of the D flip-flop and D latch can be reliably set to 1.

[0113] In the second embodiment, an example of the branching unit BUa having a built-in sensor array is shown, but the present invention is not limited to this. The branching unit does not have to have a built-in sensor array. The input / output unit IOU may have multiple ports.

[0114] The technology of this specification is intended to generate paths for continuously reading out the outputs of all sensors on the sensor network 1. Therefore, the type of output signal to be read out is not limited to a time constant output pulse. The technology of this specification can be applied to various output signals such as digital output signals.

[0115] In the sensor unit SU(N) of Fig. 3, the resistance value of the sensing element TH is used as the physical quantity to be sensed, but the present invention is not limited to this, and various physical quantities can be sensed. For example, the sensing object may be the sensing current of the photodiode PD or the capacitance of a variable capacitance element. [Explanation of symbols]

[0116] 1: Sensor network SU(1)~SU(3): Sensor unit BU: Branch unit IOU: Input / output unit LA: First signal line LB: Second signal line DRI_1 and DEI_1: First input terminal DRI_2 and DEI_2: Second input terminal DRO_1 and DEO_1: First output terminal DRO_2 and DEO_2: Second output terminal SW1 and SW2: Switching section SE1: First sensor SE2: Second sensor PT1~PT3: Port

Claims

1. A sensor network including N sensor units (N is a natural number equal to or greater than 2) and a branching unit, the sensor network has a serial connection structure in which the first to Nth sensor units are connected starting from the branching unit and then the serial connection structure returns to the branching unit, The sensor network includes: a first signal line for transmitting a pulse signal that is transmitted in a first direction from the branching unit and returns to the branching unit; a second signal line for transmitting a pulse signal from the branching unit in a second direction opposite to the first direction and returning to the branching unit; Equipped with Each of the N sensor units has a first input terminal, a first output terminal, a second input terminal, and a second output terminal; the first input terminal of a K-th sensor unit (K is a natural number not less than 2 and not more than N-1) is connected to the first output terminal of the K-1-th sensor unit via the first signal line; the first output terminal of the K-th sensor unit is connected to the first input terminal of the K+1-th sensor unit via the first signal line; the second input terminal of the K-th sensor unit is connected to the second output terminal of the K+1-th sensor unit via the second signal line; the second output terminal of the K-th sensor unit is connected to the second input terminal of the K-1-th sensor unit via the second signal line; Each of the N sensor units a first switching unit configured to detect whether or not the first signal line connecting the first input terminal and the first output terminal of the (K-1)th sensor unit is disconnected; a second switching unit configured to detect the presence or absence of a break in the second signal line connecting the second input terminal and the second output terminal of the (K+1)th sensor unit; It also has Each of the N sensor units when no break is detected by the first switching unit and the second switching unit, the pulse signal input to the first input terminal is transmitted to the first output terminal, and the pulse signal input to the second input terminal is transmitted to the second output terminal; When a break is detected by the first switching unit, the pulse signal input to the second input terminal is transmitted to the first output terminal; When a break is detected by the second switching unit, the pulse signal input to the first input terminal is transmitted to the second output terminal; Each of the N sensor units a first set including a first identification signal generating unit and a first sensor that are arranged in series on a transmission path of the pulse signal from the first input terminal to the first output terminal; a second set including a second identification signal generating unit and a second sensor that are arranged in series on a transmission path of the pulse signal from the second input terminal to the second output terminal; At least one set of the first identification signal generation unit is a circuit that generates a first identification signal for identifying the first sensor constituting the first set in response to the pulse signal being input from the first input terminal, adds the generated first identification signal to the pulse signal, and outputs the resultant signal to the first sensor; the first sensor is a circuit that starts a detection operation in response to the pulse signal to which the first identification signal has been added being input from the first identification signal generating unit, and adds a first sensor detection signal detected by the first sensor to the first identification signal and outputs the result to the first output terminal, the second identification signal generation unit is a circuit that generates a second identification signal for identifying the second sensor constituting the second set in response to the pulse signal being input from the second input terminal, adds the generated second identification signal to the pulse signal, and outputs the resultant signal to the second sensor; the second sensor is a circuit that starts a detection operation in response to the pulse signal to which the second identification signal has been added being input from the second identification signal generating unit, and adds a second sensor detection signal detected by the second sensor to the second identification signal and outputs the result to the second output terminal, the branching unit outputs the pulse signal including L first identification signals and L first sensor detection signals generated by L first sets (L is a natural number greater than or equal to 0 and less than or equal to N) included in the N sensor units, and M second identification signals and M second sensor detection signals generated by M second sets (M is a natural number greater than or equal to 0 and less than or equal to N) included in the N sensor units. Sensor network.

2. the first identification signal is a single pulse having a unique first pulse width for identifying the first sensor; the second identification signal is a single pulse having a unique second pulse width for identifying the second sensor; the L first identification signals generated by the L first identification signal generators and the M second identification signals generated by the M second identification signal generators all have different pulse widths. The sensor network of claim 1 .

3. the first identification signal and the second identification signal are pulse signals each including Q successive pulses having P different pulse widths, The P and the Q are natural numbers between 2 and N-1, the first identification signal and the second identification signal are configured to be capable of generating P×Q bit patterns; the L first identification signals generated by the L first identification signal generators and the M second identification signals generated by the M second identification signal generators all have the bit patterns different from each other; The sensor network of claim 1 .

4. the first set further includes a first dummy signal generating unit disposed on a transmission path of the pulse signal from the first input terminal to the first identification signal generating unit, the second set further includes a second dummy signal generating unit disposed on a transmission path of the pulse signal from the second input terminal to the second identification signal generating unit, the first dummy signal generating unit is a circuit that generates a first dummy signal for one pulse in response to the pulse signal being input from the first input terminal, adds the generated first dummy signal to the pulse signal, and outputs the resultant signal to the first identification signal generating unit; the second dummy signal generating unit is a circuit that generates a second dummy signal for one pulse in response to the pulse signal being input from the second input terminal, adds the generated second dummy signal to the pulse signal, and outputs the resultant signal to the second identification signal generating unit. The sensor network according to claim 2 or 3.

5. the pulse signal is a signal whose voltage transitions between a first level and a second level different from the first level, the first set outputs, from the first output terminal, a first pulse train to which the first dummy signal, the first identification signal, and the first sensor detection signal have been added in response to a transition of a voltage inputted from the first input terminal from the first level to the second level; the number of pulses in the first pulse train is such that a voltage at the completion of output of the first pulse train becomes the first level, the second set outputs, from the second output terminal, a second pulse train to which the second dummy signal, the second identification signal, and the second sensor detection signal have been added in response to a transition of a voltage input from the second input terminal from the first level to the second level; The number of pulses in the second pulse train is set so that a voltage at the completion of output of the second pulse train becomes the first level. The sensor network of claim 4.

6. the branching unit includes a third input terminal, a third output terminal, a fourth input terminal, and a fourth output terminal; the third output terminal is connected to the first input terminal of a first sensor unit via the first signal line, the third input terminal is connected to the first output terminal of the N-th sensor unit via the first signal line; the fourth output terminal is connected to the second input terminal of the N-th sensor unit via the second signal line; the fourth input terminal is connected to the second output terminal of a first sensor unit via the second signal line, The branching unit includes a third switching unit, The third switching unit is a first state in which the pulse signal is output from the third output terminal and the pulse signal input to the fourth input terminal is transmitted to the fourth output terminal; a second state in which the pulse signal is output from the fourth output terminal and the third output terminal is set to a high impedance state; The above configuration is possible. The third switching unit is maintain the first state when the pulse signal output from the third output terminal is input to the fourth input terminal during the period from when the pulse signal is output from the third output terminal to when the pulse signal transmitted through the sensor network and returned is input to the third input terminal; when the pulse signal is input to the third input terminal without the pulse signal being input to the fourth input terminal after the pulse signal is output from the third output terminal, the switching to the second state is performed. The sensor network of claim 1 .

7. A sensor network including N sensor units (N is a natural number equal to or greater than 2) and a branching unit, the sensor network has a serial connection structure in which the first to Nth sensor units are connected starting from the branching unit and then the serial connection structure returns to the branching unit, The sensor network includes: a first signal line for transmitting a pulse signal that is transmitted in a first direction from the branching unit and returns to the branching unit; a second signal line for transmitting a pulse signal from the branching unit in a second direction opposite to the first direction and returning to the branching unit; Equipped with Each of the N sensor units has a first input terminal, a first output terminal, a second input terminal, and a second output terminal; the first input terminal of a K-th sensor unit (K is a natural number not less than 2 and not more than N-1) is connected to the first output terminal of the K-1-th sensor unit via the first signal line; the first output terminal of the K-th sensor unit is connected to the first input terminal of the K+1-th sensor unit via the first signal line; the second input terminal of the K-th sensor unit is connected to the second output terminal of the K+1-th sensor unit via the second signal line; the second output terminal of the K-th sensor unit is connected to the second input terminal of the K-1-th sensor unit via the second signal line; the branching unit includes a third input terminal, a third output terminal, a fourth input terminal, and a fourth output terminal; the third output terminal is connected to the first input terminal of a first sensor unit via the first signal line, the third input terminal is connected to the first output terminal of the N-th sensor unit via the first signal line; the fourth output terminal is connected to the second input terminal of the N-th sensor unit via the second signal line; the fourth input terminal is connected to the second output terminal of a first sensor unit via the second signal line, The branching unit includes a third switching unit, The third switching unit is a first state in which the pulse signal is output from the third output terminal and the pulse signal input to the fourth input terminal is transmitted to the fourth output terminal; a second state in which the pulse signal is output from the fourth output terminal and the third output terminal is set to a high impedance state; The above configuration is possible. The third switching unit is maintain the first state when the pulse signal output from the third output terminal is input to the fourth input terminal during the period from when the pulse signal is output from the third output terminal to when the pulse signal transmitted through the sensor network and returned is input to the third input terminal; when the pulse signal is input to the third input terminal without the pulse signal being input to the fourth input terminal after the pulse signal is output from the third output terminal, switching to the second state; Each of the N sensor units a first set including a first identification signal generating unit and a first sensor that are arranged in series on a transmission path of the pulse signal from the first input terminal to the first output terminal; a second set including a second identification signal generating unit and a second sensor that are arranged in series on a transmission path of the pulse signal from the second input terminal to the second output terminal; At least one set of the first identification signal generation unit is a circuit that generates a first identification signal for identifying the first sensor constituting the first set in response to the pulse signal being input from the first input terminal, adds the generated first identification signal to the pulse signal, and outputs the resultant signal to the first sensor; the first sensor is a circuit that starts a detection operation in response to the pulse signal to which the first identification signal has been added being input from the first identification signal generating unit, and adds a first sensor detection signal detected by the first sensor to the first identification signal and outputs the result to the first output terminal, the second identification signal generation unit is a circuit that generates a second identification signal for identifying the second sensor constituting the second set in response to the pulse signal being input from the second input terminal, adds the generated second identification signal to the pulse signal, and outputs the resultant signal to the second sensor; the second sensor is a circuit that starts a detection operation in response to the pulse signal to which the second identification signal has been added being input from the second identification signal generating unit, and adds a second sensor detection signal detected by the second sensor to the second identification signal and outputs the result to the second output terminal, the branching unit outputs the pulse signal including L first identification signals and L first sensor detection signals generated by L first sets (L is a natural number greater than or equal to 0 and less than or equal to N) included in the N sensor units, and M second identification signals and M second sensor detection signals generated by M second sets (M is a natural number greater than or equal to 0 and less than or equal to N) included in the N sensor units. Sensor network.

8. the first identification signal is a single pulse having a unique first pulse width for identifying the first sensor; the second identification signal is a single pulse having a unique second pulse width for identifying the second sensor; the L first identification signals generated by the L first identification signal generators and the M second identification signals generated by the M second identification signal generators all have different pulse widths. The sensor network of claim 7.

9. the first identification signal and the second identification signal are pulse signals each including Q successive pulses having P different pulse widths, The P and the Q are natural numbers between 2 and N-1, the first identification signal and the second identification signal are configured to be capable of generating P×Q bit patterns; the L first identification signals generated by the L first identification signal generators and the M second identification signals generated by the M second identification signal generators all have the bit patterns different from each other; The sensor network of claim 7.

10. the first set further includes a first dummy signal generating unit disposed on a transmission path of the pulse signal from the first input terminal to the first identification signal generating unit, the second set further includes a second dummy signal generating unit disposed on a transmission path of the pulse signal from the second input terminal to the second identification signal generating unit, the first dummy signal generating unit is a circuit that generates a first dummy signal for one pulse in response to the pulse signal being input from the first input terminal, adds the generated first dummy signal to the pulse signal, and outputs the resultant signal to the first identification signal generating unit; the second dummy signal generating unit is a circuit that generates a second dummy signal for one pulse in response to the pulse signal being input from the second input terminal, adds the generated second dummy signal to the pulse signal, and outputs the resultant signal to the second identification signal generating unit. The sensor network according to claim 8 or 9.

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