Semiconductor device

Abstract

To provide a semiconductor device in which the electric field concentration in a boundary region between an IGBT part and a diode is alleviated and breakdown is reduced.SOLUTION: A semiconductor device 100 according to an embodiment includes a diode part 20 placed on a semiconductor substrate 101 and an IGBT part 10 placed around the diode part. The IGBT part includes: a first semiconductor region 6 of a first conductivity type; a second semiconductor region 7 of a second conductivity type, provided on the first semiconductor region; and a trench 14 penetrating the second semiconductor region in a depth direction. The diode part includes: the first semiconductor region; a third semiconductor region 12 of the second conductivity type, provided on the first semiconductor region; and a second trench 16 penetrating the third semiconductor region in the depth direction. A fourth semiconductor region 70 of the second conductivity type is included between a first end 14EG extending from the first trench of the IGBT part in a first direction and a second end 16EG of the second trench of the diode part in the first direction, the fourth semiconductor region having a junction depth deeper than that of the second semiconductor region of the IGBT part.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, a reverse conducting IGBT (RC-IGBT) has been proposed, which is a semiconductor device in which an insulated gate bipolar transistor (IGBT) and a free wheeling diode are formed on a single semiconductor substrate. Also, an example has been disclosed in which a region called a resurf region for improving breakdown voltage is provided in the peripheral region of the semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-56498 A [Patent Document 2] JP 2018-46187 A [Patent Document 3] JP 2004-349556 A Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the embodiments is to provide a semiconductor device in which electric field concentration in the boundary region between the IGBT and the diode is alleviated, thereby reducing breakdown. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a semiconductor substrate, a diode section disposed on the semiconductor substrate, and an IGBT section disposed on the semiconductor substrate around the diode section. The IGBT section includes a first semiconductor region of a first conductivity type disposed on the semiconductor substrate, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a first trench provided to penetrate the second semiconductor region in a depth direction. The diode section includes the first semiconductor region, a third semiconductor region of a second conductivity type provided on the first semiconductor region, and a second trench provided to penetrate the third semiconductor region in a depth direction. A fourth semiconductor region of a second conductivity type having a junction depth deeper than the second semiconductor region of the IGBT section is provided between a first end of the first trench of the IGBT section in the first direction and a second end of the second trench of the diode section in the first direction. Effect of the Invention

[0006] According to the embodiment of the present invention, it is possible to provide a semiconductor device in which electric field concentration in the boundary region between the IGBT and the diode is alleviated, thereby reducing breakdown. [Brief description of the drawings]

[0007] [Figure 1] 1 is a top view of an entire structure of a semiconductor device according to an embodiment; [Diagram 2] FIG. 2 is an enlarged top view of a portion of FIG. 1; [Diagram 3] 3 is a cross-sectional view taken along line II in FIG. 2. [Figure 4] FIG. 3 is a cross-sectional view taken along line II-II in FIG. 2 . [Diagram 5] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2 . [Figure 6] 4 is a cross-sectional view taken along line IV-IV in FIG. 2 . [Figure 7] Cross-sectional view taken along line VV in Figure 1. [Figure 8] FIG. 11 is a cross-sectional view of a semiconductor device according to a modified example of the embodiment. [Figure 9] 1 is a top view of a portion of an IGBT of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of lengths of each part, etc., differ from the actual ones. Therefore, the specific dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0009] In addition, the embodiments shown below are examples of devices for embodying the technical idea of ​​this invention, and the technical idea of ​​this invention does not specify the shape, structure, arrangement, etc. of the components as described below. Various modifications can be made to the embodiments of this invention within the scope of the claims. In addition, the terms "upper" and "lower" that specify upper and lower are used in this invention for convenience of description, and even if they are provided on the side, they fall within the scope of the rights of this invention as long as they are substantially the same as the constituent elements of this invention. In addition, "upper" includes not only the case where they are formed in contact with the object, but also the case where they are formed through another layer. In addition, in this invention, "connection" is not limited to direct connection, and even if they are connected through something such as a resistor, they fall within the scope of the rights of this invention as long as they are substantially the same as the constituent elements of this invention.

[0010] In the following description, the directions of the semiconductor device are defined by the XYZ axes. In the cross-sectional view, the left-right direction is the X-axis direction, the direction perpendicular to the paper surface is the Y-axis direction, and the direction perpendicular to the XY plane is the Z-axis direction. These directions are merely examples. Depending on the arrangement of the pattern, they can be changed as appropriate. In the following description, the semiconductor device is mainly described as an IGBT, but it is sufficient that the semiconductor device has a freewheeling diode formed on one semiconductor substrate, and a MOSFET may be used instead of the IGBT. Also, other elements with an insulated gate structure such as an electron injection enhanced insulated gate transistor (IEGT) may be used. Also, a super junction MOSFET or a complementary metal oxide semiconductor field effect transistor (CMOSFET) may be used.

[0011] (Embodiment) FIG. 1 is a top view of the overall structure of a semiconductor device 100 according to an embodiment.

[0012] As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes a semiconductor substrate 101, a diode section 20 arranged on the semiconductor substrate 101, and an IGBT section 10 arranged around the diode section 20 on the semiconductor substrate 101. The semiconductor device 100 according to the embodiment configures a reverse conducting IGBT (RC-IGBT) in which the IGBT section 10 and the freewheeling diode section 20 are formed on one semiconductor substrate 101. A region for improving breakdown voltage, called a resurf region, is provided in a termination region 40 on the periphery of the semiconductor device 100. The IGBT section 10 is arranged around the diode section 20 arranged in an island shape on the semiconductor substrate 101. A boundary region 30 is provided around the diode section 20. The boundary region 30 is also called a dummy region. In the example shown in FIG. 1, a control pad section 500 is also provided on the semiconductor substrate 101. Although not shown in FIG. 1, an emitter pad 51 is provided on the IGBT section 10 and / or the diode section 20.

[0013] The control pad section 500 includes, for example, a current sense pad 50, a gate pad 52, and temperature sense pads 53 and 54. The current sense pad 50 is a control pad for detecting a current flowing in the cell region of the semiconductor device 100.

[0014] The gate pad 52 is a control pad to which a gate drive voltage is applied for controlling the on / off of the semiconductor device 100. The temperature sense pads 53 and 54 are control pads electrically connected to, for example, the anode and cathode of a temperature sense diode provided in the semiconductor device 100.

[0015] Fig. 2 is an enlarged top view of a portion of the semiconductor device 102 in Fig. 1. Fig. 2 shows the arrangement of the diode section 20, a boundary region (dummy section) 30 surrounding the diode section 20, and the IGBT section 10 surrounding the boundary region 30. The inside of the dashed line FLR represents a region where a fourth semiconductor region (FLR region) described below is provided (the boundary line between the presence or absence of the fourth semiconductor region). The dashed line DMY1 represents the boundary between the diode section 20 and the boundary region 30. The dashed line DMY2 represents the boundary between the IGBT section 10 and the boundary region 30.

[0016] In the IGBT section 10, a plurality of trenches 14 extend in a first direction (longitudinal direction, Y direction) and are arranged in parallel in a second direction (transverse direction, X direction). Some of the trenches 14 are each connected to each of the trenches 15 in the boundary region 30 in the Y direction.

[0017] A connection trench 16C2 extending in a second direction perpendicular to the Y direction is provided at the Y-direction end of the trench 16 of the diode section 20. The trenches 16 extend in the Y direction, are arranged in parallel in the second direction (short side direction, X direction), and are terminated in a T-structure at the connection trench 16C2.

[0018] In a boundary region 30 between the diode section 20 and the IGBT section 10 as viewed in the Y direction from the diode section 20, the trench 15 has an end spaced apart from the trench 16 of the diode section 20 and the connection trench 16C2 which are on an extension line in the Y direction. A connection trench 15C1 extending in the X direction is provided at an end in the Y direction of the trench 15 in the boundary region 30. In the boundary region 30, a plurality of trenches 15 extend in the Y direction and terminate in a T-shaped structure at the connection trench 15C1.

[0019] A first end 15EG in the Y direction extending from the trench 15 is connected to a first end 15EG in the Y direction extending from an adjacent trench 15 via a connection trench 15C1.

[0020] A second end 16EG in the Y direction extending from the trench 16 is connected to a second end 16EG in the Y direction extending from an adjacent trench 16 via a connection trench 16C2.

[0021] A distance Y1 between a first end 15EG in the Y direction extending from the trench 15 and a second end 16EG in the Y direction extending from the trench 16 is equal to or less than a distance X1 between adjacent trenches 15 in the X direction of the trenches 15 in the boundary region 30. In other words, Y1<=X1 holds.

[0022] 2, in a boundary region 30 between the diode section 20 and the IGBT section 10 as viewed in the X direction from the diode section 20, the trenches 15 extend in the Y direction and are arranged in parallel in the second direction (short-side direction, X direction). Each of the trenches 15 in the boundary region 30 is connected to each of the trenches 14 in the IGBT section 10 that exist in the Y direction, and the trenches 15 and the trenches 14 are continuous with each other.

[0023] With respect to the distance from the P-type fourth semiconductor region 70 with a low impurity concentration in the boundary region 30 to the emitter region 8 of the IGBT section 10 on the diode section 20 side, the trench 14 is formed so that the distance WL in the longitudinal direction (Y direction) is longer than the distance WS in the lateral direction (X direction) of the trench 14 of the IGBT section 10. In other words, WL>WS is established. There are a plurality of trenches 15 between the emitter region 8 in the X direction (WS) as viewed from the diode section 20 and the diode section 20, and these trenches 15 can prevent electrons from spreading from the emitter region to the diode section 20 side, and the distance WS can be made shorter than the distance WL.

[0024] In the IGBT section 10, a hole is formed on the P base region 7 sandwiched between the trenches 14 in the X direction, and the hole extends in the Y direction. A P-type emitter contact region 9E is formed below the bottom of the hole and above the P base region 7 in the Z direction. The n emitter region 8 is formed at the opening of the trench 14, and the n emitter region 8 is exposed on the side of the hole. The n emitter region 8 is adjacent to the trench 14 as shown in FIG. 2 and is arranged discretely in the Y direction. The n emitter regions 8 are arranged at regular intervals in the Y direction, but do not necessarily need to be arranged with regularity in the Y direction. The n emitter regions 8 may be arranged intermittently. In this way, the IGBT section 10 may include a region where the n emitter region 8 is arranged and a region where the n emitter region 8 is not arranged. By arranging the n emitter regions 8 intermittently in the IGBT section 10, excessive electron injection can be suppressed and the switching time can be shortened.

[0025] Fig. 3 is a cross-sectional view taken along line II in Fig. 2. Fig. 3 shows a cross-sectional structure taken along the XZ plane in a range spanning the diode section 20, the boundary region 30, and the IGBT section 10. In Fig. 3, a dashed line DMY1 extending in the Z direction represents the boundary between the diode section 20 and the boundary region 30. Also, a dashed line DMY2 extending in the Z direction represents the boundary between the IGBT section 10 and the boundary region 30. Note that while some of the trenches 14 taken along line II are omitted in Fig. 2, five trenches are shown in Fig. 3.

[0026] As shown in FIG. 3, the semiconductor substrate 101 includes, for example, an N-type high-resistance drift region 5, an N-type accumulation region 6 formed in the Z direction on the drift region 5 and having a higher impurity concentration than the drift region 5, a P-type base region 7 and an anode region 12 formed in the Z direction on the accumulation region 6, an N-type buffer region 4 formed below the drift region 5 (in the negative Z direction), and a P-type collector region 2 and an N-type cathode region 3 formed below the buffer region 4 (in the negative Z direction).

[0027] The diode section 20 comprises an N-type high-resistance drift region 5, an N-type accumulation region 6 arranged on the drift region 5, a P-type anode region 12 provided on the accumulation region 6, and a trench 16 provided so as to penetrate the anode region 12 in the depth direction (Z direction).

[0028] In the diode section 20, the anode region 12 extends in the Y direction, sandwiched between trenches 16 extending in the Y direction. A hole is formed in the anode region 12 in the Z direction, and a P-type anode contact region 9A is provided at the bottom of the hole. An emitter electrode (upper electrode) 11 is provided inside the hole, and the anode contact region 9A is connected to the emitter electrode (upper electrode) 11. The trench 16 includes an intra-trench electrode 16a and an insulating film 16b. The intra-trench electrode 16a is connected to the emitter electrode (upper electrode) 11. The trench 16 penetrates the anode region 12, but does not penetrate the accumulation region 6.

[0029] In the boundary region 30, an N-type accumulation region 6 is disposed on the drift region 5, and a base region 7 extends in the Y direction, sandwiched between trenches 15 extending in the Y direction. A P-type dummy contact region 9D is disposed on the base region 7 in the Z direction. The dummy contact region 9D connected to the base region 7 is connected to an emitter electrode (upper electrode) 11. The trench 15 includes an intra-trench electrode 15a and an insulating film 15b. The intra-trench electrode 15a is electrically connected to the intra-trench electrode 14a of the IGBT section 10. Unlike the IGBT section 10, an emitter region 8 is not provided on the base region 7 in the Z direction in contact with the trench 15. The trench 15 penetrates the base region 7, but does not penetrate the accumulation region 6.

[0030] The IGBT section 10 includes an N-type drift region 5, an N-type accumulation region 6 disposed on the drift region 5, a P-type base region 7 provided on the accumulation region 6, and a trench 14 provided so as to penetrate the base region 7 in the depth direction (Z direction). Here, the trench 14 does not penetrate the accumulation region 6.

[0031] In the IGBT section 10, the base region 7 extends in the Y direction, sandwiched between trenches 14 extending in the Y direction. An emitter region 8 is provided on the Z direction of the base region 7 in contact with the trenches 14. A hole is carved on the Z direction of the base region 7, and a P-type emitter contact region 9E is disposed at the bottom of the hole. The emitter contact region 9E extends in the Y direction on the base region 7 sandwiched between the trenches 14. The emitter region 8 and the emitter contact region 9E are connected to an emitter electrode (upper electrode) 11. The trench 14 includes an intra-trench electrode 14a and an insulating film 14b. The intra-trench electrode 14a is electrically connected to the gate pad 52 of FIG. 2.

[0032] An N-type emitter region 8 and a P-type emitter contact region 9E are formed in the base region 7 sandwiched between the trenches 14 in the X direction. The detailed structure will be described later with reference to FIG.

[0033] The back electrode 1 provided in the negative Z direction of the semiconductor substrate 101 is a collector electrode connected to the P-type collector region 2 in the IGBT section 10, and a cathode electrode connected to the N-type cathode region 3 in the diode section 20. In the example of FIG. 3, the boundary line BL between the collector region 2 and the cathode region 3 is provided on the boundary line between the diode section 20 and the boundary region 30. The boundary line between the diode section 20 and the boundary region 30 is indicated by a dashed line DMY1. As indicated by a dashed line BLC1, the boundary line BL between the collector region 2 and the cathode region 3 may be provided within the boundary region 30. As indicated by a dashed line BLC2, the boundary line BL between the collector region 2 and the cathode region 3 may be provided within the IGBT section 10. As indicated by a dashed line BLA, the boundary line BL between the collector region 2 and the cathode region 3 may be provided within the diode section 20. In this way, the relative areas of the P-type collector region 2 and the N-type cathode region 3 change depending on the position of the boundary line BL between the collector region 2 and the cathode region 3. This changes the amount of carrier injection, making it possible to appropriately change the switching characteristics of the semiconductor device 100 as an RC-IGBT depending on the application.

[0034] Fig. 4 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 4 shows a cross-sectional structure taken along the YZ plane spanning the diode section 20, the boundary region (dummy section) 30, and the region where the emitter electrode 11 of the IGBT section 10 is connected to the P-type emitter contact region 9E. In Fig. 4, a dashed line DMY1 extending in the Z direction represents the boundary between the diode section 20 and the boundary region 30. A dashed line DMY2 extending in the Z direction represents the boundary between the IGBT section 10 and the boundary region 30. In Fig. 4, a dashed line FLR extending in the Z direction represents the boundary of the fourth semiconductor region 70. The fourth semiconductor region 70 is formed inside the region defined by the dashed line FLR. That is, the fourth semiconductor region 70 is formed not only directly below the base region 7 of the boundary region 30 sandwiched between the connection trench 15C1 and the connection trench 16C2, but also extends partially below the base region 7 of the boundary region 30 in the negative Y direction beyond the sidewall of the connection trench 15C1, and also extends partially below the anode region 12 of the diode section 20 in the Y direction beyond the sidewall of the connection trench 16C2. The dashed line DL shows a schematic representation of a depletion layer in a thermal equilibrium state that spreads in the N-type semiconductor region 6. The connection trench 15C1 of the boundary region 30 includes an intra-trench electrode 15a and an insulating film 15b. The connection trench 16C2 of the diode section 20 includes an intra-trench electrode 16a and an insulating film 16b. As shown in FIG. 4, it can be seen that the provision of the fourth semiconductor region 70 reduces the depletion layer from penetrating in the Z direction into the region sandwiched between the connection trench 15C1 and the connection trench 16C2.

[0035] Furthermore, an anode contact region 9A is formed in the base region 7 between the connection trench 15C1 and the connection trench 16C2, and the anode contact region 9A is electrically connected to the emitter electrode 11.

[0036] 5 is a cross-sectional view taken along line III-III in FIG. 1. In FIG. 5, a cross-sectional structure spanning the diode section 20, the dummy section 30, and the IGBT section 10 is shown. That is, cross-sectional structures taken along the YZ plane of the trenches 14 and 16 are shown. In FIG. 5, a dashed line DMY1 extending in the Z direction represents the boundary between the diode section 20 and the boundary region 30. Also, a dashed line DMY2 extending in the Z direction represents the boundary between the IGBT section 10 and the boundary region 30. In FIG. 5, a dashed line FLR extending in the Z direction represents the boundary of the fourth semiconductor region 70. The dashed line DL diagrammatically represents a depletion layer in the N-type semiconductor region 6 in a thermal equilibrium state.

[0037] 5, a fourth semiconductor region 70 of the second conductivity type having a deeper junction depth than the P anode region 12 of the diode section 20 is provided between a first end 15EG in the Y direction of the extension of the trench 15 of the boundary region 30 and a second end 16EG in the Y direction of the extension of the trench 16 of the diode section 20. As shown in FIG. 5, it can be seen that the provision of the fourth semiconductor region 70 reduces the intrusion of a depletion layer in the Z direction in a region where no trench is formed between the longitudinal direction of the trench 15 and the longitudinal direction of the trench 16.

[0038] 6 is a cross-sectional view taken along line IV-IV in FIG. 1. In FIG. 6, a cross-sectional structure spanning the diode section 20, the boundary region 30, and the IGBT section 10 is shown. That is, a cross-sectional structure along the YZ plane in a range along the anode region 12, the fourth semiconductor region 70, and the P base region 7 is shown. The dashed line DL shows a schematic representation of a depletion layer in a thermal equilibrium state in which the depletion layer spreads in the N-type semiconductor region 6. As shown in FIG. 6, it can be seen that the provision of the fourth semiconductor region 70 reduces the depletion layer from penetrating in the Z direction into the region sandwiched between the connection trench 15C1 and the connection trench 16C2.

[0039] The impurity concentration NP(70) of the fourth semiconductor region 70 is lower than the impurity concentration NP(7) of the second semiconductor region (base region) 7. That is, NP(70) < NP(7) holds. Also, the impurity concentration NP(70) of the fourth semiconductor region 70 is lower than the impurity concentration NP(12) of the third semiconductor region 12. That is, NP(70) < NP(12) holds.

[0040] Also, as shown in FIG. 6, the junction depth Z4 of the fourth semiconductor region 70 is deeper than the junction depth Z3 of the third semiconductor region 12.

[0041] Also, the junction depth Z4 of the fourth semiconductor region 70 is shallower than the depth ZT1 of the trench 14 of the IGBT section 10.

[0042] Also, the junction depth Z4 of the fourth semiconductor region 70 is shallower than the depth ZT2 of the trench 16 of the diode section 20.

[0043] In the semiconductor device 100 according to the embodiment, the diode section 20 is formed in an island shape, and the IGBT section 10 is formed around the diode section 20. Note that since the portion having the trench 15 of the dummy section 30 extending from the IGBT section 10 is continuous from the trench 14, in the following description, it will be described as the trench 14 of the IGBT section (including the dummy section) 10. The trench 14 of the dummy section 30 does not include the emitter region 8, but the trench 14 of the IGBT section 10 includes the emitter region 8.

[0044] The longitudinal direction of the trench 14 of the IGBT section (including the dummy section) 10 in which the trench electrode 14a is embedded with the insulating film 14b interposed therebetween and the longitudinal direction of the trench 16 of the diode section 20 in which the trench electrode 16a having the same potential as the emitter electrode 11 is embedded with the insulating film 16b interposed therebetween are formed in the same Y direction, but the two trenches are separated from each other. It is desirable that the trench 16 of the diode section 20 is arranged on the extension line of the longitudinal direction of the trench 14 of the IGBT section (including the dummy section) 10. Thereby, when viewed in plan, the electric field concentration in the boundary region 30 can be alleviated and the spread of the depletion layer can be made gentle.

[0045] Furthermore, it is desirable that the distance Y1 between the first longitudinal end 14EG of the trench 14 in the IGBT section (including the dummy section) 10 and the second longitudinal end 16EG of the trench 16 in the diode section 20 is the same as or less than the distance X1 (trench spacing in the IGBT section 10) between adjacent trenches in the short direction (X direction) of the trench 14 in the same IGBT section (including the dummy section) 10.

[0046] A P-type semiconductor region (FLR region: fourth semiconductor region 70) having a lower impurity concentration than the P base region 7 of the IGBT section 10 is formed on the N-type drift region 5 of the boundary region 30 extending from the first longitudinal end 14EG of the trench 14 of the IGBT section (including the dummy section) 10 to the second longitudinal end 16EG of the trench 16 of the diode section 20.

[0047] This reduces the intrusion of the depletion layer in the Z direction in the accumulation region 6 below the base region 7 extending from the first longitudinal end 14EG of the trench 14 to the second longitudinal end 16EG of the trench 16. This makes it possible to make it easier for the depletion layer to spread in the semiconductor region including the fourth semiconductor region 70 in the boundary region 30 sandwiched between the first longitudinal end 14EG of the trench 14 of the IGBT section (including the dummy section) 10 and the second longitudinal end 16EG of the trench 16 of the diode section 20.

[0048] Moreover, it is desirable that the P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 has a deeper junction depth than the base region 7 of the IGBT section 10 and a deeper junction depth than the anode region 12 of the diode section 20. However, the P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 does not have to be deep enough to reach the bottoms (trench depths) of the trenches of the IGBT section 10 and the diode section 20. This is because the breakdown point is shifted from the boundary region 30 to the IGBT section 10 side.

[0049] The P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 is formed to extend further inward than the first end 14EG of the trench 14 (in the negative Y direction, which is on the IGBT section 10 side than the first end 14EG of the trench 14) so ​​as to include the first end 14EG of the trench 14 in the IGBT section (including the dummy section) 10. Similarly, the fourth semiconductor region 70 is formed to extend further inward than the second end 16EG of the trench 16 (in the Y direction) in the diode section 20 so as to include the second end 16EG of the trench 16 in the diode section 20.

[0050] The first end 15EG of the trench 15 is connected to the first end 15EG of the adjacent trench 15 by the connection trench 15C1. That is, the first end 15EG of the trench 15 is T-shaped. The adjacent intra-trench electrodes 14a in the IGBT section 10 are connected through the intra-trench electrode 15a in the trench 15 and the intra-trench electrode 15a in the connection trench 15C1. This eliminates the need to form a gate bus line on the semiconductor substrate 101 in the boundary region 30, and the gate bus line does not interfere with the formation of the upper electrode 11 on the semiconductor substrate 101 continuously from the IGBT section 10 to the diode section 20. In addition, since the intra-trench electrode 15a and the intra-trench electrode 16a extend in the X direction, the electric field distribution in the X direction in the region sandwiched between the connection trench 15C1 and the connection trench 16C2 can be made more uniform.

[0051] As shown in FIG. 2, in the short direction (X direction) of the trench 14 of the IGBT section 10 when viewed from the dashed line FLR (fourth semiconductor region 70), a dummy trench 15 in which no emitter region 8 is formed is arranged in parallel to the trench 14 of the IGBT section 10 between the P-type fourth semiconductor region 70 of the boundary region 30 with a low impurity concentration and the emitter region 8 so that the P-type fourth semiconductor region 70 of the boundary region 30 does not contact (reach) the emitter region 8.

[0052] The boundary BL between the P collector region 2 and the N cathode region 3 is formed in approximately the Z direction of the boundary region 30, but the boundary BL between the P collector region 2 and the N cathode region 3 does not have to be formed directly below the boundary region 30, and may be shifted. For example, the boundary BL between the P collector region 2 and the N cathode region 3 may be on the diode section 20 side of the boundary region 30. Or, it may be on the IGBT section 10 side.

[0053] A P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 is connected to the upper electrode (emitter electrode) 11 .

[0054] (Resurf structure) FIG. 7 is a cross-sectional view taken along line EE in FIG.

[0055] The semiconductor device 100 according to the embodiment includes a first resurf region 220 and a second resurf region 230 in the termination region 40. The first resurf region 220 is connected to the P base region 7 to improve the breakdown voltage. The second resurf region 230 is connected to the first resurf region 220 via a depletion layer. A dashed line BLL extending in the Z direction indicates a boundary between the IGBT section 10 and the termination region 40. The back electrode 1 is connected to the P-type collector region 2 of the IGBT section 10. The back electrode 1 is also connected to the N-type semiconductor region 33 of the termination region 40. The N-type semiconductor region 33 is at the same potential as the cathode region 3 of the diode section 20. The N-type semiconductor region 33 is at the same potential as the N-type stopper layer 260 of the termination section. The boundary between the P-type collector region 2 of the IGBT section 10 and the N-type semiconductor region 33 is indicated by BL3.

[0056] The semiconductor substrate 101 has an N-type drift region 5 constituting one surface thereof. The multiple RESURF regions 220, 230 are made of P-type semiconductor regions having a lower impurity concentration than the P base region 7, and are formed in the surface region of the drift region 5 so as to surround the IGBT section 10. The RESURF regions 220, 230 are formed simultaneously with the P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30, and therefore the junction depth is formed shallower than the trench 14 and deeper than the P base region 7.

[0057] Floating limiting ring diffusion layers 240, 250 are disposed on the further outer periphery of the second RESURF region 230. Furthermore, an N-type stopper layer 260 is disposed at the end portion. The stopper layer 260 is connected to the stopper electrode 130.

[0058] The floating limiting ring diffusion layers 240, 250 are provided to smooth the shape of the depletion layer and to alleviate electric field concentration. The floating limiting ring diffusion layers 240, 250 are formed of a P-type diffusion layer that is equal to or shallower than the resurf regions 220, 230. The impurity concentration of the floating limiting ring diffusion layers 240, 250 is set to be equal to or higher than the impurity concentration of the resurf regions 220, 230.

[0059] The P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 can be formed simultaneously with the first RESURF region 220 and the second RESURF region 230. Therefore, even if the P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 is additionally formed, an increase in the number of steps due to this can be suppressed.

[0060] The semiconductor device 100 according to the embodiment includes the resurf regions 220 and 230, and thus can easily achieve a high breakdown voltage.

[0061] (Modification) 8 is a cross-sectional view corresponding to FIG. 3 of a semiconductor device 103 according to a modification of the embodiment. In the semiconductor device 103 according to the modification of the embodiment, the P base region 7 in the boundary region 30 may be connected to the upper electrode (emitter electrode) 11 via a resistor R. The P base region 7 of the IGBT section 10 close to the boundary region 30 may also be connected to the upper electrode (emitter electrode) 11 via a resistor R. The P anode region 12 of the diode section 20 close to the boundary region 30 may also be connected to the upper electrode (emitter electrode) 11 via a resistor R.

[0062] The P-type fourth semiconductor region 70 having a low impurity concentration in the boundary region 30 may be connected via a resistor to the upper electrode (emitter electrode) 11. For example, since the P-type fourth semiconductor region 70 has a low impurity concentration and is connected to the upper electrode 11 with a relatively large contact resistance, the amount of holes injected from the P-type fourth semiconductor region 70 in the boundary region 30 to the N-type drift region 5 when the diode section 20 is on can be reduced, thereby shortening the reverse recovery time of the diode section 20.

[0063] (emitter contact structure) FIG. 9 is a top view of a portion of the semiconductor device according to the embodiment.

[0064] In the IGBT section 10, the P base region 7 extends in the Y direction, sandwiched between trenches 14 extending in the Y direction. An n emitter region 8 is disposed above the P base region 7 in the Z direction in contact with the trenches 14. A hole is formed between adjacent trenches 14, and a P-type emitter contact region 9E is disposed below the bottom of the hole and above the P base region 7 in the Z direction. The P-type emitter contact region 9E extends in the Y direction over the P base region 7 sandwiched between the trenches 14. The n emitter region 8 exposed on the side surface of the hole and the emitter contact region 9E at the bottom of the hole are connected to an emitter electrode (upper electrode) 11 embedded in the hole.

[0065] A structure is formed consisting of an n-emitter region 8 / base region 7 / n-emitter region 8 exposed on the side surface of the hole in the Y direction where the P-type emitter contact region 9E is formed. The structure is arranged on the ZY plane of the hole. The n-emitter regions 8 do not necessarily need to be arranged with regularity in the Y direction. By arranging the n-emitter regions 8 intermittently in the IGBT section 10, excessive electron injection can be suppressed and the switching time can be shortened.

[0066] (Other embodiments) As described above, the present invention has been described by the embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will become apparent to those skilled in the art. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters related to the scope of the claims appropriate from the above description. For example, although an example has been shown in which the trenches 14, 15, and 16 do not penetrate the accumulation region 6, at least one trench may penetrate the accumulation region 6, or the accumulation region 6 may not be provided in any one of the IGBT section 10, the diode section 20, and the dummy section 30. [Explanation of symbols]

[0067] 1...Back electrode (collector electrode, cathode electrode) 2…Collector region 3…Cathode area 4...Buffer area 5…Drift area 6…Storage area 7…Base area 8…Emitter area 9A…Anode contact area 9B…Base contact region 9D…Dummy contact area 9E…Emitter contact area 10…IGBT section 11...Emitter electrode (upper electrode) 12...Anode region 13...Interlayer insulation layer 14…First trench 14a, 15a, 16a...Trench electrodes 14b, 15b, 16b...insulating film 14EG…1st end 15...Third trench (dummy trench) 16…Second trench 16EG…2nd end 14C1, 16C2…Connection trench 20…Diode section 30...Boundary area (dummy part) 33...N-type semiconductor region 40…Terminal area 51, 52, 53, 54…Pads 70…Fourth semiconductor region 100, 102, 103...Semiconductor device 101...Semiconductor substrate 130...Stopper electrode 220, 230...Resurf area 240, 250...Floating limiting ring diffusion layer 260…Stopper layer 500…Control pad section

Claims

1. A semiconductor substrate; a diode portion disposed on the semiconductor substrate; an IGBT section disposed around the diode section on the semiconductor substrate; Equipped with The IGBT section is a first semiconductor region of a first conductivity type disposed on the semiconductor substrate; a second semiconductor region of a second conductivity type provided on the first semiconductor region; The second semiconductor region is provided so as to penetrate the second semiconductor region in a depth direction. The first trench and Equipped with The diode portion is The first semiconductor region; a third semiconductor region of a second conductivity type provided on the first semiconductor region; a second trench provided so as to penetrate the third semiconductor region in a depth direction; Equipped with a fourth semiconductor region of a second conductivity type having a deeper junction depth than the second semiconductor region of the IGBT section, between a first end of the first trench of the IGBT section in a first direction to which the first trench extends and a second end of the second trench of the diode section in the first direction.

2. The semiconductor device according to claim 1 , wherein an impurity concentration of said fourth semiconductor region is lower than an impurity concentration of said second semiconductor region.

3. The semiconductor device according to claim 1 , wherein an impurity concentration of said fourth semiconductor region is lower than an impurity concentration of said third semiconductor region.

4. The semiconductor device according to claim 1 , wherein said fourth semiconductor region has a deeper junction depth than said third semiconductor region.

5. The semiconductor device according to claim 1 , wherein the second trench of the diode section is disposed on an extension of the first trench of the IGBT section in the first direction.

6. 2. The semiconductor device according to claim 1, wherein a distance between the first end in the first direction extending from the first trench of the IGBT section and the second end in the first direction of the second trench of the diode section is equal to or less than a distance between adjacent first trenches in the second direction of the first trench of the same IGBT section.

7. The semiconductor device according to claim 1 , wherein a junction depth of said fourth semiconductor region is shallower than a depth of said first trench in said IGBT section.

8. a first connection trench extending in a second direction perpendicular to the first direction; the first end in the first direction extending from the first trench of the IGBT portion is connected to the first end in the first direction extending from an adjacent first trench via the first connection trench; a second connection trench extending in the second direction; 8. The semiconductor device according to claim 1, wherein the second end of the diode portion in the first direction extending from the second trench is connected to the second end of the diode portion in the first direction extending from an adjacent second trench via the second connection trench.

9. The semiconductor device according to claim 1 , further comprising a fifth semiconductor region disposed above the second semiconductor region.

10. 10. The semiconductor device according to claim 9, wherein, when viewed from the diode portion side, a distance in the first direction along the first trench between the fourth semiconductor region and the fifth semiconductor region is longer than a distance in a second direction perpendicular to the first direction between the fourth semiconductor region and the fifth semiconductor region.

11. The semiconductor device according to claim 9 , wherein the fifth semiconductor region is intermittently disposed on the second semiconductor region extending in the first direction.

12. a third trench provided in parallel with the first trench between the fourth semiconductor region and the fifth semiconductor region as viewed from the diode portion side; The semiconductor device according to claim 9 .

13. a fifth semiconductor region disposed on the second semiconductor region; an upper electrode electrically connected to the fifth semiconductor region; Equipped with The semiconductor device according to claim 1 , wherein said fourth semiconductor region is electrically connected to said upper electrode via a resistor.

14. The semiconductor device includes a resurf region in a peripheral portion, The semiconductor device according to claim 1 , wherein said fourth semiconductor region can be formed simultaneously with said RESURF region.

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