Printed wiring board

Abstract

To improve the quality of a printed wiring board.SOLUTION: A printed wiring board 2 has: a first conductor layer 10; a resin insulation layer 20 having a first surface 22 and a second surface 24 opposite to the first surface, which has the second surface 24 formed on the first conductor layer in a manner facing the first conductor layer 10, and which has a via hole 26 for exposing the first conductor layer 10; a second conductor layer 30 formed on the first surface 22 of the resin insulation layer 20; a via conductor 40 which is formed inside the via hole 26 so as to connect the first conductor layer 10 to the second conductor layer 30; a bonding layer 100 which is formed on the first conductor layer between the first conductor layer and the resin insulation layer 20 so as to bond the resin insulation layer 20 to the first conductor layer 10, and which has an opening 100H that is continuous with the via hole 26 so as to expose the first conductor layer 10; and a seed layer 30a constituting a portion of the via conductor 40, which makes contact with an inner wall surface 27 of the via hole 26 but is spaced away from an inner wall surface 100T of the opening 100H. Viewing from the center of the via hole 26, the inner wall surface 100T of the opening 100H is located further outside than the inner wall surface 27 of the via hole 26.SELECTED DRAWING: Figure 2B

Description

[Technical field]

[0001] The present disclosure relates to a printed wiring board. [Background technology]

[0002] Patent Document 1 describes that a chemical conversion coating having excellent oxidation resistance and corrosion resistance is formed on the copper surface of a printed wiring board by using a surface treatment agent containing a first tetrazole compound, ammonia, and a pH buffer at appropriate concentrations. Patent Document 1 also describes that a chemical conversion coating having excellent oxidation resistance, corrosion resistance, and water repellency is formed on the copper surface of a printed wiring board by using a surface treatment agent containing a first tetrazole compound, ammonia, and a second tetrazole compound at appropriate concentrations. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-54987 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a structure in which a resin insulating layer is formed on a conductor layer, it is desirable to suppress peeling of the resin insulating layer from the conductor layer. [Means for solving the problem]

[0005] The printed wiring board of the present disclosure is a printed wiring board having a first conductor layer, a first surface and a second surface opposite to the first surface, the second surface being formed on the first conductor layer facing the first conductor layer, and having a via hole exposing the first conductor layer, a second conductor layer formed on the first surface of the resin insulating layer, a via conductor formed in the via hole connecting the first conductor layer and the second conductor layer, an adhesive layer formed on the first conductor layer and between the resin insulating layer and adhering the resin insulating layer to the first conductor layer, the adhesive layer having an opening connected to the via hole and exposing the first conductor layer, and a seed layer forming a part of the via conductor, in contact with an inner wall surface of the via hole and spaced from the inner wall surface of the opening, wherein the inner wall surface of the opening is located outward relative to the inner wall surface of the via hole when viewed from the center of the via hole.

[0006] According to the embodiments of the present disclosure, in a structure in which a resin insulating layer is formed on a conductor layer, peeling of the resin insulating layer from the conductor layer can be suppressed. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing a printed wiring board according to a first embodiment of the present disclosure. [Figure 2A] 1 is a cross-sectional view showing a partially enlarged view of a printed wiring board according to a first embodiment of the present disclosure. [Figure 2B] 1 is a cross-sectional view showing a partially enlarged view of a printed wiring board according to a first embodiment of the present disclosure. [Figure 3A] 3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. [Figure 3B] 3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. [Figure 3C] 3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. [Figure 3D] 3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. [Figure 3E] 3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. [Figure 3F]3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. [Figure 3G] 3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. [Figure 3H] 3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. [Figure 3I] 3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. [Figure 3J] 3A to 3C are cross-sectional views showing an example of a manufacturing process for the printed wiring board according to the first embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an example of an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0009] Components indicated by the same reference numerals in each drawing are the same or similar components. Duplicate descriptions and reference numerals in the embodiments described below may be omitted. All drawings used in the following description are schematic. The dimensional relationships of each element, the ratios of each element, and the like shown in the drawings do not necessarily match the actual ones. The dimensional relationships of each element, the ratios of each element, and the like also do not necessarily match between multiple drawings.

[0010] Fig. 1 is a cross-sectional view showing a printed wiring board 2 of an embodiment. Figs. 2A and 2B are enlarged cross-sectional views showing a part of the printed wiring board 2 of the embodiment. As shown in Fig. 1, the printed wiring board 2 has an insulating layer 4, a first conductor layer 10, a resin insulating layer 20, a second conductor layer 30, and a via conductor 40.

[0011] The insulating layer 4 is formed using a resin. The insulating layer 4 may contain inorganic particles such as silica. The insulating layer 4 may contain a reinforcing material such as glass cloth. The insulating layer 4 has a third surface 6 (upper surface in the figure) and a fourth surface 8 (lower surface in the figure) opposite to the third surface 6.

[0012] The first conductor layer 10 is formed on the third surface 6 of the insulating layer 4. The first conductor layer 10 includes a signal wiring 12 and a pad 14. The first conductor layer 10 may also include a conductor circuit other than the signal wiring 12 and the pad 14. The first conductor layer 10 is mainly made of copper. The first conductor layer 10 is formed of a seed layer 10a on the insulating layer 4 and an electrolytic plating layer 10b on the seed layer 10a. The seed layer 10a is formed of a first layer 11a on the third surface 6 and a second layer 11b on the first layer 11a. The first layer 11a is formed of an alloy (copper alloy) containing copper, silicon, and aluminum. The second layer 11b is formed of copper. The electrolytic plating layer 10b is formed of copper. The first layer 11a is in contact with the insulating layer 4.

[0013] In the first conductor layer 10, the portion other than the portion in contact with the third surface 6 of the insulating layer 4 is the surface of the first conductor layer 10. The surface of the first conductor layer 10 includes a first surface and a second surface. The first surface is the surface exposed from the via hole 26 of the resin insulating layer 20. The second surface is the portion of the surface of the first conductor layer 10 other than the first surface. The first surface is not covered with the adhesive layer 100. The second surface includes a portion covered with the adhesive layer 100 and a portion located in the gap GP. The gap GP is formed between the inner wall surface 100T of the adhesive layer 100 and the seed layer 30a. The adhesive layer 100 is formed of a nitrogen-based organic compound. The nitrogen-based organic compound forming the adhesive layer 100 is, for example, a tetrazole compound. The nitrogen-based organic compound may be a tetrazole compound disclosed in JP 2015-54987 A. The adhesive layer 100 covers the second surface of the first conductor layer 10. Furthermore, the adhesive layer 100 covers the third surface 6 exposed from the first conductor layer 10 .

[0014] The resin insulating layer 20 is formed on the third surface 6 of the insulating layer 4 and on the first conductor layer 10. The resin insulating layer 20 is formed between the first conductor layer 10 and the third surface 6 via an adhesive layer 100. The resin insulating layer 20 has a first surface 22 (upper surface in the figure) and a second surface 24 (lower surface in the figure) opposite the first surface 22. The first conductor layer 10 is embedded inside the second surface 24 of the resin insulating layer 20. The second surface 24 of the resin insulating layer 20 faces the first conductor layer 10 through a portion that contacts the upper surface and side surface of the first conductor layer 10 in the figure. The resin insulating layer 20 includes a resin 80 and a large number of inorganic particles 90. The resin 80 may be, for example, a thermosetting resin or a photocurable resin. The resin 80 may be, for example, an epoxy resin. The large number of inorganic particles 90 are dispersed in the resin 80. The inorganic particles 90 may be, for example, silica or alumina. The inorganic particles 90 have an average particle diameter of, for example, 0.5 μm and a particle diameter range of 0.1 μm to 5.0 μm. The resin insulation layer 20 has a via hole 26 as a through hole penetrating in the thickness direction. The inner wall surface 27 of the via hole 26 is formed of the resin 80 and the inorganic particles 90.

[0015] As shown in FIG. 2A, first surface 22 of resin insulation layer 20 is formed only from resin 80. Inorganic particles 90 are not exposed from first surface 22. Specifically, first surface 22 does not include the surfaces of inorganic particles 90. No irregularities are formed on first surface 22 of resin insulation layer 20. First surface 22 is not roughened. First surface 22 is formed smoothly. The arithmetic mean roughness (Ra) of first surface 22 is, for example, 0.02 μm or more and 0.06 μm or less.

[0016] On the other hand, as shown in FIG. 2B, a part of the inorganic particles 90 is exposed on the inner wall surface 27 of the via hole 26. The inner wall surface 27 of the via hole 26 includes the surfaces of the inorganic particles 90. The inner wall surface 27 of the via hole 26 has irregularities. The inner wall surface 27 of the via hole 26 is formed by the exposed surface of the resin 80 and the exposed surface of the inorganic particles 90. The inner wall surface 27 of the via hole 26 is a non-roughened surface and is not roughened. The arithmetic mean roughness (Ra) of the inner wall surface 27 of the via hole 26 is, for example, in the range of 0.03 μm or more and 0.10 μm or less. While the inorganic particles 90 are exposed on the inner wall surface 27 of the via hole 26, the inorganic particles 90 are not exposed from the first surface 22 of the resin insulating layer 20. Therefore, the arithmetic mean roughness (Ra) of the inner wall surface 27 of the via hole 26 is greater than the arithmetic mean roughness (Ra) of the first surface 22 while satisfying the above range.

[0017] The thickness of the resin insulating layer 20 is at least twice the thickness of the second conductor layer 30. The thickness T of the resin insulating layer 20 is the distance between the first surface 22 and the upper surface of the first conductor layer .

[0018] 2B, the inner wall surface 27 of the via hole 26 is inclined. The angle (inclination angle) θ1 between the upper surface of the pad 14 and the inner wall surface 27 is, for example, not less than 70° and not more than 85°. The upper surface of the pad 14 is included in the upper surface of the first conductor layer 10. The angle (inclination angle) θ2 between the first surface (upper surface) 22 of the resin insulating layer 20 and the inner wall surface 27 is, for example, not less than 95° and not more than 110°.

[0019] As shown in FIG. 2B, a part of the first conductor layer 10 is covered with an adhesive layer 100. In the pad 14, the adhesive layer 100 is formed so as to surround the periphery of the via conductor 40. The adhesive layer 100 has an opening 100H. The opening 100H is connected to the via hole 26. The first surface of the first conductor layer 10 is exposed from the opening 100H. In the adhesive layer 100, an inner wall surface 100T on the side of the center of the via hole 26 (see center line CL) is the inner wall surface of the opening 100H. It is located outside the end 27T of the inner wall surface 27 of the via hole 26 as viewed from the center of the via hole 26. The end 27T of the inner wall surface 27 of the via hole 26 is on the first conductor layer 10 side on the inner wall surface 27 of the via hole 26 and is the end on the center side of the via hole 26. The first conductor layer 10 side is a position that is 20% or less of the thickness T of the resin insulating layer 20 from the upper surface of the first conductor layer 10. In the following, the terms "inner side" and "outer side" refer to the inner side (the side relatively closer to the center line CL) and the outer side (the side farther from the center line CL) as viewed from the center line CL. Note that these terms "inner side" and "outer side" may be defined in terms of the distance from the normal to the third surface 6 along the surface of the third surface 6 within the via hole 26, rather than the center line CL.

[0020] The resin insulating layer 20 has an inclined surface 29. The inclined surface 29 is located inside the inner wall surface 100T of the adhesive layer 100, and is a surface that is inclined in a direction away from the pad 14 as it goes inward. The inclined surface 29 is a portion of the via hole 26 on the first conductor layer 10 side. The inclined surface 29 widens toward the first conductor layer 10. The inner diameter of the inclined surface 29 gradually increases toward the first conductor layer 10. In the example shown in FIG. 2B, the inner end of the inclined surface 29 coincides with the end 27T of the inner wall surface 27 of the via hole 26.

[0021] In the cross section shown in Fig. 2B, the distance from end 27T of inner wall surface 27 of via hole 26 to inner wall surface 100T of adhesive layer 100 is defined as distance L1. In the example shown in Fig. 2B, distance L1 is, for example, 0.1 µm or more and 1 µm or less.

[0022] A portion of the seed layer 30a penetrates from the inside between the upper surface of the pad 14 and the inclined surface 29 of the resin insulating layer 20. The tip of the portion of the seed layer 30a that penetrates between the upper surface of the pad 14 and the inclined surface 29 of the resin insulating layer 20 is the outer edge 31 of the seed layer 30a. The outer edge 31 of the seed layer 30a is separated from the inner wall surface 100T of the adhesive layer 100. A gap GP is formed between the outer edge 31 of the seed layer 30a and the inner wall surface 100T of the adhesive layer 100.

[0023] In the cross section shown in Fig. 2B, the distance from the outer edge 31 of the seed layer 30a to the inner wall surface 100T of the adhesive layer 100 is defined as a distance L2. The outer edge 31 of the seed layer 30a is an end of the seed layer 30a at a portion that contacts the pad 14. In the example shown in Fig. 2B, for example, the distance L2 is equal to or less than the above-mentioned distance L1 and is equal to or less than 2 µm.

[0024] As shown in FIG. 1, the second conductor layer 30 is formed on the first surface 22 of the resin insulating layer 20. The second conductor layer 30 includes a first signal wiring 32, a second signal wiring 34, and a land 36. The second conductor layer 30 may also include a conductor circuit other than the first signal wiring 32, the second signal wiring 34, and the land 36. The first signal wiring 32 and the second signal wiring 34 form a pair wiring. The second conductor layer 30 is mainly formed of copper. The second conductor layer 30 is formed of a seed layer 30a on the first surface 22 and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a is formed of a first seed layer 31a on the first surface 22 and a second seed layer 31b on the first seed layer 31a. The first seed layer 31a is formed of an alloy (copper alloy) containing copper, silicon, and aluminum. The second seed layer 31b is formed of copper. The electrolytic plating layer 30b is formed of copper. The first seed layer 31a is in contact with the first surface 22. The second seed layer 31b is bonded to the electrolytic plating layer 30b. The surface of the second conductor layer 30 that faces the first surface 22 of the resin insulating layer 20 is formed along the surface shape of the first surface 22. The second conductor layer 30 does not extend into the inside of the first surface 22 of the resin insulating layer 20.

[0025] The via conductor 40 is formed in the via hole 26. The via conductor 40 connects the first conductor layer 10 and the second conductor layer 30 adjacent to each other in the stacking direction. The stacking direction is the direction in which the layers are stacked, and is the same as the thickness direction of each layer. In this embodiment, the stacking direction is the same as the up-down direction. In FIG. 1, the via conductor 40 connects the pad 14 and the land 36. The via conductor 40 is formed of a seed layer 30a and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a forming the via conductor 40 and the seed layer 30a forming the second conductor layer 30 are common. The first seed layer 31a is in contact with the inner wall surface 27.

[0026] A coating layer 35 is formed on the surfaces of the resin insulating layer 20 and the second conductor layer 30. The coating layer 35 enhances adhesion between the resin insulating layer 20 and the second conductor layer 30 and other layers laminated on the resin insulating layer 20 and the second conductor layer 30. The coating layer 35 is not necessary.

[0027] [Method of manufacturing printed wiring board 2 according to embodiment]

[0028] 3A to 3J show a method for manufacturing a printed wiring board 2 of an embodiment. Fig. 3A to Fig. 3J are cross-sectional views. Fig. 3A shows an insulating layer 4 and a first conductor layer 10. The first conductor layer 10 is formed on a third surface 6 of the insulating layer 4. The first conductor layer 10 is formed by a semi-additive method.

[0029] As shown in FIG. 3B, an adhesive layer 100 is formed on the surface of the first conductor layer 10. The surface of the first conductor layer 10 is adjusted to have an arithmetic mean roughness (Ra) in the range of 0.02 μm to 0.5 μm at the same time as the seed layer 30a is removed by an etching solution. The first conductor layer 10 having the rough surface can reduce transmission loss. The adhesive layer 100 covers the surface of the first conductor layer 10. Furthermore, the adhesive layer 100 covers the third surface 6 exposed from the first conductor layer 10. The first conductor layer 10 is formed by a semi-additive method. The adhesive layer 100 is formed by immersing the insulating layer 4 and the first conductor layer 10 in a chemical solution containing a nitrogen-based organic compound. Alternatively, the adhesive layer 100 is formed by applying the above-mentioned chemical solution on the insulating layer 4 and the first conductor layer 10.

[0030] As shown in FIG. 3C, a resin insulating layer 20 and a protective film 50 are formed on an adhesive layer 100. The second surface 24 of the resin insulating layer 20 faces the third surface 6 of the insulating layer 4. The protective film 50 is formed on a first surface 22 of the resin insulating layer 20. The resin insulating layer 20 has a resin 80 and inorganic particles 90. The inorganic particles 90 are embedded in the resin 80. The first surface 22 of the resin insulating layer 20 is formed only by the resin 80. The inorganic particles 90 are not exposed from the first surface 22. The first surface 22 does not include the surfaces of the inorganic particles 90. No irregularities are formed on the first surface 22 of the resin insulating layer 20.

[0031] The protective film 50 completely covers the first surface 22 of the resin insulating layer 20. The protective film 50 is, for example, a film made of polyethylene terephthalate (PET). A layer made of a release agent is formed between the protective film 50 and the resin insulating layer 20.

[0032] As shown in Fig. 3D, laser light L is irradiated from above the protective film 50. The laser light L penetrates the protective film 50 and the resin insulating layer 20 at the same time. A via hole 26 for a via conductor is formed, which reaches the adhesive layer 100 that covers the pad 14. The laser light L is, for example, a UV laser light or a CO2 laser light. The via hole 26 has an inner wall surface 27.

[0033] The adhesive layer 100 is not completely removed by the laser light L. An opening 100H is formed in the adhesive layer 100. The opening 100H is connected to the via hole 26. The adhesive layer 100 covering the pad 14 is exposed by the via hole 26 and the opening 100H. When the via hole 26 is formed, the first surface 22 of the resin insulating layer 20 is covered with the protective film 50. Therefore, even if the resin scatters when the via hole 26 is formed, the resin is prevented from adhering to the first surface 22. The inner wall surface 27 of the via hole 26 after the laser light irradiation is formed of the resin 80 and the inorganic particles 90 protruding from the resin 80. An inclined surface 29 is formed in the resin insulating layer 20. The inclined surface 29 is formed in a shape that expands toward the first conductor layer 10. At the inclined surface 29, the resin insulating layer 20 is separated from the pad 14.

[0034] As shown in FIG. 3E, the inside of the via hole 26 is cleaned. By cleaning the inside of the via hole 26, the adhesive layer 100 exposed from the via hole 26 is removed. The pad 14 is exposed from the via hole 26. Resin residue generated during the formation of the via hole 26 is removed. The inside of the via hole 26 is cleaned by plasma. That is, the cleaning is performed by a dry process. The gas type of the dry process is a mixed gas of a halogen-based gas (fluorine-based gas, chlorine-based gas, etc.) and O2 gas, or a single gas of a halogen-based gas (fluorine-based gas, chlorine-based gas, etc.) or O2 gas. The cleaning includes a desmear process. The adhesive layer 100 formed between the second surface 24 of the resin insulating layer 20 and the pad 14 is not completely removed. Therefore, the adhesive layer 100 remains between the second surface 24 of the resin insulating layer 20 and the pad 14. The inner wall surface 100T of the adhesive layer 100 is located at a distance L1 (see FIG. 2B) from the end 27T of the inner wall surface 27 of the via hole 26.

[0035] Resin 80 is selectively removed by the plasma. Plasma removes resin 80 faster than inorganic particles 90. By cleaning the inside of via hole 26, inorganic particles 90 are exposed on inner wall surface 27 of via hole 26 (FIG. 3E). Inner wall surface 27 of via hole 26 includes the surfaces of inorganic particles 90. Unevenness is formed on inner wall surface 27 of via hole 26. Meanwhile, first surface 22 of resin insulation layer 20 is covered with protective film 50. First surface 22 is not affected by plasma. First surface 22 is formed only of resin 80. Inorganic particles 90 are not exposed from first surface 22. First surface 22 does not include the surfaces of inorganic particles 90. No unevenness is formed on first surface 22 of resin insulation layer 20. First surface 22 is formed smoothly.

[0036] 3F, after the inside of the via hole 26 is cleaned, the protective film 50 is removed from the resin insulating layer 20. After the protective film 50 is removed, the first surface 22 of the resin insulating layer 20 is not roughened. The first surface 22 is formed to be smooth. The arithmetic mean roughness (Ra) of the first surface 22 is, for example, not less than 0.02 μm and not more than 0.06 μm.

[0037] As shown in FIG. 3G, a seed layer 30a is formed on the first surface 22 and the inner wall surface 27 of the resin insulating layer 20. The seed layer 30a is formed by sputtering. The seed layer 30a is a sputtered film. The seed layer 30a is formed by a dry process. A first seed layer 31a is formed on the first surface 22 by sputtering. At the same time, a first seed layer 31a is formed on the inner wall surface 27 exposed from the via hole 26 and on the pad 14 by sputtering. Thereafter, a second seed layer 31b is formed on the first seed layer 31a by sputtering. The first seed layer 31a and the second seed layer 31b are made of a combination of copper alloys of different materials, or a combination of a copper alloy and copper. The first seed layer 31a is made of a copper alloy. The combination of a copper alloy and the resin insulating layer 20 has higher adhesion than the combination of copper and the resin insulating layer 20. The second seed layer 31b is made of a copper alloy or copper. The copper alloy of the first seed layer 31a and the second seed layer 31b is formed with a copper content of 90% or more of the total weight. The higher the copper content, the lower the electrical resistance, and therefore the more reliable the connection. The seed layer 30a is also formed on the upper surface of the pad 14 exposed from the via hole 26 and on the inner wall surface 27 of the via hole 26. A part of the material of the seed layer 30a penetrates between the inclined surface 29 of the resin insulating layer 20 and the upper surface of the pad 14. The first seed layer 31a is formed of an alloy containing copper, silicon, and aluminum. The second seed layer 31b is formed of copper.

[0038] As shown in FIG. 3H, a plating resist 60 is formed on the seed layer 30a. Since the first surface 22 of the resin insulating layer 20 is not roughened, the seed layer 30a can be formed with a uniform thickness on a low roughness surface. The plating resist 60 can adhere closely to the seed layer 30a without any gaps, which prevents the plating resist 60 from peeling off and suppresses short circuits between wirings when electrolytic plating is formed. The plating resist 60 has openings for forming the first signal wiring 32, the second signal wiring 34, and the land 36 (see FIG. 1).

[0039] As shown in FIG. 3I, an electrolytic plating layer 30b is formed on the seed layer 30a exposed from the plating resist 60. The electrolytic plating layer 30b is made of copper. The electrolytic plating layer 30b fills the via hole 26. The seed layer 30a and the electrolytic plating layer 30b on the first surface 22 form a first signal wiring 32, a second signal wiring 34, and a land 36. The second conductor layer 30 is formed. The seed layer 30a and the electrolytic plating layer 30b in the via hole 26 form a via conductor 40. The second conductor layer 30 and the via conductor 40 are formed simultaneously. The via conductor 40 connects the pad 14 and the land 36. The first signal wiring 32 and the second signal wiring 34 form a pair wiring.

[0040] As shown in FIG. 3J, the plating resist 60 is removed. The seed layer 30a exposed from the electrolytic plating layer 30b is removed. The surface of the second conductor layer 30 has the seed layer 30a removed with an etching solution, and the arithmetic mean roughness (Ra) is adjusted to a range of 0.02 μm to 0.5 μm. The first conductor layer 10 having a rough surface can reduce transmission loss. The second conductor layer 30 and the via conductors 40 are formed simultaneously.

[0041] Thereafter, an O2 ashing process is performed as necessary on the first surface 22 of the resin insulating layer 20. In the O2 ashing process, the first surface 22 of the resin insulating layer 20 is irradiated with O2 plasma.

[0042] Thereafter, a chemical conversion treatment is further performed on the second conductor layer 30. For example, a coating layer 35 is formed on the surfaces of the resin insulating layer 20 and the second conductor layer 30. A printed wiring board 2 of the embodiment (see FIG. 1) is obtained.

[0043] In the printed wiring board 2 of the embodiment (see FIGS. 1 to 2B), even after cleaning including a desmear treatment in the via hole 26, the adhesive layer 100 remains between the second surface 24 of the resin insulating layer 20 and the pad 14. The adhesion between the second surface 24 of the resin insulating layer 20 and the pad 14 can be ensured. In a structure in which the resin insulating layer 20 is formed on the first conductor layer 10, peeling of the resin insulating layer 20 from the first conductor layer 10 can be suppressed.

[0044] An inner wall surface 100T of the adhesive layer 100 is located outside an end 27T of an inner wall surface 27 of the via hole 26 when viewed from the center of the via hole 26 (see center line CL). A gap GP is formed between an outer edge 31 of the seed layer 30a and the inner wall surface 100T of the adhesive layer 100. When a force in the lateral direction, for example, acts on the via conductor 40, the gap GP allows the via conductor 40 to move in the lateral direction relative to the pad 14. Stress on the bottom 40B of the via conductor 40 is relieved.

[0045] The via conductor 40 includes a seed layer 30a. The seed layer 30a is in contact with the inner wall surface 27 of the via hole 26. The adhesion of the via conductor 40 to the inner wall surface 27 of the via hole 26 is improved. The outer edge 31 of the seed layer 30a is separated from the inner wall surface 100T of the adhesive layer 100. A structure in which a gap GP is formed between the outer edge 31 of the seed layer 30a and the inner wall surface 100T of the adhesive layer 100 is realized.

[0046] The distance L2 from the outer edge 31 of the seed layer 30a to the inner wall surface 100T of the adhesive layer 100 is 2 μm or less. A part of the seed layer 30a penetrates from the inside between the upper surface of the pad 14 and the inclined surface 29 of the resin insulating layer 20. That is, the part of the seed layer 30a that penetrates between the upper surface of the pad 14 and the inclined surface 29 of the resin insulating layer 20 is in contact with the inclined surface 29. The movement of the via conductor 40 in the direction away from the pad 14 (upward in FIG. 2B) can be prevented. The contact state between the via conductor 40 and the pad 14 can be maintained.

[0047] In the printed wiring board 2 of the embodiment (see FIG. 1), the first surface 22 of the resin insulating layer 20 is formed of the resin 80. The inorganic particles 90 are not exposed on the first surface 22. The first surface 22 is not uneven. The standard deviation of the relative dielectric constant of the resin insulating layer 20 in the vicinity of the first surface 22 is suppressed from increasing. The relative dielectric constant of the first surface 22 does not vary significantly depending on the location. Even if the first signal wiring 32 and the second signal wiring 34 are in contact with the first surface 22, the difference in the propagation speed of the electric signal between the first signal wiring 32 and the second signal wiring 34 can be reduced. Therefore, the printed wiring board 2 of the embodiment suppresses noise. Even if a logic IC is mounted on the printed wiring board 2 of the embodiment, the data transmitted by the first signal wiring 32 and the data transmitted by the second signal wiring reach the logic IC with almost no delay. Malfunction of the logic IC can be suppressed. Even if the length of the first signal wiring 32 and the length of the second signal wiring 34 are 5 mm or more, the difference in the propagation speed between the two can be reduced. Even if the length of the first signal wiring 32 and the length of the second signal wiring 34 are 10 mm or more and 20 mm or less, malfunction of the logic IC can be suppressed. A high-quality printed wiring board 2 is provided.

[0048] In the printed wiring board 2 of the embodiment, the seed layer 30a is formed by sputtering (see FIG. 3G). The particles forming the seed layer 30a collide with the first surface 22 perpendicularly. Therefore, the adhesion strength between the first surface 22 and the seed layer 30a is high. On the other hand, the particles forming the seed layer 30a collide with the inner wall surface 27 of the via hole 26 obliquely. However, the inner wall surface 27 of the via hole 26 has irregularities. Therefore, the adhesion strength between the seed layer 30a and the inner wall surface 27 of the via hole 26 is high. Even if the first surface 22 does not have irregularities and the inner wall surface 27 of the via hole 26 has irregularities, the difference in adhesion strength between the second conductor layer 30 and the first surface 22 and the adhesion strength between the via conductor 40 and the inner wall surface 27 of the via hole 26 can be reduced. Stress is less likely to concentrate at the interface between the second conductor layer 30 and the first surface 22. Stress is less likely to concentrate at the interface between the via conductor 40 and the inner wall surface 27 of the via hole 26. Even if printed wiring board 2 is subjected to a heat cycle, via conductor 40 is unlikely to peel off from resin insulating layer 20. Thus, printed wiring board 2 having high quality is provided.

[0049] In the technology of the present disclosure, the first seed layer 31a of the seed layer 30a is formed of copper and a second element. The second element is selected from silicon, aluminum, titanium, nickel, chromium, carbon, oxygen, tin, calcium, magnesium, iron, molybdenum, and silver. The first seed layer 31a is formed of an alloy containing copper. The second seed layer 31b is formed of copper. The amount (atomic weight %) of copper forming the second seed layer 31b is 99.9% or more. Preferably, it is 99.95% or more.

[0050] The first seed layer 31a of the seed layer 30a may be formed of any one of metals including silicon, aluminum, titanium, nickel, chromium, carbon, oxygen, tin, calcium, magnesium, iron, molybdenum, and silver.

[0051] In the printed wiring board 2 of the technique of the present disclosure, the resin insulation layer 20 contains the resin 80 and the inorganic particles 90, but may also contain a fiber reinforcement material. As the fiber reinforcement material, for example, a glass cloth, a glass nonwoven fabric, or an aramid nonwoven fabric may be used.

[0052] In printed wiring board 2 according to the technique of the present disclosure, there is one resin insulating layer, but two or more layers may be laminated.

[0053] The printed wiring board of the technology of the present disclosure is not limited to the structure illustrated in each drawing, and the structure, shape, and material illustrated in this specification. As described above, the printed wiring board of the embodiment may have any laminated structure. For example, the wiring board of the embodiment may be a coreless substrate that does not include a core substrate. The printed wiring board of the embodiment may include any number of conductor layers and insulating layers.

[0054] The method for manufacturing a printed wiring board according to the technology of the present disclosure is not limited to the method described with reference to the drawings. For example, each insulating layer may be formed using a resin in any form, not limited to a film-like resin. In the method for manufacturing a printed wiring board according to the embodiment, any process may be added in addition to the above-described processes, or some of the above-described processes may be omitted. [Explanation of symbols]

[0055] 2. Printed Wiring Board 4. Insulation Layer 6 Third side 8 Fourth side 10 First Conductor Layer 10a Seed layer 10b Electrolytic plating layer 12 Signal wiring 14 Pads 20 Resin insulation layer 22 Front page 24 Second side 26 Via holes 27 Inner wall surface 27T End of inner wall 29 Slope 30 Second Conductor Layer 30a Seed layer 30b Electrolytic plating layer 31a First seed layer 31b Second seed layer 32 First signal wiring 34 Second signal wiring 35 Coating layer 36 Rand 40 Via conductor 40B Bottom of via conductor 50 Protective film 60 Resist 80 Resin 90 Inorganic particles 100 adhesive layer 100T End of adhesive layer

Claims

1. A first conductor layer; a resin insulating layer having a first surface and a second surface opposite to the first surface, the second surface being formed on the first conductor layer so as to face the first conductor layer, the resin insulating layer having a via hole exposing the first conductor layer; a second conductor layer formed on the first surface of the resin insulating layer; a via conductor formed in the via hole and connecting the first conductor layer and the second conductor layer; an adhesive layer formed on the first conductor layer and between the resin insulating layer and the first conductor layer, the adhesive layer adhering the resin insulating layer to the first conductor layer and having an opening communicating with the via hole and exposing the first conductor layer; a seed layer that forms a part of the via conductor, that is in contact with an inner wall surface of the via hole and that is spaced apart from an inner wall surface of the opening; A printed wiring board having an inner wall surface of the opening is located outside the inner wall surface of the via hole when viewed from the center of the via hole; Printed wiring board.

2. 2. The printed wiring board according to claim 1, There is a gap between the outer edge of the seed layer and the inner wall surface of the opening.

3. 2. The printed wiring board according to claim 1, The distance from the outer edge of the seed layer to the inner wall surface of the opening is 2 μm or less.

4. 2. The printed wiring board according to claim 1, The seed layer is a sputtered film.

5. 2. The printed wiring board according to claim 1, The arithmetic mean roughness (Ra) of the surface of the first conductor layer is 0.02 μm or more and 0.5 μm or less.

6. 2. The printed wiring board according to claim 1, The via hole widens toward the first conductor layer at a portion on the first conductor layer side.

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