Printed wiring board

Abstract

To provide a printed wiring board having a high quality.SOLUTION: A printed wiring board has: a mounting conductor layer having a first electrode and a second electrode; a connection conductor layer which is located under the mounting conductor layer and has connection wiring for electrically connecting the first electrode to the second electrode; a second resin insulation layer which is disposed between the mounting conductor layer and the connection conductor layer and has a plurality of openings including a first opening and a second opening; a first resin insulation layer having a first surface and a second surface opposite to the first surface and formed under the connection conductor layer so that the connection conductor layer may be formed on the first surface; a first connection via conductor; and a second connection via conductor. The first resin insulation layer is made of inorganic particles and resin. The inorganic particles include: first inorganic particles partially embedded in the resin; and second inorganic particles embedded in the resin. The first inorganic particles are each made up of: a first portion protruding from the resin; and a second portion embedded in the resin. The first surface is made up of: an upper surface of the resin; and an exposed surface of the first portion which is exposed from the upper surface.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a printed wiring board. [Background technology]

[0002] Patent Document 1 discloses a printed wiring board that uses a mixture of a thermosetting resin and an inorganic filler as an interlayer insulating layer. In Patent Document 1, the surface of the interlayer insulating layer and the side surface of the via are formed as rough surfaces having recesses. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-19061 Summary of the Invention

[0004] [Problem of Patent Document 1] When a seed layer is formed by sputtering on an interlayer insulating layer formed using the technique of Patent Document 1, it is considered difficult to form a continuous seed layer. For example, it is considered that the thickness of the sputtering film is increased in order to form a continuous film. However, if the seed layer is thick, it is considered that the amount of etching required to remove the seed layer is large. It is considered difficult to form fine wiring. [Means for solving the problem]

[0005] The printed wiring board of the present invention comprises a mounting conductor layer having a first electrode for mounting a first electronic component and a second electrode for mounting a second electronic component, a connection conductor layer located under the mounting conductor layer and having connection wiring electrically connecting the first electrode and the second electrode, a second resin insulating layer arranged between the mounting conductor layer and the connection conductor layer and having a plurality of openings including a first opening and a second opening, a first resin insulating layer having a first surface and a second surface opposite to the first surface, and formed under the connection conductor layer so that the connection conductor layer is formed on the first surface, a first connection via conductor formed in the first opening and electrically connecting the first electrode and the connection wiring, and a second connection via conductor formed in the second opening and electrically connecting the second electrode and the connection wiring. The first resin insulation layer is formed of inorganic particles and resin, the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles embedded in the resin, the first inorganic particles are formed of a first portion protruding from the resin and a second portion embedded in the resin, and the first surface is formed by an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface.

[0006] In the printed wiring board of the embodiment of the present invention, almost no recesses are formed on the first surface of the first resin insulating layer. Therefore, when a seed layer is formed on the first resin insulating layer by sputtering, the embodiment can form a continuous seed layer even if the thickness of the sputtering film is thin. As a result, when the seed layer is removed, the embodiment can reduce the amount of etching. The embodiment can form fine connection wiring. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view illustrating a printed wiring board according to an embodiment. [Diagram 2] Cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III of FIG. 1. [Figure 4] FIG. 2 is an enlarged cross-sectional view illustrating a portion of the printed wiring board according to the embodiment. [Diagram 5]FIG. 2 is an enlarged cross-sectional view illustrating a portion of the printed wiring board according to the embodiment. [Figure 6] FIG. 2 is an enlarged cross-sectional view illustrating a portion of the printed wiring board according to the embodiment. [Figure 7] FIG. 11 is a cross-sectional view illustrating a printed wiring board according to a modified example of the embodiment. [Figure 8A] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8B] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8C] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8D] 1A to 1C are enlarged cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8E] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8F] 1A to 1C are enlarged cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8G] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8H] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8I] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 9] FIG. 1 is a cross-sectional view showing a schematic diagram of a printed wiring board having three internal conductor layers for connection. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] [Embodiment] FIG. 1 is a plan view showing a printed wiring board 2 of an embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. FIGS. 4 to 6 are enlarged cross-sectional views showing a part of the printed wiring board 2 of an embodiment. As shown in FIGS. 1 and 2, the printed wiring board 2 has an upper surface 2a and a lower surface 2b opposite to the upper surface 2a. The printed wiring board 2 has a first mounting area A1 for mounting a first electronic component E1 and a second mounting area A2 for mounting a second electronic component E2. The first mounting area A1 is located directly below the first electronic component E1. The second mounting area A2 is located directly below the second electronic component E2. The circles shown by solid lines in FIG. 1 indicate bumps (metal posts) 241, 242, 243, and 244 for mounting electronic components. The wiring drawn by dotted lines indicates the connection wiring 36 embedded in the printed wiring board 2. Examples of the first electronic component E1 and the second electronic component E2 are electronic components such as logic ICs and memories.

[0009] As shown in Figs. 1 to 3, the printed wiring board 2 has a conductor layer 10, a resin insulating layer (first resin insulating layer) 20, a connecting conductor layer 30, via conductors 41, 42, 141, 142, 143, 144, a resin insulating layer (second resin insulating layer) 120, a mounting conductor layer 130, an insulating layer 220, and bumps 241, 242, 243, 244. As shown in Fig. 2, the via conductors 41, 141, 143 are disposed directly below the first mounting area A1. The bumps 241, 243 are disposed directly above the first mounting area A1. The via conductors 42, 142, 144 are disposed directly below the second mounting area A2. The bumps 242, 244 are disposed directly above the second mounting area A2.

[0010] The connection conductor layer 30 includes a connection wiring 36. Data is transmitted from the first electronic component E1 to the second electronic component E2 via the connection wiring 36. The connection wiring 36 is a part of a path for sending data from the first electronic component E1 to the second electronic component E2. The mounting conductor layer 130 includes electrodes 131, 132, 133, and 134. A bump 241, an electrode 131, and a via conductor 141 are arranged in a path (first path) between the first electronic component E1 and the connection wiring 36. The first path is located directly below the first electronic component E1. A bump 242, an electrode 132, and a via conductor 142 are arranged in a path (second path) between the second electronic component E2 and the connection wiring 36. The second path is located directly below the second electronic component E2. The bump 241, the electrode 131, the via conductor 141, the bump 242, the electrode 132, and the via conductor 142 are also part of the path. The bumps 241 and 242 can be called connection bumps (connection metal posts). The connection bump 241 located directly under the first electronic component E1 is a first connection bump (first connection metal post), and the connection bump 242 located directly under the second electronic component E2 is a second connection bump (second connection metal post). The electrodes 131 and 132 can be called connection electrodes. The connection electrode 131 located directly under the first electronic component E1 is a first connection electrode, and the connection electrode 132 located directly under the second electronic component E2 is a second connection electrode. The via conductors 141 and 142 can be called connection via conductors. The connection via conductor 141 located directly under the first electronic component E1 is a first connection via conductor, and the connection via conductor 142 located directly under the second electronic component E2 is a second connection via conductor. The first connection bump may be called a first bump (first metal post). The first connection electrode may be called a first electrode. The first connection via conductor may be called a first via conductor. The second connection bump may be called a second bump (second metal post). The second connection electrode may be called a second electrode. The second connection via conductor may be called a second via conductor. The first bump, the first electrode, and the first via conductor located directly below the first electronic component E1 and electrically connected to the connection wiring 36 form a first path. The second bump, the second electrode, and the second via conductor located directly below the second electronic component E2 and electrically connected to the connection wiring 36 form a second path.

[0011] The via conductors 41, 42, 143, 144, the electrodes 133, 134, and the bumps 243, 244 do not form a path. These via conductors 41, 42, 143, 144, the electrodes 133, 134, and the bumps 243, 244 are electrically connected to a power line or a ground line in the electronic component. These via conductors 41, 42, 143, 144, the electrodes 133, 134, and the bumps 243, 244 are independent of the connection wiring 36. These via conductors 41, 42, 143, 144, the electrodes 133, 134, and the bumps 243, 244 are not electrically connected to the connection wiring 36.

[0012] 2, the conductor layer 10 includes pads 12 and 14. The pads 12 and 14 are exposed from the lower surface 2b of the printed wiring board 2. The pads 12 and 14 are used for connecting to another printed wiring board or electronic components. The conductor layer 10 is mainly formed of copper.

[0013] The resin insulating layer (first resin insulating layer) 20 is formed on the conductor layer 10. The resin insulating layer 20 has a first surface 20a and a second surface 20b opposite to the first surface 20a. The second surface 20b of the resin insulating layer 20 forms the lower surface 2b of the printed wiring board 2. The second surface 20b of the resin insulating layer 20 faces the conductor layer 10. The resin insulating layer 20 has openings (openings for via conductors) 21 and 22 that expose the conductor layer 10. The opening 21 is located directly below the first mounting area A1 and exposes the pad 12. The opening 21 extends from the first surface 20a of the resin insulating layer 20 to the pad 12. The opening 22 is located directly below the second mounting area A2 and exposes the pad 14. The opening 22 extends from the first surface 20a of the resin insulating layer 20 to the pad 14. The resin insulating layer 20 is formed of a resin 80 and a large number of inorganic particles 90 dispersed in the resin 80. The resin 80 is an epoxy resin. Examples of the resin are a thermosetting resin and a photosetting resin. The inorganic particles 90 are glass particles. The inorganic particles 90 may be alumina.

[0014] As shown in Figs. 2 to 4, the inorganic particles 90 include first inorganic particles 91 partially embedded in the resin 80 and second inorganic particles 92 embedded in the resin 80. The second inorganic particles are completely embedded in the resin 80. The first inorganic particles 91 and the second inorganic particles 92 are spherical in shape. As shown in Fig. 4, the first inorganic particles 91 are formed of a first portion 91a protruding from the resin 80 and a second portion 91b embedded in the resin 80. The first surface 20a of the resin insulation layer 20 is formed by the upper surface of the resin 80 and an exposed surface of the first portion 91a exposed from the upper surface of the resin 80.

[0015] The ratio R of the volume of the first portion 91a to the volume of the first inorganic particles 91 (volume of the first portion 91a / volume of the first inorganic particles 91) is greater than 0 and equal to or less than 0.4. The ratio R is preferably equal to or less than 0.2. The ratio R is more preferably equal to or less than 0.1. The ratio R is most preferably equal to or less than 0.05. When the first portion 91a protrudes from the resin 80, the first surface 20a of the resin insulating layer 20 has slight irregularities. However, the upper surface of the resin 80 is not roughened. The upper surface of the resin 80 forming the first surface 20a of the resin insulating layer 20 is almost flat. The upper surface of the resin 80 has almost no recesses. Therefore, the first surface 20a has almost no recesses. The arithmetic mean roughness (Ra) of the first surface 20a is less than 0.08 μm. The roughness Ra of the first surface 20a is preferably equal to or less than 0.05 μm. It is more preferably equal to or less than 0.03 μm. The arithmetic mean roughness (Ra) of the upper surface of resin 80 forming first surface 20a of resin insulation layer 20 is less than 0.08 μm. The roughness Ra of the upper surface of resin 80 is preferably 0.05 μm or less. The roughness Ra of the upper surface of resin 80 is more preferably 0.03 μm or less.

[0016] As shown in Figures 2 and 5, the inorganic particles 90 further include third inorganic particles 93 that form the inner wall surface of the opening (opening for a via conductor). The shape of the third inorganic particles 93 is obtained by cutting a sphere with a plane. The shape of the third inorganic particles 93 is obtained by cutting the second inorganic particles 92 with a plane. The shape of the third inorganic particles 93 is different from the shape of the second inorganic particles 92. The shape of the third inorganic particles 93 is different from the shape of the first inorganic particles 91. The shape of the first inorganic particles 91 is similar to the shape of the second inorganic particles 92.

[0017] As shown in FIG. 5, inner wall surface 23 of an opening (opening for a via conductor) is formed of resin 80 and third inorganic particles 93. FIG. 5 shows opening 21 as a representative example of an opening. Third inorganic particles 93 have flat portion 93a. Flat portion 93a forms inner wall surface 23. Inner wall surface 23 is formed of resin 80 and flat portion 93a. Flat portion 93a and the surface of resin 80 forming inner wall surface 23 form a substantially common surface. No irregularities are formed on resin 80 forming inner wall surface 23. The surface of resin 80 forming inner wall surface 23 is smooth. No irregularities are formed on exposed surface 93b of flat portion 93a (surface forming inner wall surface 23). Exposed surface 93b of flat portion 93a is smooth. Inner wall surface 23 is formed smoothly. Arithmetic mean roughness (Ra) of inner wall surface 23 is 1.0 μm or less.

[0018] The flat portion 93a of the third inorganic particle 93 approximately coincides with a surface obtained by extending the surface 80a (the surface forming the inner wall surface 23) of the resin 80 formed around the third inorganic particle 93. The flat portion 93a depicted as a substantially straight line in Figures 2 and 5 means a flat surface. In the cross sections shown in Figures 2 and 5, the flat portion 93a is a flat surface. The flat portion 93a does not have to be a perfect flat surface. The flat portion 93a is a substantially flat surface, which is an approximately smooth surface.

[0019] 5, the inner wall surface 23 of the opening 21 is inclined. The angle (inclination angle) θ1 between the upper surface of the pad 12 and the inner wall surface 23 is not less than 70° and not more than 85°. The upper surface of the pad 12 is included in the upper surface of the conductor layer 10. The angle (inclination angle) θ2 between the first surface 20a of the resin insulating layer 20 and the inner wall surface 23 is not less than 95° and not more than 110°.

[0020] 2 and 5, the shape of the openings for via conductors, such as opening 21, is shown as a substantially inverted trapezoid. However, the shape of the actual openings for via conductors is a substantially inverted truncated cone. Therefore, the inner wall surface (side wall) of the actual openings for via conductors is a substantially curved surface. In other words, the common surface formed by flat portion 93a and resin 80 includes the inner wall surface (side wall) formed as a substantially curved surface.

[0021] The inner wall surface can have a step between the exposed surface 93b of the third inorganic particle 93 and the surface 80a of the resin 80 surrounding the third inorganic particle 93 having the exposed surface 93b. The exposed surface 93b is recessed from the surface 80a of the resin 80. Alternatively, the exposed surface 93b protrudes from the surface 80a of the resin 80. For example, a step exists between the exposed surface 93b and the surface 80a of the resin 80. The amount of the step (the distance between the exposed surface 93b and the surface 80a of the resin 80) is 5 μm or less. The amount of the step is preferably 3 μm or less. The amount of the step is more preferably 1.5 μm or less. Even if a step is formed, the step is small, so that the exposed surface 93b and the surface 80a of the resin 80 form an almost common surface.

[0022] The openings 21, 22 formed in the resin insulating layer 20 are similar to each other. The openings 21, 22 formed in the resin insulating layer 20 have similar inner wall surfaces 23, 24. The inner wall surfaces 23, 24 of each of the openings 21, 22 are formed by the surface 80a of the resin 80 and the exposed surfaces 93b of the third inorganic particles 93.

[0023] As shown in FIG. 2 and FIG. 3, the connecting conductor layer (first connecting conductor layer) 30 is formed on the first surface 20a of the resin insulating layer 20. As shown in FIG. 2, the connecting conductor layer 30 includes pads 32, 34 and a connecting wire 36. The connecting wire 36 has one end and the other end opposite to the one end. The pad 32 is a first pad 32 and is directly connected to one end of the connecting wire 36. The pad 34 is a second pad 34 and is directly connected to the other end of the connecting wire 36. The first pad 32 is formed directly below the first mounting area A1. The second pad 34 is formed directly below the second mounting area A2. As shown in FIG. 3, one connecting conductor layer 30 includes a plurality of connecting wires 36. Although not shown, one connecting conductor layer 30 includes a plurality of first pads 32 and a plurality of second pads 34. One first pad 32 and one second pad 34 are connected to both ends of each connecting wire 36. The connection wiring 36 in the connecting conductor layer 30 may include a first pad 32 and a second pad 34. The first pad 32 is included in a first path. The second pad 34 is included in a second path. The pads (first pad 32, second pad 34, etc.) directly connected to the connection wiring 36 may be called connection pads. The first pad 32 may be called a first connection pad. The second pad 34 may be called a second connection pad. The first pad 32 located directly under the first electronic component E1 and directly connected to the connection wiring 36 forms the first path. The second pad 34 located directly under the second electronic component E2 and directly connected to the connection wiring 36 forms the second path.

[0024] The connection wirings 36 are arranged approximately parallel to each other. Among the multiple connection wirings 36, the connection wiring 36 having the smallest width W1 is the smallest connection wiring 36a. The width W1 of the smallest connection wiring 36a is 1 μm or more and 3 μm or less. A space 37 is present between adjacent connection wirings 36. Among the multiple spaces 37, the space 37 having the smallest width G1 is the smallest space 37a. The width G1 of the smallest space 37a is 1 μm or more and 3 μm or less.

[0025] Of the multiple connection wirings 36, the connection wiring 36 having the largest width W2 is the largest connection wiring 36b. The width W2 of the largest connection wiring 36b is 5 μm or less. It is preferable that the width W2 of the largest connection wiring 36b is 3 μm or less. Of the multiple spaces 37, the space having the largest width G2 is the largest space 37b. The width G2 of the largest space 37b is 5 μm or less. It is preferable that the width G2 of the largest space 37b is 3 μm or less.

[0026] The width of each of the connection wires 36 is preferably 1 μm or more and 3 μm or less. The width of each of the spaces 37 is preferably 1 μm or more and 3 μm or less.

[0027] Each of the connection wires 36 has an aspect ratio (thickness / width) of 2.0 or more and 4.0 or less.

[0028] The connecting conductor layer 30 is mainly made of copper. The connecting conductor layer 30 is formed of a seed layer 30a on the first surface 20a of the resin insulating layer 20 and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a is formed by sputtering. The seed layer 30a is formed of a first layer 31a on the first surface 20a of the resin insulating layer 20 and a second layer 31b on the first layer 31a. The first layer 31a is in contact with the first surface 20a of the resin insulating layer 20. For example, the seed layer 30a and the first layer 31a are formed of a copper alloy, and the second layer 31b is formed of copper. The second layer 31b is not essential. The first layer 31a and the second layer 31b are formed by sputtering. Both are sputtering films.

[0029] The first layer 31a is made of an alloy containing copper, aluminum, and a specific metal. Examples of the specific metal are nickel, zinc, gallium, silicon, and magnesium. The alloy preferably contains one type of specific metal, two types of specific metals, or three types of specific metals. The content of aluminum in the alloy is 1.0 at% or more and 15.0 at% or less. An example of the specific metal is silicon. The content of the specific metal in the alloy is 0.5 at% or more and 10.0 at% or less. The first layer 31a may contain impurities. Examples of the impurities are oxygen and carbon. The first layer 31a may contain oxygen or carbon. The first layer 31a may contain oxygen and carbon. In the embodiment, the alloy further contains carbon. The content of carbon in the alloy is 50 ppm or less. The alloy further contains oxygen. The content of oxygen in the alloy is 100 ppm or less. The above content values ​​of each element are examples. The amount of copper is the largest among the elements forming the first layer 31a. The amount of aluminum is next largest. The amount of the specific metal is less than the amount of aluminum. Therefore, copper is the major metal, aluminum is the first minor metal, and the specific metal is the second minor metal. The amount of impurities is less than the amount of the specific metal.

[0030] Second layer 31b is formed of copper. The copper content forming second layer 31b is 99.9 at% or more. It is preferable that the copper content in second layer 31b is 99.95 at% or more. Electrolytically plated layer 30b is formed of copper. The copper content forming electrolytically plated layer 30b is 99.9 at% or more. It is preferable that the copper content in electrolytically plated layer 30b is 99.9 at% or more.

[0031] In the embodiment, an adhesive layer 100 can be formed on the surface (upper surface and side surface) of the connecting conductor layer 30. The adhesive layer 100 is not essential. The surface of the connecting conductor layer 30 is formed of a first surface and a second surface. Of the surfaces, the first surface is a portion exposed by an opening for a via conductor. The second surface is a portion other than the first surface. The first surface is not covered with the adhesive layer 100, and the second surface is covered with the adhesive layer 100. The adhesive layer 100 is in contact with the connecting conductor layer 30. The adhesive layer 100 is in contact with the second surface of the connecting conductor layer 30. The adhesive layer 100 is formed of a resin. The adhesive layer 100 is formed of an organic material (organic resin). An example of the organic material is a nitrogen-based organic compound. An example of the nitrogen-based organic compound is a tetrazole compound. An example of the nitrogen-based organic compound is disclosed in JP 2015-54987 A. The adhesive layer 100 does not cover the first surface 20a of the resin insulating layer 20 exposed from the connecting conductor layer 30. The adhesive layer 100 is formed between the connecting conductor layer 30 and the second resin insulating layer 120. The adhesive layer 100 is sandwiched between the connecting conductor layer 30 and the resin insulating layer (second resin insulating layer) 120. The adhesive layer 100 bonds the connecting conductor layer 30 and the resin insulating layer 120. The connecting wiring 36 may have only a second surface.

[0032] Fig. 6 is an enlarged cross-sectional view showing a part of the adhesive layer 100 formed on the second surface of the connection wiring 36. As shown in Fig. 6, the adhesive layer 100 is formed of a substantially smooth film 102 and a plurality of protrusions 104 protruding from the smooth film 102. The adhesive layer 100 formed on the second surface of the pad (pads 32, 34, etc.) is formed of a smooth film 102 and a plurality of protrusions 104 similar to those in Fig. 6. The shape is also the same.

[0033] The smooth film 102 has a substantially uniform thickness T. The thickness T of the smooth film 102 is 10 nm or more and 120 nm or less. The ratio (S1 / S2) of the area (S1) of the smooth film 102 exposed from the protrusion 104 to the area (S2) of the adhesive layer 100 is 0.1 or more and 0.5 or less. The smooth film 102 on the second surface of the connecting conductor layer 30 is formed to substantially conform to the shape of the second surface of the connecting conductor layer 30. When undulations are formed on the top and side surfaces of the connecting conductor layer 30, the smooth film 102 follows the undulations.

[0034] The protruding portion 104 is formed of a plurality of protrusions 106. The plurality of protrusions 106 form unevenness on the upper surface of the protruding portion 104. 2 The number of protrusions 106 per unit area is 5 or more and 15 or less. The protrusions 104 have heights H1, H2 between the upper surface of the smooth film 102 and the tops of the protrusions 104. The maximum values ​​of the heights H1, H2 are 10 times or more and 30 times or less the thickness T of the smooth film 102. The heights H1, H2 are 200 nm or more and 450 nm or less.

[0035] As shown in FIG. 2, via conductors 41 and 42 are formed in the openings (openings 21 and 22 for via conductors). The via conductors 41 and 42 electrically connect the conductor layer 10 and the connecting conductor layer 30. The via conductors 41 and 42 and the connecting conductor layer 30 are formed at the same time. The via conductors 41 and 42 are formed of a seed layer 30a and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a forming the via conductors 41 and 42 and the seed layer 30a forming the connecting conductor layer 30 are common. The electrolytic plating layer 30b forming the via conductors 41 and 42 and the electrolytic plating layer 30b forming the connecting conductor layer 30 are common. The seed layer 30a forming the via conductors 41 and 42 is formed of a first layer 31a formed on the inner wall surfaces 23 and 24 of the openings 21 and 22 for via conductors and on the pads 12 and 14 exposed from the openings 21 and 22 for via conductors, and a second layer 31b on the first layer 31a. The first layer 31a is in contact with the pads 12, 14 and the inner wall surfaces 23, 24. The resin insulating layer (first resin insulating layer) 20 supports the connecting conductor layer (first connecting conductor layer) 30. The connecting conductor layer (first connecting conductor layer) 30 in contact with the first surface 20a of the resin insulating layer (first resin insulating layer) 20 and the via conductors 41, 42 penetrating the resin insulating layer (first resin insulating layer) 20 are formed simultaneously. In the embodiment, the thickness of the seed layer 30a forming the via conductors 41, 42 can be reduced. In the embodiment, the thickness of the first layer 31a forming the via conductors 41, 42 can be reduced. In the embodiment, the thickness of the second layer 31b forming the via conductors 41, 42 can be reduced. Therefore, in the embodiment, the connecting conductor layer 30 having the fine connecting wiring 36 can be formed.

[0036] A resin insulating layer (second resin insulating layer) 120 having a first surface 120a and a second surface 120b opposite to the first surface 120a is formed on the connecting conductor layer 30 and the resin insulating layer 20 via an adhesive layer 100. The resin insulating layer 120 is bonded to the connecting conductor layer 30 by the adhesive layer 100. The resin insulating layer 120 is in contact with the adhesive layer 100. The second surface 120b of the resin insulating layer 120 faces the connecting conductor layer 30. The resin insulating layer 120 is formed of a resin 80 and inorganic particles (first inorganic particles 91, second inorganic particles 92, third inorganic particles 93) 90, similar to the resin insulating layer 20. Therefore, the material of the resin insulating layer (second resin insulating layer) 120 is the same as the material of the resin insulating layer (first resin insulating layer) 20. The first surface 120a of the resin insulating layer 120 is the same as the first surface 20a of the resin insulating layer 20. The first inorganic particles 91 forming the second resin insulating layer 120 have a first portion 91a and a second portion 91b, and an exposed surface 91aR of the first portion 91a forms the first surface 20a of the second resin insulating layer 120. The first inorganic particles 91 in the first resin insulating layer 20 and the first inorganic particles 91 in the second resin insulating layer 120 have the same ratio R.

[0037] The resin insulating layer 120 has openings (openings for via conductors) 121, 122, 123, and 124. The opening 121 is a first opening 121 that exposes the first pad 32. The opening 122 is a second opening 122 that exposes the second pad 34. The first opening 121 and the opening 123 are formed directly below the first mounting area A1. The second opening 122 and the opening 124 are formed directly below the second mounting area A2. The first opening 121 and the second opening 122 reach the pads 32 and 34 that are directly connected to the connection wiring 36. Such openings (the first opening 121, the second opening 122, etc.) may be called openings for connection via conductors. The first opening 121 located directly below the first electronic component E1 is an opening for the first connection via conductor, and the second opening 122 located directly below the second electronic component E2 is an opening for the second connection via conductor. First opening 121, second opening 122, openings 123, 124 are similar to opening 21 shown in Fig. 5. Accordingly, inner wall surface 125 of first opening 121, inner wall surface 126 of second opening 122, and inner wall surfaces of openings 123, 124 are similar to inner wall surface 23 of opening 21 shown in Fig. 5. The inner wall surface of an opening for a via conductor penetrating resin insulation layer (second resin insulation layer) 120 is similar to the inner wall surface of an opening for a via conductor penetrating resin insulation layer (first resin insulation layer) 20. Each of the openings for a via conductor penetrating each resin insulation layer has a substantially similar inner wall surface.

[0038] The mounting conductor layer 130 is formed on the first surface 120a of the resin insulating layer 120. The resin insulating layer 120 supporting the mounting conductor layer 130 is the uppermost resin insulating layer. The mounting conductor layer 130 is in contact with the first surface of the uppermost resin insulating layer. The mounting conductor layer 130 includes a plurality of first electrodes 131 and a plurality of second electrodes 132. The mounting conductor layer 130 includes electrodes 133 and 134 other than the first electrode 131 and the second electrode 132. The first electrodes 131 and 133 are formed in the first mounting area A1. The first electronic component E1 is mounted on the printed wiring board 2 via the first electrodes 131 and 133. The second electrodes 132 and 134 are formed in the second mounting area A2. The second electronic component E2 is mounted on the printed wiring board 2 via the second electrodes 132 and 134. The mounting conductor layer 130 may further have a plurality of connection wirings (second connection wirings). In this case, the second connection wirings have one end and the other end opposite to the one end. One end of the second connection wirings is directly connected to one first electrode 131. The other end of the second connection wirings is directly connected to one second electrode 132. The second connection wirings electrically connect the first electrode 131 and the second electrode 132. Data is transmitted from the first electronic component E1 to the second electronic component E2 via the second connection wirings. The connection wirings in the mounting conductor layer 130 are not essential. The connection wirings in the mounting conductor layer 130 may include the first electrode 131 and the second electrode 132.

[0039] The mounting conductor layer 130 and the connection conductor layer 30 are similar. Therefore, the mounting conductor layer 130 is formed of a seed layer 130a and an electrolytic plating layer 130b on the seed layer 130a. The seed layer 130a is formed of a first layer 131a and a second layer 131b on the first layer 131a. The seed layer 130a forming the mounting conductor layer 130 and the seed layer 30a forming the connection conductor layer 30 are similar. The first layer 131a forming the mounting conductor layer 130 and the first layer 31a forming the connection conductor layer 30 are similar. The second layer 131b forming the mounting conductor layer 130 and the second layer 31b forming the connection conductor layer 30 are similar. The electrolytic plating layer 130b forming the mounting conductor layer 130 and the electrolytic plating layer 30b forming the connection conductor layer 30 are similar.

[0040] When the mounting conductor layer 130 includes connection wiring, the connection wiring in the mounting conductor layer 130 is similar to the connection wiring 36 in the connection conductor layer 30. Therefore, the widths W1, G1, W2, and G2 of the connection wiring in the mounting conductor layer 130 are similar to the widths W1, G1, W2, and G2 of the connection wiring 36 in the connection conductor layer 30. The aspect ratio (thickness / width) of the connection wiring in the mounting conductor layer 130 is 2.0 or more and 4.0 or less.

[0041] In the embodiment, an adhesive layer 150 can be formed on the surface (upper surface and side surface) of the mounting conductor layer 130. The adhesive layer 150 is not essential. The surface of the mounting conductor layer 130 is formed of a third surface and a fourth surface. Of the surfaces, the third surface is a portion exposed by an opening. An example of an opening is an opening for forming a bump. The fourth surface is a portion other than the third surface. The third surface is not covered with the adhesive layer 150, and the fourth surface is covered with the adhesive layer 150. The adhesive layer 150 covering the fourth surface of the mounting conductor layer 130 is similar to the adhesive layer 100 covering the second surface of the connecting conductor layer 30. Therefore, the adhesive layer 150 is formed of a substantially smooth smooth film 102 and a protruding portion 104 protruding from the smooth film 102 (see FIG. 6). The adhesive layer 150 does not cover the first surface 120a of the resin insulating layer 120 exposed from the mounting conductor layer 130. The adhesive layer 150 bonds the mounting conductor layer 130 and the insulating layer 220. If the mounting conductor layer 130 includes a connecting wire, the connecting wire may only have a fourth surface.

[0042] Via conductors 141, 142, 143, and 144 are formed in the openings (openings for via conductors) 121, 122, 123, and 124 penetrating the resin insulating layer 120. The via conductor 141 formed in the first opening 121 is the first connection via conductor 141. The first connection via conductor 141 is connected to the first pad 32 extending from one end of the connection wiring 36. The via conductor 142 formed in the second opening 122 is the second connection via conductor 142. The second connection via conductor 142 is connected to the second pad 34 extending from the other end of the connection wiring 36. The first connection via conductor 141 and the second connection via conductor 142 electrically connect the connection conductor layer 30 and the mounting conductor layer 130. The first connection via conductor 141 electrically connects the first pad 32 and the first electrode 131. The second connection via conductor 142 electrically connects the second pad 34 and the second electrode 132. The first connection via conductor 141 electrically connects the first electrode 131 and the connection wiring 36. The second connection via conductor 142 electrically connects the second electrode 132 and the connection wiring 36. The inner wall surfaces 125, 126 of the openings 121, 122 for the connection via conductors 141, 142 are formed by the exposed surface 93b of the third inorganic particles 93 and the surface 80a of the resin 80. The exposed surface 93b of the third inorganic particles 93 and the surface 80a of the resin 80 form an almost common surface. The inner wall surface of the opening for the connection via conductor is almost flat. Therefore, when data from the first electrode 131 to the second electrode 132 passes through the connection via conductors 141, 142, the data is unlikely to deteriorate. The connection via conductor of the embodiment is suitable as a via conductor for transmitting high-speed data. The printed wiring board 2 of the embodiment can transmit a large amount of data through the connection via conductor.

[0043] The connection via conductor is formed by a seed layer 130a and an electrolytic plating layer 130b on the seed layer 130a. The first connection via conductor 141 and the second connection via conductor 142 are examples of connection via conductors. The seed layer 130a forming the connection via conductors 141, 142 and the seed layer 130a forming the mounting conductor layer 130 are common. The first layer 131a forming the connection via conductors 141, 142 and the first layer 131a forming the mounting conductor layer 130 are common. The second layer 131b forming the connection via conductors 141, 142 and the second layer 131b forming the mounting conductor layer 130 are common. The electrolytic plating layer 130b forming the connection via conductors 141, 142 and the electrolytic plating layer 130b forming the mounting conductor layer 130 are common. The seed layer 130a forming the connection via conductors 141, 142 is composed of a first layer 131a formed on inner wall surfaces 125, 126 of the openings 121, 122 for the connection via conductor and on the pads 32, 34 exposed from the openings 121, 122 for the connection via conductor, and a second layer 131b on the first layer 131a. The first layer 131a is in contact with the inner wall surfaces 125, 126 and the pads 32, 34. Via conductors 143, 144 are formed in the openings 123, 124 other than the openings 121, 122 for the connection via conductor.

[0044] The mounting conductor layer is formed directly on the resin insulation layer (mounting resin insulation layer) that supports the mounting conductor layer. The mounting conductor layer contacts the mounting resin insulation layer. The seed layer that forms the mounting conductor layer and the seed layer that forms the via conductor penetrating the mounting resin insulation layer are common. Both are formed at the same time. The first layer that forms the mounting conductor layer and the first layer that forms the via conductor penetrating the mounting resin insulation layer are common. Both are formed at the same time. The second layer that forms the mounting conductor layer and the second layer that forms the via conductor penetrating the mounting resin insulation layer are common. Both are formed at the same time. The first layer and the second layer form a seed layer. The electrolytic plating layer that forms the mounting conductor layer and the electrolytic plating layer that forms the via conductor penetrating the mounting resin insulation layer are common. Both are formed at the same time. The inner wall surface of the opening for the via conductor penetrating the mounting resin insulation layer and the inner wall surface 23 of the opening 21 shown in FIG. 5 are similar. Therefore, the embodiment can reduce the thickness of the seed layer that forms the mounting conductor layer. The mounting conductor layer may have fine connecting wiring.

[0045] An insulating layer 220 having a first surface 220a and a second surface 220b opposite to the first surface 220a is formed on the mounting conductor layer 130 and the first surface 120a of the resin insulating layer 120. In the embodiment, an adhesive layer 150 can be formed on the mounting conductor layer 130. In that case, the insulating layer 220 is formed on the mounting conductor layer 130 via the adhesive layer 150. The adhesive layer 150 formed on the mounting conductor layer 130 and the adhesive layer 100 on the connecting conductor layer 30 are the same. The insulating layer 220 is bonded to the mounting conductor layer 130 by the adhesive layer 150. The second surface 220b of the insulating layer 220 faces the mounting conductor layer 130. The insulating layer 220 functions as a solder resist layer. It is preferable that the material of the insulating layer 220 is different from the material of the resin insulating layers 20 and 120. The insulating layer 220 is formed using, for example, an epoxy resin or a polyimide resin containing a photosensitive agent.

[0046] The insulating layer 220 has openings (bump openings) 221, 222, 223, 224 that expose the electrodes 131, 132, 133, 134. The opening 221 is a first opening (first bump opening) 221 that exposes the first electrode 131. The opening 222 is a second opening (second bump opening) 222 that exposes the second electrode 132. The first opening 221 and the opening 223 are formed directly above the first mounting area A1. The second opening 222 and the opening 224 are formed directly above the second mounting area A2.

[0047] Bumps 241, 242, 243, and 244 are formed on the electrodes 131, 132, 133, and 134 exposed from the openings (openings for bumps) 221, 222, 223, and 224. The bump 241 formed on the first electrode 131 exposed from the first opening (first opening for bumps) 221 is the first bump 241. The bump 242 formed on the second electrode 132 exposed from the second opening (second opening for bumps) 222 is the second bump 242. The bumps 241, 242, 243, and 244 are examples of bumps for mounting electronic components (first electronic component E1, second electronic component E2, etc.) on the printed wiring board 2. The first bump 241 and the bump 243 are located on the first mounting area A1, and the first electronic component E1 is mounted on the printed wiring board 2 via these bumps 241 and 243. The second bumps 242 and 244 are located on the second mounting area A2, and the second electronic component E2 is mounted on the printed wiring board 2 via these bumps 242, 244.

[0048] Each of the bumps 241, 242, 243, 244 is formed by a portion (first portion) filling the openings 221, 222, 223, 224 and a second portion (land) on the first portion. The second portion is formed on the first surface 220a of the insulating layer 220 directly above the first portion and around the openings 221, 222, 223, 224. The second portion protrudes from the first surface 220a of the insulating layer 220. The first portion and the second portion are continuous. Both are formed integrally. The first bump 241 electrically connects the first electronic component E1 and the first electrode 131. The second bump 242 electrically connects the second electronic component E2 and the second electrode 132. The first electronic component E1 and the second electronic component E2 are connected via the first bump 241, the first connection via conductor 141, the connection wiring 36, the second connection via conductor 142, and the second bump 242. When data is sent from the first electronic component E1 to the second electronic component E2, the data is transmitted through a path including the connection via conductors and the connection wiring. Since the connection via conductors and the connection wiring include a sputtered seed layer formed on a substantially flat surface, the printed wiring board 2 of the embodiment can transmit a large amount of data at high speed from the first electronic component E1 to the second electronic component E2. When the data is transmitted, degradation of the data is unlikely to occur.

[0049] The bumps 241, 242, 243, and 244 are formed of a seed layer 230a and an electrolytic plating layer 230b on the seed layer 230a. The seed layer 230a is formed of a first layer 231a and a second layer 231b on the first layer 231a. The seed layer 230a forming the bumps (first bump 241, second bump 242, etc.) and the seed layer 30a forming the connecting conductor layer 30 are the same. The first layer 231a forming the bumps and the first layer 31a forming the connecting conductor layer 30 are the same. The second layer 231b forming the bumps and the second layer 31b forming the connecting conductor layer 30 are the same. The electrolytic plating layer 230b forming the bumps and the electrolytic plating layer 30b forming the connecting conductor layer 30 are the same. In the modified example, the bumps 241, 242, 243, and 244 may be formed of solder.

[0050] A functional layer 260 is formed on the tops of the bumps 241, 242, 243, and 244. The functional layer 260 is, for example, a plating film of nickel, tin, palladium, gold, or the like. The functional layer 260 is not essential.

[0051] [Modifications of the embodiment] Fig. 7 is a cross-sectional view showing a printed wiring board 3 according to a modified example of the embodiment. As shown in Fig. 7, the printed wiring board 3 has the printed wiring board 2 according to the embodiment and a support 4. The support 4 is attached to the lower surface 2b of the printed wiring board 2 according to the embodiment. The support 4 includes a base material 5, a first metal layer 6 laminated on both sides of the base material 5, a release layer 7 formed on the first metal layer 6, and a second metal layer 8 laminated on the release layer 7. The printed wiring board 2 according to the embodiment is laminated on the second metal layer 8.

[0052] An example of the base material 5 is a substrate containing a reinforcing material such as glass, silicon, or glass fiber. The rigidity of the base material 5 is higher than the rigidity of the printed wiring board 2. Therefore, the modified printed wiring board 3 can increase the connection reliability between the printed wiring board and electronic components (the first electronic component E1, the second electronic component E2, etc.).

[0053] [Method of manufacturing printed wiring board 2 according to embodiment] 8A to 8I show a method for manufacturing a printed wiring board 2 according to an embodiment. FIGS. 8A to 8C, 8E, and 8G to 8I are cross-sectional views. FIGS. 8D and 8F are enlarged cross-sectional views. FIG. 8A shows a support 4 and a conductor layer 10 formed on the support 4. The support 4 is the same as the support 4 in FIG. 7. A plating resist is formed on the second metal layer 8. A conductor layer 10 including pads 12, 14 is formed on the second metal layer 8 exposed from the plating resist. The second metal layer 8 serves as a seed layer for forming the conductor layer 10. The plating resist is then removed. In an embodiment, the upper surface of the conductor layer 10 can be polished by, for example, CMP (Chemical Mechanical Polishing) before removing the plating resist.

[0054] As shown in FIG. 8B, a resin insulation layer (first resin insulation layer) 20 and a protective film 50 are formed on the second metal layer 8 and the conductor layer 10. The second surface 20b of the resin insulation layer 20 faces the second metal layer 8. The protective film 50 is formed on the first surface 20a of the resin insulation layer 20. The resin insulation layer 20 has resin 80 and inorganic particles (second inorganic particles 92) 90. The inorganic particles 90 are embedded in the resin 80. The first surface 20a of the resin insulation layer 20 is formed only from the resin 80. The inorganic particles 90 are not exposed from the first surface 20a of the resin insulation layer 20. The first surface 20a of the resin insulation layer 20 does not include the surfaces of the inorganic particles 90. No irregularities are formed on the first surface 20a of the resin insulation layer 20.

[0055] As shown in FIG. 8C, laser light L is irradiated from above the protective film 50. The laser light L penetrates the protective film 50 and the resin insulating layer 20 at the same time. Openings 21, 22 for via conductors are formed, leading to the pads 12, 14 of the conductor layer 10. The laser light L is, for example, a UV laser light or a CO2 laser light. The pads 12, 14 are exposed by the openings 21, 22. When the openings 21, 22 for the via conductors are formed, the first surface 20a of the resin insulating layer 20 is covered with the protective film 50. Therefore, even if resin scatters when the openings 21, 22 for the via conductors are formed, the resin is prevented from adhering to the first surface 20a of the resin insulating layer 20.

[0056] FIG. 8D shows the inner wall surface 23b of the opening (opening for via conductor) after the laser light irradiation. The opening 21 is depicted as a representative example of the opening for the via conductor. The opening 22 and the opening 21 are similar. The inner wall surface 24b of the opening 22 and the inner wall surface 23b of the opening 21 are similar. The inner wall surface 23b is formed of the resin 80 and the inorganic particles 90 protruding from the resin 80. In order to control the shape of the inner wall surface, the inner wall surface 23b after the laser light irradiation is treated. It is preferable to selectively remove the inorganic particles 90 protruding from the resin 80. As a result, the third inorganic particles 93 are formed from the inorganic particles 90. For example, the inorganic particles 90 protruding from the resin 80 are selectively removed by treating the inner wall surface 23b after the laser light irradiation with a chemical. Alternatively, the inorganic particles 90 protruding from the resin 80 are selectively removed by treating the inner wall surface 23b after the laser light irradiation with plasma. Selectively removing includes that the etching rate of the inorganic particles 90 is greater than the etching rate of the resin 80. For example, the difference in etching rate between the two is 10 times or more. Alternatively, the difference in etching rate between the two is 50 times or more. Alternatively, the difference in etching rate between the two is 100 times or more. By processing the inner wall surface 23b after the laser light irradiation, the third inorganic particles 93 having the flat portion 93a are obtained. By controlling the conditions for processing the inner wall surface 23b after the laser light irradiation, the embodiment can control the shape of the inner wall surface 23. Examples of the conditions are temperature, concentration, time, and type and pressure of gas. The etching rate of the inorganic particles 90 and the etching rate of the resin are controlled.

[0057] By irradiating the resin insulating layer 20 with laser light L, a part of the second inorganic particles 92 embedded in the resin 80 forms the inner wall surface 23b after the laser light irradiation. The second inorganic particles 92 forming the inner wall surface 23b after the laser light irradiation are formed by a protruding portion P protruding from the resin 80 and a portion E embedded in the resin 80. The inner wall surface 23b after the laser light irradiation is treated. For example, the inner wall surface 23b is treated with plasma of a gas containing tetrafluoromethane. The protruding portion P is selectively removed to form the inner wall surface 23 of the embodiment. The third inorganic particles 93 are formed from the second inorganic particles 92. The protruding portion P is selectively removed to form the third inorganic particles 93 having a flat portion 93a. The flat portion 93a is a flat surface. When the second inorganic particles 92 having a spherical shape are cut by a flat surface, the shape of the third inorganic particles 93 is obtained. The inner wall surface 23 is formed by the flat portion 93a and the surface 80a of the resin 80, and the exposed surface 93b of the flat portion 93a and the surface 80a of the resin 80 are located on approximately the same plane. For example, when the seed layer 30a is formed on the inner wall surface 23b by sputtering, the protruding portion P inhibits the growth of the sputtered film (sputtering film formation). For example, the seed layer 30a is not formed continuously on the inner wall surface 23b. Alternatively, it is necessary to increase the thickness of the seed layer 30a. According to the reference example, it is difficult to form a fine conductor circuit. In the embodiment, the protruding portion P is removed. In the embodiment, the thickness of the seed layer 30a formed by sputtering can be reduced. Even if the thickness of the seed layer 30a formed by sputtering is thin, a continuous seed layer 30a can be obtained. The width of the connection wiring 36 satisfies the target value. The width of the space 37 between adjacent connection wirings 36 satisfies the target value. The via conductor formed on the inner wall surface 23b having the protruding portion P is the via conductor of the reference example. If the via conductor of the reference example is present in the path, data moving from the first electronic component E1 to the second electronic component E2 must pass through the via conductor of the reference example. In that case, it is considered that the data will be deteriorated due to the influence of the protruding portion P. In the embodiment, the protruding portion P is removed. The embodiment can suppress the deterioration of the data.

[0058] Forming an opening (opening for a via conductor) includes forming inorganic particles (second inorganic particles 92) 90 having protruding portions P. An opening 21 is a representative example of an opening (opening for a via conductor). The protruding portions P protrude from the resin 80 forming the inner wall surface 23b of the opening 21. The third inorganic particles 93 are formed by removing the protruding portions P of the inorganic particles (second inorganic particles 92) 90. The inner wall surface 23 of the opening 21 includes the exposed surfaces 93b of the third inorganic particles 93. The exposed surfaces 93b of the third inorganic particles 93 are formed by removing the protruding portions P.

[0059] Obtaining the shape of the third inorganic particle 93 by cutting the spherical second inorganic particle 92 on a plane includes removing the protruding portion P of the inorganic particle 90. The inner wall surface 23 of the actual opening 21 is a substantially curved surface. Since the flat portion 93a is formed by removing the protruding portion P, the exposed surface 93b of the flat portion 93a includes a curved surface. In other words, forming a common surface between the flat portion 93a and the resin 80 includes forming the inner wall surface 23 that is substantially formed as a curved surface.

[0060] No irregularities are formed on the inner wall surface 23. The inner wall surface 23 is formed smoothly. The size of the irregularities is controlled by controlling the conditions for processing the inner wall surface 23b after the laser light irradiation.

[0061] The inside of the opening 21 is cleaned. By cleaning the inside of the opening 21, resin residue generated when the opening 21 is formed is removed. The inside of the opening 21 is cleaned by plasma. That is, the cleaning is performed by a dry process. The cleaning includes a desmear process.

[0062] When the inside of the opening 21 is cleaned, the first surface 20a of the resin insulating layer 20 is covered with the protective film 50. The first surface 20a is not affected by the plasma. The first surface 20a is formed only of the resin 80. The inorganic particles 90 are not exposed from the first surface 20a. The first surface 20a does not include the surfaces of the inorganic particles 90. The first surface 20a does not have any irregularities. The first surface 20a is formed to be smooth.

[0063] In the case where processing the inner wall surface 23b after the laser light irradiation includes cleaning the inside of the opening 21, the embodiment can omit cleaning the inside of the opening 21.

[0064] As shown in Fig. 8E, after cleaning the insides of the via conductor openings 21, 22, the protective film 50 is removed from the resin insulating layer 20. When processing the inner wall surfaces 23b, 24b after the laser light irradiation includes cleaning the insides of the via conductor openings, the protective film 50 is removed from the resin insulating layer 20 after processing the inner wall surfaces 23b, 24b after the laser light irradiation. When the inner wall surfaces 23b, 24b after the laser light irradiation are processed, the protective film 50 covers the first surface 20a of the resin insulating layer 20. After the protective film 50 is removed, the first surface 20a is not roughened.

[0065] After removing the protective film 50, the first surface 20a of the resin insulating layer 20 is cleaned. The resin 80 forming the first surface 20a is removed by a dry process. For example, the first surface 20a of the resin insulating layer 20 is cleaned by reverse sputtering. For example, cleaning the first surface 20a of the resin insulating layer 20 is performed by sputtering (argon sputtering) using argon gas. Figures 8F(a) and 8F(b) show the first surface 20a of the resin insulating layer 20 before and after cleaning. As shown in Figures 8F(a) and 8F(b), the resin 80 forming the resin insulating layer 20 is removed by about 20 nm by cleaning by sputtering or the like. For example, the adhesive for bonding the protective film 50 to the resin insulating layer 20 is removed. The resin 80 is selectively removed by cleaning. The thickness of the resin 80 is reduced. A part of the inorganic particles 90 (second inorganic particles 92) is partially exposed from the upper surface of the resin 80 by cleaning. The first inorganic particles 91 are obtained by exposing the second inorganic particles 92 embedded in the resin 80 from the upper surface of the resin 80. The first inorganic particles 91 are formed from the second inorganic particles 92. The first inorganic particles 91 and the second inorganic particles 92 have the same shape. Both are spherical. As shown in FIG. 8F(b), the first inorganic particles 91 are formed of a first portion 91a protruding from the resin 80 and a second portion 91b embedded in the resin 80. The first surface 20a of the resin insulating layer 20 is formed of the upper surface 80R of the resin 80 and an exposed surface 91aR of the first portion 91a protruding from the upper surface 80R of the resin 80. The exposed surface 91aR of the first portion 91a is exposed by cleaning. The first surface 20a of the resin insulating layer 20 is not roughened. Therefore, almost no recesses are formed on the first surface 20a. The first surface 20a has almost no recesses. The upper surface 80R of the resin 80 is almost flat. The upper surface 80R of the resin 80 does not have any recesses.

[0066] The ratio R is calculated, for example, using a cross-sectional view of the first inorganic particle 91 shown in FIG. 8F(b). FIG. 8F(b) is obtained by cutting the resin insulating layer 20 on a plane perpendicular to the upper surface 80R. The connecting conductor layer 30 is omitted in FIG. 8F(b). The connecting conductor layer 30 is formed on the first inorganic particle 91 in FIG. 8F(b). The exposed surface 91aR in FIG. 8F(b) is covered with the connecting conductor layer 30. Using FIG. 8F(b), the cross-sectional area 91aS of the first portion 91a is obtained. Similarly, the cross-sectional area 91S of the first inorganic particle 91 is obtained. For example, the ratio R is represented by the ratio of the cross-sectional area 91aS to the cross-sectional area 91S (cross-sectional area 91aS of the first portion 91a / cross-sectional area 91S of the first inorganic particle 91). For example, when the ratio R is evaluated, 50 first inorganic particles 91 are observed. Fifty of the first inorganic particles 91 satisfy the ratio R.

[0067] As shown in FIG. 8G, a seed layer 30a is formed on the first surface 20a. The seed layer 30a is formed by sputtering. The seed layer 30a is formed by a dry process. The seed layer 30a is also formed on the inner wall surfaces 23, 24 of the opening for the via conductor and the pads 12, 14 exposed from the openings 21, 22 for the via conductor. The seed layer 30a is mainly formed of copper. A first layer 31a is formed on the first surface 20a by sputtering. The first layer 31a is also formed on the inner wall surfaces 23, 24 of the opening for the via conductor and the pads 12, 14 exposed from the openings 21, 22 for the via conductor. A second layer 31b is formed on the first layer 31a by sputtering. The inner wall surfaces 23, 24 of the opening for the via conductor are formed by the exposed surfaces 93b of the third inorganic particles 93 and the surface 80a of the resin 80. The exposed surfaces 93b and the surface 80a of the resin 80 are substantially on the same plane. The inner wall surface of the opening for the via conductor is substantially flat. Therefore, the embodiment can reduce the thickness of the first layer 31a and the thickness of the second layer 31b on the inner wall surface. Since the thickness is thin, the embodiment can reduce the variation in the thickness of the seed layer 30a. The first layer 31a on the inner wall surfaces 23, 24 and the first layer 31a on the first surface 20a of the resin insulating layer 20 are formed simultaneously. The second layer 31b on the inner wall surfaces 23, 24 and the second layer 31b on the first surface 20a of the resin insulating layer 20 are formed simultaneously. Therefore, the embodiment can reduce the thickness of the first layer 31a and the thickness of the second layer 31b on the first surface 20a of the resin insulating layer 20. Almost no recesses are formed on the first surface 20a. Therefore, the first layer 31a on the first surface 20a is formed almost flat. The second layer 31b is formed almost flat. The embodiment can reduce the variation in thickness of the first layer 31a and the variation in thickness of the second layer 31b on the first surface 20a of the resin insulating layer 20. The width of the connection wiring 36 on the first surface 20a of the resin insulating layer 20 satisfies the target value. The width of the space 37 between adjacent connection wirings 36 satisfies the target value. The embodiment can reduce the variation in the width of the connection wiring 36. The embodiment can reduce the variation in the width of the space 37. Even if multiple connection wirings 36 are formed on the first surface 20a of the resin insulating layer 20, data transmitted via each connection wiring 36 reaches the electronic component with almost no delay.

[0068] For example, the first layer 31a is formed of a copper alloy. The first layer 31a of the seed layer 30a is formed of an alloy containing copper, aluminum, and silicon. Aluminum has high ductility and high malleability. Therefore, the adhesive strength between the resin insulating layer 20 and the first layer 31a is high. Even if the resin insulating layer 20 expands and contracts due to heat cycles, it is considered that the seed layer 30a containing aluminum can follow the expansion and contraction. Even if the first surface 20a of the resin insulating layer 20 is smooth, the seed layer 30a is difficult to peel off from the resin insulating layer 20. It is considered that aluminum is easily oxidized. If the third inorganic particles 93 are inorganic particles 90 containing oxygen (oxygen element), it is considered that the first layer 31a formed on the inner wall surfaces 23, 24 adheres to the third inorganic particles 93 via the oxygen in the inorganic particles 90 forming the inner wall surfaces 23, 24. The first layer 31a and the inner wall surfaces 23, 24 are strongly bonded. The embodiment can increase the adhesive strength between the inner wall surfaces 23, 24 and the first layer 31a. The seed layer 30a is unlikely to peel off from the inner wall surfaces 23, 24. The inorganic particles 90 forming the inner wall surfaces 23, 24 preferably contain oxygen elements.

[0069] The first layer 31a of the seed layer 30a contacts the exposed surface 91aR of the first portion 91a of the first inorganic particles 91 forming the first surface 20a of the resin insulating layer 20. When the first layer 31a contains aluminum and the first inorganic particles 91 contain oxygen, it is considered that the adhesive strength between the first layer 31a and the first inorganic particles 91 is improved. Examples of inorganic particles (such as the first inorganic particles) 90 containing oxygen are glass particles and alumina particles. Therefore, when the first layer 31a is formed of an alloy containing copper and aluminum, the first layer 31a is unlikely to peel off from the resin insulating layer 20 even if the first surface 20a of the resin insulating layer 20 does not have a recess. The amount of aluminum in the first layer 31a is 1.0 at% or more and 15.0 at% or less. When the inorganic particles including the first inorganic particles 91 (the first inorganic particles 91, the second inorganic particles 92, and the third inorganic particles 93) are glass particles and the first layer 31a further includes silicon, both of them include silicon. In this case, the first layer 31a is formed of an alloy including copper, aluminum, and silicon. The amount of silicon is 0.5 at% or more and 10.0 at% or less. It is considered that the two are strongly bonded via silicon. Therefore, it is considered that the adhesive force between the first layer 31a and the inorganic particles including the first inorganic particles 91 is further improved. In the embodiment, fine connection wiring 36 can be formed. The width of the fine connection wiring 36 is 1 μm or more and 3 μm or less. Even if the printed wiring board 2 having the fine connection wiring 36 is subjected to thermal shock, the connection wiring 36 is unlikely to peel off from the resin insulating layer 20.

[0070] A plating resist is formed on the seed layer 30a. The plating resist has openings for forming the via conductors 41, 42, the connection wiring 36, and the pads 32, 34 extending from the connection wiring 36. If the first surface 20a has a recess, air due to the recess is likely to be trapped between the plating resist and the seed layer 30a. However, in the embodiment, the first surface 20a has almost no recess. Therefore, the seed layer 30a on the first surface 20a is formed almost flat. The seed layer 30a has almost no recess. Air is unlikely to remain between the plating resist and the seed layer 30a. The contact area between the plating resist and the seed layer 30a is large. Even if the width of the plating resist for forming the space (space 37) between the connection wirings 36 is 10 μm or less, the plating resist is unlikely to peel off from the upper surface of the seed layer 30a. Even if the width of the plating resist is 3 μm or more and 8 μm or less, the embodiment can form the plating resist on the seed layer 30a. Even if the width of the plating resist is 6 μm or less, the plating resist is unlikely to peel off from the seed layer 30a.

[0071] An electrolytic plating layer 30b is formed on the seed layer 30a exposed from the plating resist. The electrolytic plating layer 30b fills the openings in the plating resist. The electrolytic plating layer 30b fills the openings 21 and 22. A portion of the electrolytic plating layer 30b protrudes above the top surface of the plating resist. In this case, the electrolytic plating layer 30b partially covers the top surface of the plating resist. Alternatively, the electrolytic plating layer 30b completely covers the top surface of the plating resist.

[0072] The electrolytic plating layer 30b is polished. The thickness of the electrolytic plating layer 30b is reduced by polishing. The sum of the thickness of the electrolytic plating layer 30b and the thickness of the seed layer 30a reaches a predetermined value. The plating resist is also polished together with the electrolytic plating layer 30b. An example of a polishing method is CMP. The arithmetic mean roughness (Ra) of the upper surface of the electrolytic plating layer 30b after polishing is 0.3 μm or less.

[0073] After polishing the electrolytic plating layer 30b, the plating resist is removed. The seed layer 30a exposed from the electrolytic plating layer 30b is removed. As shown in FIG. 8H, the pads 32, 34 and the connection wiring 36 are formed by the seed layer 30a and the electrolytic plating layer 30b on the resin insulating layer 20. The connecting conductor layer 30 is formed. The seed layer 30a and the electrolytic plating layer 30b in the openings 21, 22 for the via conductors form the via conductors 41, 42. The connecting conductor layer 30 and the via conductors 41, 42 are formed simultaneously.

[0074] As shown in FIG. 8I, an adhesive layer 100 is formed on the upper surface and side surface of the connecting conductor layer 30. The adhesive layer 100 is formed by immersing the intermediate substrate shown in FIG. 8H in a chemical solution containing a nitrogen-based organic compound. The pH of the chemical solution is 7 or less. By immersing the intermediate substrate in the chemical solution, an adhesive layer 100 having a smooth film 102 and a protruding portion 104 is formed on the upper surface and side surface of the connecting conductor layer 30. Before the intermediate substrate is immersed in the chemical solution, the oxide film covering the upper surface and side surface of the connecting conductor layer 30 is removed. In the modified example, the adhesive layer 100 is formed by applying a chemical solution onto the connecting conductor layer 30. After the adhesive layer 100 is formed, the intermediate substrate is removed from the chemical solution. The adhesive layer 100 is dried. The upper surface of the adhesive layer 100 before drying may be smooth. In that case, a part of the adhesive layer is coagulated by drying. By coagulation, an adhesive layer 100 including the smooth film 102 and the protruding portion 104 is formed.

[0075] A resin insulating layer (second resin insulating layer) 120, a mounting conductor layer 130, and via conductors 141, 142, 143, and 144 are formed on the connecting conductor layer 30 and the resin insulating layer 20. The via conductors include connecting via conductors. Examples of the connecting via conductors are the first connecting via conductor 141 and the second connecting via conductor 142. The resin insulating layer 120 and the resin insulating layer 20 are formed in a similar manner. The mounting conductor layer 130 and the connecting conductor layer 30 are formed in a similar manner. The via conductors 141, 142, 143, and 144 and the via conductors 41 and 42 are formed in a similar manner. When the openings 121, 122, 123, and 124 for the via conductors are formed in the resin insulating layer 120 by the laser light L, the laser light L removes the adhesive layer 100 covering the connecting conductor layer 30. Alternatively, the adhesive layer 100 is not completely removed by the laser light L. In this case, the adhesive layer 100 at the bottom of the openings 121, 122, 123, 124 for the via conductor is removed by cleaning the insides of the openings 121, 122, 123, 124 for the via conductor. The openings 121, 122, 123, 124 for the via conductor expose the connecting conductor layer 30. The openings for the via conductor include openings for the connecting via conductor. Examples of the openings for the connecting via conductor are the first opening (opening for the first connecting via conductor) 121 and the second opening (opening for the second connecting via conductor) 122.

[0076] In the embodiment, the thickness of the first layer forming the connection via conductor can be reduced. In the embodiment, the thickness of the second layer forming the connection via conductor can be reduced. The first layer and the second layer form a seed layer. In the embodiment, the volume of the opening for the connection via conductor after the seed layer is formed can be increased. The opening for the connection via conductor after the seed layer is formed can be called the opening after the seed layer is formed. By forming an electrolytic plating layer in the opening after the seed layer is formed, a connection via conductor consisting of the seed layer and the electrolytic plating layer is formed. Even if the diameter of the opening for the connection via conductor is small, the electrolytic plating solution easily enters the opening for the connection via conductor after the seed layer is formed. The electrolytic plating layer forming the connection via conductor is unlikely to include voids. A low-resistance connection via conductor is formed. Even if the path includes the connection via conductor, the printed wiring board 2 of the embodiment can transmit high-speed data. An example of the openings 210 and 211 after the seed layer is formed is shown in FIG. 8G. The openings 210 and 211 after the seed layer is formed are surrounded by the seed layer. The bottom and side of the openings 210 and 211 are in contact with the seed layer.

[0077] An adhesive layer 150 is formed on the upper and side surfaces of the mounting conductor layer 130. The adhesive layer 150 and the adhesive layer 100 are similar. An insulating layer 220 is formed on the mounting conductor layer 130 and the resin insulating layer 120. The insulating layer 220 has openings 221, 222, 223, 224 that expose the electrodes (first electrode 131, second electrode 132, etc.). Bumps (first bump 241, second bump 242, etc.) are formed on the electrodes 131, 132, 133, 134 exposed by the openings 221, 222, 223, 224. A functional layer 260 is formed on the bumps 241, 242, 243, 244. A modified printed wiring board 3 is obtained.

[0078] The support 4 is removed. The release layer 7 of the support 4 is softened or weakened, for example, by heating or ultraviolet light irradiation. The first metal layer 6 and the second metal layer 8 are separated from each other. The second metal layer 8 is then removed by etching. The lower surface 2b of the printed wiring board 2 is exposed. The printed wiring board 2 of the embodiment is obtained.

[0079] In the printed wiring board 2 of the embodiment, the inner wall surface of the opening for the via conductor is formed by the flat portion 93a of the third inorganic particles 93 and the resin 80. The flat portion 93a and the surface 80a of the resin 80 forming the inner wall surface form a substantially common surface. The inner wall surface is formed smoothly. Therefore, a seed layer 30a of uniform thickness is formed on the inner wall surface of the opening. The seed layer 30a is formed thin. When the seed layer 30a is removed, the amount of etching is small. Therefore, the amount of etching of the electrolytic plating layer 30b is small. Each conductor circuit in the connecting conductor layer 30 and the mounting conductor layer 130 has a width according to the design value. A printed wiring board 2 having high quality is provided.

[0080] Data is transmitted from the first electronic component E1 to the second electronic component E2 through the connection wiring 36. When data is transmitted, low loss is preferable. When the connection conductor layer is an inner layer conductor layer, the path for data transmission between the first electronic component E1 and the second electronic component E2 includes a via conductor connected to the connection wiring. The via conductor forming the path is a connection via conductor. Even if the path includes a via conductor (connection via conductor), the inner wall surface of the opening for the connection via conductor of the printed wiring board 2 of the embodiment is formed by the exposed surface 93b of the third inorganic particle 93 and the surface 80a of the resin 80. The inner wall surface is almost flat. According to the embodiment, when data passes through the via conductor, the printed wiring board 2 of the embodiment can suppress loss. The inner layer conductor layer is sandwiched between adjacent resin insulating layers. When there are multiple connection conductor layers (connection internal conductor layers) formed by the inner layer conductor layers, the number of connection internal conductor layers CI is preferably 3 or more. The number of connection internal conductor layers CI is preferably 7 or less. Furthermore, the number of connection internal conductor layers CI is preferably 5 or less. An example of a printed wiring board 200 having three connection internal conductor layers CI is shown in FIG. 9. As shown in FIG. 9, when the path connecting the first connection pad P1 and the first connection electrode D1 has a plurality of via conductors V1, V2, and V3, all of the via conductors V1, V2, and V3 in the path are formed in openings for via conductors similar to the opening 21 shown in FIG. 5. The via conductors V1, V2, and V3 are first connection via conductors and form a first path. The via conductors V1, V2, and V3 are formed in different resin insulating layers. When the path connecting the second connection pad P2 and the second connection electrode D2 has a plurality of via conductors V4, V5, and V6, all of the via conductors V4, V5, and V6 in the path are formed in openings for via conductors similar to the opening 21 shown in FIG. 5. The via conductors V4, V5, and V6 are second connection via conductors and form a second path. The via conductors V4, V5, and V6 are formed in different resin insulating layers.

[0081] The connecting internal conductor layer is preferably sandwiched between resin insulating layers containing third inorganic particles 93 and second inorganic particles 92. Both resin insulating layers sandwiching the connecting internal conductor layer have openings for via conductors. The inner wall surface of the opening for the via conductor is formed by the exposed surface 93b of the third inorganic particles 93 and the surface 80a of the resin 80. The connecting wiring 36 is in contact with the exposed surface 91aR of the first portion 91a of the first inorganic particles 91. Each connecting wiring forming the connecting internal conductor layer has a width close to the design value. The embodiment can form a high-density group of connecting wirings.

[0082] Since the inner wall surface of the opening for each via conductor is formed by the exposed surface 93b of the third inorganic particles 93 and the surface 80a of the resin 80, the shape of the inner wall surface of each via conductor is approximately the same. Even if there are multiple paths including connecting via conductors, the embodiment can reduce the difference in transmission speed between the paths.

[0083] In the printed wiring board 2 of the embodiment, the first surface 20a of the resin insulating layer 20 is formed by the upper surface 80R of the resin 80 and the exposed surface 91aR of the first portion 91a exposed from the upper surface 80R of the resin 80. The first surface 20a and the upper surface 80R have almost no recesses. Therefore, when the seed layer 30a is formed on the resin insulating layer 20 by sputtering, the embodiment can form a continuous seed layer 30a even if the thickness of the sputtering film is thin. The seed layer 30a is formed thin. When the seed layer 30a is removed, the amount of etching is small. Therefore, the amount of etching of the electrolytic plating layer 30b is small. The connection wiring 36 has a width as designed. Fine wiring is formed. A printed wiring board 2 having high quality is provided.

[0084] In the embodiment, the thickness of the first layer 31a made of an alloy containing aluminum can be reduced. The aluminum content in the connection wiring 36 is small, and the copper content is large. In the embodiment, the connection wiring 36 having low resistance can be provided. In the embodiment, the connection wiring 36 having high adhesion to the resin insulating layers 20, 120 can be provided.

[0085] In the printed wiring board 2 of the embodiment, the first surface 20a of the resin insulating layer 20 has almost no recesses. The standard deviation of the relative dielectric constant in the vicinity of the first surface 20a of the resin insulating layer 20 is suppressed from increasing. The relative dielectric constant of the first surface 20a of the resin insulating layer 20 does not vary greatly depending on the location. Even if a plurality of connection wirings 36 are in contact with the first surface 20a of the resin insulating layer 20, the embodiment can reduce the difference in the propagation speed of the electric signal between the connection wirings 36. Therefore, noise is suppressed in the printed wiring board 2 of the embodiment. Even if a logic IC is mounted on the printed wiring board 2 of the embodiment, data transmitted through each connection wiring 36 reaches the logic IC almost simultaneously. The embodiment can suppress malfunction of the logic IC. Even if the length of each connection wiring 36 is 5 mm or more, the embodiment can reduce the difference in the propagation speed. Even if the length of each connection wiring 36 is 10 mm or more and 20 mm or less, the embodiment can suppress malfunction of the logic IC. First surface 120a of resin insulating layer 120 is similar to first surface 20a of resin insulating layer 20. Therefore, the connection wiring in mounting conductor layer 130 has the same effect as connection wiring 36 in connecting conductor layer 30. A high-quality printed wiring board 2 is provided.

[0086] In the printed wiring board 2 of the embodiment, the first layer 31a and the second layer 31b of the seed layer 30a are formed by sputtering. Since the sputtering is performed in a vacuum, the first layer 31a and the second layer 31b are sufficiently adhered to each other. The second layer 31b is unlikely to peel off from the first layer 31a. Even if the diameter of the openings 21 and 22 is small, the connection reliability between the via conductors 41 and 42 and the pads 12 and 14 is high. The connection resistance through the via conductors 41 and 42 is unlikely to increase. As shown in FIG. 8E, the diameter D of the openings 21 and 22 (the diameter of the via conductors 41 and 42) is measured on the pads 12 and 14. The diameter D is 20 μm or more and 50 μm or less. Even if the length of each side of the printed wiring board 2 exceeds 50 mm, the connection resistance through the via conductors 41 and 42 is unlikely to increase for a long period of time even if the length of each side of the printed wiring board 2 is 100 mm or more. A high-quality printed wiring board 2 is provided.

[0087] The printed wiring board 2 of the embodiment has an adhesive layer 100 between the connecting conductor layer 30 and the resin insulating layer 120. The adhesive layer 100 bonds the connecting conductor layer 30 and the resin insulating layer 120. Therefore, even if the upper surface and side surface of the connection wiring 36 are smooth, the resin insulating layer 120 is unlikely to peel off from the connection wiring 36. It is preferable not to roughen the upper surface and side surface of the connection wiring 36. The adhesive layer 100 is formed of a substantially smooth smooth film 102 and a protruding portion 104 protruding from the smooth film 102. The adhesive layer 100 has unevenness formed by the protruding portion 104 and the smooth film 102. The adhesive layer 100 has unevenness formed by a plurality of protrusions 106. Therefore, the connecting conductor layer 30 and the resin insulating layer 120 are sufficiently adhered to each other via the adhesive layer 100. A printed wiring board 2 having high quality is provided. For example, even if the length of each side of the printed wiring board 2 is 50 mm or more, the resin insulating layer 120 is unlikely to peel off from the connecting conductor layer 30. Even if the length of each side of the printed wiring board 2 is 100 mm or more, cracks caused by the adhesive layer 100 are unlikely to occur in the resin insulating layer 120. Even if the connecting conductor layer 30 includes a conductor circuit having a width of 5 μm or less, the resin insulating layer 120 is unlikely to peel off from the connecting conductor layer 30. Even if the connecting conductor layer 30 includes a conductor circuit having a width of 3 μm or less, cracks caused by the adhesive layer 100 are unlikely to occur in the resin insulating layer 120. The adhesive layer 150 formed between the mounting conductor layer 130 and the insulating layer 220 has the same effect as the adhesive layer 100. A high-quality printed wiring board 2 is provided.

[0088] When the first layer contains silicon as the specific metal and the inorganic particles are glass particles, the first layer and the third inorganic particles 93 on the inner wall surface contain silicon. It is considered that the two are strongly bonded via silicon. The seed layer is difficult to peel off from the inner wall surface.

[0089] When the first layer contains aluminum and the inorganic particles (first inorganic particles 91, second inorganic particles 92, third inorganic particles 93) 90 contain oxygen, it is believed that the first layer and the inorganic particles (inorganic particles containing oxygen, such as glass particles) 90 are strongly bonded. When the first layer contains aluminum and the inorganic particles 90 contain oxygen, the first layer does not need to contain the specific metal. In this case, the first layer is formed of copper, aluminum, and impurities.

[0090] [Example 1 of the embodiment] In another embodiment, the specific metal contained in the alloy forming the first layer is at least one of nickel, zinc, gallium, silicon, and magnesium.

[0091] [Another embodiment 2] In another embodiment, the alloy forming the first layer does not contain carbon.

[0092] [Example 3 of the embodiment] In another embodiment, the alloy forming the first layer does not contain oxygen.

[0093] In this specification, the term "plane" is used for the shape of the inner wall surface, the shape of the flat portion 93a, and the shape of the third inorganic particle 93. The meaning of the plane used for these is shown in Fig. 2 and Fig. 5. That is, in Fig. 2 and Fig. 5, the inner wall surface is drawn almost straight. The shape of the inner wall surface in Fig. 2 and Fig. 5 is almost straight. In this specification, the plane includes a substantially straight line shown in a cross section. As shown in the cross section of the third inorganic particle 93 in Fig. 2 and Fig. 5, in a cross section, cutting with a plane includes cutting with a straight line. In this specification, the plane does not mean a perfect plane but includes a substantially flat plane. A substantially flat plane may include small irregularities. [Explanation of symbols]

[0094] 2: Printed wiring board 30: Conductive layer for connection 36: Connection wiring 37: Space 90: Inorganic particles 91: 1st inorganic particle 92:Second inorganic particle 93:Third inorganic particle 93a: Flat part 93b: Exposed surface 100: Adhesive layer 102: Smooth film 104:Protrusion 120: Resin insulation layer 121: First opening 122: Second opening 125: Inner wall surface 126: Inner wall surface 130: Conductive layer for mounting 131: 1st electrode 132:Second electrode 141: First connecting via conductor 142: Second connecting via conductor 150: Adhesive layer 241: First Bump 242: 2nd Bump E1: First electronic component E2: 2nd electronic component

Claims

1. a mounting conductor layer having a first electrode for mounting a first electronic component and a second electrode for mounting a second electronic component; a connection conductor layer located under the mounting conductor layer and having a connection wiring that electrically connects the first electrode and the second electrode; a second resin insulating layer disposed between the mounting conductor layer and the connection conductor layer and having a plurality of openings including a first opening and a second opening; a first resin insulating layer having a first surface and a second surface opposite to the first surface, the first resin insulating layer being formed under the connecting conductor layer such that the connecting conductor layer is formed on the first surface; a first connection via conductor formed in the first opening and electrically connecting the first electrode and the connection wiring; a second connection via conductor formed in the second opening and electrically connecting the second electrode and the connection wiring, The first resin insulation layer is formed of inorganic particles and resin, the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles embedded in the resin, the first inorganic particles are formed of a first portion protruding from the resin and a second portion embedded in the resin, and the first surface is formed by an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface.

2. 2. The printed wiring board according to claim 1, wherein a ratio of a volume of the first portion to a volume of the first inorganic particles is greater than 0 and is equal to or smaller than 0.

4.

3. 2. The printed wiring board of claim 1, wherein the inorganic particles are glass particles.

4. A printed wiring board according to claim 1, wherein the second resin insulation layer is formed from inorganic particles and resin, the inorganic particles include third inorganic particles that form an inner wall surface of the opening, the inner wall surface is formed from the third inorganic particles and the resin, the third inorganic particles have a flat portion, and the flat portion forms the inner wall surface.

5. 5. The printed wiring board according to claim 4, wherein the flat portion and a surface of the resin forming the inner wall surface form a substantially common surface.

6. 5. The printed wiring board according to claim 4, wherein the second inorganic particles have a spherical shape, and the shape of the third inorganic particles is obtained by cutting the second inorganic particles along a plane.

7. A printed wiring board according to claim 4, wherein forming the opening includes forming the inorganic particles having protruding portions protruding from the resin forming the inner wall surface of the opening, and the third inorganic particles are formed by removing the protruding portions of the inorganic particles.

8. A printed wiring board according to claim 4, wherein forming the opening includes forming an inorganic particle having a protruding portion from the second inorganic particle, and the inner wall surface of the opening includes an exposed surface of the third inorganic particle formed by removing the protruding portion.

9. 2. The printed wiring board of claim 1, further comprising an adhesive layer between the connecting conductor layer and the second resin insulation layer, the adhesive layer being in contact with the connecting conductor layer, and the second resin insulation layer being in contact with the adhesive layer.

10. 10. The printed wiring board according to claim 9, wherein the adhesive layer is formed of a substantially flat smooth film and a protruding portion protruding from the flat smooth film.

11. 2. The printed wiring board of claim 1, wherein the number of the first electrodes, the number of the second electrodes, and the number of the connection wirings are multiple, each of the connection wirings is arranged approximately in parallel, the connection wiring having the smallest width among the multiple connection wirings is the smallest connection wiring, the width of the smallest connection wiring is 1 μm or more and 3 μm or less, there is a space between adjacent connection wirings, and the space having the smallest width among the multiple spaces is the smallest space, the width of the smallest space is 1 μm or more and 3 μm or less.

12. 5. The printed wiring board according to claim 4, wherein the inorganic particles contain oxygen elements.

13. 13. A printed wiring board according to claim 12, wherein the connecting conductor layer is formed of a seed layer consisting of a first layer and a second layer on the first layer, and an electrolytic plating layer on the seed layer, the first layer and the second layer being sputtered films, the first layer being made of an alloy containing copper and aluminum, and the second layer being formed of copper.

14. 14. The printed wiring board of claim 13, wherein the alloy further comprises silicon.

Images