Processing device

Abstract

To provide a processing device capable of continuing other processing even when any of processing among a plurality of pieces of processing using a clock signal cannot be continued.SOLUTION: In a vehicle 30, a processing device 10 of an ECU 20 comprises: a processor core 120 which includes a first processing unit 102 for performing first processing and a second processing unit 104 for performing second processing different from the first processing; a first frequency divider 84 which generates a first clock signal used for an interrupt to the first processing by dividing a frequency of a reference clock signal; and a second frequency divider 94 which differs from the first frequency divider and generates a second clock signal used for an interrupt to the second processing by dividing the frequency of the reference clock signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a processing device. [Background technology]

[0002] Patent Document 1 discloses a microcomputer as an information processing device. Signals from various sensors, such as a vehicle speed sensor, are input to the microcomputer via a selector. Each sensor input signal is stored in each register according to an internal clock signal obtained by dividing a system clock signal. The microcomputer performs a number of processes, such as engine control process, body control process, and navigation process, using each sensor input signal stored in each register according to the internal clock signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-101568 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the information processing device disclosed in Patent Document 1, if a fault occurs in the supply of a clock signal, one of the multiple processes using the clock signal may become unable to continue, which may cause other processes to become unable to continue as well.

[0005] The present invention aims to solve the above-mentioned problems. [Means for solving the problem]

[0006] One aspect of the present invention is a processing device comprising a first frequency divider that generates a first clock signal used to interrupt a first process by dividing the frequency of a reference clock signal, and a second frequency divider, different from the first frequency divider, that generates a second clock signal used to interrupt a second process by dividing the frequency of the reference clock signal. Effect of the Invention

[0007] According to the present invention, even if one of a plurality of processes using a clock signal becomes unable to continue, the other processes can continue. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram for explaining a processing device according to an embodiment. [Diagram 2] FIG. 2 is a diagram for explaining the operations of the first timer and the second timer. [Diagram 3] FIG. 3 is a diagram for explaining a third timer and a fourth timer used for task processing in the processing device. [Figure 4] FIG. 4 is a flowchart showing the procedure of the first process and the second process performed by the processing device. [Diagram 5] FIG. 5 is a diagram illustrating an example of memory area allocation of the third memory in the first modification. [Figure 6] FIG. 6 is a diagram illustrating a first processing cycle of the first process and a second processing cycle of the second process in the second modification. [Figure 7] FIG. 7 is a diagram for explaining a processing apparatus according to the third modification. [Figure 8] FIG. 8 is a diagram for explaining a processing device according to the fourth modification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] 1 is a diagram for explaining a processing device 10 according to an embodiment. The processing device 10 includes a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). That is, the processing device 10 includes a processing circuitry.

[0010] The processing device 10 receives a sensor signal, which will be described later, from an input circuit 12. The first memory / third memory 14 includes a first memory and a third memory. The first memory stores data used for reading and / or writing in either the first process or the second process. The third memory stores programs executed by the processing device 10. The processing device 10, the input circuit 12, and the first memory / third memory 14 are included in an ECU (Electronic Control Unit) 20.

[0011] In this embodiment, the ECU 20 is mounted on the vehicle 30 and is used for driving source output control of the vehicle 30 and braking control for the vehicle 30. The ECU 20 may be used for other controls in the vehicle 30. The driving source (not shown) of the vehicle 30 is, for example, an internal combustion engine, but may also be a motor. In this embodiment, the driving source of the vehicle 30 is an internal combustion engine. Furthermore, the vehicle 30 on which the ECU 20 is mounted is, for example, a motorcycle, but may also be another vehicle having wheels (such as a four-wheeled motor vehicle). In this embodiment, the vehicle 30 is a motorcycle.

[0012] The input circuit 12 inputs sensor signals from various sensors to the processing device 10. The various sensors include, for example, a speed sensor 40, a crank angle sensor 52, a throttle position sensor 54, an intake air pressure sensor 56, and the like. The speed sensor 40 outputs a pulse signal as a sensor signal every time the wheels and axles rotate a predetermined angle. Therefore, the sensor signal output by the speed sensor 40 is a pulse signal corresponding to the speed of the vehicle 30. Note that a speed sensor 40 may be provided for each wheel of the vehicle 30. In other words, a sensor signal may be input to the processing device 10 from each of the multiple speed sensors 40.

[0013] The crank angle sensor 52 outputs a sensor signal corresponding to the rotation angle of a crankshaft (not shown). The throttle position sensor 54 outputs a sensor signal corresponding to the opening degree of the throttle (accelerator). The intake pressure sensor 56 outputs a sensor signal corresponding to the intake pressure of the air drawn into the internal combustion engine. In FIG. 1, the sensor signal input from the crank angle sensor 52, the throttle position sensor 54, and the intake pressure sensor 56 to the processing device 10 is omitted. Note that when the driving source of the vehicle 30 is a motor, a sensor that outputs a sensor signal corresponding to detection of the rotation position of the motor may be used.

[0014] The processing device 10 includes a control circuit 72, a clock supply unit 74, a first timer 82, a first frequency divider 84, a second timer 92, a second frequency divider 94, a first processing unit 102, a second processing unit 104, and a second memory 110. The first processing unit 102 and the second processing unit 104 are realized by the processing device 10 executing a program stored in a third memory within the first memory / third memory 14. The programs stored in the third memory include a first program corresponding to the first processing unit 102 and a second program corresponding to the second processing unit 104.

[0015] In this embodiment, the processing device 10 has a single processor core 120. The processor core 120 has a first processing unit 102 and a second processing unit 104. The information transmission delay between the first processing unit 102 and the second processing unit 104 in the same processor core 120 is smaller than when the first processing unit 102 and the second processing unit 104 are included in separate processor cores.

[0016] In this embodiment, a sensor signal from the speed sensor 40 is input to a control circuit 72 of the processing device 10 from one input terminal of the processing device 10 via the input circuit 12. The control circuit 72 outputs the sensor signal input to the control circuit 72 as an output signal to a first timer 82 and a second timer 92 different from the first timer 82. That is, even if only one input terminal is assigned to input of the sensor signal, the control circuit 72 can output an output signal according to the sensor signal to the first timer 82 and the second timer 92. The clock supply unit 74 supplies a reference clock signal into the processing device 10 using an external clock signal.

[0017] The first frequency divider 84 divides the frequency of the reference clock signal by a first division ratio to generate a first clock signal. The first frequency divider 84 supplies the first clock signal to the first timer 82. The second frequency divider 94, which is different from the first frequency divider 84, divides the frequency of the reference clock signal by a second division ratio to generate a second clock signal. The second frequency divider 94 supplies the second clock signal to the second timer 92.

[0018] The first timer 82 counts the number of pulses of the first clock signal supplied from the first frequency divider 84. When a sensor signal is input from the speed sensor 40, the above-mentioned output signal is output from the control circuit 72 to the first timer 82. In this case, the first timer 82 holds the counted number of pulses of the first clock signal as a first count value. Furthermore, the first timer 82 outputs a first interrupt signal Si1 to the first processing unit 102 to generate an interrupt to a first process (described later) performed by the first processing unit 102.

[0019] The second timer 92 counts the number of pulses of the second clock signal supplied from the second frequency divider 94. When a sensor signal is input from the speed sensor 40, the above output signal is output from the control circuit 72 to the second timer 92. In this case, the second timer 92 holds the counted number of pulses of the second clock signal as a second count value. Furthermore, the second timer 92 outputs a second interrupt signal Si2 to the second processing unit 104 to generate an interrupt to a second process (described later) performed by the second processing unit 104. The operations of the first timer 82 and the second timer 92 will be described later with reference to FIG. 2.

[0020] The first timer 82 and the first frequency divider 84 used for interrupting the first process by the first processing unit 102 are different from the second timer 92 and the second frequency divider 94 used for interrupting the second process by the second processing unit 104. Therefore, even if the first timer 82 or the first frequency divider 84 fails, the second process can be continued because the second timer 92 and the second frequency divider 94 are not affected by the failure. In other words, when a failure occurs in either the first process or the second process, it is possible to prevent the other process from also failing.

[0021] The first processing unit 102 performs, for example, a first process related to drive source output control of the vehicle 30. When the drive source is an internal combustion engine of a motorcycle, the drive source output control includes fuel injection control of a fuel injection valve 140, ignition timing control of an ignition plug 142, throttle valve control of a throttle valve 144, and the like.

[0022] The first processing includes a task processing periodically performed at every first processing cycle TP1 and an interrupt processing triggered by a first interrupt signal Si1. The first processing unit 102 performs the task processing to calculate control parameters required for the drive source output control and to control the drive source output based on the control parameters. The drive source output control uses the sensor signals of the crank angle sensor 52, the throttle position sensor 54, and the intake pressure sensor 56, and the speed of the vehicle 30 calculated by a process described later.

[0023] The first processing unit 102 calculates the speed of the vehicle 30, which is used to calculate the control parameters, by interrupt processing. The speed of the vehicle 30 is calculated using a first count value held by the first timer 82. The first count value indicates the output interval of the pulse signal output as a sensor signal from the speed sensor 40. Therefore, the speed of the vehicle 30 can be calculated based on the first count value. The speed of the vehicle 30 calculated in this manner by interrupt processing is used for the drive source output control of the vehicle 30, which is performed in task processing.

[0024] The second processing unit 104 performs, for example, a second process related to braking control for the vehicle 30. The braking control includes control of the brake actuator 146. The brake actuator 146 includes a front wheel brake actuator and a rear wheel brake actuator. The second process includes a task process that is periodically performed at every second processing cycle TP2, and an interrupt process that is triggered by a second interrupt signal Si2. The second processing unit 104 calculates control parameters required for braking control and performs braking control based on the control parameters by the task process. For the braking control, the speed of the vehicle 30 calculated by a process described later is used.

[0025] The second processing unit 104 calculates the speed of the vehicle 30, which is used to calculate the control parameters, by interrupt processing. The speed of the vehicle 30 is calculated using a second count value held by the second timer 92. The second count value indicates the output interval of the pulse signal output as a sensor signal from the speed sensor 40. Therefore, the speed of the vehicle 30 can be calculated based on the second count value. The speed of the vehicle 30 calculated in this manner by interrupt processing is used for braking control of the vehicle 30, which is performed in task processing.

[0026] The second memory 110 and the first memory of the first / third memories 14 each store data used for reading and / or writing in the first process and the second process. For example, the first data used in the first process is stored in the first memory, and the second data used in the second process is stored in the second memory 110.

[0027] Of the first data, the data used for reading in the first process is data for absorbing individual differences of the vehicle 30. An example of data for absorbing individual differences of the vehicle 30 is data for zero point adjustment of the valve closing position of the throttle valve 144. Of the first data, the data used for writing in the first process is, for example, data recorded or saved for analyzing a fault of the vehicle 30, such as a fault diagnosis result and fault information. Of the second data, the data used for writing in the second process is, for example, fault information and the operation history of the antilock brake system.

[0028] That is, the first memory in which the first data is stored and the second memory 110 in which the second data is stored are provided physically separately. Therefore, even if the first memory fails, the second memory 110 is not affected by the failure, so the second process can be continued. That is, when one of the first process and the second process cannot be continued due to a memory failure, it is possible to avoid the other process also being unable to be continued.

[0029] As described above, the first processing unit 102 calculates the control parameters necessary for the drive source output control. The first processing unit 102 controls the fuel injector 140, the spark plug 142, the throttle valve 144, and the like based on the calculated control parameters. The second processing unit 104 calculates the control parameters necessary for braking control. The second processing unit 104 controls the brake actuator 146, and the like based on the calculated control parameters.

[0030] There may be a calculated value that is commonly used in the first process related to the drive source output control by the first processing unit 102 and the second process related to the braking control by the second processing unit 104. For example, attitude angle information of the motorcycle, which is the vehicle 30, is used for both the drive source output control and the braking control.

[0031] When such a calculation value is obtained during the first process, the first processing unit 102 may transmit the calculation value to the second processing unit 104. In that case, the second processing unit 104 can use the calculation value transmitted from the first processing unit 102 in the second process. Conversely, the second processing unit 104 may transmit the calculation value obtained during the second process to the first processing unit 102. In that case, the first processing unit 102 can use the calculation value transmitted from the second processing unit 104 in the first process. As described above, since the information transmission delay between the first processing unit 102 and the second processing unit 104 is small, the common calculation value can be efficiently used in the first process or the second process.

[0032] 2 is a diagram for explaining the operation of the first timer 82 and the second timer 92. A time chart Cs shows an output signal that the control circuit 72 outputs to the first timer 82 and the second timer 92 in response to a pulsed sensor signal from the speed sensor 40. In the time chart Cs, an edge rises at time t1, and then a falling edge occurs at time t2, generating a rectangular pulse-shaped output signal.

[0033] The first timer 82 has a counter and a register, both of which are not shown. The first timer 82 counts the number of pulses of the first clock signal supplied from the first frequency divider 84 by incrementing the counter every first clock period TC1. When the edge of the output signal from the control circuit 72 falls at time t2, as shown in the time chart C1, the first timer 82 starts a process of storing the count value of the counter at time t2 in the register.

[0034] At time t3 after time t2, the process of storing the count value in the register is completed. Thus, the first timer 82 can store the number of pulses of the first clock signal counted by the counter in the register as the first count value. After the first count value is stored in the register, the first timer 82 may reset the counter. When the first count value is stored in the register at time t3, the first timer 82 outputs a first interrupt signal Si1 to the first processing unit 102 to generate an interrupt to the first processing performed by the first processing unit 102.

[0035] The first processing unit 102 reads the first count value from the register and calculates the speed of the vehicle 30 using the first count value. After the first processing unit 102 reads the first count value, the first timer 82 may reset the register. If the counter is not reset after the first count value is held in the register, the first processing unit 102 may store the first count value read from the register in the first memory. The first processing unit 102 calculates the speed of the vehicle 30 using the difference between the first count value read this time and the first count value read and stored previously.

[0036] The second timer 92 also operates in the same manner as the first timer 82. The second timer 92 has a counter and a register, both of which are not shown. The second timer 92 counts the number of pulses of the second clock signal supplied from the second frequency divider 94 by incrementing a counter every second clock period TC2. When the edge of the output signal from the control circuit 72 falls at time t2, as shown in time chart C2, the second timer 92 starts a process of storing the count value of the counter at time t2 in the register.

[0037] At time t3 after time t2, the process of storing the count value in the register is completed. Thus, the second timer 92 can hold the number of pulses of the second clock signal counted by the counter in the register as the second count value. After the second count value is saved in the register, the second timer 92 may reset the counter. When the second count value is held in the register at time t3, the second timer 92 outputs a second interrupt signal Si2 to the second processing unit 104 to generate an interrupt to the second processing performed by the second processing unit 104.

[0038] The second processing unit 104 reads the second count value from the register and calculates the speed of the vehicle 30 using the second count value. After the second processing unit 104 reads the second count value, the second timer 92 may reset the register. If the counter is not reset after the second count value is held in the register, the second processing unit 104 may store the second count value read from the register in the first memory. The second processing unit 104 calculates the speed of the vehicle 30 using the difference between the second count value read this time and the second count value read and stored previously.

[0039] In the time chart Cs, the edge rises at time t4, which is after time t3, and then falls at time t5, whereby a rectangular pulse-shaped output signal is generated again. At time t5, the first timer 82 should start a process of storing the first count value in the register. However, if the first timer 82 fails, or if the first frequency divider 84 fails, the process of storing the first count value in the register is not started at time t5, as shown in the time chart C1. Therefore, the first interrupt signal Si1, which should be output to the first processing unit 102 at time t6, which is after time t5, is not output either.

[0040] It is assumed that neither the second timer 92 nor the second frequency divider 94 has a failure. In this case, as shown in the time chart C2, at time t5, the second timer 92 starts a process of storing the second count value in the register. At time t6, the process of storing the second count value in the register is completed, and the second interrupt signal Si2 is output to the second processing unit 104.

[0041] The second timer 92 is a different timer from the first timer 82. Therefore, a failure of the first timer 82 does not affect the second timer 92. The second frequency divider 94 is a different frequency divider from the first frequency divider 84. Therefore, a failure of the first frequency divider 84 does not affect the second frequency divider 94. Therefore, even if the first process cannot be continued due to a failure of the first timer 82 or the first frequency divider 84, the second process can be continued.

[0042] Conversely, a failure of the second timer 92 does not affect the first timer 82. A failure of the second frequency divider 94 does not affect the first frequency divider 84. Therefore, even if the second process cannot be continued due to a failure of the second timer 92 or the second frequency divider 94, the first process can be continued.

[0043] As described above, the first processing unit 102 performs task processing to calculate the control parameters and control the drive source output based on the control parameters. The task processing by the first processing unit 102 is performed periodically for each first processing cycle TP1. The second processing unit 104 performs task processing to calculate the control parameters and control braking based on the control parameters. The task processing by the second processing unit 104 is performed periodically for each second processing cycle TP2. FIG. 3 is a diagram for explaining the third timer 182 and the fourth timer 192 used for task processing in the processing unit 10.

[0044] 1, the processing device 10 further includes a third timer 182, a fourth timer 192, and a third frequency divider 194. The third timer 182 includes a counter and a register, both of which are not shown. The counter of the third timer 182 counts the number of pulses of the reference clock signal supplied from the clock supply unit 74. A register value corresponding to the first processing period TP1 is preset in the register of the third timer 182.

[0045] When the count value counted by the counter as time passes becomes equal to the register value set in the register, the third timer 182 outputs an interrupt signal corresponding to the first processing cycle TP1 to the first processing unit 102. This restarts the first processing cycle TP1 of the task processing by the first processing unit 102. The third timer 182 resets the counter.

[0046] 3, a frequency divider corresponding to the third timer 182 is not provided, but a frequency divider other than the third frequency divider 194 may be provided. In that case, for example, the first frequency divider 84 may be used as the frequency divider corresponding to the third timer 182.

[0047] The third frequency divider 194 divides the frequency of the reference clock signal by a third division ratio to generate a third clock signal. The third frequency divider 194 supplies the third clock signal to the fourth timer 192. The fourth timer 192 has a counter and a register, both of which are not shown. The counter of the fourth timer 192 counts the number of pulses of the third clock signal supplied from the third frequency divider 194. A register value corresponding to the second processing period TP2 is preset in the register of the fourth timer 192.

[0048] When the count value counted by the counter as time passes becomes equal to the register value set in the register, the fourth timer 192 outputs an interrupt signal corresponding to the second processing cycle TP2 to the second processing unit 104. This restarts the second processing cycle TP2 of the task processing by the second processing unit 104. The fourth timer 192 resets the counter.

[0049] The fourth timer 192 is a timer different from the third timer 182. Therefore, a failure of the third timer 182 does not affect the fourth timer 192. Therefore, even if the first process cannot be continued due to a failure of the third timer 182, the second process can be continued.

[0050] Conversely, a failure of the fourth timer 192 does not affect the third timer 182. In addition, the third timer 182 does not receive a clock signal from the third frequency divider 194. Therefore, a failure of the third frequency divider 194 does not affect the third timer 182. Therefore, even if the second process cannot be continued due to a failure of the fourth timer 192 or the third frequency divider 194, the first process can be continued.

[0051] 4 is a flowchart showing the processing procedure of the first process and the second process performed by the processing device 10. This processing procedure is performed by the processing device 10 executing a program stored in the third memory of the first memory / third memory 14. This processing procedure is started when the processing device 10 detects an ignition-on signal. When this processing procedure is started, in step S1, it is determined whether or not the processor core 120 has detected an ignition-off signal. If the answer is YES in step S1, this processing procedure ends. If the answer is NO in step S1, this processing procedure proceeds to step S11.

[0052] In step S11, the processor core 120 determines whether or not an interrupt signal has been detected. If the result is YES in step S11, the process proceeds to step S21. If the result is NO in step S11, the process returns to step S1. In step S21, the first processing unit 102 determines whether or not the interrupt signal detected in step S11 is the first interrupt signal Si1 from the first timer 82. If the result is YES in step S21, the process proceeds to step S22. If the result is NO in step S21, the process proceeds to step S41.

[0053] The first interrupt signal Si1 in step S21 triggers the start of the interrupt process of the first process. In step S22, the first processing unit 102 reads out the first count value held in the register of the first timer 82. In step S23, the first processing unit 102 calculates the speed of the vehicle 30 based on the first count value. When the process of step S23 is completed, the interrupt process ends and the process returns to step S1.

[0054] In step S41, the second processing unit 104 determines whether or not the interrupt signal detected in step S11 is the second interrupt signal Si2 from the second timer 92. If the result in step S41 is YES, the process proceeds to step S42. If the result in step S41 is NO, the process proceeds to step S61.

[0055] The second interrupt signal Si2 in step S41 triggers the start of the interrupt process of the second process. In step S42, the second processing unit 104 reads out the second count value held in the register of the second timer 92. In step S43, the second processing unit 104 calculates the speed of the vehicle 30 based on the second count value. When the process of step S43 is completed, the interrupt process ends and the process returns to step S1.

[0056] In step S61, the first processing unit 102 determines whether or not the interrupt signal detected in step S11 is an interrupt signal corresponding to the first processing cycle TP1 from the third timer 182. If the result in step S61 is YES, the process proceeds to step S62. If the result in step S61 is NO, the process proceeds to step S81.

[0057] The interrupt signal in step S61 triggers the start of task processing in the first processing. In step S62, the first processing unit 102 executes task processing for driving source output control of the vehicle 30, using the speed of the vehicle 30 calculated in step S23. When the processing in step S62 is completed, the interrupt processing ends, and the processing procedure returns to step S1.

[0058] In step S81, the second processing unit 104 determines whether or not the interrupt signal detected in step S11 is an interrupt signal corresponding to the second processing cycle TP2 from the fourth timer 192. If the result in step S81 is YES, the process proceeds to step S82. If the result in step S81 is NO, the process returns to step S1.

[0059] The interrupt signal in step S81 triggers the start of task processing in the second processing. In step S82, the second processing unit 104 executes task processing of braking control for the vehicle 30, using the speed of the vehicle 30 calculated in step S43. When the processing in step S82 is completed, the interrupt processing ends, and the processing procedure returns to step S1.

[0060] [Variations] The above embodiment may be modified as follows.

[0061] (Variation 1) In the above embodiment, the third memory in the first memory / third memory 14 stores programs executed by the processing device 10. The programs include a first program corresponding to the first processing unit 102 and a second program corresponding to the second processing unit 104. The first program and the second program may be stored in different memory areas of the third memory. Fig. 5 is a diagram showing an example of memory area allocation of the third memory in the first modification.

[0062] The first memory / third memory 14 includes a first memory 14f and a third memory 14t. A first program memory area 14a and a second program memory area 14b are allocated to the third memory 14t. The first program memory area 14a and the second program memory area 14b are different memory areas. Therefore, in the example shown in FIG. 5, the first program and the second program are stored in different memory areas of the third memory 14t.

[0063] There are cases where both the first program and the second program stored in the third memory 14t are updated. In such a case, the first program and the second program can be updated simultaneously by storing them in different memory areas. Therefore, the program can be updated efficiently.

[0064] (Variation 2) In the above embodiment, the task processing of the first process by the first processing unit 102 is periodically performed for each first processing cycle TP1, triggered by an interrupt signal from the third timer 182. The task processing of the second process by the second processing unit 104 is periodically performed for each second processing cycle TP2, triggered by an interrupt signal from the fourth timer 192. The first processing unit 102 and the second processing unit 104 are in the same processor core 120.

[0065] Assume that the start timing of a first processing cycle TP1 of the task processing in the first process and the start timing of a second processing cycle TP2 of the second process coincide with each other. In this case, for example, after the task processing of the first process is completed, the task processing of the second process is started. The time from the start to the completion of the task processing of the first process is not necessarily constant.

[0066] Therefore, the interval between task processes of the second process may not be constant. Variations in the interval between task processes of the second process may affect the duty output used to control a solenoid valve in a hydraulic circuit for braking control, the lighting interval of an indicator, and the like. Therefore, it is preferable that the interval between task processes of the second process is constant. Therefore, a predetermined time lag may be provided between the start timing of the first processing cycle TP1 and the start timing of the second processing cycle TP2.

[0067] 6 is a diagram illustrating a first processing cycle TP1 of the first process and a second processing cycle TP2 of the second process in Modification 2. At each first processing cycle TP1, the third timer 182 is restarted and task processing of the first process is started. In the example shown in FIG. 6, at time t11, the subsequent time t12, and the further subsequent time t13, the third timer 182 is restarted and task processing of the first process is started.

[0068] The fourth timer 192 is restarted at each second processing cycle TP2, and the task processing of the second process is started. In the example shown in Fig. 6, the fourth timer 192 is restarted at time t21, the subsequent time t22, and the further subsequent time t23, and the task processing of the second process is started.

[0069] There is a delay of a predetermined time Ts between time t11, which is the start timing of the first processing cycle TP1, and time t21, which is the start timing of the second processing cycle TP2. Therefore, the second processing cycle TP2 starts at time t21, which is a predetermined time Ts after the first processing cycle TP1 starts at time t11. The second processing cycle TP2 starts at time t22, which is a delay of time Ts1 from the start of the first processing cycle TP1 at the subsequent time t12. The second processing cycle TP2 starts at time t23, which is a delay of time Ts2 from the start of the first processing cycle TP1 at time t13.

[0070] A predetermined time Ts from the start timing of the first processing cycle TP1 to the start timing of the second processing cycle TP2 is determined in advance. When the first processing cycle TP1 and the second processing cycle TP2 are equal, the above-mentioned times Ts1 and Ts2 are both equal to the predetermined time Ts. In this case, it is preferable that the predetermined time Ts is determined according to the time required for task processing of the first process and / or the time required for task processing of the second process.

[0071] As a result, the task processing of the first process may be completed between the restart of the third timer 182 and the restart of the fourth timer 192. The task processing of the second process may be completed between the restart of the fourth timer 192 and the restart of the third timer 182. Therefore, while the interval of the task processing of the first process is kept constant, the interval of the task processing of the second process can also be kept constant.

[0072] When the first processing cycle TP1 and the second processing cycle TP2 are different, the predetermined time Ts is not a multiple of the greatest common denominator D of the first processing cycle TP1 and the second processing cycle TP2. In that case, a time difference can be provided between the restart of the third timer 182 and the restart of the fourth timer 192. Therefore, if the task processing of the first process and / or the task processing of the second process are completed during that time difference, the interval of the task processing of the first process can be kept constant, while the interval of the task processing of the second process can also be kept constant.

[0073] The first processing period TP1 is expressed by equation (1) obtained by multiplying a natural number p by the greatest common divisor D. The second processing period TP2 is expressed by equation (2) obtained by multiplying a natural number q by the greatest common divisor D. The natural numbers p and q are mutually prime. The predetermined time Ts is not a multiple of the greatest common divisor D, and is therefore expressed by equation (3) using an integer a equal to or greater than 0, a number b greater than 0 and less than D, and the greatest common divisor D. TP1=p D (p>0) (1) TP2=q D (q>0) (2) Ts=a D+b (a>=0,0 <b<D) ···(3)

[0074] If the first processing period TP1 and / or the second processing period TP2 are not integer values, both the first processing period TP1 and the second processing period TP2 are multiplied by a power of 10 to change the unit, and values ​​converted to integers are used. For example, if the first processing period TP1 is 1 [s] and the second processing period TP2 is 0.5 [s], which is not an integer value, then 10 3By multiplying, the first processing cycle TP1 is converted to 1000 [ms], and the second processing cycle TP2 is converted to 500 [ms] which is an integer value.

[0075] As shown by the times t11, t12, and t13 in FIG. 6, the time T1(t) at which the first processing cycle TP1 is repeated is represented by Expression (4) using an integer n of 0 or more based on Expression (1). As shown by the times t21, t22, and t23 in FIG. 6, the time T2(t) at which the second processing cycle TP2 is repeated is represented by Expression (5) using a natural number m based on Expression (2). Regarding the time T2(t), Expression (6) is obtained based on Expressions (3) and (5). T1(t)=n·p·D (n>=0) ···(4) T2(t)=m·q·D+Ts (m>0) ···(5) T2(t)=(m·q+a)·D+b ···(6)

[0076] As described above, since 0 < b < D, there is no case where T1(t) shown in Expression (4) and T2(t) shown in Expression (5) match. Therefore, when the predetermined time Ts is not a multiple of the greatest common divisor D, a time difference can be provided between the restart of the third timer 182 and the restart of the fourth timer 192.

[0077] (Modification Example 3) In the above-described embodiment, the processing device 10 has a single processor core 120. The processing device 10 may have a plurality of processor cores 120. FIG. 7 is a diagram for explaining the processing device 10 according to Modification Example 3. The processing device 10 according to this modification example has a first processor core 212 and a second processor core 214 instead of the single processor core 120 among the respective members shown in FIGS. 1 and 3.

[0078] The first processor core 212 has a first processing unit 102. The second processor core 214 has a second processing unit 104. In this modification, one of the first processor core 212 and the second processor core 214 has a determination unit 220, and the other has a notification unit 230. In the example shown in FIG. 7, the first processor core 212 has the determination unit 220, and the second processor core 214 has the notification unit 230.

[0079] The processing device 10 has the first processor core 212 and the second processor core 214, and thus the first process and the second process can be performed in parallel. As described above, in the interrupt process of the first process, the first processing unit 102 reads out the first count value held by the first timer 82. In the interrupt process of the second process, the second processing unit 104 reads out the second count value held by the second timer 92.

[0080] The determination unit 220 of the first processor core 212 acquires the first count value read by the first processing unit 102. The notification unit 230 of the second processor core 214 notifies the determination unit 220 of the second count value read by the second processing unit 104. The determination unit 220 calculates the count difference between the first count value and the second count value. If the count difference is greater than a predetermined value, the determination unit 220 determines that at least one of the first count value and the second count value is an abnormal value.

[0081] In this case, the determination unit 220 may notify an external device (not shown) of the determination result. Based on the determination result of the determination unit 220, the user or manager of the vehicle 30 can determine that any one of the first timer 82, the first frequency divider 84, the second timer 92, and the second frequency divider 94 has failed.

[0082] The determination unit 220 may acquire the speed of the vehicle 30 instead of the first count value. In that case, the notification unit 230 notifies the determination unit 220 of the speed of the vehicle 30 instead of the second count value. The determination unit 220 can thus acquire two speeds of the vehicle 30. The determination unit 220 calculates the speed difference between the two acquired speeds. If the speed difference is greater than a predetermined value, the determination unit 220 determines that at least one of the two speeds is an abnormal value.

[0083] (Variation 4) In the above embodiment, the sensor signal from the speed sensor 40 is input from one input terminal of the processing device 10 via the input circuit 12 to the control circuit 72 of the processing device 10. The control circuit 72 outputs an output signal corresponding to the input sensor signal to the first timer 82 and the second timer 92. If it is possible to assign multiple input terminals of the processing device 10 to input of the sensor signal from the speed sensor 40, the control circuit 72 does not need to be provided.

[0084] 8 is a diagram for explaining a processing device 10 according to a fourth modified example. In FIG. 8, compared to FIG. 1, the control circuit 72 is not provided, and instead a first input terminal 252 and a second input terminal 254 of the processing device 10 are provided. The input circuit 12 outputs a sensor signal from the speed sensor 40 to the first input terminal 252 and the second input terminal 254. The sensor signal input to the first input terminal 252 is further input to a first timer 82. In addition, the sensor signal input to the second input terminal 254 is further input to a second timer 92.

[0085] As a result, if the connection circuit between the input circuit 12 and the first input terminal 252 or the first input terminal 252 is defective, the first timer 82 cannot continue operating, and so the first process may not be able to continue. However, the second timer 92 continues operating without being affected, and so the second process may not be able to continue. Also, if the connection circuit between the input circuit 12 and the second input terminal 254 or the second input terminal 254 is defective, the second timer 92 cannot continue operating, and so the second process may not be able to continue. However, the first timer 82 continues operating without being affected, and so the first process may be able to continue.

[0086] (Variation 5) The above-mentioned modifications 1 to 4 may be combined in any manner.

[0087] In addition to the above disclosure, the following notes are also disclosed.

[0088] (Appendix 1) A processing device (10) including a first processing unit (102) performing a first processing and a second processing unit (104) performing a second processing different from the first processing includes a first frequency divider (84) that generates a first clock signal used to interrupt the first processing by dividing the frequency of a reference clock signal, and a second frequency divider (94) different from the first frequency divider that generates a second clock signal used to interrupt the second processing by dividing the frequency of the reference clock signal. With this configuration, even if one of a plurality of processings using clock signals becomes unable to continue, the other processings can continue.

[0089] (Appendix 2) The processing device according to appendix 1 may further include a first timer (82) that counts the number of pulses of the first clock signal, and when a sensor signal is input, holds the counted number of pulses of the first clock signal as a first count value, and outputs a first interrupt signal (Si1) to the first processing unit to generate the interrupt to the first process, and a second timer (92) different from the first timer that counts the number of pulses of the second clock signal, and when the sensor signal is input, holds the counted number of pulses of the second clock signal as a second count value, and outputs a second interrupt signal (Si2) to the second processing unit to generate the interrupt to the second process, and the first processing unit may read the first count value from the first timer when the first interrupt signal is output, and the second processing unit may read the second count value from the second timer when the second interrupt signal is output. With this configuration, even if one timer or one frequency divider fails, processing using another timer or another frequency divider can be continued.

[0090] (Appendix 3) In the processing device described in Supplementary Note 1, when a sensor signal corresponding to the speed of the vehicle (30) is input, the first processing unit may calculate the speed using the first clock signal and the sensor signal, and the second processing unit may calculate the speed using the second clock signal and the sensor signal. With this configuration, even if any of the processes for calculating the speed using the clock signal becomes impossible to continue, the other processes can continue.

[0091] (Appendix 4) The processing device according to any one of Supplementary Notes 1 to 3 may further include a first memory (14) that stores first data used in the first processing by the first processing unit, and a second memory (110) that stores second data used in the second processing by the second processing unit and is different from the first memory. With this configuration, even if one of the memories fails, the other memory is not affected by the failure, so that processing using the data stored in the other memory can be continued.

[0092] (Appendix 5) The processing device according to any one of Supplementary Notes 1 to 4 may further include a third memory (14) that stores a first program executed by the first processing unit to perform the first processing and a second program executed by the second processing unit to perform the second processing, and the first program and the second program may be stored in different memory areas (14a, 14b) of the third memory. With this configuration, a plurality of programs can be updated simultaneously, making it possible to efficiently update the programs.

[0093] (Appendix 6) In the processing device according to any one of Supplementary Notes 1 to 5, a predetermined time (Ts) is set between the start timing of a first processing cycle (TP1) of the first process and the start timing of a second processing cycle (TP2) of the second process, and when the first processing cycle and the second processing cycle are different, the predetermined time does not have to be a multiple of the greatest common denominator (D) of the first processing cycle and the second processing cycle. With this configuration, it is possible to keep the interval between one of a plurality of processes constant while keeping the interval between the other process constant.

[0094] (Appendix 7) In the processing device according to any one of Supplementary Notes 1 to 6, the first processing unit may perform the first process related to output control of a drive source of a vehicle, the second processing unit may perform the second process related to braking control for the vehicle, the first processing unit may transmit a calculated value obtained during the first process to the second processing unit, and the second processing unit may use the calculated value transmitted from the first processing unit in the second processing. With this configuration, a common calculated value can be efficiently used in a plurality of processes.

[0095] (Appendix 8) The processing device according to Supplementary Note 2 may further include a first processor core (212) having the first processing unit, and a second processor core (214) having the second processing unit and different from the first processor core, wherein one of the first and second processor cores further includes a determination unit (220), which calculates a count difference between the first count value and the second count value, and determines that at least one of the first count value and the second count value is an abnormal value when the count difference is greater than a predetermined value. With this configuration, a user or manager of the vehicle can determine that the timer or the frequency divider has failed based on the determination result of the determination unit.

[0096] (Appendix 9) The processing device described in Supplementary Note 2 may further include a first input terminal (252) to which the sensor signals are respectively input, and a second input terminal (254) different from the first input terminal, and the sensor signal input to the first input terminal may be further input to the first timer, and the sensor signal input to the second input terminal may be further input to the second timer. With this configuration, if one input terminal is defective, the timer to which the sensor signal is input from the other input terminal may continue to operate.

[0097] (Appendix 10) The processing device described in Supplementary Note 2 may further include a control circuit (72) to which the sensor signal is input, and the control circuit may output an output signal corresponding to the input sensor signal to the first timer and the second timer. With this configuration, even if only one input terminal is assigned to input of the sensor signal, the output signal corresponding to the sensor signal can be output to the first timer 82 and the second timer 92.

[0098] (Appendix 11) A processing method for performing a first process and a second process different from the first process includes a first count value reading step (S22) of reading a first count value from a first timer, the first timer holding, as a first count value, the number of pulses of a first clock signal generated by a first divider dividing the frequency of a reference clock signal when a sensor signal is input, and a second count value reading step (S42) of reading a second count value from a second timer, the second timer holding, as a second count value, the number of pulses of a second clock signal generated by a second divider dividing the frequency of the reference clock signal when the sensor signal is input, when a second interrupt signal is output. With this configuration, even if one of a plurality of processes using clock signals becomes impossible to continue, the other processes can continue.

[0099] The present invention is not limited to the above disclosure, and various configurations can be adopted without departing from the gist of the present invention. [Explanation of symbols]

[0100] 10... Processing device 12... Input circuit 14... First memory / third memory 20... ECU 30... Vehicle 40... Speed ​​sensor 52... Crank angle sensor 54... Throttle position sensor 56... Intake pressure sensor 72... Control circuit 74... Clock supply unit 82... First timer 84... First frequency divider 92... Second timer 94... Second frequency divider 102... First processing unit 104... Second processing unit 110... Second memory 120... Processor core 140... Fuel injector 142... Spark plug 144... Throttle valve 146... Brake actuator 182... Third timer 192... Fourth timer 194... Third frequency divider 212... First processor core 214... Second processor core 220... Determination unit 230... Notification unit 252... First input terminal 254... Second input terminal

Claims

1. A processing device including a first processing unit that performs a first process and a second processing unit that performs a second process different from the first process, a first frequency divider that generates a first clock signal used for interrupting the first process by dividing a frequency of a reference clock signal; a second frequency divider different from the first frequency divider, the second frequency divider dividing a frequency of the reference clock signal to generate a second clock signal used for interrupting the second process; A processing device comprising:

2. 2. The processing device according to claim 1, a first timer that counts the number of pulses of the first clock signal, and when a sensor signal is input, holds the counted number of pulses of the first clock signal as a first count value, and outputs a first interrupt signal to the first processing unit to generate the interrupt to the first processing; a second timer different from the first timer, which counts a number of pulses of the second clock signal, and when the sensor signal is input, holds the counted number of pulses of the second clock signal as a second count value, and outputs a second interrupt signal to the second processing unit to generate the interrupt to the second processing; Further equipped with the first processing unit, when the first interrupt signal is output, reads the first count value from the first timer; The second processing unit reads the second count value from the second timer when the second interrupt signal is output.

3. 2. The processing device according to claim 1, A processing device, when a sensor signal corresponding to a vehicle speed is input, the first processing unit calculates the speed using the first clock signal and the sensor signal, and the second processing unit calculates the speed using the second clock signal and the sensor signal.

4. 2. The processing device according to claim 1, a first memory that stores first data used in the first processing by the first processing unit; a second memory different from the first memory, the second memory storing second data used in the second processing by the second processing unit; The processing device further comprises:

5. 2. The processing device according to claim 1, a third memory that stores a first program that is executed by the first processing unit to perform the first processing and a second program that is executed by the second processing unit to perform the second processing, The processing device, wherein the first program and the second program are stored in different memory areas of the third memory.

6. 2. The processing device according to claim 1, a predetermined time lag is provided between a start timing of a first processing cycle of the first processing and a start timing of a second processing cycle of the second processing, When the first processing cycle and the second processing cycle are different, The processing device, wherein the predetermined time is not a multiple of a greatest common divisor between the first processing period and the second processing period.

7. 2. The processing device according to claim 1, The first processing unit performs the first process related to an output control of a drive source of a vehicle, The second processing unit performs the second process related to a braking control for the vehicle, The first processing unit transmits a calculated value obtained during the first processing to the second processing unit; The second processing unit uses the calculated value transmitted from the first processing unit in the second processing.

8. 3. The processing device according to claim 2, a first processor core having the first processing unit; a second processor core different from the first processor core, the second processor core having the second processing unit; Further equipped with one of the first processor core and the second processor core further includes a determination unit; The processing device, wherein the determination unit calculates a count difference between the first count value and the second count value, and if the count difference is greater than a predetermined value, determines that at least one of the first count value and the second count value is an abnormal value.

9. 3. The processing device according to claim 2, a first input terminal to which the sensor signal is input, and a second input terminal different from the first input terminal; The sensor signal input to the first input terminal is further input to the first timer, The sensor signal input to the second input terminal is further input to the second timer.

10. 3. The processing device according to claim 2, A control circuit to which the sensor signal is input is further provided, The control circuit outputs an output signal corresponding to the input sensor signal to the first timer and the second timer.

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